SEMICONDUCTOR DEVICE

Abstract

Semiconductor device (100) comprising the following: a semiconductor substrate (10) containing a drift region (18) of a first conductivity type; a transistor section (70) containing an emitter region (12) of a first conductivity type which has a higher doping concentration than the drift region (18) in a region in contact with a top surface (21) of the semiconductor substrate (10); a diode section (80) comprising a cathode region (82) of a first conductivity type having a higher doping concentration than the drift region (18) in a region in contact with a bottom surface of the semiconductor substrate (10), an overlap region (26) of a second conductivity type in a region other than the cathode region (82), and arranged side by side with the transistor section (70) in a preset orientation in a top surface (21) of the semiconductor substrate (10); an emitter electrode (52) arranged above the semiconductor substrate (10); and a dielectric intermediate layer provided between the semiconductor substrate (10) and the emitter electrode (52) and provided with a contact hole (54) for connecting the emitter electrode (52) and the diode section (80), wherein the cathode region (82) is located closer to a central side of the diode section (80) than an end section of the emitter region (12) in the arrangement direction and the overlap region (26) is provided such that it has a first length between the end section of the emitter region (12) and an end section of the cathode region (82), the cathode region (82) is provided in a stretching direction that is perpendicular to the arrangement direction, closer to the middle side of the diode section (80) than an end section of the contact hole (54), and the overlap region (26) is provided such that it has a second length between the end section of the contact hole (54) and the end section of the cathode region (82), and the first length is greater than the second length.

Description

BACKGROUND 1. TECHNICAL AREA

[0001] The present invention relates to a semiconductor device. 2. RELATED AREA

[0002] A semiconductor device is already known in which a transistor section such as an insulated-gate bipolar transistor (IGBT) and a diode section such as a freewheeling diode (FWD) are provided in a common semiconductor substrate (see, for example, patent literature 1 to 7). Patent literature 1: WO 2017 / 155 122 A1 Patent Literature 2: Japanese Patent Publication No. JP 2017 - 11 001 A Patent literature 3: WO 2015 / 068 203 A1 Patent Literature 4: Japanese Patent Publication No. JP 2017 - 45 949 A Patent Literature 5: Japanese Patent Publication No. JP 2012 - 69 579 A Patent literature 6: US 2018 / 0 108 737 A1 Patent literature 7: US 2007 / 0 158 680 A1

[0003] A semiconductor device preferably possesses high avalanche resistance. GENERAL DISCLOSURE

[0004] A first aspect of the present invention relates to a semiconductor device according to claim 1. Further aspects of the invention are the subject of the dependent claims, the drawings and the description of exemplary embodiments.

[0005] The semiconductor device can be provided with a well region of a second conductivity type, which is arranged in the stretching direction adjacent to the diode section in the semiconductor substrate. The overlap region can be configured such that it has a third length in the stretching direction between an end section of the well region and the end section of the cathode region. The first length can be greater than the third length.

[0006] The diode section can have one longitudinal side in the stretching direction on the top side of the semiconductor substrate.

[0007] The semiconductor device can be provided with a top-side lifetime control section located on the upper side of the semiconductor substrate. The top-side lifetime control section can be situated in a region within the transistor section that is in contact with the diode section. The length of the top-side lifetime control section can be greater than the length in the arrangement direction from the end of the transistor section to the end of the top-side lifetime control section.

[0008] The first length at the center of the overlap area in the stretching direction can be smaller than the first length at the end in the stretching direction.

[0009] The transistor section can contain a collector region of a second conductivity type in a region that is in contact with one side of the semiconductor substrate. The overlap region in the arrangement direction can contain a section with a higher doping concentration than the collector region.

[0010] The overlap region in the arrangement direction may contain a thick section that has a greater thickness in the depth direction of the semiconductor substrate than the collector region.

[0011] The summary section does not necessarily describe all the necessary features of the embodiments of the present invention. The present invention may also be a subcombination of the features described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the invention. Fig. Figure 2 is a top view illustrating the surroundings of a diode section 80 on an enlarged scale. Fig. 3 is a top view showing area A in Fig. 2 illustrated on an enlarged scale. Fig. Figure 4 is a diagram showing an example of an aa cross-section in Fig. 3 illustrated. Fig. 5 is a diagram showing an example of a cross-section along bb in Fig. 3 was taken, illustrated. Fig. Figure 6 is a diagram that shows another example of the aa cross-section in Fig. 3 illustrated. Fig. Figure 7 is a diagram illustrating an arrangement example of a cathode region 82 and an overlap region 26 in a top view. Fig. Figure 8 is a diagram that shows another example of the aa cross-section in Fig. 3 illustrated. Fig. Figure 9 is a diagram that shows another example of the aa cross-section in Fig. 3 illustrated. Fig. Figure 10 is a top view illustrating an arrangement example of a thick section 28. Fig. Figure 11 is a diagram illustrating an arrangement example of the thick section 28 in the diode section 80 and in a transistor section 70. Fig. 12 is a top view showing area B in Fig. 11 illustrated on an enlarged scale. Fig. Figure 13 is a diagram that shows an example of a cross-sectional area in Fig. 12 illustrated. Fig. Figure 14 is a diagram illustrating an example of a relationship between a buffer area 20 and the thick section 28. Fig. Figure 15 is a diagram showing an example of the thickness of a sub-area 19 (of a collector area 22 in Fig. 15) and the collector area 22 is illustrated. Fig. Figure 16 is a diagram illustrating another configuration example of the buffer area 20. DESCRIPTION OF EXAMPLE FORMS OF EXECUTION

[0012] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as the "top" and the other side as the "bottom". One of the two principal surfaces of the substrate, layer, or other elements is referred to as a top surface and the other surface as a bottom surface. The "up" and "down" directions are not limited to the direction of gravity or the direction in which a semiconductor device is mounted.

[0013] This specification allows technical content to be described using rectangular coordinate axes: an X-axis, a Y-axis, and a Z-axis. The rectangular coordinate axes serve only to define the relative position of components and do not restrict any specific direction. For example, the Z-axis is not limited to a vertical direction relative to the ground surface. Furthermore, a +Z-axis direction and a -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating its sign, it means that the direction is parallel to both the +Z-axis and the -Z-axis. In this specification, viewing from the +Z-axis direction can be described as "in a top view."

[0014] In this specification, the terms "same" or "equal" may include a case where a defect is due to a manufacturing variation or similar cause. The corresponding defect is, for example, within 10%.

[0015] In this specification, the conductivity-type doping range is doped with impurities described as either P-type or N-type. However, the conductivity type of each doping range can be of opposite polarity. Additionally, in this specification, the terms P+-type or N+-type mean that the doping concentration is higher than that of the P-type or N-type, respectively, and the terms P--type or N---type mean that the doping concentration is lower than that of the P-type or N-type, respectively.

[0016] In this specification, the doping concentration indicates the concentration of impurities that are activated as either a donor or an acceptor. Within this specification, the concentration difference between the donor and the acceptor can be defined as the doping concentration. This concentration difference can be measured using a capacitance / voltage (CV) method. Alternatively, a carrier concentration measured using a scattering resistance (SR) method can be used as the doping concentration. Furthermore, if a doping concentration distribution exhibits a peak value, this peak value can be used as the doping concentration within the corresponding range.If the doping concentration is nearly uniform in an area where the donor or the acceptor is present, an average doping concentration can be used as the doping concentration in that area. Additionally, the dopant concentration in this specification specifies separate concentrations of the donor and the acceptor.

[0017] Fig. Figure 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the invention. Fig. Figure 1 illustrates positions obtained by projecting elements onto the top surface of a semiconductor substrate 10. Fig. Figure 1 illustrates only some elements of the semiconductor device 100, however some elements are omitted.

[0018] The semiconductor device 100 is provided with the semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed from a semiconductor material such as silicon or a composite semiconductor. The semiconductor substrate 10 has one edge face 102 in a top view. The semiconductor substrate 10 of this example has two sets of edge faces 102 facing each other in a top view. Fig. 1. The X-axis and the Y-axis are parallel to one of the edge faces 102. Additionally, the Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0019] An active section 120 is created in the semiconductor substrate 10. The active section 120 is a region in which a main current flows in the depth direction between the top and bottom of the semiconductor substrate 10 when the semiconductor device 100 is switched to an ON state. A transistor section 70, containing a transistor element such as an IGBT, and a diode section 80, containing a diode element such as an FWD, are created in the active section 120. The active section 120 can be a region in which the transistor section 70 and the diode section 80 are located.

[0020] In Fig. The symbol "I" is placed at the area where transistor section 70 is located, and the symbol "F" is placed at the area where diode section 80 is located. Transistor section 70 and diode section 80 are arranged side by side in a predetermined orientation (along the X-axis). Fig. 1) arranged. The transistor section 70 and the diode section 80 can be arranged alternately next to each other in the X-axis direction. In this specification, a direction perpendicular to the arrangement direction in a top view is referred to as a stretching direction (the Y-axis direction in Fig. 1) denoted. The transistor section 70 and the diode section 80 can each contain one long side in the stretching direction. In other words, the length in the Y-axis direction of the transistor section 70 is greater than the width in the X-axis direction. Correspondingly, the length in the Y-axis direction of the diode section 80 is greater than the width in the X-axis direction. If the active section 120 is subdivided in a top view, the transistor section 70 and the diode section 80 can be arranged alternately next to each other in the X-axis direction in each region of the active section 120.

[0021] A p-type well region 11 is provided in the semiconductor substrate 10. The well region 11, which has a higher doping concentration than a base region described later, is formed such that it rests against the top surface of the semiconductor substrate 10 and is positioned deeper than the bottom surface of the base region. The depth is measured from the top surface of the semiconductor substrate 10 as a reference point. Fig. Figure 1 illustrates an example arrangement of the trough area 11 in the top surface of the semiconductor substrate 10. Fig. 1 is the bathtub area hatched with diagonal lines.

[0022] The basin area 11 can be configured to surround the active section 120 in a top view. The basin area 11 can surround several areas in a top view and be provided with the active section 120 in each area. In the example of Fig. In Figure 1, two active sections 120 are arranged side by side in the Y-axis direction. The basin area 11 is located between the two active sections 120 in a top view.

[0023] The semiconductor device 100 can be provided with a gate contact 51 and a gate distributor 48. The gate distributor 48 in Fig. Figure 1 is illustrated with a thick solid line. The gate contact 51 and the gate distributor 48 are arranged above the semiconductor substrate 10. A dielectric intermediate layer is provided between the semiconductor substrate 10 and the gate contact 51 and the gate distributor 48, but is in Fig. 1 omitted.

[0024] The gate contact 51 is an electrode containing a metal such as aluminum. The gate distributor 48 is a wiring arrangement for electrically connecting the gate contact 51 and the transistor section 70. The gate distributor 48 can be a metal wiring arrangement containing a metal such as aluminum, or it can be a semiconductor wiring arrangement containing polysilicon doped with impurities. The gate distributor 48 can include a section in which the metal wiring or the semiconductor wiring is provided, or it can include a section in which both the metal wiring and the semiconductor wiring are connected in parallel.

[0025] The gate contact 51 and the gate distributor 48 are arranged above the basin area 11. In a top view, the gate contact 51 is located between the active section 120 and the edge face 102. The gate distributor 48 can be arranged to surround the active section 120. The gate distributor 48 can include a section in which, in a top view, it is located between the active section 120 and the edge face 102. The gate distributor 48 can also include a section in which, in a top view, it is located between two active sections 120.

[0026] A predetermined gate voltage is applied to gate contact 51. The gate voltage applied to gate contact 51 is supplied to transistor section 70 via the gate distributor 48.

[0027] An emitter electrode is provided on the upper side of the active section 120, but it is located in Fig. 1 is omitted. The emitter electrode can cover the entire active section 120. The emitter electrode is an electrode containing a metal such as aluminum. A dielectric intermediate layer is provided between the emitter electrode and the semiconductor substrate 10. The emitter electrode and the semiconductor substrate 10 are connected via a contact hole provided on the dielectric intermediate layer. In Fig. 1. The insulating layer and the contact hole are omitted.

[0028] The semiconductor device 100 can be provided with an edge termination structure section 90 between the well area 11 and the edge side 102 of the semiconductor substrate 10. The edge termination structure section 90 reduces the concentration of an electric field on the top side of the semiconductor substrate 10. The edge termination structure section 90 has the structure of, for example, a guard ring in a ring shape surrounding the active section 120, a field plate, a RESURF, or a combination thereof.

[0029] Fig. Figure 2 is a top view illustrating the environment of the diode section 80 at an enlarged scale. The diode section 80 contains a cathode region 82, which is in contact with the underside of the semiconductor substrate 10. The cathode region 82 is an N-type region. The transistor section 70 contains a P-type underside region 19, which is in contact with the underside of the semiconductor substrate 10. In this example, the underside region 19 is provided across the entire transistor section 70. Additionally, the underside region 19 is also provided in a section in contact with the transistor section 70 within the diode section 80.

[0030] Avalanche breakdown is a known mode of destruction for the semiconductor device 100. In the semiconductor device 100, which contains the IGBT and the like, it is desirable to improve the current density. Additionally, the semiconductor substrate 10 can be manufactured to have a high resistivity in order to reduce its thickness. If the current density is improved and the semiconductor substrate 10 is manufactured to have a high resistivity, the electric field at the time of the short circuit is concentrated on the underside of the semiconductor substrate 10. Therefore, a backside avalanche breakdown is likely to occur.

[0031] The resistance to backside avalanche breakdown can be improved by increasing the number of hole implants from the underside of the semiconductor substrate 10. However, since an N-type cathode region is generally provided on the underside of the diode section 80, the number of hole implants from the underside of the diode section 80 is relatively small. Therefore, it is likely that backside avalanche breakdown will occur at the boundary between the transistor section 70 and the diode section 80.

[0032] In the semiconductor device 100 of this example, the underside region 19 is located in a portion of the diode section 80 in contact with the transistor section 70 instead of the cathode region 82. As a result, the number of holes implanted from the underside in the boundary between the transistor section 70 and the diode section 80 increases. Therefore, it is possible to improve the backside avalanche resistance.

[0033] In this example, the length in the arrangement direction (the X-axis direction) of the underside region 19, which is provided in the diode section 80, is set to L1. If the length L1 increases, the number of hole implantations from the underside in the boundary between the transistor section 70 and the diode section 80 increases.

[0034] The transistor section 70 and the diode section 80 can be arranged adjacent to the well area 11 in the stretch direction (the Y-axis direction). In this example, the transistor section 70 and the diode section 80 are clamped in the stretch direction by two well areas 11. The diode section 80 can also be provided with the underside area 19 at its boundary with respect to the well area 11. As described above, the well area 11 has a relatively high density and depth. Therefore, the breakdown voltage is reduced if the distance between the well area 11 and the cathode area 82 is too small. In a top view, the underside area 19 is positioned between the well area 11 and the cathode area 82 such that the distance between the well area 11 and the cathode area 82 can be ensured and the breakdown voltage can be reliably maintained.

[0035] Fig. 3 is a top view showing area A in Fig. Figure 2 is shown on an enlarged scale. The semiconductor substrate 10 of this example is provided with a gate trench section 40 in contact with the top surface of the semiconductor substrate 10, a placeholder trench section 30, the well area 11, an emitter area 12, a base area 14, and a contact area 15. Additionally, the semiconductor substrate 10 of this example is provided with the cathode area 82 and the bottom surface area 19, which are in contact with the bottom surface of the semiconductor substrate 10.

[0036] Additionally, an emitter electrode 52 and the gate distributor 48 are provided above the semiconductor substrate 10. Fig. Figure 3 illustrates the area where the emitter electrode 52 is marked with a dotted line. The emitter electrode 52 is positioned above the transistor section 70 and the diode section 80. The emitter electrode 52 may include a section that overlaps with the well area 11.

[0037] The dielectric intermediate layer is provided between the emitter electrode 52 and the top surface of the semiconductor substrate 10, however it is in Fig. 3 omitted. In the dielectric intermediate layer of this example, a contact hole 56 and a contact hole 54 are provided such that they extend through the dielectric intermediate layer.

[0038] The emitter electrode 52 is in contact with the emitter region 12, the contact region 15, and the base region 14 in the top surface of the semiconductor substrate 10 via the contact hole 54. Additionally, the emitter electrode 52 is connected to a placeholder conductor section in the placeholder trench section 30 via the contact hole 56. A connecting section 25, formed from a conductive material such as impurity-doped polysilicon, can be provided between the emitter electrode 52 and the placeholder conductor section. The connecting section 25 is located in the top surface of the semiconductor substrate 10. An insulating layer, such as a thermooxide layer, is provided between the connecting section 25 and the semiconductor substrate 10.

[0039] An insulating layer, such as a thermooxide layer, is provided between the gate distributor 48 and the semiconductor substrate 10. The gate distributor 48 is connected to a gate conductor section in the gate trench section 40 in the top surface of the semiconductor substrate 10. The gate distributor 48 is not connected to a placeholder conductor section in the placeholder trench section 30. The gate distributor 48 in this example is configured to overlap an edge section 41 of the gate trench section 40. The edge section 41 is the end section in the extension direction (the Y-axis direction) of the gate trench section 40. The gate conductor section in the edge section 41 of the gate trench section 40 is exposed to the top surface of the semiconductor substrate 10 and is in contact with the gate distributor 48.

[0040] The emitter electrode 52 is formed from a material containing metal. For example, at least one section of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the lower layer of the section formed from aluminum or the like. Furthermore, a plug formed with added tungsten may be contained in the contact hole such that it is in contact with the barrier metal and the aluminum.

[0041] Transistor section 70 is equipped with gate trench section 40. Diode section 80 is equipped with placeholder trench section 30. Transistor section 70 may also be equipped with placeholder trench section 30.

[0042] In transistor section 70 of this example, the gate trench section 40 and the placeholder trench section 30 are arranged alternately at a predetermined interval in the X-axis direction. In diode section 80 of this example, the placeholder trench section 30 is arranged at a predetermined interval.

[0043] The gate trench section 40 of this example can contain two extension sections 39 (a trench section of a straight shape in the Y-axis direction) extending in the Y-axis direction, and the edge section 41 for connecting the two extension sections 39. At least a portion of the edge section 41 is preferably provided in a curved shape. The concentration of the electric field at the apex of the gate trench section 40 can be reduced by connecting the two extension sections 39 of the gate trench section 40 to form the edge section 41.

[0044] The placeholder trench section 30 of this example is located between the stretch sections 39. These placeholder trench sections 30 can be in a straight line extending along the Y-axis. Additionally, similar to the gate trench section 40 in the diode section 80, the placeholder trench section 30 can include a stretch section 29 and an edge section 31. The length of the placeholder trench section 30 along the Y-axis can be shorter than that of the gate trench section 40. The edge section 31 is positioned overlapping the emitter electrode 52 and is connected to the emitter electrode 52 via the connecting section 25.

[0045] In the semiconductor substrate 10, an area clamped by the stretched sections of the trench sections is referred to as a mesa section. A mesa section 60 is provided in the transistor section 70, and a mesa section 61 is provided in the diode section 80. The mesa section is an area on the upper side of the lowest floor of the trench section in the section of the semiconductor substrate 10 that is clamped by the trench sections.

[0046] Base area 14 is present in every mesa segment. Base area 14 in this example is of a P-type. Base area 14 is partially exposed on the top surface of the mesa segment.

[0047] The contact area 15 and the emitter area 12 are located on the top surface of the base area 14 of the mesa section 60 of the transistor section 70. The contact area 15 of this example is of a P+ type, which has a higher doping concentration than the base area 14. The emitter area 12 of this example is of an N+ type, which has a higher doping concentration than a drift area, which will be described later.

[0048] The emitter region 12 is configured to be in contact with the gate trench section 40 in the top surface of the semiconductor substrate 10. The emitter region 12 and the contact region 15 of this example extend from one trench section that clamps the mesa section 60 to the next trench section. In the top surface of the mesa section 60 of this example, the contact region 15 and the emitter region 12 are arranged alternately in the Y-axis direction. The contact region 15, located at the outermost section in the Y-axis direction between the contact regions 15 provided in the mesa section 60, may be positioned overlapping the end section in the Y-axis direction of the contact hole 54. The emitter region 12 is located in a region where the contact hole 54 is provided in the Y-axis direction.

[0049] In another example, the contact area 15 and the emitter area 12 can be arranged in a strip shape in the extension direction of the mesa section 60. For example, the emitter area 12 is located in an area in direct contact with the trench section, and the contact area 15 is located in an area clamped between the emitter areas 12. The base area 14 can be arranged in the top of the mesa section 60, clamping the area containing the contact area 15 and the emitter area 12 in the Y-axis direction. The trough area 11 can also be arranged in the top of the mesa section 60, clamping the area containing the contact area 15, the emitter area 12, and the base area 14 in the Y-axis direction. The edge section 41 of the gate trench section 40 is arranged at a position that overlaps with the trough area 11.

[0050] In this specification, the region in which the gate trench section 40 and the emitter region 12 are regularly arranged is set to the transistor section 70. The emitter region 12, which is located at the outermost section in the X-axis direction between the emitter regions 12 regularly arranged in the X-axis direction, is set to the emitter region 12 of the end of the transistor section 70. In this specification, an end position Xb of the X-axis direction of the emitter region 12 of the end is set to delimit it between the transistor section 70 and the diode section 80 in the X-axis direction. The end position Xb of the X-axis direction of the emitter region 12 of the end is set to delimit it between the emitter region 12 and the trench section in the top surface of the semiconductor substrate 10.

[0051] The emitter region 12 need not be provided in the mesa section 61 of the diode section 80. A P-type region may be arranged in the top surface of the mesa section 61. In this example, the base region 14 is provided in the top surface of the mesa section 61. The base region 14 may occupy an area larger than half the area of ​​the top surface of the mesa section 61. The contact region 15 may be arranged in the top surface of the mesa section 61. The contact region 15 of the mesa section 61 may be positioned so that it overlaps the end of the contact hole 54 in the Y-axis direction. The base region 14 may be provided in the top surface of the mesa section 61, clamping the contact region 15 in the Y-axis direction. The upper surface of the mesa section 61 can include the basin area 11, which clamps the area in which the base area 14 and the contact area 15 are provided in the Y-axis direction.The edge section 31 of the placeholder trench section 30 is arranged at a position that overlaps with the trough area 11.

[0052] The contact hole 54 provided in transistor section 70 and the contact hole 54 provided in diode section 80 can have the same length or different lengths in the Y-axis direction. In transistor section 70, contact hole 54 is located above contact area 15 and emitter area 12, respectively. In this example, contact hole 54 is not located in the area corresponding to base area 14 and well area 11 of mesa section 60. In diode section 80, contact hole 54 is located above contact area 15 and base area 14. However, contact hole 54 is not located above base area 14, which is clamped by contact area 15 and well area 11, in mesa section 61.

[0053] In diode section 80, the N+-type cathode region 82 is located in an area that contacts the underside of the semiconductor substrate 10. The underside region 19 is located in an area where the cathode region 82 is not located in the area that contacts the underside of the semiconductor substrate 10. In this example, the underside region 19, which is located in transistor section 70, is connected to a collector region 22. Additionally, the underside region 19, which is located in diode section 80, is connected to an overlap region 26. The collector region 22 and the overlap region 26 can have the same doping concentration or they can have different doping concentrations. Fig. Figure 3 illustrates the boundaries between the cathode area 82, the overlap area 26 and the collector area 22 with a dotted line.

[0054] In this example, the cathode region 82 is positioned closer to the middle side of the diode section 80 in the X-axis direction than the end position Xb of the emitter region 12. In other words, the diode section 80 contains the overlap region 26 in the X-axis direction between the end position Xb of the emitter region 12 and the end section of the cathode region 82. The length of the overlap region 26 in the X-axis direction is set to a first length L1.

[0055] Additionally, the cathode region 82 is positioned closer to the middle side of the diode section 80 in the Y-axis direction than an end position Yc of the contact hole 54. In other words, the diode section 80 contains the overlap region 26 in the Y-axis direction between the end position Yc of the contact hole 54 and the end section of the cathode region 82. The length of the overlap region 26 between the end position Yc of the contact hole 54 and the end section of the cathode region 82 is set to a second length L2.

[0056] The first length L1 of the overlap region 26 is greater than the second length L2. This allows for an increase in the number of holes implanted from the underside of the semiconductor substrate 10 at the boundary between the diode section 80 and the transistor section 70 in the X-axis direction. As a result, the backside avalanche resistance is improved. The first length L1 can be two or more times, or five or more times, the second length L2. Additionally, the area of ​​the cathode region 82 can be ensured by making the second length L2 relatively small.

[0057] In this example, the overlap region 26 in the Y-axis direction is also provided between an end position Yw of the well region 11 and the end position Yc of the contact hole 54. In other words, the diode section 80 in the Y-axis direction contains the overlap region 26 between the end position Yw of the well region 11 and the end section of the cathode region 82. The length of the overlap region 26 between the end position Yw of the well region 11 and the end section of the cathode region 82 is set to a third length L3.

[0058] The first length L1 of the overlap region 26 can be greater than the third length L3. This makes it possible to further increase the number of holes implanted from the underside of the semiconductor substrate 10 at the boundary between the diode section 80 and the transistor section 70 in the X-axis direction. Therefore, it is possible to further improve the backside avalanche resistance. The first length L1 can be twice or more than the third length L3. Additionally, it is possible to ensure the area of ​​the cathode region 82 by making the third length L3 relatively small.

[0059] The first length L1 of the overlap region 26 can be 20 µm or more, 50 µm or more, or 100 µm or more. Additionally, the overlap region 26 can extend over multiple mesa sections 61 in the X-axis direction. By increasing the first length L1, it is possible to increase the number of holes implanted from the underside of the semiconductor substrate 10 at the boundary between the diode section 80 and the transistor section 70 in the X-axis direction.

[0060] Additionally, the diode section 80 can have a longitudinal side in the Y-axis direction on the top surface of the semiconductor substrate 10. The diode section 80 can be a region surrounded by the transistor section 70 and the well region 11 on the top surface of the semiconductor substrate 10. The diode section 80 can be a region where the gate trench section 40 and the emitter region 12 are not present. If the diode section 80 has a longitudinal side in the Y-axis direction, the boundary region between the diode section 80 and the transistor section 70 increases, and backside avalanche breakdown is likely to occur. On the other hand, backside avalanche breakdown can be suppressed by increasing the first length L1 of the overlap region 26.

[0061] Fig. 4 is a diagram showing an example of aa cross-section in Fig. Figure 3 illustrates this. The aa cross-section is the XZ plane passing through the emitter region 12. The semiconductor device 100 of this example contains the semiconductor substrate 10, a dielectric intermediate layer 38, the emitter electrode 52, and a collector electrode 24 in the corresponding cross-section. The emitter electrode 52 is located in the top surface of the semiconductor substrate 10 and the dielectric intermediate layer 38. The dielectric intermediate layer 38 can be a thermooxide layer, a glass such as BPSG, or it can consist of further insulating layers. Additionally, the dielectric intermediate layer 38 can be a layer in which several insulating layers are stacked on top of each other.

[0062] The collector electrode 24 is provided in a subsurface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed from a conductor material such as metal or the like. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as a depth direction.

[0063] The base region 14 of the P-type transistor is located on the top side 21 of the semiconductor substrate 10 in the corresponding cross-section. In the corresponding cross-section, the emitter region 12 of the N+ type and the base region 14 of the P- type are located on the top side 21 of the semiconductor substrate 10 in the transistor section 70 such that they are sequential from the top side 21 of the semiconductor substrate 10. An enhancement region of the N+ type may be located below the base region 14. In the corresponding cross-section, the base region 14 of the P- type is located on the top side 21 of the semiconductor substrate 10 in the diode section 80.

[0064] In transistor section 70 and diode section 80, an N-type drift region 18 is provided below the base region 14. In transistor section 70 and diode section 80, an N+-type buffer region 20 is provided below the drift region 18.

[0065] The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 can serve as a field stop layer, preventing a depletion layer extending from the bottom of the base region 14 from reaching the collector region 22, the overlap region 26 and the cathode region 82.

[0066] In transistor section 70, the collector region 22 of the P+ type is provided below the buffer region 20. In diode section 80, the overlap region 26 of the P+ type and the cathode region 82 are provided below the buffer region 20. The overlap region 26 is arranged between the cathode region 82 and the collector region 22. As in Fig. As described in Figure 3, the overlap area 26 has the first length L1 in the X-axis direction.

[0067] The doping concentration of the overlap region 26 is higher than that of the base region 14. In this example, the doping concentration of the overlap region 26 is the same as the doping concentration of the collector region 22. Additionally, the thickness in the Z-axis direction of the overlap region 26 is the same as the thickness in the Z-axis direction of the collector region 22. The overlap region 26 can be formed in the same process as the collector region 22.

[0068] On the top side 21 of the semiconductor substrate 10, one or more gate trench sections 40 and one or more placeholder trench sections 30 are provided. Each trench section is configured to extend from the top side 21 of the semiconductor substrate 10 through the base region 14 to reach the drift region 18. In the region where the emitter region 12 and / or the contact region 15 are located, each trench section also passes through these regions and reaches the drift region 18. The configuration in which the trench section passes through the doping region is not limited to the configuration produced in the sequence of forming the doping region followed by forming the trench section. The configuration in which the doping region is formed between the trench sections, after the trench section has been formed, includes a configuration in which the trench section passes through the doping region.

[0069] The gate trench section 40 contains a gate insulating layer 42 and a gate conductor section 44, which are provided on the top surface 21 of the semiconductor substrate 10. The gate insulating layer 42 is designed to cover the inner wall of the gate trench section 40. The gate insulating layer 42 can be formed by oxidizing or nitriding a semiconductor material on the inner wall of the gate trench section 40. The gate conductor section 44 is located inside the gate insulating layer 42 within the gate trench section 40. In other words, the gate insulating layer 42 insulates the gate conductor section 44 from the semiconductor substrate 10. The gate conductor section 44 is made of a conductor material such as polysilicon or the like.

[0070] The gate conductor section 44 includes a region that clamps the gate insulating layer 42 and faces the base region 14. The gate trench section 40, with the corresponding cross-section, is covered by the dielectric intermediate layer 38 in the top surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductor section 44, a channel is formed through an electron inversion layer on the top surface of the base region 14 at the boundary in contact with the gate trench.

[0071] The placeholder trench section 30 can have the same structure as the gate trench section 40 in the corresponding cross-section. The placeholder trench section 30 includes a placeholder trench provided on the side of the top surface 21 of the semiconductor substrate 10, a placeholder insulating layer 32, and a placeholder conductor section 34. The placeholder insulating layer 32 is provided to cover the inner wall of the placeholder trench. The placeholder conductor section 34 is provided within the placeholder trench and is located on the inside of the placeholder insulating layer 32. The placeholder insulating layer 32 insulates the placeholder conductor section 34 from the semiconductor substrate 10. The placeholder conductor section 34 can be made of the same material as the gate conductor section 44.

[0072] Fig. Figure 5 is a diagram showing an example of a bb cross-section in Fig. Figure 3 illustrates this. The bb cross-section is the YZ plane, which contains the diode section 80. In the diode section 80, the base region 14 is located in a region that is in contact with the top surface 21 of the semiconductor substrate 10. The base region 14 is connected to the emitter electrode 52 via the contact hole 54, which is provided in the dielectric intermediate layer 38. At the end position Yc of the contact hole 54, the contact region 15 is located in a region where it is in contact with the top surface 21 of the semiconductor substrate 10. As shown in Fig. As described in 3, the overlap area 26 between the end position Yc of the contact hole 54 and the end position of the cathode area 82 has the second length L2.

[0073] In the Y-axis direction, the well region 11 is located on the outside of the diode section 80. The boundary between the well region 11 and the base region 14 can be the end section in the Y-axis direction of the diode section 80. If the boundary between the base region 14 and the well region 11 is unclear, the position closest to the base region 14 among those where the average doping concentration of the base region 14 is Da and the doping concentration in the well region 11 is 2 × Da can be considered the boundary between the base region 14 and the well region 11. The doping concentration in the top surface 21 of the semiconductor substrate 10 can be used as a reference point. As shown in Fig. As described in 3, the overlap area 26 between the end position Yw of the trough area 11 and the end position of the cathode area 82 has the third length L3.

[0074] Fig. Figure 6 is a diagram that shows another example of the aa cross-section in Fig. Figure 3 illustrates this. The semiconductor device 100 of this example includes a top-side lifetime control section 92 located on the top side of the semiconductor substrate 10. The top side of the semiconductor substrate 10 indicates a region closer to the top surface 21 than the center of the depth direction of the semiconductor substrate 10. The top-side lifetime control section 92 is a region in which the concentration of the recombination center of carriers (electrons or holes) is adjusted to be higher than that of the surrounding area. The recombination center can be a vacancy defect such as a vacancy or vacancy cluster, a dislocation, interstitial atoms, a transition metal, or the like.

[0075] The upper lifetime control section 92 can be formed, for example, by locally implanting particles such as helium or proton from the upper surface 21 of the semiconductor substrate 10.

[0076] The upper lifetime control section 92 of this example is provided throughout the entire diode section 80. As a result, the lifetime of the diode section 80 can be reduced, and the reverse recovery time can be shortened. Additionally, the upper lifetime control section 92 itself is located in the area in contact with the diode section 80 within the transistor section 70. Consequently, it is possible to suppress the current of the carriers between the top surface of the transistor section 70 and the cathode area 82 of the diode section 80.

[0077] In this example, the length in the X-axis direction of the upper lifetime control section 92 provided in transistor section 70 is set to a fourth length L4. The fourth length L4 is a length in the X-axis direction from the end position Xb of transistor section 70 to the end position of the upper lifetime control section 92.

[0078] The first length L1 of the overlap region 26 in the diode section 80 can be longer than the fourth length L4 of the top-side lifetime control section 92. By increasing the first length L1 of the overlap region 26, the backside avalanche breakdown in the boundary between the transistor section 70 and the diode section 80 can be suppressed. Additionally, by increasing the first length L1 of the overlap region 26, the cathode region 82 can be positioned away from the transistor section 70. As a result, it is possible to suppress the carrier current between the top of the transistor section 70 and the cathode region 82 of the diode section 80, even if the fourth length L4 of the top-side lifetime control section 92 is reduced.By reducing the fourth length L4 of the upper lifetime control section 92, it is possible to reduce the influence of the upper lifetime control section 92 on the properties of the transistor section 70.

[0079] Fig. Figure 7 is a diagram illustrating an example arrangement of the cathode region 82 and the overlap region 26 in a top view. In the example of Fig. In the overlap region 26 (i.e., the bottom surface region 19 of the P-type in the diode section 80), the overlap region 26 has a constant width L1 in the X-axis direction. In other words, the overlap region 26 has a rectangular shape in a top view. In the overlap region 26 of this example, a first length L1b at the center in the Y-axis direction is smaller than a first length L1a at the end in the Y-axis direction.

[0080] It is likely that the electric field will concentrate at the end in the Y-axis direction of the diode section 80 (i.e., the corner of the diode section 80 in a top view), and the occurrence of backside avalanche breakdown is more likely than at the center in the Y-axis direction. In this example, backside avalanche breakdown at the corner of the diode section 80 can be suppressed by setting the first length L1a larger than the first length L1b. Additionally, the area of ​​the cathode region 82 is increased by decreasing the first length L1b such that the properties of the diode section 80 can be improved. The first length L1b can be zero. In other words, the overlap region 26 does not have to be located at the center in the Y-axis direction of the diode section 80. In the example of Fig. 7 The width of the overlap area 26 is changed in steps in the X-axis direction, however, the width of the overlap area 26 can be changed continuously in the X-axis direction.

[0081] Fig. Figure 8 is a diagram that shows another example of the aa cross-section in Fig. Figure 3 illustrates this. The overlap region 26 of this example contains a high-concentration section 27, which has a higher doping concentration than the collector region 22. The doping concentration of the high-concentration section 27 can be two or more, five or more, or ten or more times the doping concentration of the collector region 22. The high-concentration section 27 allows for a further increase in the amount of hole implantation from the underside of the diode section 80.

[0082] The high-concentration section 27 can be in contact with the cathode region 82. In another example, the high-concentration section 27 can be in contact with the collector region 22. Part of the overlap region 26 can be the high-concentration section 27. The entire overlap region 26 can be the high-concentration section 27.

[0083] Fig. Figure 9 is a diagram that shows another example of the aa cross-section in Fig. Figure 3 illustrates this. The overlap region 26 of this example contains a thick section 28 whose thickness in the Z-axis direction is greater than that of the collector region 22. The thickness of the thick section 28 can be 1.2 times or more, 1.5 times or more, or 2 times or more the thickness of the collector region 22. The thickness of the collector region 22 can be its average thickness. The thickness of the thick section 28 can be the maximum thickness of the overlap region 26.

[0084] The thick section 28 allows for a further increase in the amount of hole implantation from the underside of the diode section 80. The thick section 28 can be in contact with the cathode region 82. In another example, the thick section 28 can be in contact with the collector region 22. The entire overlap region 26 can be the thick section 28. Additionally, the thick section 28 can be the high-concentration section 27. In other words, the overlap region 26 can contain a section where the doping concentration is higher than that of the collector region 22 and the thickness is large.

[0085] Fig. Figure 10 is a top view illustrating an arrangement example of the thick section 28. In Fig. In Figure 10, the thick section 28 is hatched with diagonal lines. The thick section 28 is located at the end of the bottom surface area 19. The thick section 28 can be located at the end of the bottom surface area 19 in the X-axis direction. The thick section 28 can be located at the end of the bottom surface area 19 in the Y-axis direction.

[0086] The end of the bottom surface area 19 includes a section that is in contact with the cathode area 82 in the bottom surface area 19. The thick section 28 can be provided in a section that is in contact with the cathode area 82 in the X-axis direction in the bottom surface area 19. The thick section 28 can also be provided in a section that is in contact with the cathode area 82 in the Y-axis direction in the bottom surface area 19. The thick section 28 can be arranged such that it surrounds the cathode area 82 in a top view.

[0087] Additionally, the thick section 28 can be provided in the underside region 19 at the end of the semiconductor substrate 10. The thick section 28 can itself be arranged between the edge face 102 of the semiconductor substrate 10 and the active section 120. The thick section 28 can also be provided in the area that overlaps with the well region 11. The thick section 28 can also be provided in the edge termination structure section 90.

[0088] The thick section 28 can have a thickness greater than that of the further section of the underside region 19. As in Fig. 1 to Fig. As described in Figure 9, the bottom surface area 19 can contain the overlap area 26 in the X-axis direction. In this case, the end of the bottom surface area 19 is located in the diode section 80 in the X-axis direction. Therefore, as described in Figure 9, the bottom surface area 19 can be located in the X-axis direction. Fig. Figure 9 illustrates the thick section 28 being arranged in the diode section 80.

[0089] In another example, the bottom surface area 19 need not include the overlap area 26 in the X-axis direction. In this case, the boundary between the transistor section 70 and the diode section 80 becomes the end of the bottom surface area 19 in the X-axis direction. In other words, the positions of the end of the diode section 80 in the X-axis direction and the end of the cathode area 82 are aligned. Therefore, the thick section 28 is positioned in an area that is in contact with the diode section 80 in the transistor section 70. Fig. Figure 10 illustrates an example in which the sub-area 19 does not contain the overlap area 26 in the X-axis direction.

[0090] The thick section 28 can be configured such that, in a top view, it surrounds each transistor section 70. The collector area 22 can be surrounded by the thick section 28 in a top view.

[0091] Fig. Figure 11 is a diagram illustrating an arrangement example of the thick section 28 in the diode section 80 and the transistor section 70. In this example, the thick section 28 is located at the boundary between the diode section 80 and the transistor section 70 within the transistor section 70. The thick section 28 can be arranged such that it is in contact with the boundary between the transistor section 70 and the diode section 80. In another example, the thick section 28 can be located within the diode section 80, as shown in Fig. Figure 9 illustrates this.

[0092] Additionally, the thick section 28 is also provided at the ends of the diode section 80 and the transistor section 70 in the Y-axis direction. With this configuration, the diode section 80 and the transistor section 70 are each surrounded by the thick section 28. As a result, the number of holes implanted from the underside at the ends of the diode section 80 and the transistor section 70 can be increased.

[0093] Fig. 12 is a top view showing area B in Fig. Figure 11 is illustrated on an enlarged scale. In the semiconductor device 100 of this example, the arrangement of the cathode region 82 and the bottom surface region 19 (the collector region 22 and the thick section 28) is shown in Fig. 12) of the semiconductor device 100, which is in Fig. Figure 3 illustrates different configurations. The other configurations are the same as those of semiconductor device 100, which is shown in Figure 100. Fig. Figure 3 illustrates this.

[0094] In this example, the cathode region 82 extends along the entire diode section 80 in the X-axis direction. The thick section 28 is located between the cathode region 82 and the collector region 22 in the X-axis direction. With this structure, the number of holes implanted from the underside at the boundary between the diode section 80 and the transistor section 70 can be increased.

[0095] Fig. Figure 13 is a diagram that shows an example of a cross-sectional area in Fig. 12 illustrates. As in Fig. As described in Figure 12, the thick section 28 is arranged between the cathode region 82 and the collector region 22. Furthermore, the thick section 28 can have the same doping concentration as the high-concentration section 27, which is described in Figure 12. Fig. As described in section 8. In other words, at the end of the underside region 19, a section can be provided which has a higher doping concentration than the collector region 22 and has a large thickness in the Z-axis direction. As a result, the amount of hole implantation from the underside at the boundary between the diode section 80 and the transistor section 70 can be further increased.

[0096] At least part of the thick section 28 can be provided within the buffer area 20. In other words, the thick section 28 can be provided such that it projects from the underside of the buffer area 20 into the interior of the buffer area 20.

[0097] A distance D1 between the thick section 28 and the drift region 18 in the Z-axis direction (i.e., the thickness of the buffer region 20 between the thick section 28 and the drift region 18) can be 1 µm or more. The distance D1 can be 2 µm or more. If the distance D1 is ensured to be 1 µm or more, it is possible to prevent the depletion layer spreading from the top side of the semiconductor substrate 10 from reaching the thick section 28.

[0098] The distance between the collector area 22 and the drift area 18 in the Z-axis direction is set to D2. The distance D2 corresponds to the thickness of the buffer area 20. The distance D1 can be equal to or less than half, or equal to or less than 1 / 4 of the distance D2.

[0099] Fig. Figure 14 is a diagram illustrating an example of the relationship between buffer region 20 and thick section 28. The buffer region 20 in this example has several doping concentration peaks, P1 to P4, in the Z-axis direction. For example, the multiple concentration peaks in buffer region 20 can be generated by repeatedly injecting impurities, such as protons, into buffer region 20 at different ranges.

[0100] Among the multiple concentration peak values ​​P, the one closest to the bottom surface 23 of the semiconductor substrate 10 is set to P1. The concentration peak value P1 can be the one with the highest doping concentration among the multiple concentration peak values. The doping concentrations of the multiple concentration peak values ​​are adjusted such that the depletion layer spreading from the top surface of the semiconductor substrate 10 does not exceed the concentration peak value P1, thus preventing it from spreading to the bottom surface 23.

[0101] The upper end of the thick section 28 is located on the side of the lower surface 23 of the concentration peak value P1. As a result, it is possible to suppress the depletion layer spreading from the upper surface of the semiconductor substrate 10 from reaching the thick section 28.

[0102] Fig. Figure 15 is a diagram showing an example of the thicknesses of the bottom surface area 19 (of the collector area 22 in Fig. 15) and the collector region 22 is illustrated. The p-type dopant concentration of the collector region 22 in this example is higher than the N-type dopant concentration in the cathode region 82. The collector region 22 can contain the N-type dopant having the same concentration as the cathode region 82. Since the cathode region 82 is formed across the entire bottom surface 23 of the semiconductor substrate 10, the collector region 22 can be formed by counter-doping with a p-type dopant. The thickness of the collector region 22 can be greater than the thickness of the cathode region 82.

[0103] Fig.Figure 16 is a diagram illustrating another configuration example of the buffer region 20. In this example, the buffer region 20 contains a high-concentration region 71 and a low-concentration region 72. The low-concentration region 72 is located adjacent to the high-concentration region 71 in the X-axis direction and has a lower doping concentration than the high-concentration region 71. The low-concentration region 72 may be sandwiched between the high-concentration region 71 and the high-concentration region 71. Additionally, the low-concentration region 72 may be shorter than the high-concentration region 71 in the X-axis direction. By providing the low-concentration region 72, the amount of implantable saturate can be further increased from the bottom.

[0104] The thick section 28 is preferably positioned so that it does not overlap with the low-concentration region 72. When the thick section 28 and the low-concentration region 72 are arranged in the Z-axis direction, it is likely that the depletion layer spreading from the top side of the semiconductor substrate 10 will reach the thick section 28. By arranging the thick section 28 and the low-concentration region 72 such that they are offset, the amount of hole implantation from the bottom side can be further increased while preventing the depletion layer from reaching the thick section 28.

[0105] In the X-axis direction, the low-concentration region 72 can be located on the middle side of the transistor section 70 adjacent to the thick section 28. By placing the low-concentration region 72 within the transistor section 70, it is possible to reduce its influence on the properties of the diode section 80. The thick section 28 can be located at either end of the transistor section 70 in the X-axis direction. The low-concentration region 72 can also be located within the transistor section 70 between two thick sections 28. The distance between the low-concentration region 72 and the thick section 28 in the X-axis direction can be less than the width of a mesa section 60 in the X-axis direction. REFERENCE MARK LIST 10 Semiconductor substrate 11 Bathtub area 12 emitter area 14 Basic area 15 Contact area 18 Drift range 19 subpages 20 Buffer area 21 Top 22 Collector area 23 Underside 24 Collector electrode 25 Connecting section 26 Overlap area 27 High Concentration Section 28 thick section 29th section 30 Placeholder trench section 31 edge section 32 Placeholder insulation layer 34 Placeholder ladder section 38 dielectric intermediate layer 39 Section 40 Gate Trench Section 41 edge section 42 Gate insulation layer 44 Gate ladder section 48 gate distributors 51 Gate Contact 52 Emitter electrode 54, 56 Contact hole 60, 61 Mesa section 70 Transistor section 71 High concentration area 72 Low concentration range 80 diode section 82 Cathode area 90 Edge connection structure section 92 top lifetime control section 100 semiconductor devices 102 edge side 120 active section

Claims

Semiconductor device (100) comprising: a semiconductor substrate (10) containing a drift region (18) of a first conductivity type; a transistor section (70) containing an emitter region (12) of a first conductivity type having a higher doping concentration than the drift region (18) in a region in contact with a top surface (21) of the semiconductor substrate (10); a diode section (80) containing a cathode region (82) of a first conductivity type having a higher doping concentration than the drift region (18) in a region in contact with a bottom surface of the semiconductor substrate (10), an overlap region (26) of a second conductivity type in a region other than the cathode region (82), and arranged adjacent to the transistor section (70) in a preset orientation on a top surface (21) of the semiconductor substrate (10); a emitter electrode (52),which is arranged above the semiconductor substrate (10); and a dielectric intermediate layer provided between the semiconductor substrate (10) and the emitter electrode (52) and provided with a contact hole (54) for connecting the emitter electrode (52) and the diode section (80), wherein the cathode region (82) is located closer to a central side of the diode section (80) in the arrangement direction than an end section of the emitter region (12), and the overlap region (26) is provided such that it has a first length between the end section of the emitter region (12) and an end section of the cathode region (82), the cathode region (82) is located closer to the central side of the diode section (80) than an end section of the contact hole (54) in a stretching direction perpendicular to the arrangement direction, and the overlap region (26) is provided such thatthat it has a second length between the end section of the contact hole (54) and the end section of the cathode region (82), and the first length is greater than the second length. Semiconductor device (100) according to claim 1, wherein the first length is five times or more than the second length. Semiconductor device (100) according to claim 1 or 2, wherein the first length is 20 µm or more. Semiconductor device (100) according to one of claims 1 to 3, further comprising: a well region (11) of a second conductivity type, which is arranged side by side with the diode section (80) in the semiconductor substrate (10) in the stretching direction, wherein the overlap region (26) is provided such that it has a third length in the stretching direction between an end section of the well region (11) and the end section of the cathode region (82), and the first length is greater than the third length. Semiconductor device (100) according to claim 4, wherein the first length is twice or more than the third length. Semiconductor device (100) according to one of claims 1 to 5, wherein the diode section (80) has a longitudinal side in the stretching direction in the top side (21) of the semiconductor substrate (10). Semiconductor device (100) according to one of claims 1 to 6, further comprising: a top lifetime control section (92) provided on a side of a top surface (21) of the semiconductor substrate (10), wherein the top lifetime control section (92) is provided in a region in contact with the diode section (80) of the transistor section (70) and the first length in the arrangement direction is greater than a length from an end section of the transistor section (70) to an end section of the top lifetime control section (92). Semiconductor device (100) according to one of claims 1 to 7, wherein the first length at a center of the overlap region (26) in the stretching direction is smaller than the first length at an end section of the overlap region (26) in the stretching direction. Semiconductor device (100) according to one of claims 1 to 8, wherein the transistor section (70) in a region which is in contact with the underside of the semiconductor substrate (10) contains a collector region (22) of a second conductivity type and the overlap region (26) in the arrangement direction contains a section which has a higher doping concentration than the collector region (22). Semiconductor device (100) according to one of claims 1 to 8, wherein the transistor section (70) in a region which is in contact with the underside of the semiconductor substrate (10) includes a collector area (22) of a second conductivity type and the overlap area (26) in the arrangement direction includes a thick section (28) which has a greater thickness in a depth direction of the semiconductor substrate (10) than the collector area (22).

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