METHOD FOR PRODUCING OXIDE-RESISTIVE WORK MEMORY

Abstract

A method for fabricating a semiconductor structure, the method comprising: providing a sacrificial gate structure on a surface of a semiconductor substrate, wherein a first dielectric spacer and a second dielectric spacer laterally surround the sacrificial gate structure; forming a source region and a drain region in the semiconductor substrate and on opposite sides of the sacrificial gate structure, wherein the source region and the drain region have faceted sidewall surfaces; performing a self-limiting etch of the drain region to impart a faceted top surface to the drain region, wherein an interlayer dielectric material protects the source region during the performance of the self-limiting etch; and forming elements of an oxide resistive working memory unit, ReRAM, in contact with the faceted top surface of the drain region.

Description

BACKGROUNDThe present invention relates to a method for manufacturing semiconductor structures comprising an oxide resistive random access memory (ReRAM) that is co-integrated with a drain region of a field effect transistor (FET).Many modern electronic devices include electronic memory. An electronic memory may be a volatile memory or a nonvolatile memory. A non-volatile memory retains its stored data even when no power is supplied, while a volatile memory loses its stored data when power is interrupted. Resistive random access memory (ReRAM or RRAM) is a promising candidate for the next generation of nonvolatile memories due to its simple structure and its compatibility with complementary metal oxide semiconductor (CMOS) logic device fabrication techniques.For oxide ReRAMs, electrical forming of a current conducting filament is required. This method is associated with randomness so that the position of the filament in the oxide ReRAM is not well controlled. This results in higher device voltage and variability when the ReRAM cell is scaled. Further, oxide ReRAMs usually require a current control field effect transistor to form a 1T1R structure (i.e., a transistor, a resistive element). This complicates the process integration. Therefore, cointegration of an FET with an oxide ReRAM in close proximity is required.Some documents have already been published in this technical field. For example, document US 2015 / 0 325 626 A1 describes a nonvolatile memory having a substrate and a find structure, a walk-on structure, a transition layer and a metal layer. The fin rises above the substrate. In addition, first and second source / drain regions are formed as part of the fin. In comparison, document US 2010 / 0 090 289 A 1 describes a semiconductor transistor component and associated manufacturing methods, which are suitable for enabling silicide contacts with an increased effective size in comparison to conventional silicide contacts.Furthermore, document DE 11 2005 001 828 T5 describes planarizing a semiconductor structure for forming replacement metal gates. In this case, provision is made for forming a sacrificial gate structure, removing the sacrificial gate structure, replacing the sacrificial gate structure with a metal gate electrode and covering the metal gate electrode with a nitride layer. Furthermore, document US 2016 / 0 380 190 A1 describes a phase-chance memory cell having a compact structure, which consists, among other things, of an element with variable resistance. Finally, the document US 2014 / 0 084 369 A1 describes a semiconductor component with a doped epitaxial region and corresponding methods for the production thereof. In this case, the epitaxial region is deposited on a substrate by means of a cylindrical deposition-etching process.The object is to create a cointegrated component.SUMMARYThe object is achieved by methods according to independent patent claims 1 and 10.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a cross-sectional view of an example semiconductor structure at an early stage of fabrication, including a plurality of sacrificial gate structures disposed on a surface of a semiconductor substrate, each sacrificial gate structure laterally surrounded by a first dielectric spacer. FIG. 2 is a cross-sectional view of the example semiconductor structure of FIG. 1 after forming a source region and a drain region in the semiconductor substrate and at a base surface of each sacrificial gate structure. FIG. 3 is a cross-sectional view of the example semiconductor structure of FIG. 2 after forming a second dielectric spacer on the first dielectric spacer and then forming an interlayer dielectric (ILD) material layer. FIG. 4 is a cross-sectional view of the example semiconductor structure of FIG. 3 after forming an opening in the ILD material layer that physically exposes a surface of the drain region. FIG. 5 is a cross-sectional view of the example semiconductor structure of FIG. 4 after performing a self-limiting etch in the physically exposed drain region to impart a faceted top surface to the drain region. FIG. 6 is a cross-sectional view of the example semiconductor structure of FIG. 5 after forming a resistive switching layer and a top electrode material in the opening. FIG. 7 is a cross-sectional view of the example semiconductor structure of FIG. 6 after the resistive switching layer and the top electrode material are omitted. FIG. 8 is a cross-sectional view of the example semiconductor structure of FIG. 7 after filling a top portion of the opening with additional ILD material and replacing each sacrificial gate structure with a functional gate structure. FIG. 9 is a cross-sectional view of the example semiconductor structure of FIG. 8 after forming contact structures. FIG. 10 is a cross-sectional view of another exemplary semiconductor structure according to the present application including a ReRAM device including a bottom electrode, a resistive switching liner, and a top electrode.DETAILED DESCRIPTIONThe present application will now be described in more detail by the following description and drawings accompanying the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, therefore, the drawings are not drawn to scale. It is further noted that the same and corresponding elements are denoted by the same reference numerals.In the following description, numerous specific details are described, such as particular structures, components, materials, dimensions, processing steps, and methods, to provide an understanding of the various embodiments of the present application. However, it will be apparent to those skilled in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.It should be noted that when an element such as a layer, region, or substrate is referred to as being "on" or "over" another element, it may be directly disposed on the other element or intervening elements may also be present. On the other hand, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. Further, it should be noted that when an element is referred to as being "below" or "below" another element, it may be disposed directly below or below the other element or intervening elements may be present. On the other hand, when an element is referred to as being "directly below" or "directly below" another element, there are no intervening elements present.FIG. 1 shows an example semiconductor structure according to the present application at an early stage of manufacturing, comprising a plurality of sacrificial gate structures arranged on a surface of a semiconductor substrate 10, each sacrificial gate structure being laterally surrounded by a first dielectric spacer 16. Although a plurality of sacrificial gate structures are described and illustrated, the present application may also be employed when only a single sacrificial gate structure is employed.The semiconductor substrate 10 that can be used according to the present application contains at least one semiconductor material having semiconducting properties. Examples of semiconductor materials that can be used as the semiconductor substrate 10 include, for example, silicon (Si), a silicon germanium (SiGe) alloy, a silicon germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductor, and II / VI compound semiconductor. In one embodiment, the semiconductor substrate 10 is a bulk semiconductor substrate. The term "bulk semiconductor substrate" refers to a substrate that is comprised entirely of one or more semiconductor materials. In one example, the bulk semiconductor substrate is made entirely of Si.In some embodiments, the semiconductor substrate 10 is a semiconductor-on-insulator (SOI) substrate. An SOl substrate usually comprises a handle substrate, an insulator layer and a top semiconductor material layer. In some embodiments, the handle substrate of the SOI substrate may include a semiconductor material as described above. In other embodiments, the handle substrate may be omitted or the handle substrate may be made of a conductive material and / or an insulator material. The insulator layer of the SOI substrate may include a crystalline or non-crystalline dielectric material. In one example, the insulator layer of the SOI substrate may be comprised of silicon dioxide and / or boron nitride. The uppermost semiconductor layer of the SOI substrate is made of a semiconductor material as defined above.Typically, each sacrificial gate structure includes a sacrificial gate material 12 and a sacrificial gate capping material 14. In some embodiments (not shown), each sacrificial gate structure may further include a sacrificial gate dielectric material disposed below the sacrificial gate material 12. In further embodiments, the sacrificial gate structures are comprised entirely of the sacrificial gate material 12.The sacrificial gate structures may be formed from a capping layer (or layers) of a sacrificial material (or different sacrificial materials) and then patterning the sacrificial material (or different sacrificial materials) by lithography and an etch. In an embodiment, the sacrificial gate structures may be formed by first depositing a capping layer of a sacrificial gate dielectric material. The sacrificial gate dielectric material may be an oxide, nitride, and / or oxynitride. In an example, the sacrificial gate dielectric material may be a high-k material having a higher dielectric constant than silicon dioxide. In some embodiments, a multilayer dielectric structure including various dielectric materials, e.g., silicon dioxide, and a high-k dielectric material may be formed and used as the sacrificial gate dielectric material. The sacrificial gate dielectric material may be formed by any deposition method, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition.After forming the sacrificial gate dielectric material capping layer, a sacrificial gate dielectric material capping layer 12 may be formed on the sacrificial gate dielectric material capping layer. The sacrificial gate material 12 may include any material including, for example, polysilicon, amorphous silicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), an alloy of at least two elemental metals, or multi-layer combinations thereof. The sacrificial gate material 12 may be formed using a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or other such deposition processes.After forming the sacrificial gate material capping layer 12, a sacrificial gate capping layer 14 may be formed. The sacrificial gate capping material 14 may include a hard mask material, such as silicon dioxide and / or silicon nitride. The sacrificial gate capping material 14 may be formed by any suitable deposition method, such as chemical vapor deposition or plasma enhanced chemical vapor deposition. The various cap layers of sacrificial materials are then patterned by lithography and etching to provide the sacrificial gate structures on the surface of the semiconductor substrate 10.The first dielectric spacers 16 may be formed by depositing a first dielectric spacer material and then etching the first dielectric spacer material. Illustrative examples of first dielectric spacer materials that may be used in accordance with the present application include, but are not limited to, silicon dioxide, silicon nitride, and silicon oxynitrides. In some embodiments, the first dielectric spacer material (and thus the first dielectric spacers 16) and the sacrificial gate capping material are both made of the same dielectric material, such as silicon nitride. The deposition method that may be used to provide the first dielectric spacer material includes, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD). The etch used to etch the deposited first dielectric spacer material may include a dry etching process, such as reactive ion etching.FIG. 2 shows the example semiconductor structure of FIG. 1 after forming a source region 18S and a drain region 18D in the semiconductor substrate 10 and at a base surface of each sacrificial gate structure. When an SOI substrate is employed, the source region 18S and the drain region 18D are formed in the uppermost semiconductor layer of the SOI substrate. The source region 18S and the drain region 18D may be formed by first performing a self-limiting etch. The term "self-limiting etch" is used throughout the present application to refer to an etch that removes certain levels of a material more quickly than other levels of the same material. For example, a self-limiting etch of silicon removes {100} and / or {110} planes faster than {111} planes. The self-limiting etch may also be referred to herein as crystallographic etching. An example of a self-limiting etch is a sigma etch. Some illustrative examples of etchants that may be used in the self-limiting etch include tetramethylammonium hydroxide (TMAH), ammonia (NH 4 OH), and / or potassium hydroxide (KOH). In the present application, the self-limiting etch provides source / drain trenches (and thus the source region 18S and the drain region 18D) with faceted sidewall surfaces. In one embodiment, the source / drain trenches (and thus the source region 18S and the drain region 18D) are sigma-shaped.Subsequently, doped semiconductor material is formed in each of the source / drain trenches using an epitaxial growth (or deposition) process that provides the source region 18S and the drain region 18D. The terms "epitaxial growth and / or deposition" and "epitaxially grown and / or deposited" mean growth of a semiconductor material on a deposition surface of a semiconductor material in which the grown semiconductor material has the same crystalline properties as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters adjusted so that the deposition atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around the surface and align with the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline properties as the deposition surface on which it is formed.Examples of various epitaxial growth process units that may be used in accordance with the present application include, for example, fast thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature for epitaxial deposition is usually in the range of 550° C. to 900° C. A higher temperature usually leads to a faster deposition, but the faster deposition may lead to crystal defects and layer cracks. Epitaxial growth of the doped semiconductor material may be performed using any well known precursor gas or gas mixture. Carrier gases such as hydrogen, nitrogen, helium and argon may be used.The semiconductor material providing the doped semiconductor material and thus the source region 18S and the drain region 18D may include the same or a different semiconductor material as / than the semiconductor substrate 10. In one example, both the doped semiconductor material and the semiconductor substrate 10 are made of silicon.The doped semiconductor material also includes a dopant, which is usually introduced into the precursor gas that provides the semiconductor material of the source region 18S and the drain region 18D in the epitaxial growth process. The dopant may be a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor that produce a lack of valence electrons. For a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. "n-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. For a silicon-containing semiconductor material, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In an example, the doped semiconductor material providing the source region 18S and the drain region 18D includes silicon or a silicon-germanium alloy having a dopant concentration of 4×10 20 atoms / cm 3 to 3×10 21 atoms / cm 3.FIG. 3 illustrates the example semiconductor structure of FIG. 2 after forming a second dielectric spacer 20 on the first dielectric spacer 16 and then forming an interlayer dielectric (ILD) material layer 22. The ILD material layer 22 surrounds and is present over each sacrificial gate structure and the first and second dielectric spacers (16, 20).The second dielectric spacer 20 may be formed by depositing a second dielectric spacer material and then etching the second dielectric spacer material. In some embodiments, the second dielectric spacer material is made of a different dielectric spacer material than the first dielectric spacer material. In other embodiments, the second dielectric spacer material is made of the same dielectric spacer material as the first dielectric spacer material. Illustrative examples of second dielectric spacer materials that may be used in the present application include, but are not limited to, silicon dioxide, silicon nitride, and silicon oxynitrides. In one embodiment, the first dielectric spacer material (and thus the first dielectric spacers 16) and the sacrificial gate capping material are both made of silicon nitride, while the second dielectric spacer material (and thus the second dielectric spacers 20) is made of silicon dioxide. The deposition method that may be used to provide the second dielectric spacer material includes, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition, or physical vapor deposition (PVD). The etch used to etch the deposited second dielectric spacer material may include a dry etching process, such as reactive ion etching.The ILD material layer 22 may be made of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a low-k chemical vapor deposition (CVD) dielectric layer, or any combination thereof. The term "low-k" as used throughout the present application denotes a dielectric material having a lower dielectric constant than silicon dioxide. In another embodiment, a self-planarizing material, such as a spin-on glass (SOG) or a spin-on low-k dielectric material, such as SiLK™ may be used as the ILD material layer 22. In an embodiment, the ILD material layer may be formed using a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), vapor deposition, or spin-on.FIG. 4 shows the example semiconductor structure of FIG. 3 after forming an opening 26 in the ILD material layer 22 that physically exposes a surface of the drain region 18D. The opening 26 may be formed by first providing a patterned mask 24 on the ILD material layer 22. The patterned mask 24 may include a hard mask material such as silicon nitride. The patterned mask 24 may be formed by depositing a capping layer of the hard mask material and then patterning the capping layer of the hard mask material. Patterning the capping layer of the hard mask material may include an etch, such as a reactive ion etch. This etch or a separate etch may be used to provide the opening 26 in the ILD material layer 22.FIG. 5 illustrates the example semiconductor structure of FIG. 4 after performing a self-limiting etch into the physically exposed drain region 18D. The self-limiting etch used in this step of the present application is the same as that described above. The etched drain region 18D has a faceted top surface 19 defined by a recess formed in the drain region 18D that will provide a peak region for the subsequently formed ReRAM device. After the drain region 18D is self-limiting etched, the patterned mask 24 is removed from the pattern using any material removal process, such as chemical mechanical polishing (CMP). In this step of the present application, the source region 18S is not etched because it is protected by the patterned mask 24 and the ILD material layer 22.FIG. 6 illustrates the example semiconductor structure of FIG. 5 after forming a resistive switching layer 28 and an upper electrode material 30 in the opening 26.When present, the bottom electrode material layer is formed in the opening 26 and a portion of the bottom electrode material layer is in direct physical contact with the faceted top surface of the drain region 16D'. The lower electrode material layer may include, for example, a conductive metal or a conductive metal nitride. The conductive metal that can provide the lower electrode material layer may include at least one metal selected from Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The conductive metal nitride that can provide the lower electrode material layer may include a nitride of at least one metal selected from Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. In an embodiment, the lower electrode material layer is made of TiN or an alloy of TiN and TiAlC. The lower electrode material layer may be formed by a deposition method such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or sputtering. The lower electrode material layer may have a thickness of 2 nm to 10 nm. Other thicknesses are also possible for the lower electrode material layer as long as the lower electrode material layer does not fill the entire opening 26.The resistive switching layer 28 may include an insulating metal oxide. In some embodiments, the insulating metal oxide that provides the resistive switching layer 28 has an energy gap of less than 5 eV. The insulating metal oxide contains at least one insulating material selected from the group consisting of TiO 2, NiO, HfO, HfO 2, ZrO, ZrO 2, Ta 2 O 5, ZnO, WO 3, CoO, and Nb 2 O 5. Although the present application is not limited thereto, and in other embodiments, the energy gap of the resistive switching layer 28 may be adjusted according to an actual requirement. The resistive switching layer 28 may be formed by a deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or sputtering. The resistive switching layer 28 may have a thickness of 2 nm to 10 nm. Other thicknesses are also possible for the resistive switching layer 28 as long as the resistive switching layer 28 does not fill the entire opening 26.The upper electrode material 30 is formed on the surface of the resistive switching layer 28. The upper electrode material 30 contains one of the conductive metals or conductive metal nitrides mentioned above for the lower electrode material layer. In some embodiments, the upper electrode material 30 and the lower electrode material are made of the same conductive metal or conductive metal nitride. In other embodiments, the upper electrode material 30 is made of a different conductive metal or conductive metal nitride than the lower electrode material. In one embodiment, the upper electrode material 30 is made of TiN or an alloy of TiN and TiAlC. The upper electrode material 30 may be formed by a deposition method such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or sputtering. The upper electrode material 30 completely fills the remaining volume of the opening 26.The structure shown in FIG. 6 may be formed by first depositing the various material layers (i.e., optional lower electrode material layer, resistive switching layer 28, and upper electrode material 30) into opening 26 and onto ILD material layer 22, and then using a planarization process to remove optional lower electrode material layer, resistive switching layer 28, and upper electrode material 30 from the top surface of ILD material layer 22.FIG. 7 shows the example semiconductor structure of FIG. 6 after recessing the resistive switching layer 28 and the top electrode material 30 from a top portion of the opening 26 while maintaining a portion of the resistive switching layer 28 and a portion of the top electrode material 30 in a bottom portion of the opening 26.The remaining portion of the resistive switching layer 28 may be referred to as a resistive switching liner 28L and the remaining portion of the upper electrode material 30 may be referred to herein as an upper electrode 30S. In this embodiment, a ReRAM device is provided in the lower portion of the opening 26 that includes an upper portion (i.e., the faceted upper surface 19) of the etched drain region 18D as a lower electrode, the resistive switching liner 28L, and the upper electrode 30S. In some embodiments (see, for example, FIG. 10 ), the ReRAM device includes a deposited lower electrode material layer as the lower electrode, the resistive switching liner 28L, and the upper electrode 30S.In the present application, the resistive switching liner 28L is disposed directly below an entirety of the upper electrode 30S, and the resistive switching liner 28L and the upper electrode 30S have top surfaces coplanar with each other. In embodiments where a lower electrode made of a deposited conductive metal or metal nitride is formed (see, for example, FIG. 10 ), the lower electrode is disposed under the entirety of the resistive switching liner 28L, and the lower electrode, the resistive switching liner 28L, and the upper electrode 30S have top surfaces coplanar with each other.FIG. 8 shows the example semiconductor structure of FIG. 7 after filling the top of the opening 26 with additional ILD material and replacing the sacrificial gate structures 12 with a functional gate structure ( 32, 34). The additional ILD material is usually the same ILD material as the ILD material layer 22.The sacrificial gate structures 12 and, if present, the sacrificial gate capping material 14 are then removed using one or more anisotropic etching processes, such as by reactive ion etching. During this etch, a portion of the ILD material layer 22 (not shown in the cross-sectional views) may be removed prior to removing the sacrificial gate structures 12 and, if present, the sacrificial gate capping material 14. Gate cavities (not shown) are formed by removing the sacrificial gate structures 12 and, if present, the sacrificial gate capping material 14. A functional gate structure (32, 34) is then formed in the gate cavities. By "functional gate structure" is meant a permanent gate structure used to control the output current (i.e., flow of carriers in the channel) of a semiconductor device by electric or magnetic fields.The functional gate structures may include a gate dielectric portion 32 and a gate conductor portion 34. The gate dielectric portion 32 may include a gate dielectric material. The gate dielectric material may be an oxide, nitride and / or oxynitride. In an example, the gate dielectric material may be a high-k material having a higher dielectric constant than silicon dioxide. Exemplary high-k dielectrics include, but are not limited to, HfO 2, ZrO 2, La 2 O 3, Al 2 O 3, TiO 2, SrTiO 3, LaAlO 3, Y 2 O3, HfOxNy, ZrOxNy, La 2 O x N y, Al 2 O x N y, TiO x N y, SrTiO x N y, LaAlOxNy, Y2OxNy, SiON, SiNx, a silicate thereof, and an alloy thereof. Each value of x is independently 0.5 to 3 and each value of y is independently 0 to 2.The gate dielectric material may be formed by any deposition method including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition. In an embodiment of the present application, the gate dielectric material used in the providing may have a thickness in a range of 1 nm to 10 nm. Other thicknesses less than or greater than the aforementioned thickness range may also be used for the gate dielectric material that may provide the gate dielectric portion 32.The gate conductor portion 34 may be made of a gate conductor material. The gate conductor material may include any conductive material including, for example, doped polysilicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), an alloy of at least two elemental metals, a nitride of an elemental metal (e.g., tungsten nitride, aluminum nitride, and titanium nitride), a silicide of an elemental metal (e.g., tungsten silicide, nickel silicide, and titanium silicide), and multi-layered combinations thereof. In an embodiment, the gate conductor portion 34 may include an nFET gate metal. In another embodiment, the gate conductor portion 34 may include a pFET gate metal.The gate conductor material may be formed using a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), and other such deposition processes. When a metal silicide is formed, a conventional silicide method is employed. In an embodiment, the gate conductor material may have a thickness of 50 nm to 200 nm. Other thicknesses less than or greater than the above-mentioned thickness range may also be used for the gate conductor material.The functional gate structure may be formed by providing a functional gate material stack of the gate dielectric material and the gate conductor material. The forming of the functional gate material stack may be followed by a planarization process.FIG. 9 shows the example semiconductor structure of FIG. 8 after forming contact structures, namely a source contact structure 36, a gate contact structure 38 and a ReRAM contact structure 40, which are formed as shown in FIG. 9. The various contact structures (36, 38 and 40) may be formed by first providing contact openings to expose a conductive region (i.e., the source region 18S, the gate conductor portion 34, the top electrode 30S) of the structure. The contact openings may be formed by lithography and etching. Each contact opening is then filled with a / a contact metal or metal alloy. Examples of contact metals include, but are not limited to, tungsten (W), aluminum (Al), copper (Cu), and cobalt (Co). An example of a contact metal alloy is a Cu-Al alloy. The filling of each contact opening with the contact metal or metal alloy / s may be followed by a planarization process. The various contact structures (36, 38, 40) are embedded in the ILD material 22.FIG. 9 shows an example semiconductor structure including an oxide resistive random access memory (ReRAM) unit 52 co-integrated with a drain region 18D of a field effect transistor (FET) 50; the FET has a source region 18S and a functional gate structure (32, 34). The ReRAM device 52 includes a tip region 42 defined by a pointed cone that contacts a faceted top surface 19 of the drain region 18D of the FET 50. The tip portion 42 enhances the electric forming of a current conductive filament of the ReRAM unit 52. As shown, the ReRAM device 52 is laterally adjacent to the functional gate structure (32, 34) and is separated from the functional gate structure (32, 34) by the first dielectric spacer 16 and the second dielectric spacer 20. As further shown, the source region 18S and the drain region 18D are embedded in the semiconductor substrate 10 and each have faceted sidewall surfaces.FIG. 10 illustrates another exemplary semiconductor structure according to the present application, including a ReRAM device 52 including a bottom electrode 27S, a resistive switching liner 28L, and a top electrode 30S. In this embodiment, element 54L refers to a material stack that includes a bottom electrode 27A and resistive switching liner 28L. In this embodiment, the lower electrode 27S is made of a lower electrode deposited material as described above. The exemplary structure of FIG. 10 is fabricated using the same major process steps described above and illustrated in FIGS. 1-9. The exemplary structure of FIG. 10 includes an oxide resistive random access memory (ReRAM) unit 52 that is co-integrated with a drain region 18D of a field effect transistor (FET) 50. The ReRAM device 52 has a tip region 42 that contacts the faceted top surface 19 of the drain region 18D of the FET 50. The tip portion 42 improves the electric forming of a current conductive filament of the ReRAM unit 52. As further shown, the source region 18S and the drain region 18D are embedded in the semiconductor substrate 10 and each have faceted sidewall surfaces.

Claims

A method of manufacturing a semiconductor structure, the method comprising: providing a sacrificial gate structure on a surface of a semiconductor substrate, wherein a first dielectric spacer and a second dielectric spacer laterally surround the sacrificial gate structure; forming a source region and a drain region in the semiconductor substrate and on opposite sides of the sacrificial gate structure, wherein the source region and the drain region have faceted sidewall surfaces; performing a self-limiting etch of the drain region to impart a faceted top surface to the drain region, wherein an interlayer dielectric material layer protects the source region during the performing of the self-limiting etch; and forming elements of an oxide resistive random access memory device, ReRAM, in contact with the faceted top surface of the drain region.The method of claim 1, further comprising, after forming the elements of the ReRAM device, replacing the sacrificial gate structure with a functional gate structure, wherein the functional gate structure comprises a gate dielectric material portion and a gate conductor portion.The method of claim 2, further comprising forming a source contact structure in contact with the source region, a gate contact structure in contact with the gate conductor portion, and a contact structure in contact with a top electrode of the ReRAM device.The method of claim 1, wherein forming the elements of the ReRAM device comprises forming a resistive switching layer and a top electrode material and recessing the resistive switching layer and the top electrode material.The method of claim 1, wherein forming the elements of the ReRAM device comprises forming a bottom electrode layer, a resistive switching layer, and a top electrode material, and recessing the bottom electrode layer, the resistive switching layer, and the top electrode material.The method of claim 1, wherein forming the source region and the drain region comprises performing an etch to provide source / drain trenches in the semiconductor substrate having faceted sidewalls and filling the source / drain trenches with a doped semiconductor material.The method of claim 1, wherein the ReRAM device has a tip region that contacts the faceted top surface of the drain region.The method of claim 1, wherein the self-limiting etch comprises an etchant containing at least one of tetramethylammonium hydroxide, TMAH, ammonia, NH4OH, and potassium hydroxide, KOH.The method of claim 1, wherein performing the self-limiting etching of the drain region comprises: forming an interlayer dielectric material layer laterally surrounding and disposed over the sacrificial gate structure; forming an opening in the interlayer dielectric material layer that physically exposes the drain region; and etching a top surface of the drain region.A method of manufacturing a semiconductor structure, the method comprising: providing a sacrificial gate structure on a surface of a semiconductor substrate, wherein a first dielectric spacer and a second dielectric spacer laterally surround the sacrificial gate structure; forming a source region and a drain region in the semiconductor substrate and on opposite sides of the sacrificial gate structure, wherein the source region and the drain region have faceted sidewall surfaces; Performing a self-limiting etch of the drain region to impart a faceted top surface to the drain region, forming elements of an oxide resistive random access memory, ReRAM, device in contact with the faceted top surface of the drain region, wherein forming the ReRAM device comprises forming at least one resistive switching layer and top electrode material and recessing the resistive switching layer and the top electrode material.

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