SEMICONDUCTOR UNIT

Abstract

Semiconductor unit (101, 102, 103, 104, 105) comprising: - a first frame (7) surrounding an outer periphery of a semiconductor chip (11); and - a second frame (2) surrounding an outer periphery of the first frame (7); wherein the second frame (2) consists of an outer wall (3) surrounding the outer periphery of the first frame (7) and a fibrous reinforcing element (4) for restricting deformation of the outer wall (3) wound on an outer periphery of the outer wall (3), and where the outer wall (3) is arranged to have a polygonal shape as its outer shape and a circular shape as its inner shape.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. STATE OF THE ART

[0002] With increasing operating speeds and improved performance of semiconductor devices, the voltages applied to them are becoming higher than ever before. An increase in the amount of current flowing through the semiconductor device can potentially cause a semiconductor chip within it to fail. Due to a short-circuit current that can flow due to the semiconductor chip failure, the semiconductor chip can melt, causing the interior of the semiconductor device to reach a high temperature.

[0003] This can lead to a rapid increase in air pressure inside the semiconductor device, causing the device to break. To ensure the reliability of a semiconductor device operating at high voltage and large current, it is necessary to prevent a system connected to the semiconductor device from breaking when the semiconductor chip inside the semiconductor device breaks. Therefore, the strength of the semiconductor device needs to be improved.

[0004] Regarding the above requirement for improving the reliability of the semiconductor unit, for example, Patent Document 1 discloses attaching a stretchable protective cover to a case enclosing the semiconductor unit so that fragments of a case possibly generated by the breakage thereof caused by the breakage of the semiconductor chip are intercepted by the protective cover, thereby preventing objects around the semiconductor unit from being broken.

[0005] Furthermore, Patent Document 2 discloses that fibers are contained in a resin frame surrounding a semiconductor chip in a semiconductor unit, thereby preventing breakage of another semiconductor chip in the semiconductor unit without causing a short-circuit breakage. Furthermore, Patent Document 3 discloses such a technique for a concept in which the inner diameter of a ceramic package enclosing a semiconductor unit is reduced to increase the thickness of the package, thereby limiting damage to the exterior of the semiconductor unit due to breakage of a semiconductor element in the semiconductor unit.

[0006] Furthermore, Patent Document 4 discloses a high-performance semiconductor module comprising a housing enclosing at least one semiconductor element and having an explosion-proof element. This explosion-proof element is a protective sheath surrounding at least part of the housing, which catches fragments ejected during an explosion of the semiconductor element. This prevents such fragments from causing injury to persons or neighboring modules. LITERATURE LISTPatent documents Patent Document 1: Japanese Patent Application Laid-Open No. JP 2000-91455A (Sections 0010 to 0018; Fig. 1) Patent Document 2: Japanese Patent Application Laid-Open No. JP 2017 - 84 850 A (Sections 0079 to 0081; Fig. 14) Patent Document 3: Japanese Patent Application Laid-Open No. JP 2016 - 82 105 A (Sections 0017 to 0043; Fig. 2) Patent Document 4: CN 1 246 728 A SUMMARY OF THE INVENTION Problems to be solved by the invention

[0007] In the semiconductor device having the protective enclosure as shown in Patent Document 1, it is possible to contain the fragments of a package generated due to breakage of the semiconductor device caused by melting of the semiconductor chip. However, in the case of a structure in which a plurality of semiconductor devices and components are adjacent to each other, there is a problem that discharge of hot air, etc., may affect the exterior of the semiconductor device, and thus the reliability of such an entire system cannot be ensured.

[0008] Furthermore, there is a problem in that the thickness and inner diameter of the housing enclosing the semiconductor device are subject to dimensional restrictions, and these restrictions may hinder downsizing of the semiconductor device with a view to eliminating the effects of breakage of the housing.

[0009] Further, according to Patent Document 2, when a casing forming a partition between the inside and outside of the semiconductor unit breaks apart, there is a problem that it is difficult to prevent discharge of hot air, etc., caused by melting of the semiconductor chip and to prevent dispersion of a broken internal component from affecting the outside of the semiconductor unit.

[0010] Furthermore, according to Patent Document 3, since the inner diameter and thickness of the ceramic package are subject to dimensional restrictions, there is a problem that an increase in flexibility of a concept for the semiconductor unit and a system partially including the semiconductor unit is prevented, so that it is not possible to meet the demand for downsizing the semiconductor unit.

[0011] The invention discloses a technique for solving such problems as described above, and its object is to provide a semiconductor device in which not only breakage due to a high voltage and a large amount of current is suppressed, thereby achieving an improvement in the reliability of the entire system, but also achieving a downsizing of the semiconductor device. Means to solve the problems

[0012] The object underlying the invention is achieved by a semiconductor purity device having the features of independent patent claim 1. Advantageous developments of the semiconductor purity device according to the invention are specified in dependent claims 2 to 9. Effect of the invention

[0013] According to the invention, due to the arrangement of the second frame configured with the outer wall and the reinforcing member, it is possible not only to suppress breakage due to high voltage and a large amount of current, thereby achieving an improvement in the reliability of the entire system, but also to achieve a downsizing of the semiconductor unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The figures show: Fig. 1 is a longitudinal sectional view showing a configuration of a semiconductor unit according to Embodiment 1; Fig. 2 is a side view showing a configuration of the semiconductor unit according to Embodiment 1; Fig. 3 is a cross-sectional view showing a configuration of the semiconductor unit according to Embodiment 1; Fig. 4 is a side view showing another configuration related to the semiconductor device according to Embodiment 1; Fig. 5 is a plan view showing configuration elements of the semiconductor unit according to Embodiment 1; Fig. 6 is a diagram showing an effect of the semiconductor device according to Embodiment 1; Fig. 7 is a cross-sectional view showing a configuration of a semiconductor unit according to Embodiment 2; Fig. 8 is a cross-sectional view showing a configuration of a semiconductor unit according to Embodiment 3; Fig. 9 is a side view showing a configuration of an outer wall in a semiconductor unit according to Embodiment 4; Fig. 10 is a longitudinal sectional view showing a configuration of a semiconductor unit according to Embodiment 5. TYPES OF REALIZING THE INVENTION

[0015] Embodiments according to the invention will be described in detail below. It should be noted that the embodiments described below do not limit the invention, and the figures used for the description only schematically illustrate the content of the invention, and thus any shape, dimension, or positional relationship is not limited to those in the figures. Embodiment 1

[0016] Embodiment 1 will be described. The semiconductor unit here is a semiconductor unit represented by a power conversion semiconductor unit using at least one semiconductor chip, which is used in, for example, a substation device, that is, a so-called pressure-contact type semiconductor unit having a cover plate on the upper side of the semiconductor chip and a base plate on the lower side of the semiconductor chip; however, the type of semiconductor unit according to the invention is not limited to this.

[0017] The semiconductor chip is located under the cover plate and above the base plate, and is electrically connected to each of the adjacent elements while receiving pressure from a power supply element and an electrode plate arranged on the upper and lower sides of the semiconductor chip, respectively. Furthermore, the semiconductor chip is a power switching element, and such a structure is provided here, in which a plurality of semiconductor chips are separated from each other by means of an inner frame arranged in the semiconductor unit.

[0018] In addition to the power supply element, a signal terminal is arranged on the semiconductor chip to effect current switching. One end of the signal terminal is connected to a signal pad of the semiconductor chip, while the other end is connected to a gate / emitter signal plate arranged under the cover plate. The outer periphery of the inner frame is surrounded by an outer frame, and the outer frame is configured such that an outer wall arranged to surround the inner frame is surrounded by a reinforcing member.

[0019] Furthermore, there may be cases where one semiconductor unit is used, and cases where multiple semiconductor units are used in a stacked manner. Furthermore, in the case of the absence of the inner frame as a component or constituent, a structure in which the semiconductor chips are surrounded by the outer frame is specified.

[0020] Fig. 1 is a longitudinal sectional view showing a configuration of a semiconductor unit 101 according to Embodiment 1. The semiconductor unit 101 includes semiconductor chips 11. The semiconductor chips 11 are each electrically connected to an over-chip electrode plate 9 disposed on the main electrode 10 via a main electrode 10 disposed on the semiconductor chip 11, and the over-chip electrode plate 9 is connected to a power supply member 8 disposed on the over-chip electrode plate 9.

[0021] Furthermore, an under-chip electrode plate 12 is arranged on the lower side of the semiconductor chip 11. The power supply element 8 and the under-chip electrode plate 12 are electrically connected to each other in such a way that they are subjected to pressure by and between a cover plate 5 arranged on the power supply element 8 and a base plate 6 arranged on the lower side of the under-chip electrode plate 12.

[0022] The cover plate 5 and the electrode plate 12 under the chip serve as a collector electrode and an emitter electrode, respectively. When a terminal is pulled out from the semiconductor chip 11, the terminal can be used as a gate terminal. Each semiconductor chip 11 is a semiconductor chip represented by an IGBT (Insulated Gate Bipolar Transistor) or the like. The semiconductor chip 11 is provided with a signal terminal 14 and is connected via a gate / emitter electrode 15 to a gate / emitter signal plate 13 connected to the cover plate 5.

[0023] Further, the respective semiconductor chips 11 and the electrodes, etc., connected to the semiconductor chips 11 are spatially separated from each other by an inner frame 7 as a first frame formed of a thermosetting resin such as an epoxy resin, a polyimide resin, or the like, or a thermoplastic resin such as PPS (polyphenylene sulfide), PET (polyethylene terephthalate), PBT (polybutylene terephthalate), or the like.

[0024] To improve the insulating property, the interior of the semiconductor unit 101 is sealed with a sealing agent or sealing material 16 formed of an electrically insulating gas, a silicone gel, or the like. The material and filling ratio of the sealing agent or sealing material 15 can be arbitrarily determined. Furthermore, an outer frame 2 as a second frame is arranged on the outer periphery of the inner frame 7. The outer frame 2 is configured with an outer wall 3 and a reinforcing member 4, such as a fiber.

[0025] Fig. 2 is a side view showing a configuration of the semiconductor unit 101 according to Embodiment 1 of the invention. The semiconductor unit 101 has a configuration whose periphery is surrounded by the outer frame 2, and the outer wall 3 as a configuration element of the outer frame 2 is surrounded by the reinforcing member 4. The reinforcing member 4 is wound on the outer periphery of the outer wall 3 to ensure its fracture resistance with respect to the direction in which the fragments generated due to a short-circuit fracture of the semiconductor chip 11 are scattered.

[0026] This serves to limit deformation of the outer wall 3, which may be caused by scattering of the fragments of the semiconductor chip 11, due to the reinforcing member 4, thereby preventing the outer wall 3 from causing breakage. According to this configuration, it is possible to effectively achieve an improvement in the fracture strength of the semiconductor device.

[0027] It should be noted that the winding width, the winding direction and the winding pitch for the reinforcing element 4 as well as the force for the winding can be arbitrarily determined in ranges that have no effect on the operation of the semiconductor unit, as long as they are sufficient to restrict the deformation of the outer wall 3, thereby achieving an effect of preventing the outer wall 3 from breaking apart.

[0028] Furthermore, the number of turns can be arbitrarily determined, and from a similar point of view, the reinforcing member 4 can be wound in a multi-layered manner around the outer wall 3. When the reinforcing member 4 is wound in a multi-layered manner, the constraining effect for preventing deformation of the outer wall 3 can be enhanced.

[0029] As through Fig. 4, the reinforcing member 4 may further be processed into a fabric having structural strength, thereby enhancing the restraining effect against deformation of the outer wall 3 that may be caused by breakage. Furthermore, the shape of the reinforcing member 4 surrounding the outer wall 3 may be arbitrarily determined, and the reinforcing members 4 having different shapes and different materials may overlap to surround the outer wall 3, thereby meeting a desired impact resistance.

[0030] Fig. 3 is a cross-sectional view along an arrow AA of the Fig. 1 according to Embodiment 1 of the invention. The inner frame 7 surrounds at least one semiconductor chip 11, and, as can be seen from Fig. 5, which is shown as a plan view of the inner frame 7 and the outer frame 2, the semiconductor chips 11, the electrode plates 9 above the chip, the electrode plates 12 below the chip and respective components associated with them are arranged in the inner frame 7, and the sealing means or sealing material 16 is sealed therein as previously described.

[0031] When the semiconductor chip 11 in the thus-configured semiconductor unit 101 experiences a short circuit, an overcurrent flows in the semiconductor chip 11, thereby significantly increasing the temperature inside the inner frame 7 as the semiconductor chip 11 melts. As the temperature inside the inner frame 7 increases, the pressure of a closed area inside the inner frame 7 rapidly increases, thereby creating a risk that the inner frame 7 may break apart.

[0032] Assuming that one of the mutually separated semiconductor chips 11 is short-circuited, causing the inner frame 7 to break apart, in order to prevent the inner frame 7 from being affected by this break apart, the inner frame may have a structure that improves shock resistance, for example, a structure that includes fibers in this frame. However, it is difficult to completely prevent the break apart from being affected by the break apart on the exterior of the semiconductor unit, as well as by using only the inner frame, which is subject to restrictions on a design of the semiconductor unit to ensure a reduced size, an electrically insulating property, or the like.

[0033] As in Fig. 1 to Fig. 3, the outer frame 2 is arranged outside the inner frame 7, so that breakage of the inner frame separating the inside and outside of the semiconductor unit 101 is restricted and the exterior of the semiconductor unit is prevented from being affected by the breakage even if the inner frame is broken.

[0034] The invention is intended to prevent damage to the exterior of the semiconductor device due to the breakage of the inner frame. If the inner frame breaks due to the failure of the semiconductor chip 11, fragments of the inner frame 7 may splash toward the outer frame 2; however, these fragments are intercepted by the outer wall 3 forming the semiconductor device 101, which is formed of a polymer material having a higher impact resistance than that used for the inner frame 7. Here, the "polymer material" means one having a molecular weight of ten thousand or more.

[0035] As the material used for the inner frame 7, the aforementioned thermosetting resin or thermoplastic resin is adopted, while the polymeric material used for the outer wall 3, in order to withstand a momentary impact caused at the time of breakage of the inner frame 7, has impact resistance and impact absorption higher than those of the material used for the inner frame 7 constituting the semiconductor unit 101.

[0036] Furthermore, after the inner frame 7 breaks due to an increase in pressure inside the inner frame 7 caused by melting of the semiconductor chip 11, such an increase in pressure also affects the exterior of the inner frame 7, and this may cause deformation of the outer wall 3; however, the deformation of the outer wall is restricted by the reinforcing member 4, which is formed of a polymeric material having a fracture strength higher than that of the material used for the outer wall 3, so that the increased pressure is not concentrated locally on the outer wall 3, and thus, breakage of the outer wall 3 does not occur.

[0037] Accordingly, it is possible to prevent the exterior of the outer frame 2 from being affected by the breakage, so that units such as another semiconductor unit, a cooling unit, etc., or portions thereof arranged adjacent to the semiconductor unit 101 can be protected.

[0038] It should be noted that the materials used for the inner frame 7, the outer wall 3 and the reinforcing member 4 described above can be determined using a selection method in which properties of materials to be used for the respective components or constituents are compared.

[0039] Fig. 6 is a diagram illustrating an effect caused when the semiconductor unit 101 according to Embodiment 1 of the invention is used. When the semiconductor chip 11 in the semiconductor unit 101 cracks and melts, the temperature and pressure inside the semiconductor unit 101 increase. Since the semiconductor unit 101 has a closed structure, an increase in the pressure inside the semiconductor unit 101 causes a structural object surrounding the semiconductor chip 11, for example, the inner frame 7, to break apart, so that fragments 26 splash out in a direction toward the outside of the semiconductor unit 101.

[0040] Since the outer wall 3 is formed of a material having a shock resistance higher than that of the material used for the inner frame 7 constituting the semiconductor unit 101 and thus having a high load-bearing capacity, it is possible to intercept the projecting splashing fragments 26 without allowing them to pass through this wall.

[0041] It should be noted again that due to an increase in pressure, deformation of the outer wall 3 may occur. If the deformation occurs and is locally significant, the increased pressure is concentrated there, resulting in a fracture originating from a region of this deformation. According to the invention, the reinforcing element 4 is arranged outside the outer wall 3, which has a fracture strength higher than that of the material used for the outer wall 3. This prevents the occurrence of such local deformation, and thus prevents deterioration of the exterior of the semiconductor device due to the breakage of the inner frame 7.

[0042] When only the surrounding outer wall 3 of the semiconductor unit 101 is used, the outer wall 3 breaks apart due to deformation due to an increase in the internal pressure of the semiconductor unit 101 caused by melting of the semiconductor chip 11. Furthermore, when the outer wall 3 is not attached and the reinforcing member 4 is not used as a protective covering for intercepting the fragments 26 of the inner frame 7 through the outer wall 3, the reinforcing member 4 breaks due to the fragments 26 of the inner frame 7 splashing out due to the breakage of the inner frame 7. As described above, no significant effect is achieved when one of the outer wall 3 and the reinforcing member 4 is used alone; however, combining multiple structures thereof in the above manner enables improvement in impact resistance.

[0043] Therefore, in a system configured to include the semiconductor unit 101 of the invention as part of the whole, due to the effects described above, it becomes easier to make the system sufficiently redundant to enable the system to operate as a whole even if the semiconductor unit 101 itself has failed.

[0044] Furthermore, the upper and lower sides of the semiconductor unit 101 are pressed in a sandwich-like manner by the cover plate 5 and the base plate 6 to thereby make pressure contact with these plates, so that ejection of hot air, etc. in a vertical direction of the semiconductor unit 101 caused by the breakage does not affect the exterior of the semiconductor unit 101.

[0045] In the pressure-contact type semiconductor unit 101, respective elements in the semiconductor unit 101 can be electrically connected to each other without using a bonding wire or the like. In this case, since no bonding wire is used for electrical connection, there is no wire bonding portion in the semiconductor unit 101 that can cause thermal fatigue, and thereby an effect of improving the heat resistance of the semiconductor unit is achieved. However, as with a semiconductor unit of another type, such as a package type, respective elements in the semiconductor unit can also be electrically connected, for example, by using a bonding wire or the like.

[0046] Furthermore, the outer frame 2 has a structure that restricts deformation of the outer wall 3 by means of the reinforcing member 4 to thereby withstand the increase in pressure inside the semiconductor unit 101 caused by melting of the semiconductor chip 11, so that it is not necessary to design the outer wall 3 itself to have a dimension, such as a thickness or the like, that does not allow the outer wall to break apart.

[0047] Thus, if the outer wall 3 is designed to have a thickness that allows deformation of the outer wall 3, causing it to split, the outer frame 2 will not cause it to split because the reinforcing member 4 restricts the splitting of the outer wall 3. This effect allows the outer frame 2 to be downsized while maintaining its impact resistance, thus improving the design flexibility of the entire system.

[0048] Furthermore, the dimensions and shapes of the semiconductor unit 101 to which the outer frame 2 is applied are not limited. That is, since the outer wall 3 and the reinforcing members 4 are highly processable, there is no limitation on the thickness of the outer wall 3 and the length of the reinforcing member 4, so whether or not to use the outer frame 2 is not determined by the number of semiconductor chips 11 constituting the semiconductor unit 101 and the magnitude of the voltage applied to the semiconductor unit 101. The outer wall 3 and the reinforcing member 4 can be designed to have dimensions adapted to the energy involved in the semiconductor unit 101 at the time of melting and the dimension of the semiconductor unit 101.A portion of the outer periphery of the semiconductor unit 101 is surrounded by the outer wall 3, which is formed of a polymer material with high shock resistance to momentary shock. Further, as the material forming the outer wall, an ultra-high molecular weight polyethylene resin is preferred, which is superior to other polymer materials in terms of shock resistance to momentary shock. Here, "ultra-high molecular weight" means a molecular weight of one million or more.

[0049] Further, the outer wall 3 is surrounded by the reinforcing member 4 made of a polymer material with high tensile strength, thereby forming the outer frame 2. Examples of the polymer material with high tensile strength to be used for the reinforcing member 4 include, for example, polyamide, a modified polyphenylene ether, and the like. However, as the material constituting the reinforcing member 4, ultra-high molecular weight polyethylene fibers are preferred, which are superior to other polymer materials in tensile strength.

[0050] In this way, the outer periphery of the inner frame 7 is surrounded by the outer frame 2, improving impact resistance. The ultra-high molecular weight polyethylene resin has very low water absorption capacity, making it a material that does not absorb water. Accordingly, moisture is prevented from entering the semiconductor device, making it possible to prevent deterioration of the semiconductor device due to water absorption.

[0051] Furthermore, the ultra-high molecular weight polyethylene resin is superior in wear resistance, so that it can be expected to achieve an extended lifetime and improved reliability of the semiconductor device 101 when the ultra-high molecular weight polyethylene resin is used as the material for the outer wall 3.

[0052] However, the elements of the semiconductor unit 101 are formed from a variety of materials, and thus, due to the difference in thermal expansion between the respective materials, repeated stresses occur in the semiconductor unit 101, where heat is generated during its operation. The ultra-high molecular weight polyethylene fiber used for the reinforcing member 4 is superior in fatigue resistance and can thus ensure high fracture strength even when the aforementioned stresses are repeatedly encountered, so that an extended service life of the semiconductor unit 101 can be expected.

[0053] In particular, the exemplary polymeric materials shown in the aforementioned embodiment, such as an ultra-high molecular weight polyethylene resin used for the outer wall 3 and ultra-high molecular weight polyethylene fibers used for the reinforcing member 4, are characterized by being lighter than ceramics, compactly sintered inorganic materials, and metals. This enables not only downsizing of the semiconductor device but also designing a lightweight structure.

[0054] Furthermore, the ultra-high molecular weight polyethylene fiber is a material with high fatigue resistance, and thus it does not break easily even if an increase in temperature and an increase in pressure in the semiconductor device repeatedly occur under the use conditions of the semiconductor device, so that the achievement of improved reliability of the semiconductor device can be expected.

[0055] The above-mentioned ultra-high molecular weight polyethylene resin used for the outer wall 3 has been used for a bulldozer blade and a bulletproof plate against large bullets, and the ultra-high molecular weight polyethylene fibers used for the reinforcing member 4 are fibers that have been used for ropes for yachts, fishing lines for very large fish such as spearfish, or the like, and are materials suitable for achieving the effects of the invention.

[0056] Although the inner frame 7 is formed of a material having electrical insulation properties, such as a thermoplastic resin or a thermosetting resin, which were exemplified above, it is conceivable that the material and shape of the inner frame 7 are not as specified above, and that the semiconductor unit is the one that does not include the inner frame 7, although this depends on the type of embodiment. However, using the inner frame 7 makes it possible to separate the respective semiconductor chips 11 from each other, thereby more effectively preventing deterioration of the exterior of the semiconductor unit 101 due to breakage due to breakage and melting of the semiconductor chip 11.

[0057] The cover plate 5 and the base plate 6 are formed of electrically conductive substances, and examples of materials for the cover plate 5 and the base plate 6 include molybdenum. These plates make uniform pressure contact with the semiconductor chips 11 from the upper and lower sides, so that the semiconductor chips 11 are electrically connected to the cover plate 5 and the base plate 6.

[0058] A gaseous insulating material or a solid insulating material is used as the sealing agent or sealing material 16. When a gaseous sealing material is used as the sealing agent or sealing material 16, an inert gas is filled into the semiconductor device, thereby hermetically sealing it. This prevents corrosion of the respective electrode plates, etc., so that a prolonged lifespan of the semiconductor device 101 can be expected. When a solid sealing agent or sealing material, such as a silicone gel, is used as the sealing agent or sealing material 16, shock resistance is further improved because air is less likely to expand around the semiconductor chip 11.

[0059] To reduce the extent of deformation of the outer wall 3, it is recommended to avoid a gap between the outer wall 3 and the reinforcing member 4. To achieve this, it is assumed that an adhesive is applied to the reinforcing member 4, thereby adhering it to the outer wall 3. However, how the reinforcing member is to be attached to the outer wall can be arbitrarily determined, and it is convenient if the outer wall 3 and the reinforcing member 4 are attached to each other without creating a gap between them.

[0060] As described above, the semiconductor device 101 according to Embodiment 1 includes the inner frame 7 surrounding the outer periphery of the semiconductor chip 11; and the outer frame 2 surrounding the outer periphery of the inner frame 7; the outer frame 2 is configured with the outer wall 3 surrounding the outer periphery of the inner frame 7 and the fibrous reinforcing member 4 wound on the outer periphery of the outer wall 3. Thus, it is possible to not only suppress breakage due to high voltage and a large amount of current, thereby achieving an improvement in the reliability of the entire system, but also achieve a downsizing of the semiconductor device.

[0061] Furthermore, the shape of the outer frame 2 can be designed arbitrarily. Regarding the design of the entire system partially including the semiconductor unit according to the invention, units such as a cooling unit and a power source, which, if damaged, may affect the operation of the entire system, or parts thereof, circuits, or the like, can be located near the semiconductor unit, thus further enhancing the design flexibility of the entire system. Embodiment 2

[0062] In Embodiment 1, a case is described in which the outer frame 2 is arranged whose cross section is rectangular, while in Embodiment 2, a case is described in which an outer frame is arranged whose cross section is circular.

[0063] Fig. 7 is a cross-sectional view showing a configuration of a semiconductor unit 102 according to Embodiment 2. As in Fig. As shown in Figure 7, an outer frame 2 is arranged in a cylindrical shape in the semiconductor unit 102. The outer frame 2 is configured with a cylindrical outer wall 3 surrounding the inner frame 7 and a fibrous reinforcing member 4 wound around the cylindrical outer wall 3. The material forming the outer wall 3 is a polymer material with good moldability, for example, an ultra-high molecular weight polyethylene resin, and thus can form any predetermined shape.

[0064] The other configuration of the semiconductor unit 102 according to Embodiment 2 is similar to that of the semiconductor unit 101 of Embodiment 1, and thus the same reference numerals are given to the equivalent portions, so that a description thereof is omitted.

[0065] As described above, according to the semiconductor unit 102 according to Embodiment 2, the outer frame 2 is arranged in a cylindrical shape, so that it is possible to achieve an improvement in shock resistance and fracture resistance. Embodiment 3

[0066] In Embodiment 1 and Embodiment 2, cases are described in which the thickness of the outer wall 3 is uniform, while in Embodiment 3, a case is described in which a specific portion of the outer wall 3 is made thicker than the other portion.

[0067] Fig. 8 is a cross-sectional view showing a configuration of a semiconductor unit 103 according to Embodiment 3. As in Fig. As shown in FIG. 8, an outer wall 3 is arranged in an outer frame 2 of the semiconductor unit 103 to have a rectangular shape as its outer shape and a circular shape as its inner shape. This results in a configuration in which corner portions of the outer wall 3 are made thicker than the other portions. The other configuration of the semiconductor unit 103 according to Embodiment 3 is similar to that of the semiconductor unit 101 according to Embodiment 1, and thus, the same reference numerals are given to the equivalent portions, and a repeated description thereof will be omitted.

[0068] If the outer and inner peripheries of the outer wall 3 form polygonal shapes similar to each other, there is a risk that a shock wave and its reflection wave will concentrate at the corner portion at the time of breakage, resulting in a fracture originating from the corner portion. Furthermore, if the outer and inner peripheries of the outer wall 3 form circular shapes similar to each other, the fracture strength of the outer wall is improved because the shock wave and the reflection wave are uniformly reflected. However, the semiconductor device forms a circular cylinder, so an unnecessary gap may be enlarged.

[0069] Thus, with a configuration in which corner portions are made thicker as described above, it is possible to design the outer frame 2 so that it will not break apart when stress concentrations occur at the corner portions in the polygonal shape of the outer wall 3 due to the internal pressure of the semiconductor device 103 caused by melting of the semiconductor chip 11. Accordingly, due to the shape of the outer frame 2, it becomes easier to design a semiconductor device in which a useful effect can be achieved in terms of its shock resistance and its design.

[0070] As described above, according to the semiconductor device 103 according to Embodiment 3, the outer wall 3 is arranged to have a polygonal shape as the outer shape and a circular shape as the inner shape. Thus, even if the contour of the outer frame is polygonal, it is possible to prevent cracking due to stress concentration at the corner portions, thereby achieving an improvement in impact resistance. Embodiment 4

[0071] In Embodiments 1 to 3, cases are described in which the reinforcing member 4 is wound along an outer surface of the outer wall 3, while in Embodiment 4, a case is described in which a reinforcing member is wound along grooves arranged in the outer wall 3.

[0072] Fig. 9 is a side view showing a configuration of an outer wall 3 in a semiconductor unit 104 according to Embodiment 4. As in Fig. As shown in Figure 9, grooves 17 for attaching the reinforcing member 4 are formed on the outer surface of the outer wall 3 according to an outer frame 2 of the semiconductor unit 104. When the reinforcing member 4 is appropriately wound into the grooves 17 thus formed, the reinforcing member 4 is more firmly attached to the outer wall 3 than when the reinforcing member 4 is wound around the outer wall 3 in which no groove is formed.

[0073] The other configuration of the semiconductor unit 104 according to Embodiment 4 is similar to that of the semiconductor unit 101 according to Embodiment 1, and thus the same reference numerals are given to the equivalent portions, so that a repeated description thereof is omitted.

[0074] Due to an increase in the internal pressure of the semiconductor unit 104 caused by melting of the semiconductor chip 11, the outer wall 3 in the semiconductor unit 104 is deformed to locally generate a bulge. If the increased pressure is concentrated at the aforementioned local bulge, the outer wall 3 may cause breakage from this bulge. However, if the reinforcing member 4 is appropriately wound into the grooves 17 of the outer wall 3 as described above, the reinforcing member 4 is firmly attached to the outer wall 3, thus preventing the local bulge from forming in the outer wall and the pressure from concentrating thereon to cause the outer wall to break apart.

[0075] This improves the durability of the semiconductor device with respect to breakage. Such an outer frame surrounding a semiconductor device can be used not only for the semiconductor device to be downsized, but also as a structure to withstand increased pressure.

[0076] As described above, according to the semiconductor device 104 according to Embodiment 4, the grooves 17 along which the reinforcing member 4 is wound into the grooves in a suitable manner are arranged in the outer wall 3. Thus, the reinforcing member is firmly attached to the outer wall 3, preventing the outer wall from breaking apart, thereby achieving an improvement in durability. Embodiment 5

[0077] In Embodiments 1 to 4, cases are described where the semiconductor unit is of a pressure contact type, while in Embodiment 5, a case is described where the semiconductor unit is the one in which electrical connections are formed using bonding wires or the like.

[0078] Fig. 10 is a longitudinal sectional view showing a configuration of a semiconductor unit 105 according to Embodiment 5. As in Fig.As shown in Figure 10, an outer frame 2 is arranged according to the semiconductor unit 105 as a second frame surrounding not only its lateral side portion but also its front side portion. A base plate 6 is arranged on the rear side of the semiconductor unit 105, and a metal plate 22 is bonded to the base plate 6 using solder 23. Furthermore, an insulating layer 21 is bonded to the top surface of the metal plate 22, thereby forming an insulating plate 24.

[0079] Another metal plate 22 is bonded to the top surface of the insulating plate 24 using solder 23, and the semiconductor chips 11 are stacked on the metal plate 22. The semiconductor chips 11 are connected to a terminal 27 and the metal plate 22 by bonding wires 25. One end of the terminal 27 is located outside the outer frame 2, which is formed of an outer wall 3 and a reinforcing member 4, and thus the terminal 27 is configured to enable wiring for the semiconductor unit from the outside.

[0080] Further, a lateral peripheral region around the semiconductor chips 11 is surrounded by a case 20 as a first frame formed of a thermosetting resin such as an epoxy resin, a polyimide resin, or the like, or a thermoplastic resin such as PPS, PET, PBT, or the like. The outer periphery of the case 20 is surrounded by the outer frame 2 configured with the outer wall 3 and the reinforcing member 4. Furthermore, on the upper side of the semiconductor chips 11, a cover 19 is also arranged as a first frame, and the cover 19 is surrounded by the outer frame 2 configured with the outer wall 3 and the reinforcing member 4.

[0081] To improve the insulating property, a sealant or sealing material 16 is sealingly disposed in the housing 20, or the sealant or sealing material 16 is filled therein. Here, the material and filling ratio of the sealant or sealing material 16 can be arbitrarily determined. Note that the solder 23 as an adhesive may be replaced with sintered silver or a liquid-phase diffusion material whose melting temperature is higher than that of the solder to enable the semiconductor device 105 to operate at high temperatures.

[0082] As described above, according to the invention, not only in the case of a semiconductor unit according to Embodiment 1 having a pressure contact type, but also in the case of a semiconductor unit in which electrical connections are formed using bonding wires or the like, it is possible to prevent deterioration of the exterior of the semiconductor unit due to breakage of internal components caused by melting of the semiconductor chip 11 because of the provision of the outer frame 2 configured with the outer wall 3 and the reinforcing member 4. Accordingly, whether or not to employ the outer frame 2 should not be determined depending on the shape of the semiconductor unit, so the semiconductor unit may have any shape.

[0083] As described above, according to the semiconductor unit 105 according to Embodiment 5, even if the semiconductor unit is not of a pressure-contact type but a semiconductor unit in which electrical connections are formed using bonding wires or the like, it is possible to prevent the fragments of a component constituting the semiconductor unit from scattering to the outside of the semiconductor unit because of the arrangement of the outer frame 2 configured with the outer wall 3 and the reinforcing member 4. Thus, it is possible to achieve not only an improvement in the reliability of the entire system but also a downsizing of the semiconductor unit.

[0084] It should be noted that in the above embodiments, cases are described in which frames are used as a shock-resistant structure in the case where a component breaks due to an increase in pressure inside the semiconductor unit caused by melting of the semiconductor chip 11, but even in the case where the component does not break, the frames can of course be used as a structure that can withstand the increase in pressure inside the semiconductor unit.

[0085] In accordance with the invention, a variety of exemplary embodiments and examples are described; however, any feature, configuration, or function described in one or more embodiments is not limited to applying to a specific embodiment, and may also apply singularly or in any of various combinations to another embodiment.

[0086] Accordingly, it is contemplated that a non-limiting number of modified examples not exemplified herein are within the technical scope disclosed in the present specification. For example, such cases include when at least one configuration element is modified; when any configuration element is added or omitted; and further, when at least one configuration element is removed and combined with a configuration element of another embodiment. DESCRIPTION OF REFERENCE SIGNS AND SYMBOLS 2 outer frame (second frame) 3 exterior wall 4 Reinforcing element 7 inner frame (first frame) 11 semiconductor chip 101 semiconductor unit 102 semiconductor unit 103 semiconductor unit 104 semiconductor unit 105 semiconductor unit

Claims

[1] Semiconductor unit (101, 102, 103, 104, 105) comprising the following: - a first frame (7) that surrounds an outer perimeter of a semiconductor chip (11); and - a second frame (2) that surrounds an outer perimeter of the first frame (7); wherein the second frame (2) consists of an outer wall (3) surrounding the outer perimeter of the first frame (7) and a fibrous reinforcing element (4) for limiting deformation of the outer wall (3), which is wound around an outer perimeter of the outer wall (3), and where the outer wall (3) is arranged such that it has a polygonal shape as its outer form and a circular shape as its inner form. [2] Semiconductor unit (101, 102, 103, 104) according to claim 1, wherein the semiconductor chip (11) is subjected to pressure by a cover plate and a base plate and between them, such that contact and electrical connection are established with a front electrode and a rear electrode for the semiconductor chip (11). [3] Semiconductor unit (101) according to claim 1 or claim 2, wherein the outer wall (3) consists of a material having an impact resistance and an impact absorption capacity that are higher than those of the first frame (7). [4] Semiconductor unit (101) according to any one of claims 1 to 3, wherein the reinforcing element (4) consists of a material having a tensile strength higher than that of the outer wall (3). [5] Semiconductor unit (101) according to one of claims 1 to 4, wherein the outer wall (3) and the reinforcing element (4) consist of polymeric materials. [6] Semiconductor unit (101) according to any one of claims 1 to 5, wherein the outer wall (3) consists of an ultra-high molecular weight polyethylene resin. [7] Semiconductor unit (101) according to any one of claims 1 to 5, wherein the reinforcing element (4) consists of an ultra-high molecular weight polyethylene fiber. [8] Semiconductor unit (104) according to one of claims 1 to 7, wherein grooves are formed in the outer wall (3) along which the reinforcing element (4) is wound into the grooves in a suitable manner. [9] Semiconductor unit (102) according to any one of claims 1 to 8, wherein the second frame (2) is arranged in a cylindrical shape.

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