Time-to-digital converter

Abstract

Time-to-digital converter (100, 100a or 100b), comprising: an input terminal (101) into which a first signal and a second signal are input at different times; a phase information providing unit (110) including an inverter element (110+M) having an inverter delay time τ, wherein the phase information providing unit (110) outputs a plurality of digital signals, each of the digital signals having a phase different from each other, the phase shift being an amount corresponding to the inverter delay time τ; a first flip-flop group (121) comprising first to N-th D-type flip-flop circuits (121-1, 121-2, ... and 121-N), where N is a natural number equal to or greater than 2; a first to (N-1)th delay element (130-1, 130-2, ... and 130-N-1), each of the delay elements providing a time delay that is (N+1) / N times the inverter delay time τ; and a calculation unit (150) that calculates a time interval between a point of inputting the first signal and another point of inputting the second signal from the value output from each of the Q terminals of the first to N-th D-type flip-flop circuits (121-1, 121-2, ... and 121-N), wherein one of the digital signals corresponding to the first flip-flop group (121) is input to all of the D terminals of the first to N-th D-type flip-flop circuits (121-1, 121-2, ...and 121-N) in the first flip-flop group (121), a C terminal of the second D-type flip-flop circuit (121-2) in the first flip-flop group (121) is connected to one end of a first delay element (130-1), a C terminal of the first D-type flip-flop circuit (121-1) in the first flip-flop group (121) is connected to the other end of the first delay element (130-1), the other end of the first delay element (130-1) is connected to the input terminal (101), and, when N, the number of flip-flop circuits in the first flip-flop group (121), is equal to or greater than 3, for each J, a natural number from 2 to N-1, the C terminal of the (J+1)-th D-type flip-flop circuit (121-J+1) in the first flip-flop group (121) is connected to one end of the J-th delay element (130-J), and one end of the (J-1)-th delay element (130-J-1) is connected to the other end of the J-th delay element (130-J).

Description

TECHNICAL FIELDThe present disclosure relates to a time-to-digital converter.PRIOR ARTTime-to-digital converters acquire phase information on phases between individual delay elements connected in series at each of times at which two signals are input, and calculate the time interval between the two input signals from the phase difference between the two signals, the phase difference being indicated by the acquired phase information.The resolution of time-to-digital converters is determined from the inverter delay time τ of the inverter elements used. In a case where a time-to-digital converter is a typical converter without circuit redundancy, the minimum resolution of the time-to-digital converter is τ. By shortening the gate lengths of the transistors used, the time-to-digital converter is provided with a lower resolution. However, in a case where the gate lengths of the transistors are already minimum, for example, transistors manufactured by finer semiconductor processing must be used for the time-to-digital converter.To solve this problem, Patent Literature 1 discloses a time-to-digital converter having two delay chains each having a plurality of delay elements connected in series to delay a first signal input to one of the delay chains by 1 / 2τ and acquire a phase difference between the individual delay elements, thereby improving the resolution.MHIRI, Mongia [et al.]: A new hybrid TDC based on GRO-pseudo delay architecture with fractional code and wide time range detection for divisorless ADPLL, In: Analog Integrated Circuits and Signal Processing Vol. 93 (2017), No. 2, pp. 265-275, https: / / doi.org / 10.1007 / s10470-017-1032-1 describes a time-to-digital converter for a fully digital phase locked loop.JP 2014-120 901 A describes a time-to-digital converter.WO 2012 / 066 700 A1 describes a frequency synthesizer and a time-to-digital converter.LIST OF ReferencesPATENT LITERATUREPatent Literature 1: JP 2012-100 252 ASUMMARY OF THE INVENTIONTECHNICAL TASKHowever, a problem of the time-to-digital converter described in Patent Literature 1 is that the circuit size increases because a plurality of delay elements are required for each of the delay chains.The present disclosure is to solve the above problem, and therefore, an object of the present disclosure is to provide a time-to-digital converter that can improve resolution in measurements of the time interval between a first signal and a second signal without increasing the circuit size.SOLUTION OF PROBLEMA time-to-digital converter according to the present disclosure includes: an input terminal to which a first signal and a second signal are input at a different time; a phase information supply unit including an inverter element having an inverter delay time τ, the phase information supply unit outputting a plurality of digital signals, each of the digital signals having a phase different from each other, the phase shift being an amount corresponding to the inverter delay time τ; a first flip-flop group including first to N-th D-type flip-flop circuits, where N is a natural number equal to or greater than 2; a first to (N-1)-th delay elements, the delay elements each providing a time delay that is (N+1) / N times the inverter delay time τ; and a computing unit that computes a time interval between a point of inputting the first signal and another point of inputting the second signal from the value output from each of the Q terminals of the first to N-th D-type flip-flop circuits.One of the digital signals corresponding to the first flip-flop group is input to all the D terminals of the first to N-th D-type flip-flop circuits in the first flip-flop group. The C terminal of the second D-type flip-flop circuit in the first flip-flop group is connected to one end of the first delay element. The C terminal of the first D-type flip-flop circuit in the first flip-flop group is connected to the other end of the first delay element. The other end of the first delay element is connected to the input terminal. When N, the number of flip-flops in the first flip-flop group, is equal to or greater than 3, for each J, a natural number of 2 to N-1, the C terminal of the (J+1)-th D-type flip-flop circuit in the first flip-flop group is connected to one end of the J-th delay element, and one end of the (J-1)-th delay element is connected to the other end of the J-th delay element.ADVANTAGEOUS EFFECTS OF THE INVENTIONAccording to the present disclosure, resolution in measurements of the time interval between the first signal and the second signal can be improved without increasing the circuit size.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a diagram showing an example of the configuration of a main part of a time-to-digital converter according to Embodiment 1. FIG. 2 is timing charts showing an example of temporal changes of digital signals output from a phase information supply unit in the time-to-digital converter shown in FIG. 1, and the timings of a first signal and a second signal input to the C terminal of each D-type flip-flop circuit. FIG. 3 is a diagram showing an example of the configuration of a main part of a time-to-digital converter according to Embodiment 2. FIG. 4 are timing charts showing an example of temporal changes of digital signals output from a phase information supply unit in the time-to-digital converter shown in FIG. 3, and the timings of a first signal and a second signal input to the C terminal of each D-type flip-flop circuit. FIG. 5 is a diagram showing an example of the configuration of a main part of a time-to-digital converter including only one flip-flop group.DESCRIPTION OF EMBODIMENTSEmbodiments of the present disclosure will be explained in detail below with reference to the drawings.Embodiment 1.A time-to-digital converter 100 according to Embodiment 1 will be explained with reference to FIGS. 1 and 2.An example of the configuration of a main part of the time-to-digital converter 100 according to Embodiment 1 will be explained with reference to FIG. 1.FIG. 1 is a diagram showing an example of the configuration of the main part of the time-to-digital converter 100 according to Embodiment 1.The time-to-digital converter 100 according to Embodiment 1 includes an input terminal 101, a phase information supply unit 110, five flip-flop groups 121, 122, 123, 124, and 125, a single delay element 130- 1, a wave number measurement unit 140, and an arithmetic unit 150.The time-to-digital converter 100 according to Embodiment 1 is an example in which the time-to-digital converter includes the first to fifth five flip-flop groups 121, 122, 123, 124, and 125.The number of flip-flop groups included in the time-to-digital converter 100 is not limited to five. The number of flip-flop groups may be four or less, six or more, or any number as long as it is two or more. In other words, the time-to-digital converter 100 may have first to M-th (M is a natural number equal to or greater than 2) M flip-flop groups.The time-to-digital converter 100 shown in FIG. 1 is, for example, one in which each of the first to fifth five flip-flop groups 121, 122, 123, 124, and 125 includes different two D-type flip-flop circuits. The different two D-type flip-flop circuits are a first D-type flip-flop circuit 121- 1, 122- 1, 123- 1, 124- 1 or 125- 1 and a second D-type flip-flop circuit 121- 2, 122- 2, 123- 2, 124- 2 or 125- 2.In the time-to-digital converter 100, the number of D-type flip-flop circuits in each of the first to fifth flip-flop groups 121, 122, 123, 124, and 125 is not limited to two, and may be three or more. The number of D-type flip-flop circuits in a group may be arbitrary as long as it is two or more. In other words, the time-to-digital converter 100 may include first to M-th M flip-flop groups, each of the M flip-flop groups including different first to N-th N-D type flip-flop circuits, where N is a natural number equal to or greater than 2.The time-to-digital converter 100 shown in FIG. 1 is an example in which the phase information supply unit 110 includes a ring oscillator including first to fifth five inverter elements 111, 112, 113, 114, and 115. The phase information supply unit 110 shown in FIG. 1 generates first to fifth digital signals, each of the digital signals having a phase different from each other, the phase shift being an amount corresponding to an inverter delay time τ of each of the first to fifth inverter elements 111, 112, 113, 114, and 115, and outputs the generated first to fifth digital signals. In the time-to-digital converter 100 shown in FIG. 1, the respective signals input to the first to fifth inverter elements 111, 112, 113, 114, and 115 including the phase information supply unit 110 are output as the first to fifth digital signals.The number of inverter elements in the phase information supply unit 110, the phase information supply unit 110 being composed of a ring oscillator, is not limited to five. The number of inverter elements may be four or less, six or more, or any as long as the phase information supply unit 110 includes one or more inverter element(s) for respectively delaying an input signal by the inverter delay time τ, and outputting digital signals, each of the digital signals having a phase different from each other, the phase shift being an amount corresponding to the inverter delay time τ, the number of digital signals being the same as the number of flip-flop groups included in the time-to-digital converter 100. In other words, in a case where the number of flip-flop groups is M and the phase information supply is achieved by a ring oscillator, the phase information supply unit 110 may include first to M-th M inverter elements whose respective time delays are the predetermined time. In a case where the phase information supply unit 110 is composed of a ring oscillator, it is apparent that the number of inverter elements in the phase information supply unit 110 is odd.In addition, the phase information supply unit 110 is not limited to such a unit that is composed of a ring oscillator. Specifically, for example, the phase information supply unit 110 may be a unit that uses a digital signal input from an unillustrated digital signal oscillator or the like and has a predetermined period, thereby outputting digital signals, each of the digital signals having a phase different from each other by an amount corresponding to the inverter delay time τ, the number of digital signals being the same as the number of flip-flop groups included in the time-to-digital converter 100.In other words, in the case where the time-to-digital converter 100 includes M flip-flop groups, the phase information supply unit 110 may be a unit including first to (M-1)-th M-1 inverter elements and outputting first to M-th M digital signals, each of the digital signals having a phase different from each other by an amount corresponding to the predetermined time that is the inverter delay time τ.The time-to-digital converter 100 shown in FIG. 1 is an example in which the first to fifth digital signals output from the phase information supply unit 110 are respectively input to the D terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 and the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2, each D-type flip-flop circuit belonging to the corresponding group among the first to fifth flip-flop groups 121, 122, 123, 124, and 125.The time-to-digital converter 100 is not limited to a converter consisting of five flip-flop groups. The time-to-digital converter 100 may be a converter including a phase information supply unit 110 that outputs the same number of digital signals as the number of flip-flop groups in the time-to-digital converter 100. Therefore, it is possible to consider the case where the time-to-digital converter 100 includes M flip-flop groups. The time-to-digital converter 100 may be a converter in which, for each K, a natural number of 1 to M, the K-th digital signal among the plurality of digital signals output from the phase information supply unit 110 is input to the D terminals of the first to N-th D-type flip-flops in the K-th flip-flop group.Specifically, in the case where the time-to-digital converter 100 includes M flip-flop groups and each of the M flip-flop groups includes different N D-type flip-flop circuits, the time-to-digital converter 100 is configured as follows.The time-to-digital converter 100 includes first to (M-1)th M-1 inverter elements whose respective time delays are the predetermined time.Each of the D terminals of the first to N-th D-type flip-flops in the second flip-flop group 122 is connected to one end of the first inverter element 111.Each of the D terminals of the first to N-th D-type flip-flops in the first flip-flop group 121 is connected to the other end of the first inverter element 111.When M, the number of flip-flop groups, is equal to or greater than 3, for each L, a natural number of 2 to M-1, each of the D terminals of the first to N-th D-type flip-flop circuits in the (L+1)-th flip-flop group is connected to one end of the L-th inverter element.When M, the number of flip-flop groups, is equal to or greater than 3, for each L, a natural number of 2 to M-1, one end of the (L-1)-th inverter element is connected to the other end of the L-th inverter element.In addition, in a case where the number of flip-flop groups is M and the phase information supply is achieved by a ring oscillator, the time-to-digital converter 100 has the following configuration in addition to the above configuration.The phase information supply unit 110 has, in addition to the above-mentioned M-1 inverter elements, an M-th inverter element whose time delay is the predetermined time.One end of the M-th inverter element is connected 111 to the other end of the first inverter element.The other end of the M-th inverter element is connected to one end of the (M-1)-th inverter element.With the above configuration, the phase information supply unit 110 can output first to M-th M digital signals, each of the digital signals having a phase different from each other by an amount corresponding to the inverter delay time τ of each of the first to M-th inverter elements, by outputting, as the digital signals, one of the signals input to the first to M-th inverter elements or the signals output from the first to M-th inverter elements.Since the time-to-digital converter 100 shown in FIG. 1 is an example in which each of the first to fifth flip-flop groups 121, 122, 123, 124, and 125 includes different first and second two D-type flip-flop circuits, the time-to-digital converter includes the first single delay element 130- 1.The number of delay elements 130- 1 included in the time-to-digital converter 100 is not limited to one, and the number may be at least equal to the result of subtraction of 1 from the number of D-type flip-flop circuits in a flip-flop group. In other words, in the case where the first to fifth flip-flop groups 121, 122, 123, 124, and 125 include different first to N-th N D-type flip-flop circuits, the time-to-digital converter 100 may include first to (N-1)-th N-1delay elements connected in series.For example, since the time-to-digital converter 100 illustrated in FIG. 1 is one in which each of the first to fifth flip-flop groups 121, 122, 123, 124, and 125 includes different first and second two D-type flip-flop circuits, the first delay element 130- 1 is configured to provide a time delay that is 3 / 2 times the inverter delay time τ of each of the first to fifth inverter elements 111, 112, 113, 114, and 115 included in the phase information supply unit 110.The delay time set at the first delay element 130- 1 is not limited to 3 / 2 times the inverter delay time τ. The delay time is determined from the number of D-type flip-flop circuits in a flip-flop group included in the time-to-digital converter 100.Specifically, in the case where each of the first to fifth flip-flop groups 121, 122, 123, 124, and 125 included in the time-to-digital converter 100 includes different N D-type flip-flop circuits, the delay time provided by each of the first to (N-1)thdelay elements may be (N+1) / N times the predetermined time. More specifically, in the case where the first to fifth flip-flop groups 121, 122, 123, 124, and 125 included in the time-to-digital converter 100 include different N D-type flip-flop circuits, the delay time provided by each of the first to (N-1)thdelay elements may be (N+1) / N times the inverter delay time τ of each of the first to fifth inverter elements 111, 112, 113, 114, and 115 included in the phase information providing unit 110.The time-to-digital converter 100 shown in FIG. 1 is an example in which each of the C terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 is connected to one end of the first delay element 130- 1, and each of the C terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 is connected to the other end of the first delay element 130- 1.In the time-to-digital converter 100, the number of flip-flop groups is not limited to five, and the number of D-type flip-flop circuits in one flip-flop group is not limited to two. In the case where the time-to-digital converter 100 includes M flip-flop groups and each of the M flip-flop groups includes different N D-type flip-flop circuits, the time-to-digital converter 100 may be one in which each of the C terminals of the second D-type flip-flop circuits in the first to M-th flip-flop groups is connected to one end of the first delay element 130- 1, each of the C terminals of the first D-type flip-flop circuits in the first to M-th flip-flop groups is connected to the other end of the first delay element 130- 1, and when N, the number of D-type flip-flop circuits in a flip-flop group is equal to or greater than 3 in each of the flip-flop groups for each J, a natural number of 2 to N-1, the C terminal of the (J+1)-th D-type flip-flop circuit may be connected to one end of the J-th delay element.The wave number measurement unit 140 shown in FIG. 1 receives the fifth digital signal output from the phase information supply unit 110, and measures the wave number of the first digital signal. The digital signal to which the wave number measurement unit 140 performs measurement of the wave number is not limited to the fifth digital signal. Any one of the plurality of digital signals may be selected for measurement of the wave number.The arithmetic unit 150 shown in FIG. 1 is connected to each of the Q terminals and the wave number measurement unit 140, the Q terminals being terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 and the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2, the D-type flip-flop circuits being circuits of the first to fifth flip-flop groups 121, 122, 123, 124, and 125.In the time-to-digital converter 100, the number of flip-flop groups is not limited to five, and the number of D-type flip-flop circuits in one flip-flop group is not limited to two. In the case where the time-to-digital converter 100 includes M flip-flop groups and each of the M flip-flop groups includes different N D-type flip-flop circuits, the arithmetic unit 150 may be connected to each of the Q terminals of the first to N-th D-type flip-flop circuits in each of the first to M-th flip-flop groups.The arithmetic unit 150 calculates the time interval between a point at which the first signal is input to the input terminal 101 and a point at which the second signal is input to the input terminal 101 from the value output from each of the Q terminals of the first to N-th D-type flip-flop circuits in each of the first to M-th flip-flop groups.The arithmetic unit 150 may calculate the time interval between the first signal and the second signal input to the input terminal 101 from both the value output from each of the Q terminals and the wave number of the digital signal, where Q terminals are terminals of the first to N-th D-type flip-flop circuits in each of the first to M-th flip-flop groups, and the wave number is measured by the wave number measurement unit 140.By configuring the arithmetic unit 150 so that the arithmetic unit calculates the time interval between the first signal and the second signal from among both the value output from each of the Q terminals of the D-type flip-flop circuits and the wave number of the digital signal measured by the wave number measurement unit 140, the time-to-digital converter 100 can measure the time interval between the first signal and the second signal without increasing the circuit size even when the time interval between the first signal and the second signal is longer than the period of a digital signal output from the phase information supply unit 110, such as the first digital signal.The operation of the time-to-digital converter 100 shown in FIG. 1 is explained with reference to FIG. 2.FIG. 2 are timing charts showing an example of temporal changes of the digital signals output from the phase information supply unit 110 in the time-to-digital converter 100 shown in FIG. 1, and the timings of the first signal and the second signal input to the C terminal of each D-type flip-flop circuit.A timing chart illustrated in an upper row of FIG. 2 shows temporal changes of the first to fifth digital signals input to the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125. A timing chart illustrated in a lower row of FIG. 2 further shows temporal changes of the first to fifth digital signals input to the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125.For example, since the time-to-digital converter 100 shown in FIG. 1 is composed of a ring oscillator including the first to fifth inverter elements 111, 112, 113, 114, and 115, the states of the first to fifth digital signals shown in FIG. 2 change in one of the first to fifth digital signals each time the inverter delay time τ expires.Next, a case where the first and second signals are input to the input terminal 101 at a time interval of 1 / 2τ from the times shown in the timing chart of the upper row of FIG. 2 will be explained.When the first signal is input to each of the C terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 at the time shown in the timing chart in the upper row of FIG. 2, the states of the first to fifth digital signals are 0, 1, 0, 1, and 1, respectively (hereinafter, expressed by a 5-bit digital value such as "01011"). Therefore, the values output from the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 become 0, 1, 0, 1, and 1 (hereinafter, expressed by a 5-bit digital value such as "01011").For example, in the case where reset is performed so that the initial values output from the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 are all set to 0, the arithmetic unit 150 may acquire the time at which the first signal is input in accordance with the change from "00000" to "01011" of the values output from the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125.Subsequently, the second signal is input after 1 / 2τ has elapsed since the input of the first signal. Since the states of the first to fifth digital signals are "01011", when the second signal is input to each of the C terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 at the time shown in the timing chart in the upper row of FIG. 2, the values output from the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 become "01011". Since the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 output "01011" when the first signal is input, the arithmetic unit 150 cannot acquire the time at which the second signal is input from the values output from the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125.Each of the first and second signals is input to each of the C terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125, and at a time shown in the timing chart in the lower row of FIG. 2, each of the first and second signals being delayed by 3 / 2τ by the first delay element 130- 1.When the first signal is input to each of the C terminals of the second D-type flip-flops 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 at the time shown in the timing chart in the lower row of FIG. 2, the values output from the Q terminals of the second D-type flip-flops 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 become "01010".For example, in the case where reset is performed such that the initial values output from the Q terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 are all set to 0, the arithmetic unit 150 may acquire the time at which the first signal is inputted in accordance with the change from "00000" to "01010" of the values output from the Q terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125.Subsequently, the second signal is input after 1 / 2τ has elapsed since the input of the first signal. When the second signal is input to each of the C terminals of the second D-type flip-flops 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 at the time shown in the timing chart in the lower row of FIG. 2, the values output from the Q terminals of the second D-type flip-flops 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 become "11010".Since the Q terminals of the second D-type flip-flops 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flops 121, 122, 123, 124, and 125 output "01010" when the first signal is input, the arithmetic unit 150 can acquire the time at which the second signal is input in accordance with the change from "01010" to "11010" of the values output from the Q terminals of the second D-type flip-flops 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flops 121, 122, 123, 124, and 125.The arithmetic unit 150 calculates the time interval between the first signal and the second signal from the value output from each of the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 and the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125.In the example shown in FIG. 2, the arithmetic unit 150 determines that the interval time between the first signal and the second signal is less than 2τ from the change from "01010" to "11010" of the values output from the Q terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125. Further, since the arithmetic unit 150 cannot acquire the time at which the second signal is input from the value output from each of the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125, the arithmetic unit also calculates the time interval between the first signal and the second signal by determining that the time interval between the first signal and the second signal is less than τ.Since the first and second signals are input to each of the C terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125, the first and second signals being delayed by 3 / 2τ with respect to the input to each of the C terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121, 122, 123, 124, and 125 by the first delay element 130- 1, the arithmetic unit 150 can acquire the times at which the first and second signals are input, if the time interval between the first signal and the second signal is equal to or greater than 1 / 2τ. More specifically, the time-to-digital converter 100 may measure the time interval between the first signal and the second signal at a resolution of 1 / 2τ in the case where each of the first to fifth flip-flop groups 121, 122, 123, 124, and 125 includes different two D-type flip-flop circuits. In addition, in this case, the time-to-digital converter 100 may measure the time interval between the first signal and the second signal with a measurement error of 1 / 2τ.Embodiment 2.A time-to-digital converter 100 according to Embodiment 2 will be explained with reference to FIGS. 3 and 4.The time-to-digital converter 100 according to Embodiment 2 is one in which each of the first to fifth flip-flop groups 121, 122, 123, 124, and 125 includes different three D-type flip-flops, while the time-to-digital converter 100 according to Embodiment 1 is one in which each of the first to fifth flip-flop groups 121, 122, 123, 124, and 125 includes different two D-type flip-flops.An example of the configuration of a main part of the time-to-digital converter 100 according to Embodiment 2 will be explained with reference to FIG. 3.FIG. 3 is a diagram showing an example of the configuration of the main part of the time-to-digital converter 100 according to Embodiment 2.The same components as those of the time-to-digital converter 100 according to Embodiment 1 are denoted by the same reference numerals in the configuration of the time-to-digital converter 100 according to Embodiment 2, and repeated explanation of the components will be omitted below. More specifically, explanation of the components illustrated in FIG. 3 denoted by the same reference numerals as those described in FIG. 1 will be omitted below.The time-to-digital converter 100 aaccording to Embodiment 2 includes an input terminal 101, a phase information supply unit 110, five flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a, two delay elements 130- 1 and 130- 2, a wave number measurement unit 140, and an arithmetic unit 150 a.The time-to-digital converter 100 aaccording to Embodiment 2 is an example in which the time-to-digital converter includes first to fifth five flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a.The time-to-digital converter 100 amay include first to Mth M flip-flop groups.The time-to-digital converter 100 ashown in FIG. 3 is, for example, one in which each of the first to fifth five flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aincludes different three D-type flip-flop circuits. The different three D-type flip-flop circuits are the first D-type flip-flop circuit 121- 1, 122- 1, 123- 1, 124- 1 or 125- 1, the second D-type flip-flop circuit 121- 2, 122- 2, 123- 2, 124- 2 or 125- 2, and third D-type flip-flop circuit 121- 3, 122- 3, 123- 3, 124- 3 or 125- 3.The time-to-digital converter 100 amay be a converter in which each of the first to Mth M flip-flop groups includes different first to Nth D-type flip-flop circuits.The time-to-digital converter 100 ashown in FIG. 3 is an example in which the phase information supply unit 110 is made up of a ring oscillator including first to fifth five inverter elements 111, 112, 113, 114, and 115. Since the phase information supply unit 110 according to Embodiment 2 is the same as the phase information supply unit 110 according to Embodiment 1, explanation will be omitted below.The time-to-digital converter 100 aillustrated in FIG. 3 is, for example, one in which the first to fifth digital signals output from the phase information supply unit 110 are input to the respective D terminals, D terminals being terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1, the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2, and the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3, the D-type flip-flop circuits being circuits of the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124a and 125a.In a case where the time-to-digital converter 100 aincludes M flip-flop groups, the time-to-digital converter 100 amay be a converter in which the K-th digital signal output from the phase information supply unit 110 is input to each of the D terminals of the first to N-th D-type flip-flops in the K-th flip-flop group.Since the configuration of the time-to-digital converter 100 ais explained in Embodiment 1 in the case where the time-to-digital converter 100 aincludes M flip-flop groups and each of the M flip-flop groups includes different N D-type flip-flop circuits, explanation of the configuration will be omitted below.For example, since the time-to-digital converter 100 ashown in FIG. 3 is one in which each of the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aincludes different first to third three D-type flip-flop circuits, the time-to-digital converter 100 aincludes first and second two delay elements 130- 1 and 130- 2 connected in series.In the case where the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 ainclude different first to N-th D-type flip-flop circuits, the time-to-digital converter 100 amay include first to (N-1)-th N-1 delay elements connected in series.For example, since the time-to-digital converter 100 ashown in FIG. 3 is one in which each of the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aincludes different first to third three D-type flip-flop circuits, the first delay element 130- 1 and the second delay element 130- 2 are configured to provide a delay time that is 4 / 3 times the inverter delay time τ of each of the first to fifth inverter elements 111, 112, 113, 114, and 115 in the phase information supply unit 110.In the case where the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aincluded in the time-to-digital converter 100 ainclude different N D-type flip-flop circuits, the delay time provided by each of the first to (N-1)thdelay elements may be (N+1) / N times a predetermined time. More specifically, in the case where the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aincluded in the time-to-digital converter 100 ainclude different N D-type flip-flop circuits, the delay time provided by each of the first to (N- 1)thdelay elements may be (N+1) / N times the inverter delay time τ of each of the first to fifth inverter elements 111, 112, 113, 114, and 115 in the phase information providing unit 110.The time-to-digital converter 100 ashown in FIG. 3 is, for example, one in which each of the C terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 is connected to one end of the second delay element 130- 2, each of the C terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 is connected to one end of the first delay element 130- 1, and each of the C terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 is connected to the other end of the first delay element 130- 1. The above-mentioned first, second and third D-type flip-flop circuits belong to the first to fifth flip-flop groups 121a, 122a, 123a, 124a and 125a.In the case where the time-to-digital converter 100 aincludes M flip-flop groups and each of the M flip-flop groups includes different N D-type flip-flop circuits, the time-to-digital converter 100 amay be one in which each of the C terminals of the second D-type flip-flop circuits is connected to one end of the first delay element 130- 1, each of the C terminals of the first D-type flip-flop circuits is connected to the other end of the first delay element 130- 1, and when N, the number of flip-flop circuits in a flip-flop group is equal to or greater than 3, each of the C terminals of the (J+1)-th D-type flip-flops is connected to one end of the J-th delay element 130-J. The above-mentioned first, second and (J+1)-th D-type flip-flop circuits belong to the first to M-th flip-flop groups.The arithmetic unit 150 ashown in FIG. 3 is connected to each of the Q terminals and the wave number measurement unit 140, the Q terminals being terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1, the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2, and the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3, the first to third D-type flip-flop circuits being circuits of the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a.In the case where the time-to-digital converter 100 aincludes M flip-flop groups and each of the M flip-flop groups includes different N D-type flip-flop circuits, the arithmetic unit 150 amay be connected to each of the Q terminals of the first to N-th D-type flip-flop circuits in each of the first to M-th flip-flop groups. Further, in the case where the time-to-digital converter 100 aincludes M flip-flop groups and each of the M flip-flop groups includes different N D-type flip-flop circuits, the arithmetic unit 150 amay be connected to the wave number measurement unit 140 in addition to the connection to each of the Q terminals of the first to N-th D-type flip-flop circuits in each of the first to M-th flip-flop groups.The arithmetic unit 150 acalculates the time interval between a first signal and a second signal input to the input terminal 101 from a value output from each of the Q terminals of the first to N-th D-type flip-flop circuits in each of the first to M-th flip-flop groups.The arithmetic unit 150 amay calculate the time interval between the first signal and the second signal input to the input terminal 101 from both the value output from each of the Q terminals and the wave number of a digital signal, where Q terminals are terminals of the first to N-th D-type flip-flop circuits in each of the first to M-th flip-flop groups, and the wave number is measured by the wave number measurement unit 140.The operation of the time-to-digital converter 100 ashown in FIG. 3 will be explained with reference to FIG. 4.FIG. 4 are timing charts showing an example of temporal changes of the digital signals output from the phase information supply unit 110 in the time-to-digital converter 100 ashown in FIG. 3 and the timings of the first signal and the second signal input to the C terminal of each D-type flip-flop circuit.A timing chart shown in an upper row of FIG. 4 shows temporal changes of the first to fifth digital signals input to the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a. Further, a timing chart shown in a middle line of FIG. 4 shows temporal changes of the first to fifth digital signals input to the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a. Further, a timing chart in the lower row of FIG. 4 shows temporal changes of the first to fifth digital signals input to the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a.For example, since the time-to-digital converter 100 ashown in FIG. 3 is composed of the ring oscillator including the five inverter elements 111, 112, 113, 114, and 115, the states of the first to fifth digital signals shown in FIG. 4 change in one of the first to fifth digital signals each time the inverter delay time τ expires.Next, a case will be explained in which the first and second signals, with the time interval therebetween being 1 / 3τ, are input to the input terminal 101 at times shown in the timing chart in the upper row of FIG. 4.When the first signal is input to each of the C terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aat the time shown in the timing chart in the upper row of FIG. 4, the values output from the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 abecomes "01011".For example, in the case where reset is performed such that the initial values output from the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aare all set to 0, the arithmetic unit 150 amay acquire the time at which the first signal is input in accordance with the change from "00000" to "01011" of the values output from the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123a, 124a and 125a.Next, the second signal is input after 1 / 3τ has elapsed since the input of the first signal. When the second signal is input to each of the C terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aat the time shown in the timing chart in the upper row of FIG. 4, the values output from the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 abecomes "01011".Since the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aoutput "01011", when the first signal is input, the arithmetic unit 150 cannot acquire the time at which the second signal is input from the value output from each of the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a.Each of the first and second signals is input to each of the C terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aat timings shown in the time chart in the middle row of FIG. 4, each of the first and second signals being delayed by 4 / 3τ by the first delay element 130- 1.When the first signal is input to each of the C terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aat the time shown in the time chart in the middle row of FIG. 4, the values output from the Q terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 abecomes "01010".For example, in the case where reset is performed so that the initial values output from the Q terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aare all set to 0, the arithmetic unit 150 amay acquire the time at which the first signal is input in accordance with the change from "00000" to "01010" of the values output from the Q terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123a, 124a and 125a.Next, the second signal is input after 1 / 3τ has elapsed since the input of the first signal.When the second signal is input to each of the C terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aat the time shown in the time chart in the middle row of FIG. 4, the values output from the Q terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 abecomes "01010".Since the Q terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aoutput "01010" when the first signal is input, the arithmetic unit 150 cannot acquire the time at which the second signal is input from the value output from each of the Q terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a.Each of the first and second signals is input to each of the C terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aat timings shown in the timing chart in the lower row of FIG. 4, and each of the first and second signals is delayed by 8 / 3τ by the first and second delay elements 130- 1 and 130- 2.When the first signal is input to each of the C terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aat the time shown in the timing chart in the lower row of FIG. 4, the values output from the Q terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 abecomes "11010".For example, in the case where reset is performed so that the initial values output from the Q terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aare all set to 0, the arithmetic unit 150 amay calculate the time at which the first signal is input in accordance with the change from "00000" to "11010" of the Q terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 aand 125 a.Next, the second signal is input after 1 / 3τ has elapsed since the input of the first signal.When the second signal is input to each of the C terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aat the time shown in the timing chart in the lower row of FIG. 4, the values output from the Q terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 abecomes "10010".Since the Q terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aoutput "11010" when the first signal is input, the arithmetic unit 150 can acquire the time at which the second signal is input in accordance with the change from "11010" to "10010" of the values output from the Q terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a.The arithmetic unit 150 acalculates the time interval between the first signal and the second signal from the value output from each of the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1, the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2, and the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a.In the example shown in FIG. 4, the arithmetic unit 150 adetermines that the time interval between the first signal and the second signal is less than 2τ from the change from "01010" to "11010" of the values output from the Q terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a. Since the arithmetic unit 150 acannot acquire the time at which the second signal is input using the time from each of the Q terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a, the arithmetic unit determines that the time interval between the first signal and the second signal is less than τ. Further, since the arithmetic unit 150 acannot acquire the time at which the second signal is input from the value output from each of the Q terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a, the arithmetic unit calculates the time interval between the first signal and the second signal by determining that the time interval between the first signal and the second signal is less than 2 / 3τ.The first and second signals are input to each of the C terminals of the second D-type flip-flop circuits 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a, the first and second signals being delayed by 4 / 3τ with respect to the input to each of the C terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aby the first delay element 130- 1. Further, the first and second signals are input to each of the C terminals of the third D-type flip-flop circuits 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a, and the first and second signals are delayed by 8 / 3τ with respect to the input to each of the C terminals of the first D-type flip-flop circuits 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aby the first delay element 130- 1.Since the first and second signals are input to each of the C terminals of the first D-type flip-flops 121- 1, 122- 1, 123- 1, 124- 1, and 125- 1, the second D-type flip-flops 121- 2, 122- 2, 123- 2, 124- 2, and 125- 2, and the third D-type flip-flops 121- 3, 122- 3, 123- 3, 124- 3, and 125- 3 in the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a, the arithmetic unit 150 acan acquire the times at which the first and second signals are input if the time interval between the first signal and the second signal is equal to or greater than 1 / 3τ. More specifically, in the case where each of the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aincludes different three D-type flip-flop circuits, the time-to-digital converter 100 acan measure the time interval between the first signal and the second signal at a resolution of 1 / 3τ. In addition, in this case, the time-to-digital converter 100 may measure the time interval between the first signal and the second signal with a measurement error of 1 / 3τ.As explained in Embodiments 1 and 2, in the case where each of the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aincludes different two D-type flip-flop circuits, the time-to-digital converter 100 can measure the time interval between the first signal and the second signal with a resolution of 1 / 2τ. Further, in the case where each of the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aincludes different three D-type flip-flop circuits, the time-to-digital converter 100 acan measure the time interval between the first signal and the second signal at a resolution of 1 / 3τ.In the case where each of the first to fifth flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 aincludes different N D-type flip-flop circuits, the time-to-digital converter 100 or the time-to-digital converter 100 acan measure the time interval between the first signal and the second signal at a resolution of 1 / Nτ in the same manner as in Embodiment 1 or 2.As mentioned above, the time-to-digital converter 100 or the time-to-digital converter 100 ais configured such that the time-to-digital converter includes: the input terminal 101 to which first and second signals are input at a different time, the signals being digital signals; the phase information supply unit 110 outputting a digital signal; the first to Mth M flip-flop groups each including different first to Nth D-type flip-flop circuits; and the first to (N-1)th delay elements connected in series, each of the delay elements providing a delay time longer than a predetermined time. The phase information supply unit 110 outputs first to M-th digital signals, each of the digital signals having a phase different from each other by an amount corresponding to the predetermined time. The K-th digital signal output from the phase information supply unit 110 is input to each of the D terminals of the first to N-th D-type flip-flop circuits in the K-th flip-flop group. Each of the C terminals of the second D-type flip-flop circuits in the first to Mth flip-flop groups is connected to one end of the first delay element 130- 1. Each of the C terminals of the first D-type flip-flop circuits in the first to M-th flip-flop groups is connected to the other end of the first delay element 130- 1. When N, the number of D-type flip-flops in a flip-flop group, is equal to or greater than 3, each of the C terminals of the (J+1)-th D-type flip-flops in the first to M-th flip-flops is connected to one end of the J-th delay element 130- 1.With the configuration described above, the time-to-digital converter 100 or the time-to-digital converter 100 acan improve the resolution in measurements of the time interval between the first signal and the second signal without increasing the circuit size.Further, the time-to-digital converter 100 or the time-to-digital converter 100 ais configured so that each of the first to (N-1)thdelay elements provides a time delay equivalent to (N+1) / N times the predetermined time.With the configuration described above, the time-to-digital converter 100 or the time-to-digital converter 100 acan improve the resolution in measurements of the time interval between the first signal and the second signal to 1 / N times the predetermined time without increasing the circuit size.Further, the time-to-digital converter 100 or the time-to-digital converter 100 ais configured such that the time-to-digital converter includes: the phase information supply unit 110 including the first to (M-1)th inverter elements whose respective time delays are the predetermined time, wherein the phase information supply unit 110 outputs the first to Mth M digital signals, each of the digital signals having a phase different from each other by an amount corresponding to the inverter delay time τ of each of the first to (M-1)th inverter elements by outputting, as digital signals, one of signals input to the first to (M-1)th inverter elements or signals, which are output from the first to (M-1)th inverter elements.With the configuration described above, the time-to-digital converter 100 or the time-to-digital converter 100 acan improve the resolution up to 1 / N times the inverter delay time τ of each of the first to (M- 1)th inverter elements in measurements of the time interval between the first signal and the second signal without increasing the circuit size.The time-to-digital converter 100 or the time-to-digital converter 100 amay be configured such that the time-to-digital converter includes the wave number measurement unit 140 for measuring the wave number of a digital signal output from the phase information supply unit 110, and the arithmetic unit 150 acalculates the time interval between the first signal and the second signal input to the input terminal 101 from among both the value output from each of the Q terminals of the first to N-th D-type flip-flop circuits in each of the first to M-th flip-flop groups and the wave number of the digital signal measured by the wave number measurement unit 140.With the above configuration, the time-to-digital converter 100 or the time-to-digital converter 100 acan measure the time interval between the first signal and the second signal at a high resolution without increasing the circuit size even when the time interval between the first signal and the second signal is longer than the period of a digital signal such as the first digital signal output from the phase information supply unit 110.FIG. 5 is a diagram showing an example of the configuration of a main part of a time-to-digital converter 100 bincluding only one flip-flop group.Each of the time-to-digital converters explained so far was a converter including more than one flip-flop group. That is, each of the time-to-digital converter 100 according to Embodiment 1 and the time-to-digital converter 100 aaccording to Embodiment 2 was a converter including a plurality of flip-flop groups 121 a, 122 a, 123 a, 124 a, and 125 a. However, the time-to-digital converter 100 or the time-to-digital converter 100 amay be a converter including only one flip-flop group, namely, the first flip-flop group 121, like the time-to-digital converter 100 bshown in FIG. 5.More specifically, the time-to-digital converter 100 bis configured such that the time-to-digital converter includes: an input terminal 101 to which first and second signals are input at different times, the signals being digital signals; a phase information supply unit 110 outputting a digital signal; a first flip-flop group 121 bincluding first to N-th D-type flip-flop circuits 121- 1, 121- 2, 121- 3,..., and 121-N; first to (N- 1)-th delay elements 130- 1, 130- 2,..., and 130- (N- 1) connected in series each providing a time delay longer than a predetermined time. The digital signal output from the phase information supply unit 110 is input to each of the D terminals of the first to N-th D-type flip-flop circuits 121- 1, 121- 2, 121- 3,..., and 121-N in the first flip-flop group 121 b. The C terminal of the second D-type flip-flop circuit 121- 2 in the first flip-flop group 121 bis connected to one end of the first delay element 130- 1. The C terminal of the first D-type flip-flop circuit 121- 1 in the first flip-flop group 121 bis connected to the other end of the first delay element 130- 1. The other end of the first delay element 130- 1 is connected to an input terminal 101. When N, the number of flip-flops in a flip-flop group, is equal to or greater than 3, each C terminal of the (J+1)-th D-type flip-flop circuit in the first flip-flop group 121 bis connected to the one end of the J-th delay element, and one end of the (J+1)-th delay element is connected to the other end of the J-th delay element.With the configuration described above, the time-to-digital converter 100 bcan improve the resolution in measurements of the time interval between the first signal and the second signal without increasing the circuit size.It is understood that any combination of two of the above-mentioned embodiments may be made, that various changes may be made to any component according to any of the above-mentioned embodiments, or that any component according to any of the above-mentioned embodiments may be omitted within the scope of the present disclosure.INDUSTRIAL APPLICABILITYThe time-to-digital converter according to the present disclosure may be used in measurement equipment that measures physical quantities such as position, distance, speed, temperature, or a flow rate, or may be used in A / D converters or the like.LIST OF REFERENCE CHARACTERS100, 100 a, 100 btime-to-digital converter, 101 input terminal, 110 phase information supply unit, 111 first inverter element, 112 second inverter element, 113 third inverter element, 114 fourth inverter element, 115 fifth inverter element, 121, 121 a, 121 bfirst flip-flop group, 122, 122 asecond flip-flop group, 123, 123 athird flip-flop group, 124, 124 aututut flip-flop group, 125, 125 athup flip-flop group, 121- 1, 122- 1, 123- 1, 124- 1, 125- 1first D-type flip-flop circuit, 121- 2, 122- 2, 123- 2, 124- 2, 125-2 second D-type flip-flop circuit, 121-3, 122-3, 123-3, 124-3, 125-3 third D-type flip-flop circuit, 121-N N-th D-type flip-flop circuit, 130-1 first delay element, 130-2 second delay element, 130-N-1 (N-1)-th delay element, 140 wave number measurement unit, and 150, 150a arithmetic unit.

Claims

A time-to-digital converter (100, 100a or 100b) comprising: an input terminal (101) to which a first signal and a second signal are input at a different time; a phase information supply unit (110) including an inverter element (110+M) having an inverter delay time τ, wherein the phase information supply unit (110) outputs a plurality of digital signals, each of the digital signals having a phase different from each other, wherein the phase shift is an amount corresponding to the inverter delay time τ; a first flip-flop group (121) including first to N-th D-type flip-flop circuits (121-1, 121-2,..., and 121-N), wherein N is a natural number equal to or greater than 2; a first to (N-1)-th delay elements (130-1, 130-2,... and 130-N-1), each of the delay elements providing a time delay that is (N+1) / N times the inverter delay time τ; and a computing unit (150) that computes a time interval between a point of inputting the first signal and another point of inputting the second signal from the value output from each of the Q terminals of the first to N-th D-type flip-flop circuits (121-1, 121-2,... and 121-N), wherein one of the digital signals corresponding to the first flip-flop group (121) is input to all of the D terminals from the first to N-th D-type flip-flop circuits (121-1, 121-2,..., and 121-N) in the first flip-flop group (121), a C terminal of the second D-type flip-flop circuit (121-2) in the first flip-flop group (121) is connected to one end of a first delay element (130-1), a C terminal of the first D-type flip-flop circuit (121-1) in the first flip-flop group (121) is connected to the other end of the first delay element (130-1), the other end of the first delay element (130-1) is connected to the input terminal (101), and when N, the number of flip-flops in the first flip-flop group (121) is equal to or greater than 3, for each J, a natural number of 2 to N-1, the C terminal of the (J+1)-th D-type flip-flop circuit (121-J+1) in the first flip-flop group (121) is connected to one end of the J-th delay element (130-J) and one end of the (J-1)-th delay element (130-J-1) is connected to the other end of the J-th delay element (130-J).The time-to-digital converter (100, 100a or 100b) according to claim 1, wherein the time-to-digital converter (100, 100a or 100b) comprises second to M-th flip-flop groups (122, 123,..., and 120+M) each comprising different first to N-th D-type flip-flop circuits (12X-1, 12X-2, 12X-3,..., and 12X-N), wherein M is a natural number equal to or greater than 2, in addition to the first flip-flop group (121), and wherein the phase information supply unit (110) outputs first to M-th digital signals, each of the digital signals having a phase different from each other by an amount, which corresponds to the predetermined time, for each K, a natural number of 1 to M, a K-th digital signal among the digital signals output from the phase information supply unit (110) is input to D terminals of the first to N-th D-type flip-flop circuits (120+K-1, 120+K-2,..., and 120+K-N) in the K-th flip-flop group (120+K), in each flip-flop group (121, 122,..., and 120+M), the C terminal of the second D-type flip-flop circuit (120X-2) is connected to the one end of the first delay element (130-1), in each flip-flop group (121, 122,... and 120+M), the C terminal of the first D-type flip-flop circuit (12X-1) is connected to the other end of the first delay element (130-1), and when N, the number of flip-flops in one flip-flop group (121, 122,... and 120+M) is equal to or greater than 3, in each flip-flop group, the C terminal of the (J+1)-th D-type flip-flop circuit (12X-J+1) is connected to the one end of the J-th delay element (130-J), and the arithmetic unit (150) has values, The outputs from the Q terminals of the first to N-th D-type flip-flop circuits (12X-1, 12X-2,..., and 12X-N) of each flip-flop group (121, 122,..., and 120+M) are used to calculate the time interval.The time-to-digital converter (100, 100a, or 100b) according to claim 2, wherein the phase information supply unit (110) includes first to (M-1)-th inverter elements (111, 112,..., and 110+M-1), each of the first to (M-1)-th inverter elements is identical to the inverter element (110+M) and has an inverter delay time identical to the predetermined time, and each of D terminals of the first to N-th D-type flip-flop circuits (122-1, 122-2,..., and 122-N) in the second flip-flop group (122) is connected to one end of the first inverter element (111), each of the D terminals of the first to N-th D-type flip-flops (121-1, 121-2,..., and 121-N) in the first flip-flop group (121) is connected to the other end of the first inverter element (111), and when M, the number of flip-flops, is equal to or greater than 3, for each L, a natural number of 2 to M-1, each of D terminals of the first to N-th D-type flip-flops (120+L+1-1, 120+L+1-2,... and 120+L+1-N) in the (L+1)-th flip-flop group (120+L+1) is connected to one end of the L-th inverter element (110+L) and one end of the (L-1)-th inverter element (110+L-1) is connected to the other end of the L-th inverter element (110+L).The time-to-digital converter (100, 100a or 100b) according to claim 3, wherein the phase information supply unit (110) is a ring oscillator.The time-to-digital converter (100, 100a, or 100b) according to claim 4, wherein the phase information supply unit (110) includes an M-th inverter element (110+M) whose inverter delay time is identical to the inverter delay time of the first to (M-1)-th inverter elements (111, 112,..., and 110+M-1), in addition to the first to (M-1)-th inverter elements (111, 112,..., and 110+M-1), and wherein each of the D terminals of the first to N-th D-type flip-flop circuits (122-1, 122-2,... and 122-N) in the second flip-flop group (122) is connected to the one end of the first inverter element (111), each of the D terminals of the first to N-th D-type flip-flop circuits (121-1, 121-2,... and 121-N) in the first flip-flop group (121) is connected to the other end of the first inverter element (111), one end of the M-th inverter element (110+M) is connected to the other end of the first inverter element (111), the other end of the M-th inverter element (110+M) is connected to one end of the (M-1)-th inverter element (110+M-1), and when M, the number of flip-flop groups, is equal to or greater than 3, each of D terminals of the first to N-th D-type flip-flop circuits (120+L+1-1, 120+L+1-2,... and 120+L+1-N) in the (L+1)-th flip-flop group (120+L+1) is connected to the one end of the L-th inverter element (110+L), and the one end of the (L-1)-th inverter element (110+L-1) is connected to the other end of the L-th inverter element (110+L).The time-to-digital converter (100, 100a or 100b) according to claim 1, wherein the time-to-digital converter (100, 100a or 100b) comprises a wave number measurement unit (140) measuring a wave number of the digital signal by receiving the digital signal output from the phase information supply unit (110).

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