MIXED CONDUCTING VOLATILE STORAGE ELEMENT FOR ACCELERATED DESCRIPTION OF A NON-VOLATILE MEMRISTIVE BUILDING ELEMENT

Abstract

Structure that exhibits: an analog storage unit with three contacts comprising a volatile storage element (620) in series with a non-volatile storage element, wherein the analog storage unit has a drain contact (610), a read contact (641) and a write contact (640), and wherein a current flow along a write path of the analog storage unit is different from a current flow along a read path of the analog storage unit.

Description

BACKGROUND

[0001] The present invention relates to memory components and in particular to memristive components.

[0002] Machine learning is a general term used to describe a primary function of electronic computer systems that learn from data as a form of artificial intelligence. In machine learning and cognitive science, artificial neural networks (ANNs) are a family of statistical learning models and algorithms inspired by the biological neural networks of animals, particularly the brain. ANNs often consist of analog components that emulate artificial neurons for machine learning. In supervised machine learning, the artificial neurons of an ANN can be used to estimate or approximate systems or functions that depend on a large number of training inputs. Trained ANNs are then used in the inference process to compute some outputs based on the initial or continued input training of the ANN's neurons.KNNs can also be used for self-training in the process of enhancing machine learning or unsupervised learning. KNN architectures, neuromorphic microchips, and ultra-high-density non-volatile memory can be built from cost-effective, high-density, low-power circuit architectures such as crossbar arrays. A basic crossbar array configuration has a group of conductive wires in rows and a group of conductive wires in columns, arranged to cross the group of wires in rows. The crossings between the two groups of wires are separated by so-called cross-point devices, which can be made of thin-film materials. Cross-point devices can be implemented as so-called resistive memory devices (colloquially known as memristive devices).Features of a memristive device can include, for example, non-volatility, the ability to store a variable analog resistance value, the ability to determine the analog resistance value without disturbing the state of the memristive device, and the ability to increase or decrease a resistance using current or voltage pulses. These memristive devices can be used in hardware to simulate the artificial neurons of a KNN (K-nearest neighbors) algorithm.

[0003] US 10 714 179 B2 discloses a hybrid storage arrangement that combines volatile and non-volatile storage elements, wherein each element has multiple conductive layers separated by dielectric and resistive switching layers, respectively, to store data in different resistance states.

[0004] US 2009 / 0225584 A1 discloses a direct access memory in which each memory cell comprises an access transistor, a storage capacitor and a CMOS-compatible non-volatile storage element in series to store binary data based on the charge stored at the memory node.

[0005] US 2019 / 0019081 A1 discloses a neuromorphic device with pre- and postsynaptic neurons connected via intersecting row and column lines, with synapses with memristor-based structures for signal transmission arranged at the intersection points.

[0006] WO 2017 / 039608 A1 discloses a non-volatile memory cell with a volatile selector connected in series with a resistive storage element, wherein the selector comprises a silicon dioxide matrix between electrodes containing an alloy with a rapidly diffusing cation metal, as well as a corresponding storage arrangement and a manufacturing process therefor. BRIEF SUMMARY

[0007] One embodiment may include a memory structure comprising a volatile memory element in series with a non-volatile memory element. This may enable faster writing of the analog memory structure.

[0008] One embodiment can incorporate a memristive component as a non-volatile memory element. This can enable accelerated writing of the analog memory structure for use in analog computing.

[0009] One embodiment can include the volatile memory element, which is a material that temporarily changes its resistance when exposed to an electrical potential. This can enable accelerated writing of the analog memory structure.

[0010] One embodiment can include the volatile storage element, which is a material that becomes more conductive when an electrical potential is applied to it and returns to a relaxed state as soon as the electrical potential is removed. This can enable accelerated writing of the analog memory structure.

[0011] One embodiment can have the volatile memory element located between a first metal layer and a second metal layer. This can improve the stability of the device by reducing the migration of ions from the volatile memory. This can enable faster writing of the analog memory structure.

[0012] One embodiment can include the volatile storage layer comprising a mixed ionic-electronic conducting (MIEC) material that undergoes metal-insulator transitions (MIT) depending on the local ion concentration in the volatile storage layer. This can enable accelerated writing of the analog memory structure.

[0013] One embodiment may include the volatile storage layer, which contains an XCoO2, XNbO2, XVO2, XNbO3, X 4x Ti5O 12and / or XSmNiO3, where X can be an alkali metal such as Li, Na, or K. This can enable accelerated writing of the analog memory structure.

[0014] One embodiment can include the volatile memory layer, which is a write path of a three-terminal device. This can enable accelerated writing of the three-contact device.

[0015] One embodiment can include bidirectional non-volatile memory. This can enable faster writing to the bidirectional memory.

[0016] One embodiment can include a unidirectional non-volatile memory. This can enable faster writing to the unidirectional memory.

[0017] One embodiment can incorporate resistive random-access memory (RRAM). This can enable faster writing to the RRAM.

[0018] One embodiment can incorporate a conductive bridging random-access memory (CBRAM) as non-volatile memory. This can enable faster writing to the CBRAM.

[0019] One embodiment can incorporate an electrochemical random-access memory (ECRAM) as non-volatile memory. This can enable faster writing to the ECRAM.

[0020] One embodiment can incorporate a phase change memory (PCM) as non-volatile storage. This can enable faster writing to the PCM.

[0021] One embodiment may include writing to a memory structure comprising a volatile memory element in series with a non-volatile memory element. Writing to the analog memory structure may involve a first pulse to the analog memory structure and a second pulse to the analog memory structure. Writing to the analog memory structure may be performed such that the time between the first and second pulses is less than the relaxation rate of the volatile memory element. This may enable accelerated writing to the analog memory structure.

[0022] One embodiment may include writing to a memory structure comprising a volatile memory element in series with a non-volatile memory element. Writing to the analog memory structure may involve a first pulse, a second pulse, and a third negative pulse. Writing to the analog memory structure may be performed such that the time between the first and second pulses is less than the relaxation rate of the volatile memory element, and the time between the second and third negative pulses is less than the relaxation rate of the volatile memory element and greater than the first time. This may enable a reset function of the analog memory structure.

[0023] One embodiment may include writing to a memory structure comprising a volatile memory element in series with a non-volatile memory element. Writing to the analog memory structure may include a first pulse, a second pulse, and a third pulse. Writing to the analog memory structure may be performed such that the time between the first and second pulses is less than the relaxation rate of the volatile memory element, and the time between the second and third pulses is less than the relaxation rate of the volatile memory element and greater than the first time. This may allow for an approximation of an analog weight to be stored in the analog memory structure. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to 1C represent the function of an analog memory structure consisting of a volatile memory element in series with a non-volatile memristive element; Fig. Figure 2 represents a stack of materials of an exemplary analog memory structure consisting of a volatile memory element in series with a non-volatile memristive element; Fig. 3A, Fig. 3B, Fig. 3C and Fig. 3D represents exemplary operating procedures of a volatile storage element in series with a non-volatile memristive device; Fig. 4A and Fig. 4B represents a volatile memory element in series with an RRAM component; Fig. 5A and Fig. 5B represents a volatile memory element in series with an ECRAM component; Fig. 6A and Fig. 6B represents a volatile storage element in series with a mushroom-shaped PCM device; Fig. 7A and Fig. 7B represents a volatile memory element in series with an ECRAM component;

[0024] Elements of the figures are not necessarily to scale and are not intended to represent specific parameters of the invention exactly. For the sake of clarity and simplicity of illustration, the dimensions of elements may be exaggerated. The detailed description should be consulted regarding the precise dimensions. The drawings are intended to depict only typical embodiments of the invention and should therefore not be considered limiting with regard to the scope of the invention. In the drawings, identical numbering represents identical elements. DETAILED DESCRIPTION

[0025] This invention describes a method and a structure of a volatile memristive device, for example, a layer of mixed ionic electronic conducting (MIEC) material, which can be integrated in series with a non-volatile memristive device for neuromorphic computing with hardware-capable accelerated weight update. The volatile storage element consists of a material that undergoes a conductivity transition (e.g., a metal-insulator transition such as a Mott junction) when it becomes ion-depleted, resulting in a region of higher conductivity. Subsequent polarization of ions in the MIEC layer by an applied electric field results in progressively higher conductivity.

[0026] When a voltage is applied to the device, ions are polarized to one side by drift in the electric field. This creates ion depletion at one interface and ion supersaturation at the opposite interface. Certain MIEC materials, such as LiCoO₂, exhibit this characteristic. 2-x During depletion, ions undergo a change in electrical conductivity and become more metallic, while the supersaturated and saturated regions remain insulating. The layer as a whole becomes more conductive. If no bias is applied, ions relax at a rate slower than the write cycle timeframe (1 ns write, relaxation ~ 10 to 100 ns for LiCoO). 2-x ), into a state of equilibrium.

[0027] Stochastic pulses can be used to write to non-volatile memristive devices (e.g., RRAM). When successive pulses are used, the volatile storage element becomes polarized, allowing more current to flow through the non-volatile memristive device, thus enabling "accelerated writing" of the non-volatile element. After writing, the ions begin to relax, decreasing the conductivity of the MIEC [material]. If the weight is excessively amplified and write pulses reverse the polarity before complete relaxation, the "rewrite" slows down before accelerating in the opposite direction—acting like a dynamic for writing the weight.

[0028] Fig. 1A to 1C represent the function of an analog memory structure. Fig. 1A represents a memory structure comprising the first contact 10, a volatile memory element 20, a non-volatile memristive element 30, and a second contact 40. The first contact 10 and the second contact 40 can be any type of electrical conductor or lined through-hole and can be made of conductive materials such as Cu, W, TiN, TaN, or Ta.

[0029] The non-volatile memristive element 30 can be a bidirectional non-volatile memristive device such as an RRAM, CBRAM, ECRAM, or other similar structure. The non-volatile memristive element 30 can also be a unidirectional non-volatile memristive device such as a PCM or other unidirectional structures. Although the non-volatile memristive element 30 is shown as a two-terminal device, in cases where the memristive element has additional terminals (e.g., a three-terminal device with separate terminals for the read and write paths), the MIEC material should still be arranged in series with the current flow of the write path of the memristive element.

[0030] The volatile storage element 20 can be any material that temporarily changes its resistance when subjected to an electrical voltage and returns to a relaxed state of its original resistance when the voltage is removed. For example, the volatile storage element can become more conductive when an electrical voltage is applied to the material and return to a relaxed state as soon as the electrical voltage is removed. In an exemplary embodiment, MIT-MIEC materials can achieve an accelerating state from the movement of ions from one surface to another when a voltage is applied to the structure, thereby creating a depletion region and a saturation region in the material.As these regions form, the entire layer becomes more conductive, thereby increasing the current flow through the cell during write cycles and decreasing the number of write cycles required to achieve the desired resistive state of the non-volatile memristive element 30.

[0031] For example, Fig. Figure 1A represents the analog storage structure when the volatile storage element 20 is in a relaxed state, since there is no potential at the first contact 10 and the second contact 40. A plurality of mobile ions 50 are represented as positive charges randomly arranged over the volatile storage element 20. After a voltage is applied to the first contact 10 and the second contact 40, the mobile ions migrate into Fig. 1B towards the first contact 10, thereby reducing resistance and improving conductivity through the analog memory structure. In Fig. 1C, a further migration of the mobile ions 50 towards the surface of the first contact 10 takes place, either through a continuous voltage at the first contact 10 and the second contact 40 or through additional successive pulses (i.e., in a shorter time than the volatile storage element 20 needs to return to its state of Fig. 1A to relax), thereby reducing the resistance compared to Fig. 1B will be further reduced.

[0032] Referring to Fig. Figure 2 shows an exemplary arrangement of a material stack for an embodiment of the analog memory structure. The analog memory structure comprises a first contact 10, a volatile memory element 20, a non-volatile memristive element 30, and a second contact 40. The first contact 10 and the second contact can be conductive elements that connect the analog memory structure to other functional elements of the semiconductor structure. These contacts can be, for example, word lines, bit lines, vias, or any other conductive structure. The material of the first contact 10 and the second contact 40 can be, for example, copper, aluminum, titanium nitride, tantalum nitride, or tungsten.The volatile storage element 20 can have a first metal layer 21, a material layer of the volatile memory 22 and a second metal layer 23, but it must have at least one layer of the volatile memory 22.

[0033] The material layer of the volatile memory 22 can be any material that becomes more conductive when an electrical voltage is applied to it and returns to a relaxed state as soon as the electrical voltage is removed from the cell. The material layer of the volatile memory 22 can be defined by the time the material requires to return to a relaxed state after the electrical voltage is removed. In an exemplary embodiment, the volatile memory element 20 can return to a relaxed state in less than 1000 ns and preferably in less than 200 ns. The material layer of the volatile memory 22 can be a MIEC material, including a metal-insulator-transition (MIT)MIEC material, such as XCoO2, XNbO2, XVO2, XNbO3, X 4x Ti5O 12and / or XSmNiO3, where X can be an alkali metal such as Li, Na, or K. The volatile storage element 20 can have approximately 1 / 10 to approximately 1 / 1000 of the total thickness of the non-volatile memristive element 30.

[0034] The first metal layer 21 and the second metal layer 23 can be used to block the ions in the material layer of the volatile memory 22, preventing them from migrating out of the layer. The material of the first metal layer 21 and the second metal layer 23 can be, for example, a metal, metal nitrides, or other conductive materials. It should be noted that although the second metal layer 23 is shown separately from the non-volatile memory element 30, this layer (or in other orientations of the first metal layer 21) can be a metal that also functions as part of the non-volatile memory element 30. Depending on the characteristics of the device, the first metal layer 21 and the second metal layer 23 can be the same or different materials.In some embodiments, the second metal layer 23 may have wiring from one part of a component to another, or alternatively, it may be connected to component wiring, whereby the non-volatile memory element 30 and the volatile memory element 20 are not arranged together in a single memory cell.

[0035] Referring to Fig. 3A will be a method for using the analog memory structure of Fig. 1A and Fig. Figure 2 illustrates accelerated writing. In step S110, an initial electrical pulse is applied to the analog memory structure. The characteristics of the electrical pulse can be based on the characteristics of a write pulse for the type of non-volatile memristive element 30 used in the analog memory structure. For example, the electrical pulse can have 1 to 10 V, 1 to 50 ns for write pulses and 0.05 V to 1 V, 10 to 100 ns for read pulses, although the voltage and duration can lie outside these ranges based on the type of non-volatile memristive element 30 chosen.

[0036] In step S120, a second electrical pulse is applied to the analog memory structure before the volatile memory element 20 returns to a relaxed state. The second electrical pulse can be applied, for example, less than approximately 10 ns after the end of the first electrical pulse, and this can be done using similar features to the first electrical pulse. By sending the second electrical pulse in close succession (i.e., before the relaxation of the volatile memory element 20), the non-volatile memristive element 30 can undergo a greater change in state than occurred during the first electrical pulse.

[0037] In step S130, a third electrical pulse is applied to the analog memory structure before the volatile memory element 20 returns to a relaxed state. The third electrical pulse can be applied, for example, less than approximately 10 ns after the end of the second electrical pulse, and this can be done using similar features to the second electrical pulse. By sending the third electrical pulse in close succession (i.e., before the relaxation of the volatile memory element 20), the non-volatile memristive element 30 can undergo an increased change in state compared to what occurred during the second electrical pulse.

[0038] The in Fig. Although the procedure shown in Figure 3A illustrates only 3 electrical pulses, it should be noted that additional pulses can be applied in the described manner (i.e., before the relaxation of the volatile memory element 20) such that each pulse has an increased ability to change the state (i.e., to write) of the non-volatile memristive element 30 than the pulse preceding the current pulse, as well as than the first pulse, until a maximum writing speed is reached when the volatile memory element is maximally exponentially relaxed. Thus, the procedure of Fig. 3A in conjunction with the structures of Fig. 1 and Fig. 2A the write operation for an analog memory when the write operation is performed using write pulses that are executed without giving the volatile memory element 20 time to relax.

[0039] Referring to Fig. 3B will be a method for using the analog memory structure of Fig. 1A and Fig. Figure 2 illustrates non-accelerated writing. In step S113, an initial electrical pulse is applied to the analog memory structure. The characteristics of the electrical pulse can be based on the characteristics of a write pulse for the type of non-volatile memristive element 30 used in the analog memory structure. For example, 1 to 10 V, 1 to 100 ns for write pulses and 0.05 V to 1 V, 10 to 100 ns for read pulses, although the voltage and duration may lie outside these ranges based on the type of non-volatile memristive element 30 chosen.

[0040] In step S123, a second electrical pulse is applied to the analog memory structure after the volatile memory element 20 returns to a relaxed state. The second electrical pulse can be applied, for example, at least approximately 10 ns after the end of the first electrical pulse. By sending the second electrical pulse after the volatile memory element 20 returns to a resting state, the non-volatile memristive element 30 can undergo a similar change of state as occurred during the first electrical pulse.

[0041] It should be noted that the contrast between the procedure of Fig. 3A and the procedure of Fig. 3B consists in the fact that the analog memory structure achieves an accelerated write state due to the continued pulses in close succession (i.e. prior to relaxation of the volatile memory element 20) and not from a permanent change in the structure of the volatile memory element 20.

[0042] Referring to Fig. 3C will develop a method for using the analog memory structure of Fig. 1A and Fig. Figure 2 illustrates the provision of a negative pulse. In step S1155, a series of first electrical pulses is applied to the analog memory structure. The characteristics of the electrical pulse can be based on the characteristics of a write pulse for the type of non-volatile memristive element 30 used in the analog memory structure. For example, 1 to 10 V, 1 to 50 ns for write pulses and 0.05 V to 1 V, 10 to 100 ns for read pulses, although the voltage and duration can lie outside these ranges based on the type of non-volatile memristive element 30 chosen. The series of first electrical pulses can be executed 1 ns apart.

[0043] In step S125, a second electrical pulse with a polarity opposite to that of the series of first electrical pulses is applied to the analog memory structure after the volatile memory element 20 returns to a relaxed state. For example, the second electrical pulse can be applied at least 10 ns after the end of the series of first electrical pulses. By sending the second electrical pulse after the volatile memory element 20 returns to a resting state, the non-volatile memristive element 30 can undergo a similar change of state (in the opposite direction) as occurred during the first electrical pulse.

[0044] Referring to Fig. 3D will be a method for using the analog storage structure of Fig. 1A and Fig. 2 during a convergence to a weight value of the non-volatile memristive element 30 [shown]. In step S117, an initial electrical pulse is applied to the analog memory structure. The characteristics of the electrical pulse can be based on the characteristics of a write pulse for the type of non-volatile memristive element 30 used in the analog memory structure. For example, the electrical pulse can have 1 to 10 V, 1 to 50 ns for write pulses and 0.05 V to 1 V, 10 to 100 ns for read pulses, although the voltage and duration can lie outside these ranges based on the type of non-volatile memristive element 30 chosen.

[0045] In step S127, a second electrical pulse is applied to the analog memory structure with a first duration after the first pulse. The characteristics of the electrical pulse can be based on the characteristics of a write pulse for the type of non-volatile memristive element 30 used in the analog memory structure. For example, the electrical pulse can have 1 to 10 V, 1 to 50 ns for write pulses and 0.05 V to 1 V, 10 to 100 ns for read pulses, although the voltage and duration can lie outside these ranges based on the type of non-volatile memristive element 30 chosen. The first duration can, for example, be 1 ns between the first and second pulses.

[0046] In step S137, a third electrical pulse is applied to the analog memory structure for a second duration after the second pulse. The characteristics of the electrical pulse can be based on the characteristics of a write pulse for the type of non-volatile memristive element 30 used in the analog memory structure. For example, the electrical pulse can have 1 to 10 V, 1 to 50 ns for write pulses and 0.05 V to 1 V, 10 to 100 ns for read pulses, although the voltage and duration can lie outside these ranges based on the type of non-volatile memristive element 30 chosen. The second duration can, for example, be 2 ns between the first and second pulses. This duration can be longer than the first duration but shorter than the relaxation time of the volatile memory element 20.

[0047] With reference to the procedures in Fig. 3A to 3D are each an example of procedures that can be achieved alone or in combination with each other during a writing process.

[0048] Referring to Fig. 4A to 4B, Fig. 5A to 5B, Fig. 6A to 6B and Fig. Figures 7A to 7B present exemplary embodiments of the volatile memory element contained in a non-volatile memristive device. The following examples, which are not exhaustive, are instructive in terms of how the volatile memory element can be introduced into typical geometries for existing non-volatile memristive devices. However, it would be clear to those skilled in the art how such concepts can also be applied to other structures. Furthermore, these non-volatile memristive devices can be used as part of a transistor-powered crossover array or in any other arrangement of analogous memory cells.

[0049] Referring to Fig. 4A and Fig. Figure 4B presents exemplary embodiments of a bidirectional analog memory structure as used in a resistive random-access memory (RRAM). However, it is understood that the concepts shown in the illustrative RRAM embodiments are applicable to all bidirectional analog memory structures. Structures are shown that include a volatile memory element 320. The RRAM device contains a conductive element 331 and a dielectric switching layer 330. The RRAM structure shown has a lower contact 310 and an upper contact 340 arranged between an insulating dielectric 300. The RRAM device can either have the volatile memory element 320 between the lower contact 310 and the dielectric switching layer 330, as shown in Figure 4B. Fig. 4A shown, or it can have the volatile storage element 320 between the upper contact 340 and the conductive element 331, as shown in Fig. 4B shown; volatile storage element. The volatile storage element 320 can form metal layers similar to the representation in Fig. 2, but it must have at least one volatile storage layer.

[0050] Referring to Fig. 5A and Fig. Figure 5B presents bidirectional analog memory structures as used in electrochemical random-access memory (ECRAM), but it is understood that the concepts shown in the illustrative ECRAM implementations are applicable to all bidirectional analog memory structures. Fig. Figure 5B is shown to further illustrate the use of the volatile storage element in a symmetrical device. The ECRAM structure contains an ion-gate material 431 sandwiched between a first ion reservoir 430 and a second ion reservoir 432. The first ion reservoir 430 and the second ion reservoir 432 can be made of the same chemical composition, different chemical compositions, or materials with similar chemical compositions but different ion or dopant concentrations. The ECRAM structure shown has a lower contact 410 and an upper contact 440 sandwiched between an insulating dielectric 400.The ECRAM structure can also have the volatile memory element 420 between an ion reservoir 430 / 432 and a contact, for example between the first ion reservoir 430 and the lower contact 410, as in . Fig. 5A is shown. Furthermore, the volatile storage element 420 can be located between the first ion reservoir 430 and the second ion reservoir 432 and their respective contacts, as shown in Fig. 5B is shown, and thereby form a symmetrical structure. The volatile storage element 420 can form metal layers similar to the representation in Fig. 2, but it must have at least one volatile storage layer.

[0051] Referring to Fig. 6A and Fig. Figure 6B presents exemplary embodiments of a unidirectional analog memory structure as used in a mushroom-shaped PCM structure. However, it is understood that the concepts shown in the illustrative mushroom-shaped PCM embodiments are applicable to all unidirectional analog memory structures. The mushroom-shaped PCM device includes a heating element 531 and a dielectric layer 532 arranged beneath the phase-change material 530. The illustrated mushroom-shaped PCM structure has a lower contact 510 and an upper contact 540 arranged between an insulating dielectric 550. The mushroom-shaped PCM device can either include the volatile memory element 520 between the lower contact 510 and the heating element 531, as shown in Figure 6B. Fig. 6A shown, or alternatively, it can have the volatile storage element 520 between the upper contact 540 and the phase-change material 530, as shown in Fig. 6B is shown. The volatile storage element 520 can form metal layers similar to the representation in Fig. 2, but it must have at least one volatile storage layer.

[0052] Referring to Fig. 7A and Fig. Figure 7B presents exemplary embodiments of three-terminal analog memory structures as used in electrochemical random-access memory (ECRAM) structures that incorporate a volatile memory element. However, it is understood that the concepts shown in the illustrative three-terminal ECRAM are applicable to all three-terminal analog memory structures. The illustrated ECRAM structure has a drain contact 610, a read contact 641, and a write contact 640 arranged between an insulating dielectric 650, 651. The ECRAM structure may include an electrolyte layer 631 and a channel 630. In such an embodiment, the read path (i.e., the current flow from the read contact 641 to the drain contact 610) and the write path (i.e., the current flow from the read contact 641 to the drain contact 640) are defined as follows:Since the current flow from the write contact 640 to the drain contact 610 is different, the volatile storage element 620 would be located at least in the write path. As in . Fig. As shown in Figure 7A, the volatile memory element 620 can, for example, be located between the write contact 640 and the electrolyte layer 631, and thus only in the write path. Alternatively, the volatile memory element 620 can be located, as shown in Fig. 7B is shown, located at the drain contact 611 and thus in both the read and write paths. The volatile storage element 620 can be arranged in metal layers similar to the representation in Fig. 2, but it must have at least one volatile storage layer.

[0053] The formation of the volatile storage element as part of the overall formation process for each non-volatile memristive device structure can be achieved by depositing the volatile storage element at the appropriate position (e.g., before depositing the layers of the non-volatile memristive device, as in Fig. 5A shown, according to layers of the non-volatile memristive device, as in Fig. (5B shown), before the structure pattern is formed and contacts are established. Deposition of the volatile storage element can be achieved by PVD deposition such as pulsed laser deposition, sputtering, chemical vapor deposition, MOCVD, solution deposition, etc.

Claims

[1] Structure which exhibits: an analog storage unit with three contacts comprising a volatile storage element (620) in series with a non-volatile storage element, wherein the analog storage unit has a drain contact (610), a read contact (641) and a write contact (640), and wherein a current flow along a write path of the analog storage unit is different from a current flow along a read path of the analog storage unit. [2] Structure according to claim 1, wherein the non-volatile storage element comprises a memristive component. [3] Structure according to claim 1, wherein the volatile storage element comprises a material which temporarily changes its resistance when exposed to an electric field via the material. [4] Structure according to claim 1, wherein the volatile storage element comprises a material which becomes more conductive when an electrical voltage is applied to the material and returns to a relaxed state as soon as the electric field caused by the electrical voltage is removed. [5] Structure according to claim 1, wherein the volatile storage element comprises a volatile storage layer arranged between a first conductive layer and a second conductive layer. [6] Structure according to claim 1, wherein the volatile storage element comprises a volatile storage layer and wherein a material for the volatile storage layer comprises a MITMIEC material. [7] Structure according to claim 1, wherein the volatile storage element comprises a volatile storage layer and wherein a material for the volatile storage layer is selected from the group consisting of: XCoO2, XNbO2, XVO2, XNbO3, X 4x Ti5O12 and / or XSmNiO3, where X is an alkali metal. [8] Structure according to claim 2, wherein the non-volatile storage element comprises a bidirectional non-volatile memory. [9] Structure according to claim 2, wherein the non-volatile memory element comprises a unidirectional non-volatile memory. [10] Structure according to claim 2, wherein the non-volatile memory element comprises a resistive random-access memory, RRAM. [11] Structure according to claim 2, wherein the non-volatile memory element comprises a conductive bridging random-access memory, CBRAM. [12] Structure according to claim 2, wherein the non-volatile memory element comprises an electrochemical random-access memory, ECRAM. [13] Structure according to claim 2, wherein the non-volatile storage element comprises a phase change memory (PCM). [14] Storage structure which has: a three-contact memory structure comprising a volatile memory element (620) in series with a non-volatile memory element, wherein the three-contact memory structure has different terminals for a read path and a write path, and wherein the volatile memory element is arranged in the write path of the three-contact memory structure. [15] Structure according to claim 14, wherein the volatile storage layer comprises a material which temporarily changes its resistance when subjected to an electrical voltage on the material. [16] Structure according to claim 14, wherein the volatile storage layer comprises a material which becomes more conductive when an electrical voltage is applied to the material and returns to a relaxed state as soon as the electrical voltage is removed. [17] Structure according to claim 14, wherein the volatile storage layer comprises a volatile storage layer arranged between a first conductive layer and a second conductive layer. [18] Structure according to claim 14, wherein a material for the volatile storage layer is selected from the group consisting of: XCoO2, XNbO2, XVO2, XNbO3, X 4x Ti5O 12 and / or XSmNiO3, where X is an alkali metal. [19] Method for describing a storage structure which has: Applying a first pulse to a three-contact analog memory structure, wherein the analog memory structure comprises a volatile memory element (620) and a non-volatile memristive element in series, wherein the three-contact analog memory structure comprises a drain contact (610), a read contact (641), and a write contact (640), and wherein a current flow along a write path of the three-contact analog memory structure is different from a current flow along a read path of the three-contact analog memory structure; and Applying a second pulse to the analog memory structure, where the time interval between the first pulse and the second pulse is less than the relaxation rate of the volatile memory element. [20] Method according to claim 19, further comprising applying a third pulse to the analog memory structure, wherein the time interval between the second pulse and the third pulse is greater than the time interval between the first pulse and the second pulse and less than the relaxation rate. [21] Method for describing a storage structure which has: Applying a first pulse to an analog memory structure with three contacts, wherein the analog memory structure comprises a volatile memory element (620) and a non-volatile memristive element in series, wherein the analog memory structure with three contacts comprises a drain contact (610), a read contact (641) and a write contact (640), and wherein a current flow along a write path of the analog memory structure with three contacts is different from a current flow along a read path of the analog memory structure with three contacts; Applying a second pulse to the analog memory structure, wherein a first time interval between the first pulse and the second pulse is less than a relaxation rate of the volatile memory element; and Applying a third negative pulse to the analog memory structure, wherein a second time interval between the second pulse and the third negative pulse is less than a relaxation rate of the volatile memory element and greater than the first time interval. [22] The method of claim 21, further comprising: Prior to the first pulse, a plurality of pulses are applied to the analog memory structure, each pulse being applied in such a way that it has an increased ability to write to the non-volatile memristive element than the pulse before it as well as than the first pulse, and wherein a time interval between pulses is chosen such that the volatile memory element is not given time to relax. [23] Method for writing to an analog storage structure which has: Applying a first pulse to an analog memory structure with three contacts, wherein the analog memory structure comprises a volatile memory element (620) and a non-volatile memristive element in series, wherein the analog memory structure with three contacts comprises a drain contact (610), a read contact (641) and a write contact (640), and wherein a current flow along a write path of the analog memory structure with three contacts is different from a current flow along a read path of the analog memory structure with three contacts; Applying a second pulse to the analog memory structure, wherein a first time interval between the first pulse and the second pulse is less than a relaxation rate of the volatile memory element; and Applying a third pulse to the analog memory structure, wherein a second time interval between the second pulse and the third pulse is less than a relaxation rate of the volatile memory element and greater than the first time interval. [24] The method of claim 23, further comprising: Prior to the first pulse, a plurality of pulses are applied to the analog memory structure, each pulse being applied in such a way that it has an increased ability to write to the non-volatile memristive element than the pulse before it as well as than the first pulse, and wherein a time interval between pulses is chosen such that the volatile memory element is not given time to relax.

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