Power converter unit

Abstract

A power converter arrangement (1) comprises a multi-level power converter (10) of the neutral-point clamp type and a control arrangement (20). The control arrangement (20) comprises a modulation voltage generator (21) that generates modulation phase voltage commands (Vua*, Vva*, Vwa*) using phase voltage commands and phase currents, and a PWM modulator (22) that generates gate signals (Gu, Gv, Gw) to drive the power converter (10) using the modulation phase voltage commands (Vua*, Vva*, Vwa*).The modulation voltage generator (21) calculates an offset voltage (VX) such that - for a middle phase where the high-low rank is in the middle among the phase voltage commands for the respective phases, the polarity of the phase voltage command is not opposite to the polarity of the phase current, and the offset voltage (VX) is superimposed as the first common voltage on the phase voltage commands for the respective phases, thus generating the modulation phase voltage commands (Vua*, Vva*, Vwa*).

Description

Technical area

[0001] The present invention relates to a power converter device. State of the art

[0002] An example of a circuit for converting high-power DC energy into AC energy is a multi-level inverter of the neutral-point clamp type.

[0003] In a conventional power conversion device, using pulse width modulation (PWM) control, a controller compares a voltage command value for each of the three phases of a three-phase N-level inverter (N is an odd number not less than 3), which is a main circuit, with (N - 1) carrier signals and thus generates switching signals for switching elements of the N-level inverter.

[0004] The control device of the multi-level inverter described in Patent Document 1 includes: a maximum current phase selection unit that selects a maximum current phase in which the current amplitude is largest based on the absolute values ​​of current detection values ​​or current amplitude values ​​for the respective three phases; a subtraction unit that subtracts the voltage command value for the selected maximum current phase from the voltage command value for each of the three phases of the N-level inverter; and a carrier comparator 55 that compares the voltage command value for each of the three phases after the subtraction with the (N-1) carrier signals, thereby generating switching signals for the switching elements of the N-level inverter. BibliographyPatent document

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. JP 2019-30 070 A Summary of the inventionProblem to be solved by the invention

[0006] In a three-level neutral point clamp (NPC) inverter, it is known that losses and heat generation are large in a switching element connected on the AC terminal side. In the conventional technology described in Patent Document 1, switching losses are reduced for the maximum current phase, thus reducing losses in the entire power converter device, but losses in the switching element connected on the AC terminal side cannot be effectively reduced. Therefore, loss unevenness among a plurality of switching elements in each phase of the power converter device cannot be suppressed, thus limiting the improvement of conversion efficiency and output power.

[0007] The present invention has been conceived to solve the above problem, and an object of the present invention is to provide a neutral point clamp type power converter device in which losses in a semiconductor switching element connected on the AC terminal side are effectively reduced and unevenness between a plurality of switching elements in each phase is suppressed, so that high output and high efficiency are achieved. Ways to solve the problem

[0008] A power converter device according to the present invention comprises: a neutral-clamp type multi-level power converter that performs power conversion between DC power and AC power; and a controller that performs output control for the power converter through PWM control. The power converter has a multi-phase configuration including, in each phase of the power converter, an upper arm and a lower arm, each formed by connecting a first switching element on the DC terminal side and a second switching element on the AC terminal side in series, and a clamp diode connected between the neutral point and a connection point between the first and second switching elements.

[0009] The control device includes a modulation voltage generator that generates modulation phase voltage commands based on phase voltage commands and phase currents, and a PWM modulator that generates gate signals for driving the first and second switching elements of the power converter based on the modulation phase voltage commands. The modulation voltage generator calculates an offset voltage such that, for a middle phase where the high-low rank among the phase voltage commands for the respective phases is in the middle, the polarity of the phase voltage command is not opposite to the polarity of the phase current, and the offset voltage is superimposed as the first common voltage on the phase voltage commands for the respective phases, thus generating the modulation phase voltage commands. Effect of the invention

[0010] The power converter device according to the present invention makes it possible to provide a power converter device in which the loss in a second switching element connected on the AC terminal side can be effectively reduced and unevenness between a plurality of switching elements in each phase is suppressed, so that high output power and high efficiency are achieved. Short description of the drawings Fig. 1 is a configuration diagram showing a power converter device according to Embodiment 1. Fig. 2 is a current path diagram showing the basic operation of the power conversion device according to Embodiment 1. Fig. 3 is a current path diagram showing the basic operation of the power conversion device according to Embodiment 1. Fig. 4 is a flowchart showing the operation of a modulation voltage generator according to Embodiment 1. Fig. 5 are waveform diagrams showing the operation of a PWM modulator according to Embodiment 1. Fig. 6 are waveform diagrams showing the operation of the PWM modulator according to Embodiment 1. Fig. 7 are waveform diagrams showing the operation of a power conversion device in a comparative example of Embodiment 1. Fig. 8 are waveform diagrams showing the operation of the power conversion device according to Embodiment 1. Fig. 9 is a configuration diagram showing a power conversion device according to Embodiment 2. Fig. 10 is a flowchart showing the operation of a modulation voltage corrector according to Embodiment 2. Fig. 11 are waveform diagrams showing the operation of the power conversion device according to Embodiment 2. Fig. 12 is a configuration diagram showing a power conversion device according to Embodiment 3. Fig. 13 is a configuration diagram showing an example of hardware for implementing functions of a control device according to any one of Embodiments 1 to 3. Fig. 14 is a configuration diagram showing another example of hardware for implementing functions of the control device according to any one of Embodiments 1 to 3. Description of embodimentsEmbodiment 1

[0011] Embodiments are described below with reference to the drawings.

[0012] Fig. 1 is a configuration diagram showing a power converter device according to Embodiment 1.

[0013] As in Fig. 1, a power converter device 1 is connected, for example, between a DC power supply 2 and a motor which is a load 3, and it converts DC power of the DC power supply 2 into AC power and supplies the AC power to the load 3.

[0014] The power converter device 1 may be capable of bidirectional operation, and it may convert regenerative energy from the load 3 into DC energy and charge the DC power supply 2.

[0015] The power converter device 1 includes an NPC inverter 10 as a three-phase three-level power converter and a control device 20 that performs output control for the NPC inverter 10 by PWM control.

[0016] The NPC inverter 10 includes two capacitors C1, C2 connected in series between DC buses, and upper and lower branches (UA, UB), (VA, VB), (WA, WB) for each phase (U-phase, V-phase, W-phase) connected in series with each other. It also includes clamp diodes (D1u, D2u), (D1v, D2v), (D1w, D2w) for each phase. A connection point between the two capacitors C1, C2 is a star point or neutral point N, and connection points between the upper and lower branches (UA, UB), (VA, VB), (WA, WB) for the respective phases are AC terminals for the respective phases.

[0017] The upper branch UA for the U phase is formed by connecting in series a switching element Q1u as a first switching element on the DC connection side and a switching element Q2u as a second switching element on the AC connection side. The lower branch UB for the U phase is formed by connecting in series a switching element Q4u as a first switching element on the DC connection side and a switching element Q3u as a second switching element on the AC connection side. The clamp diode D1u is connected between the neutral point N and a connection point between the switching element Q1u and the switching element Q2u. The clamp diode D2u is connected between the neutral point N and a connection point between the switching element Q4u and the switching element Q3u.

[0018] The upper branch VA for the V phase is formed by connecting in series a switching element Q1v as a first switching element on the DC connection side and a switching element Q2v as a second switching element on the AC connection side. The lower branch VB for the V phase is formed by connecting in series a switching element Q4v as a first switching element on the DC connection side and a switching element Q3v as a second switching element on the AC connection side. The clamp diode D1v is connected between the neutral point N and a connection point between the switching element Q1v and the switching element Q2v. The clamp diode D2v is connected between the neutral point N and a connection point between the switching element Q4v and the switching element Q3v.

[0019] The upper branch WA for the W phase is formed by connecting, in series, a switching element Q1w as a first switching element on the DC connection side and a switching element Q2w as a second switching element on the AC connection side. The lower branch WB for the W phase is formed by connecting, in series, a switching element Q4w as a first switching element on the DC connection side and a switching element Q3w as a second switching element on the AC connection side.

[0020] The clamp diode D1w is connected between the neutral point N and a connection point between the switching element Q1w and the switching element Q2w. The clamp diode D2w is connected between the neutral point N and a connection point between the switching element Q4w and the switching element Q3w.

[0021] The first switching elements (switching elements Q1u, Q1v, Q1w) in the upper branches UA, VA, WA for the respective phases are connected to a DC terminal on the high-voltage side, and the second switching elements (switching elements Q2u, Q2v, Q2w) are connected to AC terminals for the respective phases. The first switching elements (switching elements Q4u, Q4v, Q4w) in the lower branches UB, VB, WB for the respective phases are connected to a DC terminal on the low-voltage side, and the second switching elements (switching elements Q3u, Q3v, Q3w) are connected to the AC terminals for the respective phases. The clamp diodes D1u, D1v, D1w connected to the upper branches UA, VA, WA have anodes connected to the neutral point N. The clamp diodes D2u, D2v, D2w, connected to the lower branches UB, VB, WB, have cathodes connected to the neutral point N.

[0022] The switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w are, for example, semiconductor switching elements made of silicon, and they can be insulated-gate bipolar transistors (IGBTs) with a diode connected in antiparallel, metal-oxide-semiconductor field-effect transistors (MOSFETs) with a diode connected between the source and drain, and the like. In the case of a MOSFET or a reverse-conducting (RC) IGBT, diodes included in the switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w can be used.

[0023] The control device 20 comprises: a modulation voltage generator 21 which generates modulation phase voltage commands Vua*, Vva*, Vwa* for the respective phases, and a PWM modulator 22 which generates gate signals Gu, Gv, Gw for driving the switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w for the respective phases based on the modulation phase voltage commands Vua*, Vva*, Vwa*.

[0024] The modulation voltage generator 21 receives phase voltage commands Vu*, Vv*, Vw* and phase current commands iu*, iv*, iw* for the respective phases, and generates the modulation phase voltage commands Vua*, Vva*, Vwa* through a calculation described later. In this case, the phase voltage commands Vu*, Vv*, Vw* for the respective phases have sinusoidal voltage waveforms.

[0025] Currents flowing through the load 3 when voltages according to specified phase voltage commands Vu*, Vv*, Vw* are supplied to the load 3 can be calculated using a model of the load 3 or the like, and the calculated currents can be used as the phase current commands iu*, iv*, iw*.

[0026] The phase voltage commands Vu*, Vv*, Vw* can be acquired by performing a control or calculation so that the currents flowing through the load 3 have the values ​​of the specified phase current commands iu*, iv*, iw*.

[0027] Fig. 2 and Fig. 3 are current path diagrams illustrating the basic operation of the power converter device 1.

[0028] The relationship between the output voltage for each phase of the NPC inverter 10 and a current path will be described below with reference to the drawings. In this case, the description is given for the U phase as an example, but the same applies to the V phase and the W phase.

[0029] In this case, the phase voltage Vu is a voltage relative to the neutral point N as a reference, and the phase current iu is defined such that the flow direction from the NPC inverter 10 to the load 3 is positive. Fig. 2 shows the case where the phase current iu is positive, and Fig. 3 shows the case where the phase current iu is negative.

[0030] In the U phase of the NPC inverter 10, the phase voltage Vu is output at three levels of positive, negative, and 0, and with a magnitude of 1 / 2 of the voltage Vdc of the DC power supply 2 with respect to the neutral point N as a reference.

[0031] As in Fig. 2, in a case where the phase current iu is positive, the following applies: When the phase voltage Vu is output at (Vdc / 2), the switching elements Q1u, Q2u of the upper arm QA conduct the current, and when the phase voltage Vu is 0, only the switching element Q2u of the upper arm QA conducts the current. In a case where the phase current iu is positive, the following applies: When the phase voltage Vu is output at -(Vdc / 2), the switching elements Q4u, Q3u (in the case of Fig. 2: antiparallel connected diodes) of the lower branch QB the current.

[0032] In PWM control, the phase voltage Vu is alternately switched between the two switching states (Vdc / 2) and 0, so that the phase voltage Vu is output, which is positive on average.

[0033] Therefore, in a case where the polarity of the phase current iu is positive, when the polarity of the phase voltage Vu is positive or 0, the switching element Q2u, which is the second switching element, can continue to be in a conductive state, and only the switching element Q1u, which is the first switching element, can perform the on / off switching. That is, the switching element Q2u, which is the second switching element, can be maintained in the on state, so its switching can be omitted.

[0034] As in Fig. 3, in a case where the phase current iu is negative, the following applies: When the phase voltage Vu is output at (Vdc / 2), the switching elements Q1u, Q2u (in the case of Fig. 3: antiparallel diodes) of the upper branch QA conducts the current. In a case where the phase current iu is negative, the following applies: when the phase voltage Vu is 0, only the switching element Q3u of the lower branch QB conducts the current, and when the phase voltage Vu is output at -(Vdc / 2), the switching elements Q4u, Q3u of the lower branch QB conduct the current.

[0035] In PWM control, the phase voltage Vu is alternately switched between the two switching states -(Vdc / 2) and 0, so that the phase voltage Vu is output, which is negative on average.

[0036] Therefore, in a case where the polarity of the phase current iu is negative, when the polarity of the phase voltage Vu is negative or 0, the switching element Q3u, which is the second switching element, can continue to be in a conductive state, and only the switching element Q4u, which is the first switching element, can perform the on / off switching. That is, the switching element Q3u, which is the second switching element, can be maintained in the on state, so its switching can be omitted.

[0037] As described above, when the polarity of the phase voltage Vu is the same as the polarity of the phase current iu or is 0, that is, when both polarities are not opposite to each other, the second switching element (switching element Q2u or Q3u) can be kept in the on state, so that its switching can be omitted.

[0038] Next, the operation of the modulation voltage generator 21 will be described. The modulation voltage generator 21 receives the phase voltage commands Vu*, Vv*, Vw* and the phase current commands iu*, iv*, iw* for the respective phases, and generates the modulation phase voltage commands Vua*, Vva*, Vwa*.

[0039] Fig. 4 is a timing chart illustrating the operation of the modulation voltage generator 21.

[0040] The modulation voltage generator 21 generates the modulation phase voltage commands Vua*, Vva*, Vwa* based on the phase voltage commands Vu*, Vv*, Vw* and the phase current commands iu*, iv*, iw* for the respective phases in every predetermined calculation cycle.

[0041] First, the modulation voltage generator 21 searches the middle phase in which the high-low rank is middle among the phase voltage commands Vu*, Vv*, Vw* for the respective phases (step S1), and defines the phase voltage command for the middle phase as VA* and the phase current command for the middle phase as iA* (step S2).

[0042] For example, in a period where Vw* < Vu* < Vv* is satisfied, the U phase is the middle phase, so the phase voltage command Vu* for the U phase is defined as VA* and the phase current command iu* for the U phase is defined as iA*.

[0043] Next, the modulation voltage generator 21 determines whether or not VA* is positive and iA* is negative (step S3). If "yes," the modulation voltage generator 21 sets the offset voltage VX as VX = -VA* - α (step S4). Here, α is a constant voltage value that is positive or 0.

[0044] Next, the modulation voltage generator 21 superimposes the offset voltage VX as the first common voltage on the phase voltage commands Vu*, Vv*, Vw* for the respective phases, thus generating the modulation phase voltage commands Vua*, Vva*, Vwa*. That is, Vua* = Vu* + VX, Vva* = Vv* + VX, and Vwa* = Vw* + VX are satisfied (step S5).

[0045] In step S3, in the case of "No", the modulation voltage generator 21 determines whether or not VA* is negative and iA* is positive (step S6), and if the determination result is "Yes", the modulation voltage generator 21 sets the offset voltage VX as VX = - VA* + α (step S7) and then proceeds to step S5.

[0046] In the case of “No” in step S6, the modulation voltage generator 21 sets the offset voltage VX as VX = 0 (step S8) and then proceeds to step S5.

[0047] As described above, the modulation voltage generator 21 calculates the offset voltage VX such that, for the middle phase, where the high-low order is medium, among the phase voltage commands Vu*, Vv*, Vw* for the respective phases, the polarity of the phase voltage command VA* does not become opposite to the polarity of the phase current command iA*. Specifically, the modulation voltage generator 21 calculates the offset voltage VX such that, for the middle phase, during a period in which the polarity of the phase voltage command VA* is positive and the polarity of the phase current command iA* is negative, the value of the phase voltage command VA* does not become greater than 0. In addition, the modulation voltage generator 21 calculates the offset voltage VX such that - in a period in which the polarity of the phase voltage command VA* is negative and the polarity of the phase current command iA* is positive - the value of the phase voltage command VA* does not become less than 0.

[0048] The offset voltage VX is specified so that it is not larger than necessary, and α is specified to 0 or a comparably small positive voltage value taking into account a reserve.

[0049] The modulation voltage generator 21 superimposes the offset voltage VX as the first common voltage on the phase voltage commands Vu*, Vv*, Vw* for the respective phases and thus generates the modulation phase voltage commands Vua*, Vva*, Vwa*.

[0050] Next, the operation of the PWM modulator 22 will be described. The PWM modulator 22 generates the gate signals Gu, Gv, Gw for driving the switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w for the respective phases based on the modulation phase voltage commands Vua*, Vva*, Vwa*.

[0051] Fig. 5 and Fig. 6 are waveform diagrams illustrating the operation of the PWM modulator 22.

[0052] In this case too, the description is given for the U phase as an example, but the same applies to the V phase and the W phase. Fig. 5 shows a case where the modulation phase voltage command Vua* satisfies Vua* ≥ 0, and Fig. Figure 6 shows a case where the modulation phase voltage command Vua* satisfies Vua* < 0. The gate signals Gu collectively represent gate signals G1u, G2u, G3u, G4u for the switching elements Q1u, Q2u, Q3u, Q4u for the U phase.

[0053] The PWM modulator 22 compares the modulation phase voltage command Vua* with two carrier waves, i.e., triangular waves Cr1, Cr2, to generate the gate signals Gu. The triangular wave Cr1 varies in the range from zero to (Vdc / 2), and the triangular wave Cr2 varies in the range from -(Vdc / 2) to zero.

[0054] In the NPC inverter 10, the switching element Q1u and the switching element Q3u are driven by the gate signal G1u and the gate signal G3u, which are inverted from each other between H and L. Furthermore, the switching element Q2u and the switching element Q4u are driven by the gate signal G2u and the gate signal G4u, which are inverted from each other between H and L.

[0055] As in Fig. 5, in the case where the modulation phase voltage command Vua* ≥ 0, the gate signal G2u is kept at H, and the gate signal G4u is kept at L. In a range where the modulation phase voltage command Vua* becomes larger than the triangular wave Cr1, the gate signal G1u becomes H, and the gate signal G3u becomes L. At this time, the phase voltage Vu is output at (Vdc / 2). In a range where the modulation phase voltage command Vua* is not larger than the triangular wave Cr1, the gate signal G1u becomes L, and the gate signal G3u becomes H. At this time, the phase voltage Vu is output at 0.

[0056] Consequently, the average value of the phase voltage Vu satisfies the modulation phase voltage command Vua* by PWM control.

[0057] As in Fig. 6, in the case where the modulation phase voltage command Vua* < 0, the gate signal G1u is kept at L, and the gate signal G3u is kept at H. In a range where the modulation phase voltage command Vua* becomes larger than the triangular wave Cr1, the gate signal G2u becomes H, and the gate signal G4u becomes L. At this time, the phase voltage Vu is output at 0. In a range where the modulation phase voltage command Vua* is not larger than the triangular wave Cr2, the gate signal G2u becomes L, and the gate signal G4u becomes H. At this time, the phase voltage Vu is output at -(Vdc / 2).

[0058] Consequently, the average value of the phase voltage Vu satisfies the modulation phase voltage command Vua* through the PWM control.

[0059] Fig. 7 are waveform diagrams showing the operation of the power conversion device in a comparative example of the present embodiment.

[0060] In the comparison example, the modulation voltage generator 21 is not present, ie, the phase voltage commands Vu*, Vv*, Vw* for the respective phases are used as they are to generate the gate signals Gu. Fig. Figure 7 shows the phase voltage commands Vu*, Vv*, Vw* and the phase current commands iu*, iv*, iw* for the respective phases. For the U phase, a waveform Up is shown, indicating whether the polarities of the phase voltage command Vu* and the phase current command iu* are consistent or opposite. When the phase voltage command Vu* = 0, Up is considered 1, indicating that the polarities are consistent.

[0061] As shown in the waveform Up, a section t1 where the polarities of the phase voltage command Vu* and the phase current command iu* are opposite to each other without agreeing with each other exists in a region where the U phase is the middle phase.

[0062] Fig. 8 are waveform diagrams showing the operation of the power conversion device according to the present embodiment 1.

[0063] In the present embodiment, as described above, the modulation voltage generator 21 calculates the offset voltage VX such that, for the middle phase, the polarity of the phase voltage command VA* does not become opposite to the polarity of the phase current command iA*. In this case, the offset voltage VX is calculated with α set to 0.

[0064] The modulation voltage generator 21 then superimposes the offset voltage VX as the first common voltage on the phase voltage commands Vu*, Vv*, Vw* for the respective phases and thus generates the modulation phase voltage commands Vua*, Vva*, Vwa*.

[0065] In Fig. 8, the modulation phase voltage commands Vua*, Vva*, Vwa* and the phase current commands iu*, iv*, iw* are shown for the respective phases, and for the U phase, a waveform Upa is shown indicating whether or not the polarities of the modulation phase voltage command Vua* and the phase current command iu* agree with each other.

[0066] In the case where the modulation phase voltage command Vua* = 0, Upa is considered 1, indicating that the polarities match. That is, Upa is considered 1 as long as the polarity of the modulation phase voltage command Vua* does not become opposite to the polarity of the phase current command iu*.

[0067] The modulated phase voltage commands Vua*, Vva*, Vwa* for the respective phases are generated by superimposing the same first common voltage (offset voltage VX) on the phase voltage commands Vu*, Vv*, Vw*, which have sinusoidal voltage waveforms. Consequently, the line voltages under the modulated phase voltage commands Vua*, Vva*, Vwa* for the respective phases are maintained as voltages with sinusoidal waveforms, and load 3 is not affected.

[0068] As in Fig. As shown in Figure 8, in a period in which the modulation phase voltage command Vua* corresponds to the middle phase, the offset voltage VX, which is the first common voltage, is superimposed so that the polarity of the modulation phase voltage command Vua* does not become opposite to the polarity of the phase current command iu*. That is, in a section corresponding to the section t1 in Fig. 7, the offset voltage VX is superimposed so that in the case that the phase current command iu* > 0, the modulating phase voltage command Vua* becomes α, and in the case that the phase current command iu* < 0, the modulating phase voltage command Vua* becomes -α.

[0069] In this case, the following applies: Since α is equal to 0, the modulation phase voltage command Vua* is 0, in the section corresponding to section t1 in Fig. 7.

[0070] Consequently, as shown in the waveform Upa, the polarity of the modulating phase voltage command Vua* always matches the polarity of the phase current command iu* or becomes 0 without being reversed. This feature also applies to the V-phase and W-phase, i.e., the polarities of the modulating phase voltage commands Vua*, Vva*, Vwa* for the respective phases always match the polarities of the phase current commands iu*, iv*, iw* for the respective phases or become 0 without being reversed.

[0071] As described above, for example, in the U phase, when the polarity of the phase voltage Vu is the same as the polarity of the phase current iu or is 0, that is, both polarities are not opposite to each other, the second switching element (switching element Q2u or Q3u) can be kept in the on state, so that its switching can be omitted.

[0072] In the present embodiment, the polarities of the modulation phase voltage commands Vua*, Vva*, Vwa* for the respective phases are not opposite to the polarities of the phase current commands iu*, iv*, iw* for the respective phases. Consequently, the number of times the second switching elements (Q2u, Q3u), (Q2v, Q3v), (Q2w, Q3w) connected to the AC terminals for the respective phases are switched can be significantly reduced, so that switching losses can be significantly reduced.

[0073] In the above description, it is described that, in the three-level NPC inverter, the losses and heat generation in the switching element connected to the AC terminal side are large. However, in the present embodiment, the losses in the second switching elements (Q2u, Q3u), (Q2v, Q3v), (Q2w, Q3w) connected to the AC terminals can be effectively reduced.

[0074] As described above, in the present embodiment, the power conversion device 1 includes the NPC inverter 10 and the control device 20 that performs output control for the NPC inverter 10 by PWM control. The control device 20 has the modulation voltage generator 21 which generates the modulation phase voltage commands Vua*, Vva*, Vwa* based on the phase voltage commands Vu*, Vv*, Vw* and the phase current commands iu*, iv*, iw*, and the PWM modulator 22 which generates the gate signals Gu, Gv, Gw for driving the first and second switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w of the NPC inverter 10 based on the modulation phase voltage commands Vua*, Vva*, Vwa*.

[0075] Then, the modulation voltage generator 21 calculates the offset voltage VX such that, for the middle phase where the high-low rank among the phase voltage commands Vu*, Vv*, Vw* for the respective phases is middle, the polarity of the phase voltage command VA* does not become opposite to the polarity of the phase current command iA*, and superimposes the offset voltage VX as the first common voltage on the phase voltage commands Vu*, Vv*, Vw* for the respective phases, so that the modulation phase voltage commands Vua*, Vva*, Vwa* are generated.

[0076] Consequently, the losses in the second switching elements (Q2u, Q3u), (Q2v, Q3v), (Q2w, Q3w) connected to the AC terminals can be effectively reduced. Therefore, uneven losses among the plurality of switching elements for the respective phases of the NPC inverter 10 can be suppressed, resulting in the power conversion device 1 having high output power and high efficiency.

[0077] In the present embodiment, the phase voltage commands Vu*, Vv*, Vw* are voltage commands with sinusoidal waveforms, and the modulation voltage generator 21 calculates the offset voltage VX so that, for the middle phase, the value of the phase voltage command VA* becomes not greater than 0 in a period in which the polarity of the phase voltage command VA* is positive and the polarity of the phase current command iA* is negative, and the value of the phase voltage command VA* becomes not less than 0 in a period in which the polarity of the phase voltage command VA* is negative and the polarity of the phase current command iA* is positive.

[0078] Consequently, the modulation phase voltage commands Vua*, Vva*, Vwa* for the respective phases can be surely generated while always preventing their polarities from becoming opposite to the polarities of the phase current commands iu*, iv*, iw*, so that a reduction effect for the losses of the second switching elements (Q2u, Q3u), (Q2v, Q3v), (Q2w, Q3w) can be surely obtained.

[0079] In the above embodiment, the modulation phase voltage commands Vua*, Vva*, Vwa* are generated based on the phase voltage commands Vu*, Vv*, Vw* and the phase current commands iu*, iv*, iw*. However, instead of the phase current commands iu*, iv*, iw*, phase currents iu, iv, iw can also be detected and used for the respective phases, so that the same effects can be achieved. Embodiment 2

[0080] In the above Embodiment 1, the magnitudes of the modulation phase voltage commands Vua*, Vva*, Vwa* can become greater than (Vdc / 2), which is 1 / 2 of the voltage Vdc of the DC power supply 2. In the present Embodiment 2, the magnitudes of the modulation phase voltage commands Vua*, Vva*, Vwa* are always reduced to (Vdc / 2) or less.

[0081] Fig. 9 is a configuration diagram showing a power conversion device according to Embodiment 2.

[0082] As in Fig. As shown in Figure 9, a power converter device 1A includes the NPC inverter 10 as a three-phase three-level power converter, and a control device 20A that performs output control for the NPC inverter 10 through PWM control. The power converter device 1A is connected between, for example, the DC power supply 2 and the motor constituting the load 3, and converts DC power of the DC power supply 2 into AC power and supplies the AC power to the load 3. In this case, the NPC inverter 10 has the same configuration as that in Embodiment 1 above, but the power converter device 1A includes a current detector 5 that detects phase currents iu, iv, iw for the respective phases to be output from the NPC inverter 10 to the load 3.

[0083] Here, the case is shown where the current detector detects five currents for the three phases. However, currents for two of the three phases can also be detected, and the current for the other phase can be calculated from the fact that the sum of the currents for the three phases is zero.

[0084] The control device 20A includes a modulation voltage generator 24 (hereinafter referred to as second modulation voltage generator 24) that generates modulation phase voltage commands Vub*, Vvb*, Vwb* for the respective phases, and the PWM modulator 22 that generates gate signals Gu, Gv, Gw for driving the switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w for the respective phases based on the modulation phase voltage commands Vub*, Vvb*, Vwb*.

[0085] The second modulation voltage generator 24 generates the modulation phase voltage commands Vub*, Vvb*, Vwb* based on the phase voltage commands Vu*, Vv*, Vw* and the detected phase currents iu, iv, iw for the respective phases in each predetermined calculation cycle.

[0086] The second modulation voltage generator 24 includes the same modulation voltage generator 21 as in the above embodiment 1, and a modulation voltage corrector 23 that corrects the modulation phase voltage commands Vua*, Vva*, Vwa* generated by the modulation voltage generator 21, so that the modulation phase voltage commands Vub*, Vvb*, Vwb* are generated.

[0087] The PWM modulator 22 receives the corrected modulation phase voltage commands Vub*, Vvb*, Vwb* and generates the gate signals Gu, Gv, Gw through the same processing as in the above embodiment 1.

[0088] In this case, the modulation voltage generator 21 receives the phase voltage commands Vu*, Vv*, Vw* and the detected phase currents iu, iv, iw for the respective phases and generates the modulation phase voltage commands Vua*, Vva*, Vwa* by the same calculation as in the above embodiment 1.

[0089] The modulation voltage generator 21 calculates the offset voltage VX such that, for the middle phase, where the high-low order is medium, among the phase voltage commands Vu*, Vv*, Vw* for the respective phases, the polarity of the phase voltage command VA* does not become opposite to the polarity of the phase current iA. Specifically, the modulation voltage generator 21 calculates the offset voltage VX such that, for the middle phase, during a period in which the polarity of the phase voltage command VA* is positive and the polarity of the phase current iA is negative, the value of the phase voltage command VA* does not become greater than 0. In addition, the modulation voltage generator 21 calculates the offset voltage VX such that - in a period in which the polarity of the phase voltage command VA* is negative and the polarity of the phase current iA is positive - the value of the phase voltage command VA* does not become less than 0.

[0090] The modulation voltage generator 21 then superimposes the offset voltage VX as the first common voltage on the phase voltage commands Vu*, Vv*, Vw* for the respective phases and thus generates the modulation phase voltage commands Vua*, Vva*, Vwa*.

[0091] The strengths of the generated modulation phase voltage commands Vua*, Vva*, Vwa* can be greater than (Vdc / 2), which is 1 / 2 of the voltage Vdc of the DC power supply 2 (see Fig. 8).

[0092] Next, the operation of the modulation voltage corrector 23 will be described.

[0093] Fig. 10 is a timing chart illustrating the operation of the modulation voltage corrector 23.

[0094] First, the modulation voltage corrector 23 searches the maximum phase and the minimum phase at which the high-low ranks among the modulation phase voltage commands Vua*, Vva*, Vwa* for the respective phases are the highest and the lowest, respectively (step SS1), and defines the modulation phase voltage command for the maximum phase as Vmax* and the modulation phase voltage command for the minimum phase as Vmin* (step SS2).

[0095] For example, in a period where Vwa* < Vua* < Vva* is satisfied, the V phase is the maximum phase, so Vva* is defined as Vmax*, and the W phase is the minimum phase, so Vwa* is defined as Vmin*.

[0096] Next, the modulation voltage corrector 23 determines whether or not Vmax* > (Vdc / 2) - β is satisfied (step SS3), and if "Yes," the modulation voltage corrector 23 sets the offset voltage VY, which is a correction voltage, as VY = ((Vdc / 2) - β) - Vmax* (step SS4). Here, β is a constant voltage value that is positive or 0, and ((Vdc / 2) - β) is a predetermined voltage based on the voltage Vdc of the DC power supply 2.

[0097] Next, the modulation voltage corrector 23 superimposes the offset voltage VY as the second common voltage on the modulation phase voltage commands Vua*, Vva*, Vwa* for the respective phases, thus generating the corrected modulation phase voltage commands Vub*, Vvb*, Vwb*. That is, the following are satisfied: Vub* = Vua* + VY, Vvb* = Vva* + VY, and Vwb* = Vwa* + VY (step SS5).

[0098] In the case of "No" in step SS3, the modulation voltage corrector 23 determines whether or not Vmin* < - ((Vdc / 2) - β) is satisfied (step SS6), and in the case of "Yes", the modulation voltage corrector 23 sets the offset voltage VY, which is a correction voltage, as VY = - ((Vdc / 2) - β) - Vmin* (step SS7) and then proceeds to step S5.

[0099] If “No” in step SS6, the modulation voltage corrector 23 sets the offset voltage VY as VY = 0 (step SS8) and then proceeds to step SS5.

[0100] As described above, the modulation voltage corrector 23 calculates the offset voltage (correction voltage) VY so that the modulation phase voltage command Vmax* for the maximum phase at which the high-low rank is the highest among the modulation phase voltage commands Vua*, Vva*, Vwa* for the respective phases becomes not greater than the predetermined voltage ((Vdc / 2) - β), and the strength (absolute value) of the modulation phase voltage command Vmin* for the minimum phase at which the high-low rank is the lowest becomes not greater than the predetermined voltage ((Vdc / 2) - β).

[0101] The offset voltage VY is set so that it is not larger than necessary, and β is set to 0 or a comparably small positive voltage value taking into account a reserve.

[0102] The modulation voltage corrector 23 superimposes the offset voltage VY as the second common voltage on the modulation phase voltage commands Vua*, Vva*, Vwa* for the respective phases, thus generating the corrected modulation phase voltage commands Vub*, Vvb*, Vwb*.

[0103] Fig. 11 are waveform diagrams showing the operation of the power conversion device according to the present embodiment 2.

[0104] In the present embodiment, the modulation voltage generator 21 generates the modulation phase voltage commands Vua*, Vva*, Vwa* as in the above Embodiment 1, and further, the modulation voltage corrector 23 corrects the modulation phase voltage commands Vua*, Vva*, Vwa* to generate the corrected modulation phase voltage commands Vub*, Vvb*, Vwb*. In this case, the modulation voltage corrector 23 calculates the correction voltage (offset voltage VY) with β set to 0, and superimposes the correction voltage as the second common voltage on the modulation phase voltage commands Vua*, Vva*, Vwa* for the respective phases, thus performing the correction.

[0105] In Fig. 11, the corrected modulation phase voltage commands Vub*, Vvb*, Vwb* and the phase currents iu, iv, iw are shown for the respective phases, and for the U phase, a waveform Upb is shown indicating whether or not the polarities of the modulation phase voltage command Vub* and the phase current iu coincide with each other.

[0106] In the case where the modulation phase voltage command Vub* = 0, Upb is considered 1, indicating that the polarities match. That is, Upb is considered 1 as long as the polarity of the modulation phase voltage command Vub* does not become opposite to the polarity of the phase current iu.

[0107] Also in the present embodiment, the modulation phase voltage commands Vub*, Vvb*, Vwb* for the respective phases are generated by superimposing the first common voltage (offset voltage VX) and the second common voltage (offset voltage VY), which are the same between the phases, on the phase voltage commands Vu*, Vv*, Vw* with sinusoidal voltage waveforms. Consequently, the line voltages under the modulation phase voltage commands Vub*, Vvb*, Vwb* for the respective phases are maintained as voltages with sinusoidal waveforms, and the load 3 is not affected.

[0108] As in Fig. As shown in Figure 11, the magnitudes (absolute values) of the modulation phase voltage commands Vub*, Vvb*, Vwb* for the respective phases are limited by the specified voltage ((Vdc / 2) - β). Since β is equal to 0, they are limited by the specified voltage (Vdc / 2) in this case.

[0109] As shown in the waveform Upb, in a period where the U-phase is the middle phase, there is a section t2 where the polarity of the modulation phase voltage command Vub* and the polarity of the phase current iu are opposite to each other, and in the section t2, the modulation phase voltage command Vvb*, Vwb* for the V-phase or the W-phase is limited to the predetermined voltage (Vdc / 2). The section t2 can be significantly shortened compared to the section t1, which is Fig. 7. This feature also applies to the V phase and the W phase.

[0110] As described above, in the present embodiment, the period in which the modulation phase voltage command Vub*, Vvb*, Vwb* for each phase has a polarity opposite to the phase current iu, iv, iw for the corresponding phase can be significantly shortened, and the strengths of the modulation phase voltage commands Vub*, Vvb*, Vwb* can always be reduced to (Vdc / 2) or less.

[0111] Therefore, as in Embodiment 1 above, the number of times the second switching elements (Q2u, Q3u), (Q2v, Q3v), (Q2w, Q3w) connected to the AC terminals for the respective phases are switched can be significantly reduced, so that switching losses can be significantly reduced. Therefore, unevenness in losses between the plurality of switching elements for the respective phases of the NPC inverter 10 can be suppressed, so that the power conversion device 1 having high output power and high efficiency is obtained.

[0112] Since the strengths of the modulation phase voltage commands Vua*, Vva*, Vwa* can always be reduced to (Vdc / 2) or less, the occurrence of over-modulation in PWM control can be prevented, so that distortion of output voltage and current is suppressed and the reliability of the control is improved.

[0113] In Embodiment 2 above, the modulation voltage corrector 23 searches two phases, that is, the maximum phase and the minimum phase, to calculate the offset voltage VY. However, the modulation voltage corrector 23 may also search only one phase whose magnitude (absolute value) is the largest among the modulation phase voltage commands Vua*, Vva*, Vwa* for the respective phases. In this case, the offset voltage VY is calculated so that the magnitude (absolute value) of the modulation phase voltage command for the found phase does not exceed the predetermined voltage ((Vdc / 2) - β), thus achieving the same result as in Embodiment 2 above. Embodiment 3

[0114] Fig. 12 is a configuration diagram showing a power conversion device according to Embodiment 3.

[0115] As in Fig. As shown in Figure 12, a power converter device 1B includes an NPC inverter 11 as a three-phase, three-level power converter, and the controller 20 that performs output control for the NPC inverter 11 through PWM control. The power converter device 1B is connected between, for example, the DC power supply 2 and the motor constituting the load 3, and converts DC power of the DC power supply 2 into AC power and supplies the AC power to the load 3. In this case, the NPC inverter 11 is the same as that in Embodiment 1 above, except for the element configurations of the switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w, and the controller 20 is also the same as that in Embodiment 1 above.

[0116] The first switching elements (switching elements Q1u, Q1v, Q1w) in the upper branches UA, VA, WA for the respective phases of the NPC inverter 11 are connected to the DC terminal on the high-voltage side, and the second switching elements (switching elements Q2u, Q2v, Q2w) are connected to the AC terminals for the respective phases. The first switching elements (switching elements Q4u, Q4v, Q4w) in the lower branches UB, VB, WB for the respective phases are connected to the DC terminal on the low-voltage side, and the second switching elements (switching elements Q3u, Q3v, Q3w) are connected to the AC terminals for the respective phases.

[0117] The clamp diodes D1u, D1v, D1w, connected to the upper branches UA, VA, WA, have anodes connected to the neutral point N. The clamp diodes D2u, D2v, D2w, connected to the lower branches UB, VB, WB, have cathodes connected to the neutral point N.

[0118] In the present embodiment, different switching elements are used for the first switching element (Q1u, Q1v, Q1w), (Q4u, Q4v, Q4w) and the second switching element (Q2u, Q2v, Q2w), (Q3u, Q4v, Q4w) in each of the upper and lower arms of the NPC inverter 11. Hereinafter, the first switching elements (Q1u, Q1v, Q1w) are referred to as first switching elements Q1, and the first switching elements (Q4u, Q4v, Q4w) are referred to as first switching elements Q4. Similarly, the second switching elements (Q2u, Q2v, Q2) are referred to as second switching elements Q2, and the second switching elements (Q3u, Q3v, Q3w) are referred to as second switching elements Q3.

[0119] For the first switching elements Q1, Q4, elements are used in which the switching losses are lower than for the second switching elements Q2, Q3. Meanwhile, for the second switching elements Q2, Q3, elements are used in which the conduction losses due to the on-resistance are lower than for the first switching elements Q1, Q4.

[0120] In this case, SiC (silicon carbide) MOSFETs, which can achieve low switching losses, are used for the first switching elements Q1 and Q4. Furthermore, silicon IGBTs, which can achieve low conduction losses even when a large current flows, are used for the second switching elements Q2 and Q3.

[0121] As described in Embodiment 1 above, the controller 20 generates the modulation phase voltage commands Vua*, Vva*, Vwa* such that each of their polarities is not opposite to the polarity of the corresponding phase current command iu*, iv*, iw* to perform PWM control for the NPC inverter 11. Therefore, for the second switching elements Q2, Q3, the number of times switching can be significantly reduced, but the conduction periods become long.

[0122] Power losses in each of the first and second switching elements (Q1, Q4), (Q2, Q3) can be represented by the sum of switching losses and conduction losses.

[0123] In the present embodiment, elements with small switching losses are used for the first switching elements Q1, Q4 for which the number of switching times is large, and elements with small conduction losses due to on-resistance are used for the second switching elements Q2, Q3 for which the number of switching times is significantly reduced but the conduction periods are long. Consequently, the power losses in each of the first and second switching elements (Q1, Q4), (Q2, Q3) can be effectively reduced, and the loss reduction in the entire NPC inverter 11 can be achieved, so that the power conversion device 1B with high efficiency is obtained.

[0124] The first switching elements Q1, Q4 are not limited to SiC MOSFETs, and they can also be MOSFETs made of a semiconductor material with a wider band gap than silicon. Any element with relatively small switching losses can be used. The second switching elements Q2, Q3 are also not limited to silicon IGBTs, and any element with relatively small conduction losses can be used, even when a large current flows.

[0125] In the present embodiment, as described above, the switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w of the NPC inverter 11 can be configured to reduce losses. In a case where the main controller for the NPC inverter 11 is to supply power to the load 3 through a continuous power operation, it is possible to achieve highly efficient power conversion operation while reducing both the conduction losses and the switching losses in the switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w.

[0126] In particular, in a case where load 3 is a motor for driving an aircraft thrust turbine, most of the operation is continuous power operation, and therefore the effect is large. Since a surface magnet type permanent magnet motor with a high power factor is used as the motor of load 3, the period in which the polarity of the phase voltage and the polarity of the phase current coincide with each other is long. Therefore, both the conduction loss and the switching loss in the switching elements Q1u to Q4u, Q1v to Q4v, and Q1w to Q4w can be more effectively reduced.

[0127] In the present embodiment, the control in Embodiment 1 above is used. However, the control in Embodiment 2 above may be used in the same way, and in this case, too, both the conduction loss and the switching loss in the switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w are reduced, so that a high-efficiency power converter device 1B is obtained.

[0128] In each of the above embodiments, the NPC inverter 10, 11, which is a three-phase, three-level converter, is used as a neutral-point clamp type multi-level converter. However, a multi-phase configuration (more than three phases) and a multi-level converter for more than three levels can also be used.

[0129] The functions of the control device 20, 20A in each of the above embodiments are implemented by a processing circuit.

[0130] Fig. 13 is a configuration diagram showing an example of hardware for implementing the functions of the control device 20, 20A. In this case, the control device 20, 20A is configured by a dedicated processing circuit 30, which is dedicated hardware.

[0131] The dedicated processing circuit 30 is, for example, a single circuit, a complex circuit, a programmed processor, a parallel programmed processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a combination of these.

[0132] Fig.14 is a configuration diagram showing another example of hardware for implementing the functions of the control device 20, 20A. In this case, a processing circuit 30A includes a processor 31 and a memory device 32.

[0133] In the processing circuit 30A, the functions of the control device 20, 20A are implemented through software, firmware, or a combination of software and firmware. The software and firmware are described as a program stored in the memory device 32. The processor 31 reads and executes the program stored in the memory device 32, thus implementing the functions.

[0134] The program stored in the storage device 32 can be considered a component that causes a computer to execute the procedure or method in each unit described above. However, the storage device 32 is, for example, a non-volatile or volatile semiconductor memory such as a random access memory (RAM), a read-only memory (ROM), a flash memory, an erasable programmable read-only memory (EPROM), or an electrically erasable programmable read-only memory (EEPROM). A magnetic disk, a flexible disk, an optical disk, a compact disc, a mini disc, a DVD, or the like can also be used as the storage device 32.

[0135] Of the functions of the control device 20, 20A described above, some may be implemented by dedicated hardware, and others may be implemented by software or firmware.

[0136] Consequently, the processing circuit may implement the functions of the controller 20, 20A as described above by means of hardware, software, firmware, or a combination thereof.

[0137] Although the invention has been described above in terms of various exemplary embodiments and implementations, it should be understood that the various features, aspects, and functionalities described in one or more of the individual embodiments are not limited in their applicability to the particular embodiment in which they are described, but instead may be used alone or in various combinations in one or more of the embodiments of the invention.

[0138] It is therefore understood that numerous modifications not described by way of example may be used without departing from the scope of the present invention. For example, at least one of the components may be modified, added, or omitted. At least one of the components explained in at least one of the preferred embodiments may be selected and combined with the components described in another preferred embodiment. List of reference symbols 1, 1A, 1B power converter device 10, 11 NPC inverters 20, 20A control device 21 Modulation voltage generator 22 PWM modulator 23 Modulation voltage corrector 24 second modulation voltage generator Gu, Gv, Gw gate signal N Neutral point UA, VA, WA upper branch UB, VB, WB lower branch Q1u, Q1v, Q1w first switching element Q2u, Q2v, Q2w second switching element Q3u, Q3v, Q3w second switching element Q4u, Q4v, Q4w first switching element Vu*, Vv*, Vw*, VA* phase voltage command iu*, iv*, iw*, iA* Phase current command iu, iv, iw, iA phase current Vua*, Vva*, Vwa* Modulation phase voltage command Vub*, Vvb*, Vwb* Modulation phase voltage command VX offset voltage VY offset voltage as correction voltage QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2019-30 070 A

[0005]

Claims

[1] Power converter device comprising: a multi-level power converter of the neutral point clamp type that performs energy conversion between DC energy and AC energy; and a control device that performs output control for the power converter by PWM control, wherein the power converter has a multi-phase configuration comprising, in each phase of the power converter, an upper arm and a lower arm, each formed by connecting a first switching element on the DC terminal side and a second switching element on the AC terminal side in series, and a clamp diode connected between the neutral point and a connection point between the first and second switching elements, wherein the control device comprises a modulation voltage generator that generates modulation phase voltage commands based on phase voltage commands and phase currents, and a PWM modulator that generates gate signals for driving the first and second switching elements of the power converter based on the modulation phase voltage commands, and wherein the modulation voltage generator calculates an offset voltage such that - for a middle phase where the high-low rank among the phase voltage commands for the respective phases is in the middle, the polarity of the phase voltage command does not become opposite to the polarity of the phase current, and the offset voltage is superimposed as the first common voltage on the phase voltage commands for the respective phases, thus generating the modulation phase voltage commands. [2] The power conversion device according to claim 1, wherein the phase voltage commands are voltage commands having sinusoidal waveforms, and wherein the modulation voltage generator calculates the offset voltage such that, for the middle phase, the value of the phase voltage command does not become greater than 0 in a period in which the polarity of the phase voltage command is positive and the polarity of the phase current is negative, and the value of the phase voltage command does not become less than 0 in a period in which the polarity of the phase voltage command is negative and the polarity of the phase current is positive. [3] The power converter device according to claim 1 or 2, wherein the modulation voltage generator performs correction by superimposing a second common voltage on the modulation phase voltage commands for the respective phases so that the strengths of the generated modulation phase voltage commands for the respective phases do not become greater than a predetermined voltage based on the DC voltage on the DC terminal side. [4] The power converter device according to claim 3, wherein the modulation voltage generator calculates a correction voltage such that - for a phase in which the magnitude is the largest among the generated modulation phase voltage commands for the respective phases - the value of the modulation phase voltage command takes the predetermined voltage, and superimposes the correction voltage as the second common voltage on the modulation phase voltage commands for the respective phases, thus performing the correction. [5] A power converter device according to any one of claims 1 to 4, wherein the control device generates the modulation phase voltage commands using phase current commands as the phase currents. [6] Power converter device according to one of claims 1 to 5, wherein the power converter is a three-phase three-level power converter. [7] Power converter device according to one of claims 1 to 6, wherein the conduction losses due to the on-resistance of the second switching element are smaller than the conduction losses due to the on-resistance of the first switching element. [8] Power converter device according to one of claims 1 to 7, wherein the switching losses in the first switching element are smaller than the switching losses in the second switching element. [9] A power converter device according to any one of claims 1 to 8, wherein an IGBT made of silicon is used as the second switching element. [10] A power converter device according to any one of claims 1 to 9, wherein a MOSFET made of a semiconductor material having a wider band gap than silicon is used as the first switching element.

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