DISPLAY FIELD AND DISPLAY DEVICE

Abstract

A display substrate and a display device. The display substrate comprises: a base substrate (100); a plurality of pixel units (PX) provided on the base substrate (100); a semiconductor layer (ACT) provided on the base substrate (100); a first electrically conductive layer (10) provided on a side of the semiconductor layer (ACT) close to the base substrate (100); a second electrically conductive layer (20) provided on a side of the semiconductor layer (ACT) farther from the base substrate (100);and a pixel definition layer (PDL) provided on a side of the second electrically conductive layer (20) away from the base substrate (100), wherein the pixel definition layer (PDL) comprises a plurality of apertures (80) for defining light emission areas (SPA1, SPA2, SPA3, SPA4) of a plurality of subpixels (SP1, SP2, SP3, SP4). A pixel driver circuit (SPC1, SPC2, SPC3, SPC4) comprises a sensor transistor (T3), a storage capacitor (Cst) and a capacitor wire (5), wherein the sensor transistor (T3) comprises a source (s3) and a drain (d3), wherein the storage capacitor (Cst) comprises a first capacitor electrode (Cst1) and a second capacitor electrode (Cst2) which are arranged opposite each other, and wherein the capacitor wire (5) serves to electrically connect the source (s3) or the drain (d3) of the sensor transistor (T3) to the second capacitor electrode (Cst2);The source (s3) and drain (d3) of the sensor transistor (T3) are located in the second electrically conductive layer (20), the second capacitor electrode (Cst2) and the capacitor wire (5) are located in the first electrically conductive layer (10), the capacitor wire (5) comprising a capacitor wire main body section (52) extending along a second direction (Y); and for the same subpixel (SP1, SP2, SP3, SP4), the orthographic projection of the capacitor wire main body section (52) of the pixel driver circuit (SPC1, SPC2, SPC3, SPC4) of the subpixel (SP1, SP2, SP3, SP4) on the base substrate (100) is spaced apart from the orthographic projection of the light emission area (SPA1, SPA2, SPA3, SPA4) of the subpixel (SP1, SP2, SP3, SP4) on the base substrate (100).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technology, in particular to a display panel and a display device. STATE OF THE ART

[0002] Organic light-emitting diode (OLED) display panels have the advantages of active light emission, good temperature characteristics, low power consumption, fast response, and flexibility, among others. They have gradually become one of the mainstream display technologies and are increasingly widely used in display devices such as mobile phones, computers, and televisions. Ensuring the transmittance of the light-emitting area is one of the most important issues for researchers and developers when designing the backplane of OLED display panels.

[0003] It should be noted that the information disclosed in the above paragraph on prior art is only intended to enhance the understanding of the background of the present disclosure and may therefore contain information that does not constitute prior art known to a person skilled in the art. DISCLOSURE OF THE INVENTION

[0004] In one aspect, a display substrate is provided, the display substrate comprising: a base substrate; a plurality of pixel units provided on the base substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction, at least one of the pixel units comprising a plurality of sub-pixels, at least one of the sub-pixels comprising a light-emitting element and a pixel driver circuit for driving the light-emitting element; a semiconductor layer provided on the base substrate; a first electrically conductive layer provided on a side of the semiconductor layer near the base substrate; a second electrically conductive layer provided on a side of the semiconductor layer remote from the base substrate; and a pixel definition layer provided on a side of the second electrically conductive layer remote from the base substrate, the pixel definition layer comprising a plurality of openings for defining light emission regions of the plurality of subpixels, wherein the pixel driver circuit comprises a sensor transistor, a storage capacitor, and a capacitor wire, wherein the sensor transistor comprises a source and a drain, wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode provided opposite each other, wherein the capacitor wire serves to electrically connect the source or the drain of the sensor transistor to the second capacitor electrode, wherein the source and drain of the sensor transistor are located in the second electrically conductive layer, wherein the second capacitor electrode and the capacitor wire are located in the first electrically conductive layer, wherein the capacitor wire comprises a capacitor wire main body portion extending along the second direction, and wherein, for the same subpixel, the orthographic projection of the capacitor wire main body portion of the pixel driving circuit of the subpixel on the base substrate is provided spaced from the orthographic projection of the light emitting region of the subpixel on the base substrate.

[0005] According to some exemplary embodiments, the display substrate further comprises a data line for delivering data signals, wherein the data line is located in the second electrically conductive layer, wherein the data line comprises a data line main body portion extending along the second direction; and wherein, for the same subpixel, the orthographic projection of the data line main body portion of the data line for delivering a data signal to the pixel driver circuit of the subpixel on the base substrate at least partially overlaps the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the subpixel on the base substrate.

[0006] According to some exemplary embodiments, for the same subpixel, the orthographic projection of the data line main body portion of the data line for supplying a data signal to the pixel driver circuit of the subpixel on the base substrate completely covers the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the subpixel on the base substrate.

[0007] According to some exemplary embodiments, for the same subpixel, the orthographic projection of the second capacitor electrode of the pixel driver circuit of the subpixel on the base substrate at least partially overlaps with the orthographic projection of the light emitting region of the subpixel on the base substrate; wherein the capacitor wire has a first connecting portion and a second connecting portion, wherein the capacitor wire main body portion is located between the first connecting portion and the second connecting portion, wherein the first connecting portion is connected to the second capacitor electrode, and wherein the second connecting portion is electrically connected to the source or drain of the sensor transistor.

[0008] According to some example embodiments, the display substrate further comprises a third electrically conductive layer located between the semiconductor layer and the second electrically conductive layer; wherein the display substrate further comprises a first auxiliary wire located in the third electrically conductive layer, the first auxiliary wire extending along the second direction and electrically connected to the data line; wherein, for the same subpixel, the orthographic projection of the first auxiliary wire on the base substrate, which is electrically connected to the data line for supplying data signals to the pixel driver circuit of the subpixel, at least partially overlaps the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the subpixel on the base substrate.

[0009] According to some exemplary embodiments, the first capacitor electrode is located in the semiconductor layer; wherein, for the same subpixel, the orthographic projection of the first capacitor electrode of the pixel driver circuit of the subpixel on the base substrate at least partially overlaps with the orthographic projection of the light emission region of the subpixel on the base substrate.

[0010] According to some exemplary embodiments, the display substrate further comprises a first scanning signal line and a second scanning signal line for supplying gate scanning signals, wherein the first scanning signal line and the second scanning signal line are located in the third electrically conductive layer; wherein the pixel driver circuit further comprises a switching transistor, wherein a part of the first scanning signal line that overlaps with the semiconductor layer is the gate of the switching transistor, and wherein a part of the second scanning signal line that overlaps with the semiconductor layer is the gate of the sensor transistor; wherein the first scanning signal line and the second scanning signal line for supplying gate scanning signals to a pixel driver circuit for the same row of subpixels in the second direction are respectively located on both sides of the light emitting area of ​​the same row of subpixels.

[0011] According to some exemplary embodiments, the display substrate further comprises a fourth electrically conductive layer located between the first electrically conductive layer and the semiconductor layer; wherein the display substrate further comprises a third electrically conductive connecting portion located in the fourth electrically conductive layer and a third semiconductor portion located in the semiconductor layer, wherein the third semiconductor portion comprises a third source region, a third drain region, and a channel region of the sensor transistor, wherein the third source region and the third drain region are each located on either side of the channel region of the sensor transistor;wherein the third electrically conductive connecting portion has a first part and a second part, wherein the orthographic projection of the first part of the third electrically conductive connecting portion on the base substrate overlaps with the orthographic projection of the second connecting portion of the capacitor wire on the base substrate, and wherein the orthographic projection of the third source region or the third drain region on the base substrate overlaps with the orthographic projection of the second part of the third electrically conductive connecting portion on the base substrate;

[0012] According to some example embodiments, the display substrate further comprises a first insulating layer and a second insulating layer located between the third electrically conductive layer and the second electrically conductive layer; wherein the display substrate comprises a first via hole penetrating the first insulating layer and a second via hole penetrating the second insulating layer, wherein the first via hole exposes the first part of the third electrically conductive connection portion and the second via hole exposes the first part and the second part of the third electrically conductive connection portion; wherein the orthographic projection of the source or the drain of the sensor transistor on the base substrate overlaps the orthographic projection of each of the first via hole and the second via hole on the base substrate.

[0013] According to some exemplary embodiments, the display substrate further comprises a first electrically conductive connecting portion located in the fourth electrically conductive layer, wherein the orthographic projection of the first electrically conductive connecting portion on the base substrate at least partially overlaps the orthographic projection of the first capacitor electrode on the base substrate.

[0014] According to some exemplary embodiments, the pixel driver circuit further comprises a driver transistor comprising a channel region, a gate, a source, and a drain; wherein the display substrate further comprises a first semiconductor portion located in the semiconductor layer, the first semiconductor portion comprising a first source region, a first drain region, and the channel region of the driver transistor, the first source region and the first drain region being located on either side of the channel region of the driver transistor, respectively;wherein the display substrate includes a third through-hole penetrating the first insulating layer and a fourth through-hole penetrating the second insulating layer, the third through-hole exposing a part of the first electrically conductive connecting portion, and the fourth through-hole exposing a part of the first source region or the first drain region and the third through-hole; wherein the orthographic projection of the source region or the drain region of the driver transistor on the base substrate overlaps the orthographic projection of each of the third through-hole and the fourth through-hole on the base substrate.

[0015] According to some exemplary embodiments, the switching transistor comprises a channel region, wherein the display substrate further comprises a second semiconductor portion located in the semiconductor layer, wherein the second semiconductor portion comprises a second source region, a second drain region, and the channel region of the switching transistor, wherein the second source region and the second drain region are each located on either side of the channel region of the switching transistor; wherein the second capacitor electrode and the second semiconductor portion are a continuously extending, one-piece structure.

[0016] According to some exemplary embodiments, the display substrate includes a fifth through-hole penetrating the second insulating layer; wherein the fifth through-hole exposes a part of the gate of the driver transistor and a part of the first capacitor electrode, wherein the source or drain of the switching transistor, the gate of the driver transistor, and the first capacitor electrode are electrically connected via the fifth through-hole.

[0017] According to some exemplary embodiments, two data lines are provided between two adjacent subpixels located in the same row, wherein the two adjacent subpixels located in the same row comprise a first subpixel and a second subpixel, wherein the two data lines comprise a first data line and a second data line; wherein the first data line is for supplying a data signal to the first subpixel, and wherein the orthographic projection of the data line main body portion of the data line for supplying a data signal to the pixel driver circuit of the first subpixel on the base substrate completely covers the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the first subpixel on the base substrate;wherein the second data line serves to supply a data signal to the second subpixel, and wherein the orthographic projection of the data line main body portion of the data line for supplying a data signal to the pixel driver circuit of the second subpixel on the base substrate completely covers the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the second subpixel on the base substrate;

[0018] According to some exemplary embodiments, the first connection portion of the capacitor wire of the pixel driver circuit of the first subpixel extends along the first direction toward the first data line, and wherein the first connection portion of the capacitor wire of the pixel driver circuit of the second subpixel extends along the first direction toward the second data line.

[0019] According to some exemplary embodiments, the display substrate further comprises a sensor signal line located in the second electrically conductive layer, the sensor signal line comprising a first part extending along the second direction and a second part extending along the first direction; wherein, in the first direction, the second subpixel is arranged adjacent to the sensor signal line and the first subpixel is located on the side of the second subpixel remote from the sensor signal line.

[0020] According to some exemplary embodiments, the display substrate further comprises a second electrically conductive connecting portion located in the fourth electrically conductive layer; wherein one end of the second electrically conductive connecting portion is electrically connected to another of the source and drain of the sensor transistor of the pixel driver circuit of the first subpixel via a sixth via-hole, and wherein another end of the second electrically conductive connecting portion is electrically connected to another of the source and drain of the sensor transistor of the pixel driver circuit of the second subpixel via a seventh via-hole.

[0021] According to some exemplary embodiments, the second part of the sensor signal line is electrically connected via an eighth through-hole to the other end of the second electrically conductive connecting portion and another of the source and drain of the sensor transistor of the pixel driver circuit of the second sub-pixel.

[0022] According to some exemplary embodiments, the display substrate further comprises a second auxiliary wire located in the third electrically conductive layer, the second auxiliary wire extending along the second direction and being electrically connected to the sensor signal line, the orthographic projection of the second auxiliary wire on the base substrate at least partially overlapping the orthographic projection of the sensor signal line on the base substrate.

[0023] According to some exemplary embodiments, the material of the first electrically conductive layer includes a transparent conductive material; and / or the material of the fourth electrically conductive layer includes a light-shielding material.

[0024] In another aspect, a display device is provided, the display device comprising the display substrate described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the figures and may contribute to a complete understanding of the present disclosure. Fig. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure; Fig. 3 to Fig. 12 are partial plan views of at least one film layer of a display substrate according to some exemplary embodiments of the present disclosure, wherein Fig. 3 schematically shows a partial plan view of a first electrically conductive layer of the display substrate, Fig. 4 schematically shows a partial plan view of a combination of the first electrically conductive layer and a fourth electrically conductive layer of the display substrate, Fig. 5 schematically shows a partial plan view of a semiconductor layer of the display substrate, Fig. 6 schematically shows a partial plan view of a combination of the first electrically conductive layer, the fourth electrically conductive layer and the semiconductor layer of the display substrate, Fig. 7 schematically shows a partial plan view of a third electrically conductive layer of the display substrate, Fig. 8 schematically shows a partial plan view of a combination of the first electrically conductive layer, the fourth electrically conductive layer, the semiconductor layer and the third electrically conductive layer of the display substrate, Fig. 9 schematically shows a partial plan view of a combination of the first electrically conductive layer, the fourth electrically conductive layer, the semiconductor layer, the third electrically conductive layer and a first insulating layer of the display substrate, Fig. 10 schematically shows a partial plan view of a combination of the first electrically conductive layer, the fourth electrically conductive layer, the semiconductor layer, the third electrically conductive layer, the first insulating layer and a second insulating layer of the display substrate, Fig. 11 schematically shows a partial plan view of a second electrically conductive layer of the display substrate, Fig. 12 schematically shows a partial plan view of a combination of the first electrically conductive layer, the fourth electrically conductive layer, the semiconductor layer, the third electrically conductive layer, the first insulating layer, the second insulating layer and the second electrically conductive layer of the display substrate; Fig. 13 is a partial plan view of a display substrate according to some example embodiments of the present disclosure; and Fig. 14 is a sectional view of a display substrate taken along the line AA' in Fig. 13 according to some exemplary embodiments of the present disclosure.

[0026] It should be noted that in the drawings used to describe embodiments of the present disclosure, the dimensions of layers, structures, or regions may be exaggerated or reduced for clarity, i.e., these drawings are not drawn to scale. EMBODIMENTS OF THE INVENTION

[0027] The technical solutions of the present disclosure are described in more detail below using exemplary embodiments and in conjunction with the drawings. Throughout the description, identical or similar reference numerals denote identical or similar components. The following description of the embodiments of the present disclosure with reference to the drawings is intended to explain the general inventive concept of the present disclosure and is not to be understood as limiting the present disclosure.

[0028] In the following detailed description, numerous specific details are set forth to facilitate explanation and to provide a thorough understanding of embodiments of the present disclosure. However, it will be apparent that one or more embodiments may be practiced without these specific details.

[0029] It should be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element. The term "and / or" as used herein encompasses any combination and all combinations of one or more of the related listed items.

[0030] It should be understood that when an element or layer is described as being "formed on another element or layer," the element or layer may be formed directly or indirectly on the other element or layer. That is, there may be, for example, intermediate elements or layers. On the other hand, when an element or layer is described as being "formed directly on another element or layer," there are no intermediate elements or layers. Other terms used to describe relationships between elements or layers (e.g., "between" and "immediately between," "adjacent to" and "immediately adjacent to," etc.) should be interpreted similarly.

[0031] Throughout this text, the directional terms "first direction" and "second direction" are used to describe various directions of the pixel array, such as a transverse direction and a longitudinal direction of the pixel array. It is understood that such terms are merely exemplary descriptions and do not constitute a limitation on the present disclosure.

[0032] Unless otherwise specified, the term "in the same layer" in this text generally means that a first component and a second component may be made of the same material and formed by the same patterning process. The term "A is integrally bonded to B" means that component A and component B are integrally formed, i.e., they generally comprise the same material and are formed into a structurally coherent, integral component.

[0033] The transistors used in the embodiment of the present disclosure may be thin-film transistors or field-effect transistors, or other devices with similar characteristics. Since the source and drain of the thin-film transistors used here are symmetrical, the source and drain can be interchanged. In the following examples, a P-type thin-film transistor is primarily described as the driver transistor, and other transistors are of the same or different type as the driver transistor, depending on the circuit design. Similarly, in other embodiments, the driver transistor may also be represented as an N-type thin-film transistor.

[0034] Some exemplary embodiments of the present disclosure provide a display substrate, the display substrate comprising: a base substrate; a plurality of pixel units provided on the base substrate, the plurality of pixel units being provided in an array along a first direction and a second direction, at least one of the pixel units comprising a plurality of subpixels, at least one of the subpixels comprising a light-emitting element and a pixel driver circuit for driving the light-emitting element; a semiconductor layer provided on the base substrate; a first electrically conductive layer provided on a side of the semiconductor layer near the base substrate; a second electrically conductive layer provided on a side of the semiconductor layer remote from the base substrate; and a pixel definition layer,which is provided on a side of the second electrically conductive layer remote from the base substrate, wherein the pixel definition layer comprises a plurality of openings for defining light-emitting regions of the plurality of subpixels, wherein the pixel driver circuit comprises a sensor transistor, a storage capacitor, and a capacitor wire, wherein the sensor transistor comprises a source and a drain, wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode provided opposite each other, wherein the capacitor wire serves to electrically connect the source or the drain of the sensor transistor to the second capacitor electrode, wherein the source and the drain of the sensor transistor are located in the second electrically conductive layer, wherein the second capacitor electrode and the capacitor wire are located in the first electrically conductive layer,The capacitor wire has a capacitor wire main body portion extending along the second direction, and for the same subpixel, the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the subpixel on the base substrate is spaced from the orthographic projection of the subpixel's light-emitting region on the base substrate. In the embodiment of the present disclosure, by placing most of the capacitor wire (e.g., the capacitor wire main body portion) outside the light-emitting region of the subpixel, its blocking effect on the light emitted from the light-emitting region can be reduced, thereby improving the light transmittance of the light-emitting region. In this way, the display quality of the display substrate can be improved without affecting the driving of the sensor transistor.

[0035] Fig. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure, and Fig. 13 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing more specific structures of the display substrate. In conjunction with Fig. 1 and Fig. 13, the display substrate according to an embodiment of the present disclosure may include a base substrate 100, pixel units PX provided on the base substrate 100, drive units DRU provided on the base substrate 100, and wires PL electrically connecting the pixel units PX to the drive units DRU, wherein the drive units DRU are for driving the pixel units PX.

[0036] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where pixel units PX for displaying an image are provided. Each pixel unit PX will be described later. The non-display area NA is an area where no pixel units PX are provided, that is, it may be an area where no image is displayed. The drive units DRU for driving the pixel units PX and some wires PL for connecting the pixel units PX to the drive units DRU may be provided in the non-display area NA. The non-display area NA corresponds to the frame in the final display device, and the width of the frame can be determined according to the width of the non-display area NA.

[0037] The display area AA can have various shapes. The display area AA can be provided with various shapes, such as a polygon (e.g., a rectangle) of closed shape with straight edges, a circle or ellipse with curved edges, and a semicircle or semi-ellipse with straight and curved edges, etc. In the embodiment of the present disclosure, the display area AA is provided as an area having a quadrangular shape with straight edges. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the disclosure.

[0038] The non-display area NA may be provided on at least one side of the display area AA. In the embodiment of the present disclosure, the non-display area NA may surround the perimeter of the display area AA. In the embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0039] The pixel units PX are provided in the display area AA. One pixel unit PX is the smallest unit for displaying an image, and a plurality of pixel units PX may be provided. For example, the pixel units PX may include light-emitting elements that emit white light and / or colored light.

[0040] A plurality of pixel units PX may be provided and arranged in a matrix form with rows extending in the first direction X and columns extending in the first direction Y. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel units PX, and the pixel units PX may be arranged in various forms. For example, the pixel units PX may be arranged such that a direction inclined with respect to the first direction X and the first direction Y becomes the column direction, and a direction intersecting the column direction becomes the row direction.

[0041] A pixel unit PX may comprise a plurality of subpixels. For example, a pixel unit PX may comprise three subpixels, namely a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. As another example, a pixel unit PX may comprise four subpixels, namely a first subpixel SP1, a second subpixel SP2, a third subpixel SP3, and a fourth subpixel SP4. For example, the first subpixel SP1 may be a red subpixel, the second subpixel SP2 a green subpixel, the third subpixel SP3 a blue subpixel, and the fourth subpixel SP4 a white subpixel.

[0042] Each subpixel may include a light-emitting element and a pixel driver circuit for driving the light-emitting element. For example, the first subpixel SP1 may include a first light-emitting element located in a first light-emitting region SPA1 and a first pixel driver circuit SPC1 for driving the first light-emitting element, wherein the first light-emitting element can emit red light; the second subpixel SP2 may include a second light-emitting element located in a second light-emitting region SPA2 and a second pixel driver circuit SPC2 for driving the second light-emitting element, wherein the second light-emitting element can emit green light;The third subpixel SP3 may include a third light-emitting element located in a third light-emitting region SPA3 and a third pixel driver circuit SPC3 for driving the third light-emitting element, wherein the third light-emitting element can emit blue light; The fourth subpixel SP4 may include a fourth light-emitting element located in a fourth light-emitting region SPA4 and a fourth pixel driver circuit SPC4 for driving the fourth light-emitting element.

[0043] The light-emitting region of the subpixel may be a region in which the light-emitting element of the subpixel is located. For example, in an OLED display substrate, the light-emitting element of the subpixel may include a first electrode (e.g., an anode), a light-emitting material layer, and a second electrode (e.g., a cathode) provided in layers one above the other. In this way, the light-emitting region of the subpixel may be a region corresponding to a portion of the light-emitting material layer between the anode and the cathode. As another example, in an OLED display substrate, the display substrate may include a pixel definition layer provided on the base substrate 100, wherein the pixel definition layer may include a plurality of openings corresponding to a plurality of subpixels, the plurality of openings each defining the light-emitting regions of the plurality of subpixels.

[0044] The subpixel also includes a non-light-emitting area. For example, part of the subpixel's pixel driver circuitry is located in the subpixel's non-light-emitting area. The ratio of the area of ​​the light-emitting area of ​​each subpixel to the total area of ​​the subpixel (the sum of the areas of the light-emitting area and the non-light-emitting area) determines the subpixel's aperture ratio.

[0045] The consistency of light-emitting elements of OLEDs (e.g., the light-emitting layer, referred to as EL layer for short) may not be good enough during manufacturing. For example, when the EL layers are fabricated by evaporation, the limitations of the evaporation process lead to inconsistency in the EL layers of each fabricated subpixel, resulting in uneven luminescence or chromaticity between different subpixels. Furthermore, the EL layers may age to varying degrees with increasing usage time, which also leads to inconsistency in the EL layers of each subpixel, resulting in uneven luminescence or chromaticity between different subpixels. In the embodiment of the present disclosure, the display substrate may further include a light-sensitive circuit OSC that can sense the actual light emitted by the pixel units.Thus, in the embodiment of the present disclosure, the display substrate can perform optical compensation for the subpixels within each pixel unit based on the light actually emitted by the pixel units sensed by the light-sensitive circuit OSC to improve the uniformity of light emission of the display substrate.

[0046] For example, in some exemplary embodiments of the present disclosure, a light-sensitive circuit OSC is provided in each pixel unit PX. Each light-sensitive circuit OSC senses the light actually emitted by the pixel unit PX in which it is located.

[0047] For example, in the embodiment of the present disclosure, at least two pixel units PX may share one photosensitive circuit OSC. For pixel units within the same column, two pixel units PX located in two adjacent rows may share one photosensitive circuit OSC. This eliminates the need to provide a photosensitive circuit for each pixel unit PX, which can reduce the number of photosensitive circuits and thereby increase the aperture ratio.

[0048] When the display substrate is in the display state, the light-sensitive circuit OSC can sense the light actually emitted by the two adjacent pixel units. For example, the light-sensitive circuit OSC can comprise at least one photoelectric conversion element. In this way, the light-sensitive circuit OSC can be configured to sense the light actually emitted by the two adjacent pixel units and transmit an electrical sensing signal based on the sensed light.

[0049] As a further example, with reference to Fig. 1, the light-sensitive circuit OSC sends the electrical sensing signal to an external circuit, such as a control IC of the display device. The control IC can control a control signal sent to the pixel unit PX based on the electrical sensing signal. For example, the control IC can control a data signal sent to the pixel driver circuit of each subpixel. Under the control of the data signal, each subpixel emits light accordingly.

[0050] In the embodiment according to Fig. 1, the subpixels SP1, SP2, SP3, SP4 are provided next to each other, and each subpixel SP1, SP2, SP3, SP4 can have its own data line DL.

[0051] Fig. 2 is an equivalent circuit diagram of a pixel circuit for a single subpixel of the display substrate in Fig. 1. The Fig. The pixel driver circuit shown in Figure 2 may be one of the above-mentioned pixel driver circuits SPC1, SPC2, SPC3, SPC4. Referring to Fig. 2, the pixel driver circuit may include multiple elements, such as a driver transistor T1, a switching transistor T2, a sensor transistor T3, and a storage capacitor Cst. This pixel driver circuit may be referred to as a 3T1C structure.

[0052] It should be noted that the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is described here using the 3T1C structure as an example. However, the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is not limited to the 3T1C structure.

[0053] With further reference to Fig. 2, a gate g2 of the switching transistor T2 is electrically connected to a first scanning signal line GL1, a first electrode of the switching transistor T2 is electrically connected to a data line DL, and a second electrode of the switching transistor T2 is electrically connected to a gate g1 of the driver transistor T1. For example, the second electrode of the switching transistor T2 and the gate g1 of the driver transistor T1 may be electrically connected to a node GN. The switching transistor T2 serves to control the writing of a voltage signal from the data line DL to the pixel driver circuit.

[0054] It should be noted that each transistor may include an active layer, a gate, a first electrode (e.g., a source), and a second electrode (e.g., a drain). For example, the switching transistor T2 includes a gate g2 and an active layer ACT2; the driver transistor T1 includes a gate g1 and an active layer ACT1; and the sensor transistor T3 includes a gate g3 and an active layer ACT3. In the embodiment of the present disclosure, the active layer of the transistor may be located in a semiconductor layer, and the gate may be located in an electrically conductive layer of the semiconductor layer remote from the base substrate.

[0055] It should be noted that in this text, the first electrode of the transistor can refer to either the source (e.g., s1, s2, s3) or the drain (e.g., d1, d2, d3) of the transistor, and that the second electrode of the transistor can refer to the other of the source (e.g., s1, s2, s3) and drain (e.g., d1, d2, d3) of the transistor.

[0056] The gate g1 of the driver transistor T1 is electrically connected to the node GN. The first electrode of the driver transistor T1 is electrically connected to a first power supply signal (e.g., a high-voltage level signal VDD), and the second electrode of the driver transistor T1 may be electrically connected to the anode of the light-emitting element OLED, so that a drive current can be generated based on the voltage signal to drive the light-emitting element OLED to emit light. The light-emitting element OLED may, for example, be an organic light-emitting diode (OLED).

[0057] The two ends of the storage capacitor Cst are respectively electrically connected to the gate g1 and the drain d1 of the driver transistor T1 and serve to store the voltage signal input from the data line DL. For example, one end of the storage capacitor Cst is electrically connected to the node GN, and the other end of the storage capacitor Cst is electrically connected to the node SN. The storage capacitor Cst may include, for example, a first capacitor electrode Cst1 and a second capacitor electrode Cst2. The first capacitor electrode Cst1 of the storage capacitor Cst, the second electrode (e.g., drain d2) of the switching transistor T2, and the gate g1 of the driver transistor T1 are each electrically connected to the node GN. The second capacitor electrode Cst2 of the storage capacitor Cst, the second electrode (e.g., drain d1) of the driver transistor T1, and the anode of the light-emitting element OLED are each electrically connected to the node SN.

[0058] The gate g3 of the sensor transistor T3 is electrically connected to a second sensing signal line GL2, the first electrode (e.g., source s3) of the sensor transistor T3 is electrically connected to a sensor signal line SL, and the second electrode (e.g., drain d3) of the sensor transistor T3 is electrically connected to the node SN. That is, the second capacitor electrode Cst2 of the storage capacitor Cst, the second electrode (e.g., drain d1) of the driver transistor T1, the anode of the light-emitting element OLED, and the second electrode (e.g., drain d3) of the sensor transistor T3 are each electrically connected to the node SN.

[0059] The anode of the OLED light-emitting element is electrically connected to node SN. The cathode of the OLED light-emitting element is electrically connected to a second power supply signal (e.g., a low-voltage level signal VSS). The level signals VDD and VSS are DC signals that serve to provide the required voltage to drive the OLED light-emitting element to emit light.

[0060] Fig. 13 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, and Fig. 3 to Fig. 12 are partial plan views of at least one film layer of a display substrate according to some exemplary embodiments of the present disclosure, wherein Fig. 3 schematically shows a partial plan view of a first electrically conductive layer of the display substrate, Fig. 4 schematically shows a partial plan view of a combination of the first electrically conductive layer and a fourth electrically conductive layer of the display substrate, Fig. 5 schematically shows a partial plan view of a semiconductor layer of the display substrate, Fig. 6 schematically shows a partial plan view of a combination of the first electrically conductive layer, the fourth electrically conductive layer and the semiconductor layer of the display substrate, Fig. 7 schematically shows a partial plan view of a third electrically conductive layer of the display substrate, Fig. 8 schematically shows a partial plan view of a combination of the first electrically conductive layer, the fourth electrically conductive layer, the semiconductor layer and the third electrically conductive layer of the display substrate, Fig. 9 schematically shows a partial plan view of a combination of the first electrically conductive layer, the fourth electrically conductive layer, the semiconductor layer, the third electrically conductive layer and a first insulating layer of the display substrate, Fig. 10 schematically shows a partial plan view of a combination of the first electrically conductive layer, the fourth electrically conductive layer, the semiconductor layer, the third electrically conductive layer, the first insulating layer and a second insulating layer of the display substrate, Fig. 11 schematically shows a partial plan view of a second electrically conductive layer of the display substrate, Fig. 12 schematically shows a partial plan view of a combination of the first electrically conductive layer, the fourth electrically conductive layer, the semiconductor layer, the third electrically conductive layer, the first insulating layer, the second insulating layer and the second electrically conductive layer of the display substrate. Fig. 14 is a sectional view of a display substrate taken along the line AA' in Fig. 13 according to some exemplary embodiments of the present disclosure.

[0061] With reference to Fig. 3 to Fig. 14, the display substrate may include a plurality of electrically conductive layers, a semiconductor layer, and a plurality of insulating layers. For convenience of description, the plurality of electrically conductive layers are described as a first electrically conductive layer, a second electrically conductive layer, a third electrically conductive layer, and a fourth electrically conductive layer, respectively.

[0062] The display substrate may include: a base substrate 100, a first electrically conductive layer 10 provided on the base substrate 100, a third insulating layer IDL3 provided on the side of the first electrically conductive layer 10 remote from the base substrate 100, a fourth electrically conductive layer 40 provided on the side of the third insulating layer IDL3 remote from the base substrate 100, a buffer layer BFL provided on the side of the fourth electrically conductive layer 40 remote from the base substrate 100, a semiconductor layer ACT provided on the side of the buffer layer BFL remote from the base substrate 100, a gate insulating layer GIL provided on the side of the semiconductor layer ACT remote from the base substrate 100, a third electrically conductive layer 30 provided on the side of the gate insulating layer remote from the base substrate 100 GIL is intended,a first insulating layer IDL1 provided on the side of the third electrically conductive layer 30 remote from the base substrate 100, a second insulating layer IDL2 provided on the side of the first insulating layer IDL1 remote from the base substrate 100, a second electrically conductive layer 20 provided on the side of the second insulating layer IDL2 remote from the base substrate 100, a fourth insulating layer IDL4 provided on the side of the second electrically conductive layer 20 remote from the base substrate 100, a first electrode layer 300 provided on the side of the fourth insulating layer IDL4 remote from the base substrate 100, a pixel definition layer PDL provided on the side of the first electrode layer 300 remote from the base substrate 100, a light-emitting material layer EL provided on the side of the pixel definition layer PDL remote from the base substrate 100 is intended,and a second electrode layer 600 provided on the side of the light-emitting material layer EL remote from the base substrate 100.

[0063] It should be noted that the above-mentioned individual insulating layers may comprise a single-layer structure or a lamination structure consisting of a plurality of insulating layers. For example, the fourth insulating layer IDL4 may comprise at least one passivation layer and at least one planarization layer. The specific structure of the insulating layers is not particularly limited in the embodiment of the present disclosure.

[0064] Reference is made to Fig. 3, which schematically shows a partial top view of the first electrically conductive layer 10. The material of the first electrically conductive layer 10 may be a transparent conductive material, such as indium tin oxide (ITO for short). The second capacitor electrode Cst2 of the storage capacitor Cst may be located within the first electrically conductive layer 10. In the embodiment of the present disclosure, the display substrate may further comprise a capacitor wire 5 for electrically connecting the storage capacitor Cst to the sensor transistor T3. Specifically, the capacitor wire 5 may serve to electrically connect the second capacitor electrode Cst2 of the storage capacitor Cst to the source s3 or the drain d3 of the sensor transistor T3. As shown in Fig. As shown in Figure 3, the capacitor wire 5 may include a first connecting portion 51, a second connecting portion 53, and a capacitor wire main body portion 52. The capacitor wire main body portion 52 extends along the second direction Y and is located between the first connecting portion 51 and the second connecting portion 53. The first connecting portion 51 is connected to the second capacitor electrode Cst2. The second connecting portion 53 is electrically connected to the source s3 or drain d3 of the sensor transistor T3 (described in detail below).

[0065] In some exemplary embodiments of the present disclosure, the second capacitor electrode Cst2 and the capacitor wire 5 for one and the same subpixel are formed as a continuously extending one-piece structure. For example, as shown in Fig. 3 schematically illustrates a partial top view of the first electrically conductive layer 10 for four subpixels within the same pixel unit. For each subpixel, the second capacitor electrode Cst2 has a block pattern with a relatively large area, and the capacitor wire 5 has a stripe pattern with a relatively large aspect ratio. The block pattern and the stripe pattern are interconnected, thus forming a continuously extending, integral structure. Thus, it is advantageous to form the second capacitor electrode and the capacitor wire on the same layer using the same patterning process.

[0066] It should be noted that, unless otherwise specified, the term "a continuously extending, integral structure" used herein means that at least two components on the same layer extend continuously and without interruption. That is, at least two closely spaced ends are connected to each other in the at least two components.

[0067] For example, in some exemplary embodiments of the present disclosure, for each subpixel, the first connection portion 51 of the capacitor wire 5 extends along the first direction X, and the second connection portion 52 of the capacitor wire 5 extends along the second direction Y. The extension direction of the third connection portion 53 of the capacitor wire 5 may be provided flexibly. For example, it may be provided flexibly according to the position of the source s3 or the drain d3 of the sensor transistor T to which it is to be connected. The third connection portion 53 may extend along the first direction X, or along the second direction Y, or along a direction inclined to both the first direction X and the second direction Y.

[0068] For the same subpixel, the orthographic projection of the second capacitor electrode Cst2 of the pixel driver circuit of that subpixel on the base substrate 100 at least partially overlaps with the orthographic projection of the light emission region of that subpixel on the base substrate 100.

[0069] Reference is made to Fig. 4, which schematically shows a partial plan view of the first electrically conductive layer 10 and the fourth electrically conductive layer 40. The material of the fourth electrically conductive layer 40 may include a light-shielding material, such as a metallic material. In the embodiment of the present disclosure, the display substrate may further include a first electrically conductive connecting portion 41, a second electrically conductive connecting portion 42, a third electrically conductive connecting portion 43, and a fourth electrically conductive connecting portion 44 located in the fourth electrically conductive layer 40. For the same subpixel, the first electrically conductive connecting portion 41, the second electrically conductive connecting portion 42, the third electrically conductive connecting portion 43, and the fourth electrically conductive connecting portion 44 are provided spaced apart from each other.

[0070] For the same subpixel, the orthographic projection of the first electrically conductive connecting portion 41 on the base substrate 100 at least partially overlaps with the orthographic projection of the second capacitor electrode Cst2 on the base substrate 100. The orthographic projection of the third electrically conductive connecting portion 43 on the base substrate 100 at least partially overlaps with the orthographic projection of the capacitor wire 5 on the base substrate 100.

[0071] For example, the orthographic projection of the third electrically conductive connecting portion 43 on the base substrate 100 at least partially overlaps with the orthographic projection of the second connecting portion 53 of the capacitor wire 5 on the base substrate 100. The orthographic projection of each of the second electrically conductive connecting portion 42 and the fourth electrically conductive connecting portion 44 on the base substrate 100 does not overlap with the orthographic projection of each of the second capacitor electrode Cst2 and the capacitor wire 5 on the base substrate 100.

[0072] Reference is made to Fig. 5, which schematically shows a partial plan view of the semiconductor layer ACT; and reference is made to Fig. 6, which schematically shows a partial top view of the first electrically conductive layer 10, the fourth electrically conductive layer 40, and the semiconductor layer ACT. In the embodiment of the present disclosure, the semiconductor layer ACT may include various types of semiconductor materials, such as amorphous silicon semiconductor materials, polycrystalline silicon semiconductor materials, and metal oxide semiconductor materials. Referring to Fig. 5 and Fig. 6, the display substrate in the embodiment of the present disclosure may further include a first semiconductor portion 301, a second semiconductor portion 302, and a third semiconductor portion 303 located in the semiconductor layer ACT. The first capacitor electrode Cst1 of the storage capacitor Cst is located in the semiconductor layer ACT.

[0073] For example, the first semiconductor portion 301 corresponds to the driver transistor T1 and may include a source region 301s, a drain region 301d, and a channel region 301c. The channel region 301c is the channel region of the driver transistor T1, and the source region 301s and the drain region 301d correspond to the source s1 and the drain d1 of the driver transistor T1, respectively. It is understood that the channel region may have semiconductor properties, and that the source region and the drain region may be semiconductor portions that have undergone a conductorization process. For example, they may be doped semiconductor portions.

[0074] For example, the second semiconductor portion 302 corresponds to the switching transistor T2 and may include a source region 302s, a drain region 302d, and a channel region 302c. The channel region 302c is the channel region of the switching transistor T2, and the source region 302s and the drain region 302d correspond to the source s2 and the drain d2 of the switching transistor T2, respectively.

[0075] For example, the third semiconductor portion 303 corresponds to the sensor transistor T3 and may include a source region 303s, a drain region 303d, and a channel region 303c. The channel region 303c is the channel region of the sensor transistor T3, and the source region 303s and the drain region 303d correspond to the source s3 and the drain d3 of the sensor transistor T3, respectively.

[0076] In the embodiment of the present disclosure, the first capacitor electrode Cst1 of the storage capacitor Cst is located in the semiconductor layer ACT. It should be understood that the first capacitor electrode Cst1 of the storage capacitor Cst may be a semiconductor portion that has undergone a conductorization process. For example, it may be a doped semiconductor portion.

[0077] For the same subpixel, the orthographic projection of the first capacitor electrode Cst1 of the storage capacitor Cst on the base substrate 100 at least partially overlaps with the orthographic projection of the second capacitor electrode Cst2 of the storage capacitor Cst on the base substrate 100. In this way, the first capacitor electrode Cst1 and the second capacitor electrode Cst2 are provided opposite each other to form the storage capacitor Cst. That is, in the embodiment of the present disclosure, one of the capacitor electrodes of the storage capacitor in the pixel driver circuit of the subpixel includes a transparent conductive material, and the other capacitor electrode includes a semiconductor material such as a metal oxide semiconductor.

[0078] In the embodiment of the present disclosure, the first capacitor electrode Cst1 of the storage capacitor Cst and the second semiconductor portion 302 are formed as a continuously extending, one-piece structure. Thus, it is advantageous to form semiconductor patterns of the first capacitor electrode and the switching transistor for the pixel driver circuit of the same subpixel through the same patterning process.

[0079] For the same subpixel, the combination of the first capacitor electrode Cst1 of the storage capacitor Cst and the second semiconductor section 302, the first semiconductor section 301 and the third semiconductor section 303 are provided spaced apart from each other.

[0080] For the same subpixel, the orthographic projection of the first capacitor electrode Cst1 of the pixel driver circuit of the subpixel on the base substrate 100 at least partially overlaps with the orthographic projection of the light emission region of the subpixel on the base substrate. That is, at least a portion of the first capacitor electrode Cst1 is located within the light emission region.

[0081] In some exemplary embodiments of the present disclosure, for the same subpixel, the orthographic projection of the first semiconductor portion 301 on the base substrate 100 at least partially overlaps with the orthographic projection of the first electrically conductive connection portion 41 on the base substrate 100, and the orthographic projection of the first semiconductor portion 301 on the base substrate 100 at least partially overlaps with the orthographic projection of the second capacitor electrode Cst2 on the base substrate 100.For the same subpixel, for example, the orthographic projection of the first semiconductor portion 301 on the base substrate 100 falls within the orthographic projection of the first electrically conductive connecting portion 41 on the base substrate 100, and the orthographic projection of the first semiconductor portion 301 on the base substrate 100 falls within the orthographic projection of the second capacitor electrode Cst2 on the base substrate 100.

[0082] In some exemplary embodiments of the present disclosure, for the same subpixel, the orthographic projection of the third semiconductor portion 303 on the base substrate 100 at least partially overlaps with the orthographic projection of the second electrically conductive connecting portion 42 on the base substrate 100, and the orthographic projection of the third semiconductor portion 303 on the base substrate 100 at least partially overlaps with the orthographic projection of the third electrically conductive connecting portion 43 on the base substrate 100.For example, for the same subpixel, the orthographic projection of one end of the third semiconductor portion 303 on the base substrate 100 at least partially overlaps with the orthographic projection of the second electrically conductive connecting portion 42 on the base substrate 100, and the orthographic projection of another end of the third semiconductor portion 303 on the base substrate 100 at least partially overlaps with the orthographic projection of the third electrically conductive connecting portion 43 on the base substrate 100.

[0083] Reference is made to Fig. 7, which schematically shows a partial plan view of the third electrically conductive layer 30; and reference is made to Fig. 8, which schematically shows a partial top view of the first electrically conductive layer 10, the fourth electrically conductive layer 40, the semiconductor layer ACT, and the third electrically conductive layer 30. In the embodiment of the present disclosure, the third electrically conductive layer 30 may include various types of gate materials. Referring to Fig. 7 and Fig. 8, in the embodiment of the present disclosure, the display substrate may further include a first gate conductor portion 31, a second gate conductor portion 32, a first auxiliary wire 33, a second auxiliary wire 34, and a third auxiliary wire 35 located in the third electrically conductive layer 30. The display substrate may further include a first scanning signal line GL1 and a second scanning signal line GL2 for supplying gate scanning signals, wherein the first scanning signal line GL1 and the second scanning signal line GL2 are located in the third electrically conductive layer 30.

[0084] For example, the first gate conductor section 31 corresponds to the driver transistor T1. The orthographic projection of the first gate conductor section 31 on the base substrate 100 at least partially overlaps with the orthographic projection of the first semiconductor section 301 (e.g., the channel region 301c of the driver transistor T1) on the base substrate 100. The part of the first gate conductor section 31 that overlaps with the channel region 301c of the driver transistor T1 forms the gate g1 of the driver transistor T1.

[0085] For example, the first scanning signal line GL1 corresponds to the switching transistor T2. The orthographic projection of the first scanning signal line GL1 on the base substrate 100 at least partially overlaps with the orthographic projection of the second semiconductor portion 302 (e.g., the channel region 302c of the switching transistor T2) on the base substrate 100. The part of the first scanning signal line GL1 that overlaps with the channel region 302c of the switching transistor T2 forms the gate g2 of the switching transistor T2. For example, the first scanning signal line GL1 includes a protruding portion that protrudes along the second direction Y and is the aforementioned second gate conductor portion 32.In the embodiment of the present disclosure, the first scanning signal line GL1 is located below the channel region 302c of the switching transistor T2 in the second direction Y, and the second gate conductor portion 32 of the first scanning signal line GL1 extends along an upward direction toward the channel region 302c of the switching transistor T2.

[0086] For example, the second scanning signal line GL2 corresponds to the sensor transistor T3. The orthographic projection of the second scanning signal line GL2 on the base substrate 100 at least partially overlaps with the orthographic projection of the third semiconductor section 303 (e.g., the channel region 303c of the sensor transistor T3) on the base substrate 100. The part of the second scanning signal line GL2 that overlaps with the channel region 303c of the sensor transistor T3 forms the gate g3 of the sensor transistor T3.

[0087] In the embodiment of the present disclosure, the first scanning signal line GL1 and the second scanning signal line GL2 extend substantially along the first direction X, while the first auxiliary wire 33, the second auxiliary wire 34 and the third auxiliary wire 35 extend substantially along the second direction Y.

[0088] In the embodiment of the present disclosure, the first scanning signal line GL1 and the second scanning signal line GL2 for supplying gate scanning signals to pixel driver circuits for the same row of subpixels in the second direction Y are located on both sides of the light emission area of ​​the same row of subpixels, respectively. For example, in the illustrated embodiment, the first scanning signal line GL1 and the second scanning signal line GL2 for supplying gate scanning signals to pixel driver circuits for the same row of subpixels in the second direction Y are located on the upper side and the lower side of the light emission area of ​​the same row of subpixels, respectively.

[0089] Fig. 9 schematically shows a partial plan view of the combination of the first electrically conductive layer, the fourth electrically conductive layer, the semiconductor layer, the third electrically conductive layer and the first insulating layer of the display substrate. Fig. 10 schematically shows a partial plan view of the combination of the first electrically conductive layer, the fourth electrically conductive layer, the semiconductor layer, the third electrically conductive layer, the first insulating layer and the second insulating layer of the display substrate. Fig. 9 and Fig. 10 each schematically show some through holes in the first insulating layer IDL1 and the second insulating layer IDL2.

[0090] With reference to Fig. 9 and Fig. 10, the display substrate may include a first through-hole VH1 penetrating the first insulating layer IDL1 and a second through-hole VH2 penetrating the second insulating layer IDL2. The first through-hole VH1 exposes at least a portion of the third electrically conductive connecting portion 43. The third electrically conductive connecting portion 43 may, for example, include a first portion 431 and a second portion 432. The first through-hole VH1 exposes the first portion 431 of the third electrically conductive connecting portion 43, and the second through-hole VH2 exposes both the first portion 431 and the second portion 432 of the third electrically conductive connecting portion 43.

[0091] For example, the orthographic projection of the first through-hole VH1 on the base substrate 100 at least partially overlaps with the orthographic projection of the second connecting portion 53 of the capacitor wire 5 on the base substrate 100. The orthographic projection of the second through-hole VH2 on the base substrate 100 at least partially overlaps with the orthographic projection of the second connecting portion 53 of the capacitor wire 5 on the base substrate 100, and the orthographic projection of the second through-hole VH2 on the base substrate 100 at least partially overlaps with the orthographic projection of the source region 303s or the drain region 303d of the third transistor T3 on the base substrate 100.

[0092] The display substrate may include a third through-hole VH3 penetrating the first insulating layer IDL1 and a fourth through-hole VH4 penetrating the second insulating layer IDL2. The third through-hole VH3 exposes a portion of the first electrically conductive connecting portion 41. The fourth through-hole VH4 exposes the first source region 301s or the first drain region 301d of the driver transistor T1, and the fourth through-hole VH4 also exposes the third through-hole VH3.

[0093] The display substrate may include a fifth through-hole VH5 penetrating the second insulating layer IDL2. The fifth through-hole VH5 exposes a portion of the gate g1 of the driver transistor T1 and a portion of the first capacitor electrode Cst1.

[0094] Reference is made to Fig. 11, which schematically shows a partial plan view of the second electrically conductive layer 20; and reference is made to Fig. 12, which schematically shows a partial top view of the first electrically conductive layer 10, the fourth electrically conductive layer 40, the semiconductor layer ACT, the third electrically conductive layer 30, the first insulating layer IDL1, the second insulating layer IDL2, and the second electrically conductive layer 20. In the embodiment of the present disclosure, the second electrically conductive layer 20 may include various types of source and drain materials. Referring to Fig. 11 and Fig. 12, in the embodiment of the present disclosure, the display substrate may further include a first power supply signal line VDD, a data line DL, a sensor signal line SL, a first electrically conductive portion 21, a second electrically conductive portion 22, a third electrically conductive portion 23, a fourth electrically conductive portion 24, and a fifth electrically conductive portion 25 located in the second electrically conductive layer 20. For the same subpixel, the first power supply signal line VDD, the data line DL, the sensor signal line SL, the first electrically conductive portion 21, the second electrically conductive portion 22, the third electrically conductive portion 23, the fourth electrically conductive portion 24, and the fifth electrically conductive portion 25 are provided spaced apart from each other.

[0095] The orthographic projection of the first electrically conductive portion 21 on the base substrate 100 at least partially overlaps with the orthographic projection of the third through-hole VH3 on the base substrate 100, and the orthographic projection of the first electrically conductive portion 21 on the base substrate 100 at least partially overlaps with the orthographic projection of the fourth through-hole VH4 on the base substrate 100. For example, the orthographic projection of the first electrically conductive portion 21 on the base substrate 100 may overlap the orthographic projection of the third through-hole VH3 on the base substrate 100, and the orthographic projection of the first electrically conductive portion 21 on the base substrate 100 may overlap the orthographic projection of the fourth through-hole VH4 on the base substrate 100.By such an electrically conductive switching structure, which consists of the third through-hole VH3, the fourth through-hole VH4 and the first electrically conductive portion 21, an electrical connection between the source s1 or the drain d1 of the driver transistor T1 and the second capacitor electrode Cst2 can be enabled.

[0096] The orthographic projection of the second electrically conductive portion 22 on the base substrate 100 at least partially overlaps with the orthographic projection of the fifth through-hole VH5 on the base substrate 100. For example, the orthographic projection of the second electrically conductive portion 22 on the base substrate 100 may overlap the orthographic projection of the fifth through-hole VH5 on the base substrate 100. Such an electrically conductive switching structure, which consists of the fifth through-hole VH5 and the second electrically conductive portion 22, may enable an electrical connection between the gate g1 of the driver transistor T1 and the first capacitor electrode Cst1.

[0097] The orthographic projection of the third electrically conductive portion 23 on the base substrate 100 at least partially overlaps with the orthographic projection of the first through-hole VH1 on the base substrate 100, and the orthographic projection of the third electrically conductive portion 23 on the base substrate 100 at least partially overlaps with the orthographic projection of the second through-hole VH2 on the base substrate 100. For example, the orthographic projection of the third electrically conductive portion 23 on the base substrate 100 may overlap the orthographic projection of the first through-hole VH1 on the base substrate 100, and the orthographic projection of the third electrically conductive portion 23 on the base substrate 100 may overlap the orthographic projection of the second through-hole VH2 on the base substrate 100.By means of such an electrically conductive switching structure, which consists of the first through-hole VH1, the second through-hole VH2 and the third electrically conductive section 23, an electrical connection between the source s3 or the drain d3 of the sensor transistor T3 and the capacitor wire 5 can be enabled.

[0098] The orthographic projection of the fourth electrically conductive portion 24 on the base substrate 100 at least partially overlaps with the orthographic projection of the sixth through-hole VH6 on the base substrate 100. For example, the orthographic projection of the fourth electrically conductive portion 24 on the base substrate 100 may overlap the orthographic projection of the sixth through-hole VH6 on the base substrate 100.

[0099] For example, the first power supply signal line VDD may be electrically connected to the source region s1 or the drain region d1 of the driver transistor T1 via a ninth through-hole VH9.

[0100] In the embodiment of the present disclosure, for example, for the same subpixel, the orthographic projection of the data line DL on the base substrate 100 at least partially overlaps with the orthographic projection of the first auxiliary wire 33 on the base substrate 100. For example, the orthographic projection of the data line DL on the base substrate 100 may overlap the orthographic projection of the first auxiliary wire 33 on the base substrate 100. The data line DL may be electrically connected to the first auxiliary wire 33 via a tenth through-hole VH10. For example, a plurality of tenth through-holes VH10 may be arranged spaced apart from each other along the second direction Y, and the data line DL may be electrically connected to the first auxiliary wire 33 via the plurality of spaced-apart tenth through-holes VH10.In this way, the contact area between the data line DL and the first auxiliary wire 33 can be increased, thereby reducing the contact resistance and lowering the voltage drop across the data line DL.

[0101] In the embodiment of the present disclosure, for the same subpixel, the orthographic projection of the first auxiliary wire 33 on the base substrate 100, which is electrically connected to the data line for supplying data signals to the pixel driver circuit of the subpixel, at least partially overlaps with the orthographic projection of the capacitor wire main body portion 52 of the pixel driver circuit of the subpixel on the base substrate 100.

[0102] In the embodiment of the present disclosure, for example, for the same subpixel, the orthographic projection of the sensor signal line SL on the base substrate 100 at least partially overlaps with the orthographic projection of the second auxiliary wire 34 on the base substrate 100. For example, the orthographic projection of the sensor signal line SL on the base substrate 100 may overlap the orthographic projection of the second auxiliary wire 34 on the base substrate 100. The sensor signal line SL may be electrically connected to the second auxiliary wire 34 via an eleventh through-hole VH11. For example, a plurality of eleventh through-holes VH11 may be arranged spaced apart from each other along the second direction Y, and the sensor signal line SL may be electrically connected to the first auxiliary wire 33 via the plurality of spaced-apart eleventh through-holes VH11.In this way, the contact area between the sensor signal line SL and the second auxiliary wire 34 can be increased, thereby reducing the contact resistance and lowering the voltage drop across the sensor signal line SL.

[0103] For example, in the embodiment of the present disclosure, for the same subpixel, the orthographic projection of the first power supply signal line VDD on the base substrate 100 at least partially overlaps with the orthographic projection of the third auxiliary wire 35 on the base substrate 100. For example, the orthographic projection of the first power supply signal line VDD on the base substrate 100 may overlap the orthographic projection of the third auxiliary wire 35 on the base substrate 100. The first power supply signal line VDD may be electrically connected to the third auxiliary wire 35 via a twelfth through-hole VH12.For example, a plurality of twelfth through-holes VH12 may be spaced apart along the second direction Y, and the first power supply signal line VDD may be electrically connected to the first auxiliary wire 33 via the plurality of spaced-apart twelfth through-holes VH12. In this way, the contact area between the first power supply signal line VDD and the first auxiliary wire 33 can be increased, thereby reducing the contact resistance and lowering the voltage drop across the first power supply signal line VDD.

[0104] For example, the data line DL can be electrically connected to the source region s2 or the drain region d2 of the switching transistor T2 via a thirteenth through-hole VH13.

[0105] In the embodiment of the present disclosure, two data lines DL are provided between two adjacent subpixels located in the same row. For example, the two adjacent subpixels in the same row include a first subpixel SP1 and a second subpixel SP2, wherein the two data lines include a first data line DL1 and a second data line DL2.

[0106] The first data line DL1 serves to supply a data signal to the first subpixel SP1. The orthographic projection of a data line main body portion of the data line DL1 for supplying a data signal to the pixel driver circuit of the first subpixel on the base substrate completely overlaps the orthographic projection of the capacitor wire main body portion 52 of the pixel driver circuit of the first subpixel on the base substrate.

[0107] The second data line DL2 serves to supply a data signal to the second subpixel SP2. The orthographic projection of a data line main body portion of the data line DL2 for supplying a data signal to the pixel driver circuit of the second subpixel on the base substrate completely overlaps the orthographic projection of the capacitor wire main body portion 52 of the pixel driver circuit of the second subpixel on the base substrate.

[0108] The first connection portion 51 of the capacitor wire 5 of the pixel driver circuit of the first subpixel extends along the first direction X toward the first data line DL1, and the first connection portion 51 of the capacitor wire 5 of the pixel driver circuit of the second subpixel extends along the first direction X toward the second data line DL2.

[0109] For example, the sensor signal line SL comprises a first part SL1 extending along the second direction Y and a second part SL2 extending along the first direction X. In the first direction X, the second subpixel SP2 is adjacent to the sensor signal line SL, and the first subpixel SP1 is located on the side of the second subpixel SP2 remote from the sensor signal line SL.

[0110] For example, one end of the second electrically conductive connecting portion 42 is electrically connected to another one of the source s3 and the drain d3 of the sensor transistor T3 of the pixel driving circuit of the first sub-pixel SP1 via the sixth through-hole VH6, and another end of the second electrically conductive connecting portion 42 is electrically connected to another one of the source s3 and the drain d3 of the sensor transistor T3 of the pixel driving circuit of the second sub-pixel SP2 via the seventh through-hole VH7.

[0111] The second part SL2 of the sensor signal line is electrically connected via the eighth through-hole VH8 to the other end of the second electrically conductive connecting portion 42 and another of the source s3 and drain d3 of the sensor transistor T3 of the pixel driver circuit of the second subpixel SP2. In this way, the sensor signal supplied by the sensor signal line SL can be supplied to the individual subpixels of a pixel unit.

[0112] For example, the first power supply signal line VDD is located on the side of the first subpixel SP1 remote from the second subpixel SP2. The first power supply signal line VDD can be electrically connected to the source s1 or the drain d1 of the driver transistor T1 via the fourteenth through-hole VH14, the fourth electrically conductive connecting portion 44, the fifteenth through-hole VH15, and the fifth electrically conductive portion 25.

[0113] In the embodiment of the present disclosure, with reference to Fig.13, the pixel definition layer PDL has a plurality of openings 80 for defining light-emitting regions SPA1, SPA2, SPA3, SPA4 of a plurality of subpixels. The capacitor wire 5 serves to electrically connect the source s3 or the drain d3 of the sensor transistor T3 to the second capacitor electrode Cst2. The capacitor wire 5 includes a capacitor wire main body portion 52 extending along the second direction Y. For the same subpixel, the orthographic projection of the capacitor wire main body portion 52 of the pixel driver circuit of the subpixel on the base substrate 100 is spaced apart from the orthographic projection of the light-emitting region SPA1, SPA2, SPA3, or SPA4 of that subpixel on the base substrate 100. That is, the capacitor wire main body portion 52 of the pixel driver circuit of the subpixel is not located within the light-emitting region of the subpixel.

[0114] The inventors discovered through research that the capacitor wire 5 made of a transparent conductive material is not completely light-transmitting and still has a light-blocking effect. In the embodiment of the present disclosure, by placing most of the capacitor wire (e.g., the capacitor wire main body portion 52) outside the light-emitting region of the subpixel, the blocking effect on the light emitted from the light-emitting region is reduced. This can increase the light transmittance of the light-emitting region. In this way, the display quality of the display substrate can be improved without affecting the driving of the sensor transistor.

[0115] In the embodiment of the present disclosure, the data line DL includes a data line main body portion DLS extending along the second direction Y. For the same subpixel, the orthographic projection of the data line main body portion DLS of the data line for supplying a data signal to the pixel driver circuit of the subpixel on the base substrate 100 at least partially overlaps with the orthographic projection of the capacitor wire main body portion 52 of the pixel driver circuit of the subpixel on the base substrate 100. For example, for the same subpixel, the orthographic projection of the data line main body portion DLS of the data line for supplying a data signal to the pixel driver circuit of the subpixel on the base substrate 100 completely overlaps the orthographic projection of the capacitor wire main body portion 52 of the pixel driver circuit of the subpixel on the base substrate 100.In an OLED display substrate, the data line DL is provided outside the light-emitting region. In this embodiment, by placing most of the capacitor wire (e.g., the capacitor wire main body portion 52) below the data line DL, the goal of placing most of the capacitor wire outside the light-emitting region is achieved. Furthermore, by placing most of the capacitor wire (e.g., the capacitor wire main body portion 52) below the data line DL, the capacitor wire provided outside the light-emitting region does not additionally occupy wiring space on the display substrate, which is advantageous for realizing a display substrate with a high PPI.

[0116] The present disclosure also provides a display device that may include the above-mentioned display substrate. The display device may include, but is not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigation devices, and any product or component with a display function. It is understood that the display device has the same advantageous effects as the display substrate provided in the above-mentioned embodiments.

[0117] Although some embodiments of the overall concept of the present disclosure have been illustrated and described, those of ordinary skill in the relevant technical field will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall inventive concept, and that the scope of the present disclosure is defined by the claims and their equivalents.

Claims

[1] Display substrate, characterized by that the display substrate comprises: a base substrate; a plurality of pixel units provided on the base substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction, at least one of the pixel units comprising a plurality of sub-pixels, at least one of the sub-pixels comprising a light-emitting element and a pixel driver circuit for driving the light-emitting element; a semiconductor layer provided on the base substrate; a first electrically conductive layer provided on a side of the semiconductor layer near the base substrate; a second electrically conductive layer provided on a side of the semiconductor layer remote from the base substrate; and a pixel definition layer provided on a side of the second electrically conductive layer remote from the base substrate, the pixel definition layer comprising a plurality of openings for defining light emission regions of the plurality of subpixels, wherein the pixel driver circuit comprises a sensor transistor, a storage capacitor, and a capacitor wire, wherein the sensor transistor comprises a source and a drain, wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode provided opposite each other, wherein the capacitor wire serves to electrically connect the source or the drain of the sensor transistor to the second capacitor electrode, wherein the source and drain of the sensor transistor are located in the second electrically conductive layer, wherein the second capacitor electrode and the capacitor wire are located in the first electrically conductive layer, wherein the capacitor wire has a capacitor wire main body portion extending along the second direction, and wherein, for the same subpixel, the orthographic projection of the capacitor wire main body portion of the pixel driving circuit of the subpixel on the base substrate is provided spaced from the orthographic projection of the light emitting region of the subpixel on the base substrate. [2] A display substrate according to claim 1, characterized byin that the display substrate further comprises a data line for supplying data signals, wherein the data line is located in the second electrically conductive layer, wherein the data line comprises a data line main body portion extending along the second direction; and wherein, for the same subpixel, the orthographic projection of the data line main body portion of the data line for supplying a data signal to the pixel driver circuit of the subpixel on the base substrate at least partially overlaps with the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the subpixel on the base substrate. [3] Display substrate according to claim 2, characterized bythat for the same subpixel, the orthographic projection of the data line main body portion of the data line for supplying a data signal to the pixel driver circuit of the subpixel on the base substrate completely covers the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the subpixel on the base substrate. [4] Display substrate according to one of claims 1 to 3, characterized bythat, for the same subpixel, the orthographic projection of the second capacitor electrode of the pixel driver circuit of the subpixel on the base substrate at least partially overlaps with the orthographic projection of the light emitting region of the subpixel on the base substrate; wherein the capacitor wire comprises a first connecting portion and a second connecting portion, wherein the capacitor wire main body portion is located between the first connecting portion and the second connecting portion, wherein the first connecting portion is connected to the second capacitor electrode, and wherein the second connecting portion is electrically connected to the source or the drain of the sensor transistor. [5] Display substrate according to claim 4, characterized by that the display substrate further comprises a third electrically conductive layer located between the semiconductor layer and the second electrically conductive layer; wherein the display substrate further comprises a first auxiliary wire located in the third electrically conductive layer, the first auxiliary wire extending along the second direction and being electrically connected to the data line; wherein, for the same subpixel, the orthographic projection of the first auxiliary wire on the base substrate, which is electrically connected to the data line for supplying data signals to the pixel driver circuit of the subpixel, at least partially overlaps the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the subpixel on the base substrate. [6] Display substrate according to claim 4, characterized bythat the first capacitor electrode is located in the semiconductor layer; wherein, for the same subpixel, the orthographic projection of the first capacitor electrode of the pixel driver circuit of the subpixel on the base substrate at least partially overlaps with the orthographic projection of the light emission region of the subpixel on the base substrate. [7] Display substrate according to claim 5, characterized by that the display substrate further comprises a first scanning signal line and a second scanning signal line for supplying gate scanning signals, wherein the first scanning signal line and the second scanning signal line are located in the third electrically conductive layer; wherein the pixel driver circuit further comprises a switching transistor, wherein the part of the first scanning signal line that overlaps with the semiconductor layer is the gate of the switching transistor, and wherein the part of the second scanning signal line that overlaps with the semiconductor layer is the gate of the sensor transistor; wherein the first scanning signal line and the second scanning signal line for supplying gate scanning signals to pixel driving circuits for the same row of subpixels in the second direction are respectively located on both sides of the light emitting area of ​​the same row of subpixels. [8] Display substrate according to claim 7, characterized by that the display substrate further comprises a fourth electrically conductive layer located between the first electrically conductive layer and the semiconductor layer; wherein the display substrate further comprises a third electrically conductive connecting portion located in the fourth electrically conductive layer and a third semiconductor portion located in the semiconductor layer, wherein the third semiconductor portion comprises a third source region, a third drain region, and a channel region of the sensor transistor, wherein the third source region and the third drain region are each located on both sides of the channel region of the sensor transistor; wherein the third electrically conductive connecting portion has a first part and a second part, wherein the orthographic projection of the first part of the third electrically conductive connecting portion on the base substrate overlaps with the orthographic projection of the second connecting portion of the capacitor wire on the base substrate, and wherein the orthographic projection of the third source region or the third drain region on the base substrate overlaps with the orthographic projection of the second part of the third electrically conductive connecting portion on the base substrate. [9] Display substrate according to claim 8, characterized by that the display substrate further comprises a first insulating layer and a second insulating layer located between the third electrically conductive layer and the second electrically conductive layer; wherein the display substrate comprises a first through-hole penetrating the first insulating layer and a second through-hole penetrating the second insulating layer, wherein the first through-hole exposes the first part of the third electrically conductive connecting portion and the second through-hole exposes the first part and the second part of the third electrically conductive connecting portion; wherein the orthographic projection of the source or drain of the sensor transistor on the base substrate overlaps the orthographic projection of each of the first through-hole and the second through-hole on the base substrate. [10] Display substrate according to claim 9, characterized byin that the display substrate further comprises a first electrically conductive connecting portion located in the fourth electrically conductive layer, wherein the orthographic projection of the first electrically conductive connecting portion on the base substrate at least partially overlaps the orthographic projection of the first capacitor electrode on the base substrate. [11] Display substrate according to claim 10, characterized by that the pixel driver circuit further comprises a driver transistor comprising a channel region, a gate, a source and a drain; wherein the display substrate further comprises a first semiconductor portion located in the semiconductor layer, the first semiconductor portion comprising a first source region, a first drain region, and the channel region of the driver transistor, the first source region and the first drain region being located on either side of the channel region of the driver transistor; wherein the display substrate comprises a third through-hole penetrating the first insulating layer and a fourth through-hole penetrating the second insulating layer, wherein the third through-hole exposes a part of the first electrically conductive connecting portion, and the fourth through-hole exposes a part of the first source region or the first drain region and the third through-hole; wherein the orthographic projection of the source or drain of the driver transistor on the base substrate overlaps the orthographic projection of each of the third through-hole and the fourth through-hole on the base substrate. [12] Display substrate according to claim 11, characterized by in that the switching transistor comprises a channel region, wherein the display substrate further comprises a second semiconductor portion located in the semiconductor layer, wherein the second semiconductor portion comprises a second source region, a second drain region, and the channel region of the switching transistor, wherein the second source region and the second drain region are each located on either side of the channel region of the switching transistor; wherein the second capacitor electrode and the second semiconductor portion are a continuously extending, one-piece structure. [13] Display substrate according to claim 12, characterized byin that the display substrate comprises a fifth through-hole penetrating the second insulating layer; wherein the fifth through-hole exposes a part of the gate of the driver transistor and a part of the first capacitor electrode, wherein the source or drain of the switching transistor, the gate of the driver transistor, and the first capacitor electrode are electrically connected via the fifth through-hole. [14] Display substrate according to one of claims 1 to 3, characterized by that two data lines are provided between two adjacent subpixels located in the same row, wherein the two adjacent subpixels in the same row comprise a first subpixel and a second subpixel, wherein the two data lines comprise a first data line and a second data line; wherein the first data line serves to supply a data signal to the first subpixel, and wherein the orthographic projection of a data line main body portion of the data line for supplying a data signal to the pixel driver circuit of the first subpixel on the base substrate completely covers the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the first subpixel on the base substrate; wherein the second data line serves to supply a data signal to the second subpixel, and wherein the orthographic projection of a data line main body portion of the data line for supplying a data signal to the pixel driver circuit of the second subpixel on the base substrate completely covers the orthographic projection of the capacitor wire main body portion of the pixel driver circuit of the second subpixel on the base substrate. [15] Display substrate according to claim 14, characterized by that the first connection portion of the capacitor wire of the pixel driver circuit of the first subpixel extends along the first direction toward the first data line, and that the first connection portion of the capacitor wire of the pixel driver circuit of the second subpixel extends along the first direction toward the second data line. [16] A display substrate according to claim 15, characterized by in that the display substrate further comprises a sensor signal line located in the second electrically conductive layer, the sensor signal line comprising a first part extending along the second direction and a second part extending along the first direction; wherein in the first direction the second subpixel is adjacent to the sensor signal line and the first subpixel is located on the side of the second subpixel remote from the sensor signal line. [17] Display substrate according to claim 16, characterized by in that the display substrate further comprises a second electrically conductive connecting portion located in the fourth electrically conductive layer; wherein one end of the second electrically conductive connecting portion is electrically connected to another of the source and drain of the sensor transistor of the pixel driver circuit of the first sub-pixel via a sixth through-hole, and wherein another end of the second electrically conductive connecting portion is electrically connected to the other of the source and drain of the sensor transistor of the pixel driver circuit of the second sub-pixel via a seventh through-hole. [18] Display substrate according to claim 17, characterized bythat the second part of the sensor signal line is electrically connected via an eighth through-hole to the other end of the second electrically conductive connecting portion and the other of the source and drain of the sensor transistor of the pixel driver circuit of the second sub-pixel. [19] A display substrate according to claim 18, characterized by in that the display substrate further comprises a second auxiliary wire located in the third electrically conductive layer, the second auxiliary wire extending along the second direction and being electrically connected to the sensor signal line, the orthographic projection of the second auxiliary wire on the base substrate at least partially overlapping the orthographic projection of the sensor signal line on the base substrate. [20] Display substrate according to claim 8, characterized bythat the material of the first electrically conductive layer contains a transparent conductive material; and / or that the material of the fourth electrically conductive layer contains a light-shielding material. [21] Display device, characterized by that the display device comprises a display substrate according to one of claims 1 to 20.

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