Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate comprises a base substrate and a display unit arranged on the base substrate. The display unit comprises a display area and a non-light-emitting area. The display area comprises subpixels, and the subpixels comprise a driver transistor and a light-emitting device. The driver transistor controls the magnitude of the driver current flowing through the light-emitting device, and the light-emitting device is driven by the driver current to emit light. The light-emitting device comprises a common electrode connected to a common voltage terminal. The display unit comprises an auxiliary electrode lead, a first auxiliary electrode, and an auxiliary insulating layer.The auxiliary electrode conductor comprises a longitudinal section located in the display area and a transverse section located at least partially in the non-light-emitting area, and the transverse section is connected to the longitudinal section; the first auxiliary electrode is located in the non-light-emitting area and is electrically connected to the common electrode; the auxiliary insulating layer comprises a first auxiliary through-hole located in the non-light-emitting area and exposing at least part of the transverse section, and the first auxiliary electrode is connected to the transverse section through the first auxiliary through-hole.

Description

AREA OF TECHNOLOGY

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device. STATE OF THE ART

[0002] With the continuous development of display technology, OLED technology is increasingly used in transparent displays. Transparent displays are an important area of ​​personalized display technology and refer to a case where an image is displayed in a transparent state, allowing the viewer to see not only the image on the display device but also the scene behind it. A transparent display device using AMOLED technology typically divides each pixel into a display area and a non-light-emitting area. The display area contains a pixel driver circuit and a light-emitting device to achieve image display, while the non-light-emitting area achieves light transmission. SUMMARY

[0003] At least one embodiment of the present disclosure further provides a display substrate, and the display substrate comprises a base substrate and a display unit provided on the base substrate. The display unit comprises a display area and a non-light-emitting area; the display area comprises a subpixel; the subpixel comprises a driver transistor and a light-emitting device; the driver transistor is configured to control the magnitude of a driver current flowing through the light-emitting device; and the light-emitting device is configured to receive the driver current and be driven by the driver current to emit light; the light-emitting device comprises a first electrode and a common electrode, and the common electrode is connected to a common voltage terminal.The display unit comprises an auxiliary electrode lead, a first auxiliary electrode, and an auxiliary insulating layer; the auxiliary electrode lead comprises a longitudinal section located in the display area and a transverse section located at least partially in the non-light-emitting area, and the transverse section is connected to the longitudinal section; the first auxiliary electrode is located in the non-light-emitting area and is electrically connected to the common electrode; the auxiliary insulating layer comprises a first auxiliary through-hole located in the non-light-emitting area and exposing at least part of the transverse section, and the first auxiliary electrode is connected to the transverse section through the first auxiliary through-hole; the transverse section, the first auxiliary electrode, and the first auxiliary through-hole form an auxiliary unit, and the display unit comprises a plurality of auxiliary units;and the transverse section of the auxiliary electrode conductor extends along a first direction, the longitudinal section of the auxiliary electrode conductor extends along a second direction that intersects the first direction, and the plurality of auxiliary units are spaced apart in the second direction.

[0004] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of auxiliary units comprise a first auxiliary unit and a second auxiliary unit, and the first auxiliary unit and the second auxiliary unit are each the one auxiliary unit; and a distance between a first auxiliary through-hole of the second auxiliary unit and the display area in the first direction is greater than a distance between a first auxiliary through-hole of the first auxiliary unit and the display area in the first direction.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, the length of the transverse section of the second auxiliary unit in the first direction is greater than the length of the transverse section of the first auxiliary unit in the first direction.

[0006] In the display substrate provided by at least one embodiment of the present disclosure, the first auxiliary electrode comprises, for example: a first conductive sublayer, a first stacked section, and a second stacked section. The first conductive sublayer is connected to the transverse section through the first auxiliary through-hole; the first stacked section is electrically connected to the first conductive sublayer and stacked with the first conductive sublayer in a direction perpendicular to the base substrate, is located on a side of the first conductive sublayer furthest from the base substrate, and comprises a first stacked layer and a second stacked layer stacked together in a direction perpendicular to the base substrate; the second stacked layer is located on a side of the first stacked layer furthest from the base substrate and is connected to the common electrode.wherein the second stacked section is stacked with the first conductive sublayer in the direction perpendicular to the base substrate, is located on the side of the first conductive sublayer furthest from the base substrate and is located on a side of the first stacked section furthest from the base substrate, is electrically connected to the first stacked section through the first conductive sublayer and comprises a third stacked layer and a fourth stacked layer stacked together in the direction perpendicular to the base substrate;the third stacked layer, the first stacked layer, and a light-emitting layer of the light-emitting device located in the display area are made of the same material, in the same layer, and spaced apart from each other in a direction parallel to the base substrate; and the fourth stacked layer, the second stacked layer, and the common electrode of the light-emitting device located in the display area are in the same layer and spaced apart from each other in a direction parallel to the base substrate; and the first stacked layer of the first stacked section of the second auxiliary unit has an intermediate through-hole, and the second stacked layer of the first stacked section of the second auxiliary unit is electrically connected to the first conductive sublayer of the second auxiliary unit through the intermediate through-hole.

[0007] For example, in the display substrate provided by at least one embodiment of the present disclosure, an area of ​​a planar shape of a first auxiliary through-hole of the second auxiliary unit is larger than an area of ​​a planar shape of a first auxiliary through-hole of the first auxiliary unit.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, a display unit comprises at least two first auxiliary units, and the number of second auxiliary units is greater than or equal to one.

[0009] For example, in the display substrate provided by at least one embodiment of the present disclosure, the display unit comprises at least three first auxiliary units, and in the second direction, at least one second auxiliary unit is located between the at least three first auxiliary units.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, the display unit comprises a plurality of subpixels arranged in an array, and the array comprises a first row of pixels extending along the first direction, and a second row of pixels extending along the first direction; the first row of pixels comprises a first subpixel and a second subpixel arranged adjacent to each other, and the second row of pixels comprises a third subpixel and a fourth subpixel arranged adjacent to each other; in one display unit, the at least two first auxiliary units comprise No. 1 first auxiliary unit, No. 2 first auxiliary unit, and No. 3 first auxiliary unit; and No. 1 first auxiliary unit and No. 2 first auxiliary unit are located in the second subpixel, and No.The third auxiliary unit and the second auxiliary unit are located in the fourth subpixel.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, each subpixel of the display unit comprises: a connection structure and a first transfer electrode. The connection structure electrically connects a first section of the first electrode and a second section of the first electrode and comprises a connection section located in the non-light-emitting region; and the first transfer electrode is electrically connected to a first pole of the driver transistor and comprises a section located in the non-light-emitting region, wherein the connection section in the non-light-emitting region is electrically connected to the section of the first transfer electrode located in the non-light-emitting region.the first transfer electrode comprises a first transfer section, the first transfer section is located in the display area and is electrically connected to the first pole of the driver transistor; a section of the first transfer electrode located in the non-light-emitting area is a second transfer section of the first transfer electrode, the second transfer section is electrically connected to the first transfer section, the connecting section and the second transfer section are each arranged in different layers, and the connecting section in the non-light-emitting area is electrically connected to the second transfer section by a first through-hole;The No. 1 first auxiliary unit and the No. 2 first auxiliary unit are each arranged on two opposite sides of the connection section of the second subpixel in the second direction, and the No. 3 first auxiliary unit and the second auxiliary unit are each arranged on two opposite sides of the connection section of the fourth subpixel in the second direction.

[0012] For example, in the display substrate provided by at least one embodiment of the present disclosure, in the second direction the second auxiliary unit is arranged on a side of the connection section of the fourth subpixel that is close to a connection between the fourth subpixel and the second subpixel; or in the second direction the second auxiliary unit is arranged on a side of the connection section of the fourth subpixel that is far from the connection between the fourth subpixel and the second subpixel.

[0013] For example, in the display substrate provided by at least one embodiment of the present disclosure, an area of ​​a planar shape of the first auxiliary through-hole of the first auxiliary unit is larger than an area of ​​a planar shape of the first through-hole.

[0014] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first auxiliary electrode comprises: a first conductive sublayer, a first stacked section, and a second stacked section. The first conductive sublayer is connected to the transverse section through the first auxiliary through-hole;the first stacked section is electrically connected to the first conductive sublayer and stacked with the first conductive sublayer in a direction perpendicular to the base substrate, is located on a side of the first conductive sublayer away from the base substrate and comprises a first stacked layer and a second stacked layer stacked together in a direction perpendicular to the base substrate, the second stacked layer being located on a side of the first stacked layer away from the base substrate and connected to the common electrode;the second stacked section is stacked with the first conductive sublayer in the direction perpendicular to the base substrate, is located on the side of the first conductive sublayer furthest from the base substrate, and is located on a side of the first stacked section furthest from the base substrate, is electrically connected to the first stacked section through the first conductive sublayer, and comprises a third stacked layer and a fourth stacked layer stacked together in the direction perpendicular to the base substrate, wherein the third stacked layer and the first stacked layer are made of the same material, in the same layer, and spaced apart from each other in a direction parallel to the base substrate, and the fourth stacked layer and the second stacked layer are made of the same material, in the same layer, and spaced apart from each other in a direction parallel to the base substrate.

[0015] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second stacked layer is electrically connected to the common electrode and is in contact with the first conductive sublayer; the first stacked layer is in contact with the first conductive sublayer; and the second stacked layer comprises an upper section covering an upper surface of the first stacked layer located away from the base substrate, and a side section covering a side surface of the first stacked layer that intersects with the upper surface of the first stacked layer, and the side section being in contact with the first conductive sublayer.

[0016] In the display substrate provided by at least one embodiment of the present disclosure, the second stacked section further comprises, for example, a fifth stacked layer and a sixth stacked layer. The fifth stacked layer is located between the first conductive sublayer and the third stacked layer; the sixth stacked layer is located between the fifth stacked layer and the third stacked layer, wherein the fifth stacked layer and the sixth stacked layer are stacked with the first conductive sublayer, the third stacked layer, and the fourth stacked layer in a direction perpendicular to the base substrate and are electrically connected to each other, and both the fifth stacked layer and the sixth stacked layer are spaced apart from the first stacked layer and the second stacked layer in a direction parallel to the base substrate.an orthographic projection of the sixth stacked layer on the base substrate comprises a central region and an edge region surrounding the central region, and an orthographic projection of the fifth stacked layer on the base substrate overlaps with the central region but does not overlap with the edge region; the second stacked layer is in contact with the first conductive sublayer in a first region, and an orthographic projection of the first region on the base substrate lies at least partially within an orthographic projection of the edge region on the base substrate.

[0017] In the display substrate provided by at least one embodiment of the present disclosure, the light-emitting device further comprises, for example, a first electrode and a light-emitting layer located in the display area, the light-emitting layer being inserted between the first electrode and the common electrode, and the first electrode comprising a first electrode sublayer, a second electrode sublayer and a third electrode sublayer stacked successively in a direction perpendicular to the base substrate and along a direction from a position close to the base substrate to a position farther away from the base substrate;the first conductive sublayer of the first auxiliary electrode and the first electrode sublayer are made of the same material and in the same layer; the first stacked layer and the light-emitting layer form a continuous and one-piece structure; the second stacked layer and the common electrode form a continuous and one-piece structure; the third stacked layer and the light-emitting layer are made of the same material and in the same layer; the fourth stacked layer, the second stacked layer, and the common electrode are made of the same material and in the same layer; the fifth stacked layer and the second electrode sublayer are made of the same material and in the same layer; and the sixth stacked layer and the third electrode sublayer are made of the same material and in the same layer.

[0018] In the display substrate provided by at least one embodiment of the present disclosure, the display unit further comprises, for example, a second auxiliary electrode, wherein the second auxiliary electrode is located in the display area and is electrically connected to the common electrode; the auxiliary insulating layer further comprises a second auxiliary through-hole located in the display area and exposing at least a portion of the longitudinal section of the auxiliary electrode conductor, and the second auxiliary electrode is connected to the longitudinal section of the auxiliary electrode conductor through the second auxiliary through-hole.

[0019] In the display substrate provided by at least one embodiment of the present disclosure, the second auxiliary electrode comprises, for example, a second conductive sublayer and a second stacked section, wherein the second conductive sublayer is connected to the longitudinal section of the auxiliary electrode conductor through the second auxiliary through-hole;the first stacked section is electrically connected to the second conductive sublayer of the second auxiliary electrode and is stacked in a direction perpendicular to the base substrate, is located on a side of the second conductive sublayer of the second auxiliary electrode furthest from the base substrate and comprises a first stacked layer and a second stacked layer stacked on top of each other in a direction perpendicular to the base substrate, the second stacked layer of the second auxiliary electrode being located on a side of the first stacked layer of the second auxiliary electrode furthest from the base substrate and being connected to the common electrode;The second stacked section is stacked on the second conductive sublayer of the second auxiliary electrode in the direction perpendicular to the base substrate, is located on the side of the second conductive sublayer of the second auxiliary electrode furthest from the base substrate, and is located on a side of the first stacked section of the second auxiliary electrode furthest from the base substrate, and is electrically connected to the first stacked section of the second auxiliary electrode through the second conductive sublayer, and comprises a third stacked layer and a fourth stacked layer stacked together in the direction perpendicular to the base substrate;the third stacked layer of the second auxiliary electrode and the first stacked layer of the second auxiliary electrode are made of the same material, in the same layer and spaced apart in a direction parallel to the base substrate, and the fourth stacked layer of the second auxiliary electrode and the second stacked layer of the second auxiliary electrode are made of the same material, in the same layer and spaced apart in a direction parallel to the base substrate.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second stacked layer of the second auxiliary electrode is connected to the common electrode and is in contact with the second conductive sublayer of the second auxiliary electrode.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, the transverse section of the auxiliary electrode lead extends along a first direction, and the longitudinal section of the auxiliary electrode lead extends along a second direction intersecting the first direction; the display substrate further comprises a first power supply lead, wherein the first power supply lead is connected to a first voltage terminal and is configured to supply a first power supply voltage, which is different from a common voltage, to the subpixel, and comprises a longitudinal section extending as a whole along the second direction;The longitudinal section of the first power supply line and the longitudinal section of the auxiliary electrode line are spaced apart in the first direction and are each located at a first edge of the display area in the first direction and at a second edge of the display area in the first direction, opposite the first edge; the display area is the area between an edge of the longitudinal section of the first power supply line located away from the longitudinal section of the auxiliary electrode line and an edge of the longitudinal section of the auxiliary electrode line located away from the longitudinal section of the first power supply line.

[0022] At least one embodiment of the present disclosure provides a display device, wherein the display device comprises the display substrate according to one of the display substrates provided by the embodiments of the present disclosure. SHORT DESCRIPTION OF THE CHARACTERS

[0023] To clarify the technical solution of the embodiments of the present disclosure, the drawings of the embodiments are briefly described. It is obvious that the drawings described below relate only to some embodiments of the present disclosure and are therefore not limiting to the present disclosure. Fig. Figure 1A is a schematic planar overall view of a display substrate provided by an embodiment of the present disclosure; Fig. 1B is a block diagram of a display substrate provided by at least one embodiment of the present disclosure; Fig. 2A is an equivalent circuit diagram of a pixel circuit of a display unit of a display substrate, which is provided by an embodiment of the present disclosure; Fig. 2B- Fig. 2D are signal timing diagrams of a control method for a pixel circuit provided by at least one embodiment of the present disclosure; Fig. 3A is a schematic planar view of a display unit of a display substrate provided by at least one embodiment of the present disclosure; Fig. 3B is a schematic diagram of a third subpixel in Fig. 3A; Fig. 3C is an enlarged partial view of Fig. 3B, which includes a connection structure; Fig. 4A is a schematic cross-sectional view along line AA' in Fig. 3B; Fig. 4B is a schematic cross-sectional view along line BB' and line CC' in Fig. 3B; Fig. 4C is a schematic cross-sectional view along the line DD' in Fig. 3A; Fig. 4D is a schematic diagram obtained by producing a cross-section of the display substrate provided by another embodiment of the present disclosure at a position of line AA' in Fig. 3B will be obtained; Fig. 5A is a schematic planar view of a first conductive layer of the in Fig. 3A shown display unit; Fig. 5B is a schematic planar view of a first insulating layer of the in Fig. 3A shown display unit; Fig. 5C is a schematic planar view of a semiconductor layer in Fig. 3A shown display unit; Fig. 5D is a schematic planar view of a second conductive layer of the in Fig. 3A shown display unit; Fig. 5E is a schematic planar view of a third insulating layer of the in Fig. 3A shown display unit; Fig. 5F is a schematic planar view of a third conductive layer of the in Fig. 3A shown display unit; Fig. 5G is a schematic planar view of a fourth insulating layer of the in Fig. 3A shown display unit; Fig. 5H is a schematic planar view of a fifth insulating layer of the in Fig. 3A shown display unit; Fig. 5I is a schematic planar view of a fourth conducting layer of the in Fig. 3A shown display unit; Fig. 5J is a schematic planar view of a fifth conductive layer of the in Fig. 3A shown display unit; Fig. 5K is a schematic planar view of a pixel definition layer of the in Fig. 3A shown display unit; Fig. 6A is a schematic enlarged view of part A including at least one outer ring section in Fig. 3A; Fig. 6B is a schematic enlarged view of part B including at least one inner ring section in Fig. 3A; Fig. Figure 7 is another schematic cross-sectional view along line AA' in Fig. 3B; Fig. 8A is a schematic enlarged view of part C in Fig. 7; Fig. Figure 8B is a schematic enlarged view of another display substrate provided by an embodiment of the present disclosure at a position of part C in Fig. 7; Fig. 9 is a schematic planar view of the in Fig. 8A shown part C; Fig. Figure 10 is a schematic diagram of an arrangement of a plurality of subpixels of a display unit provided by an embodiment of the present disclosure; Fig. 11A is a schematic planar local view of a first auxiliary unit H1 of the in Fig. 3A shown display unit; Fig. 11B is a schematic cross-sectional view along line EE' in Fig. 11A; Fig. Figure 11C is a schematic planar view showing the positional relationship of a second stacked layer, a fourth stacked layer, a fifth stacked layer, and an eighth stacked layer in Fig. 11B represents; Fig. 12A is a schematic planar local view of a second auxiliary unit H2 of the in Fig. 3A shown display unit; Fig. 12B is a schematic cross-sectional view along line FF' in Fig. 12A; Fig. 13A is a schematic planar local view of a third auxiliary unit H3 of the in Fig. 3A shown display unit; Fig. 13B is a schematic cross-sectional view along the line GG' in Fig. 13A; Fig. Figure 14A is a schematic diagram of a portion of layers comprising the pixel definition layer and the first electrode, which is located in Fig. 3A shown display unit; Fig. Figure 14B is a schematic enlarged view of part P0, which is enclosed by a dashed box in Fig. 14A is displayed; and Fig. Figure 15 is a schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE REVELATION

[0024] To clarify the subject matter, technical details, and advantages of the embodiments of the disclosure, the technical solutions of the embodiments are described in a clear and fully understandable manner in conjunction with the drawings relating to the embodiments of the disclosure. Obviously, the described embodiments represent only a portion, but not all, of the embodiments of the disclosure. Based on the embodiments described here, a person skilled in the art can derive other embodiments, which should fall within the scope of the disclosure, without inventive work.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as generally understood by a person skilled in the art in the field to which the present disclosure belongs. The terms "firstly," "secondly," etc., used in the description and claims of the present application for disclosure, are not intended to indicate any order, number, or meaning, but rather to distinguish different components. Similarly, the expressions "comprise," "contain," "include," "including," etc., are intended to indicate that the elements or objects mentioned before these terms include the elements or objects listed after these terms and their equivalents, but do not exclude the other elements or objects. The expressions "connect," "connected," etc.These terms are not intended to define a physical or mechanical connection, but can directly or indirectly include an electrical connection. "Up," "down," "left," "right," and the like are only used to indicate a relative positional relationship, and if the position of the described object changes, the relative positional relationship can be changed accordingly.

[0026] In the present disclosure, an orthographic projection of a certain structure onto a base substrate refers to an orthographic projection of the structure onto a surface of the base substrate on which various transistors and various signal lines are provided.

[0027] In the present disclosure, the description means that structure A and structure B form a continuous and one-piece structure, that structure A and structure B are made of the same material and have no seams between them, and that they are a one-piece structure with a uniform texture; for example, structure A and structure B are formed by the same patterning process. The letters A and B are used to refer to the corresponding structures described in the present disclosure.

[0028] At least one embodiment of the present disclosure provides a display substrate, and the display substrate comprises a base substrate and a display unit. The display unit is provided on the base substrate and comprises a display area and a non-light-emitting area; the display area comprises a subpixel, and the subpixel comprises a driver transistor and a light-emitting device; the driver transistor is configured to control the magnitude of a driver current flowing through the light-emitting device and comprises a gate electrode, a first pole, and a second pole; the light-emitting device is configured to receive the driver current and is driven by the driver current to emit light, and comprises a first electrode, and the first electrode comprises a first section and a second section spaced apart from each other;The display unit further comprises a connection structure and a first transfer electrode, and the connection structure is connected to the first section of the first electrode and the second section of the first electrode and includes a connection section located in the non-light-emitting region; and the first transfer electrode is connected to the first pole of the driver transistor and includes a section located in the non-light-emitting region, and the connection section in the non-light-emitting region is electrically connected to the section of the first transfer electrode located in the non-light-emitting region.

[0029] At least one embodiment of the present disclosure further provides a display substrate, and the display substrate comprises a base substrate, a display unit, a scanning signal line, and a longitudinal signal line. The display unit is provided on the base substrate and comprises a display area and a non-light-emitting area; the display area comprises a subpixel, the subpixel comprises a driver transistor and a light-emitting device, the driver transistor is configured to control the magnitude of a driver current flowing through the light-emitting device, and the light-emitting device is configured to receive the driver current and be driven by the driver current to emit light;wherein the scanning signal line is provided on the base substrate, extends as a whole along a first direction, passes through the non-light-emitting area and the display area, and transmits a scanning signal; the longitudinal signal line is provided on the base substrate and is located in the display area and extends as a whole along a second direction that intersects the first direction; and the scanning signal line comprises at least one outer ring segment, and each of the at least one outer ring segment comprises a first conductive line and a second conductive line. The first conductive line extends as a whole along the first direction and extends from the non-light-emitting area to the display area;The second conductive line extends along the first direction as a whole, from the non-light-emitting area to the display area, and is spaced apart from the first conductive line in the second direction; both the first conductive line and the second conductive line overlap with the longitudinal signal line in a direction perpendicular to the base substrate; and the scanning signal line comprises a body section that extends along the first direction as a whole, and both the first conductive line and the second conductive line are electrically connected to the body section. In the display substrate, the first conductive line and the second conductive line transmit the same scanning signal, and the first conductive line and the second conductive line of at least one outer ring section extend from the non-light-emitting area to the display area to overlap with the longitudinal signal line.

[0030] At least one embodiment of the present disclosure further provides a display substrate, and the display substrate comprises a base substrate and a display unit. The display unit is provided on the base substrate and comprises a display area; the display area comprises a plurality of subpixels, each subpixel in the plurality of subpixels comprising a driver transistor and a light-emitting device, and the driver transistor is configured to control the magnitude of a driver current flowing through the light-emitting device, and comprises a gate electrode, a first pole, and a second pole; the light-emitting device is configured to receive the driver current and is driven by the driver current to emit light, and comprises a first electrode, and the first electrode is connected to the first pole of the driver transistor;The display unit further comprises a pixel definition layer, and the pixel definition layer defines aperture regions of the plurality of subpixels; two adjacent subpixels among the plurality of subpixels of the display unit are each an upper subpixel and a lower subpixel, and a direction perpendicular to an arrangement direction of the upper subpixel and the lower subpixel is a reference direction; a first electrode of the upper subpixel has a first edge near the lower subpixel and a second edge that intersects the first edge of the first electrode and is located on a first side of the first edge of the first electrode in the reference direction; an aperture region of the upper subpixel has a first edge near the lower subpixel and a second edge that intersects the first edge of the aperture region and is located on a first side of the first edge of the aperture region in the reference direction;and a distance between the first edge of the first electrode of the upper subpixel and the first edge of the aperture area of ​​the upper subpixel is a first distance, a distance between the second edge of the first electrode of the upper subpixel and the second edge of the aperture area of ​​the upper subpixel is a second distance, and the first distance is greater than the second distance.

[0031] At least one embodiment of the present disclosure further provides a display substrate, and the display substrate comprises a base substrate and a display unit provided on the base substrate. The display unit comprises a display area and a non-light-emitting area; the display area comprises a subpixel; the subpixel comprises a driver transistor and a light-emitting device; the driver transistor is configured to control the magnitude of a driver current flowing through the light-emitting device; and the light-emitting device is configured to receive the driver current and be driven by the driver current to emit light; the light-emitting device comprises a first electrode and a common electrode, and the common electrode is connected to a common voltage terminal.The display unit comprises an auxiliary electrode lead, a first auxiliary electrode, and an auxiliary insulating layer; the auxiliary electrode lead comprises a longitudinal section located in the display area and a transverse section located at least partially in the non-light-emitting area, and the transverse section is connected to the longitudinal section; the first auxiliary electrode is located in the non-light-emitting area and is electrically connected to the common electrode; the auxiliary insulating layer comprises a first auxiliary through-hole located in the non-light-emitting area and exposing at least part of the transverse section, and the first auxiliary electrode is connected to the transverse section through the first auxiliary through-hole; wherein the transverse section, the first auxiliary electrode, and the first auxiliary through-hole form an auxiliary unit, and the display unit comprises a plurality of auxiliary units;and the transverse section of the auxiliary electrode conductor extends along a first direction, the longitudinal section of the auxiliary electrode conductor extends along a second direction that intersects the first direction, and the plurality of auxiliary units are spaced apart in the second direction.

[0032] At least one embodiment of the present disclosure further provides a display device, and the display device comprises one of the display substrates provided by the embodiments of the present disclosure.

[0033] The display substrate provided by the present disclosure can be applied to a transparent display device, such as a large-format transparent display device, wherein the large-format transparent display device, for example, comprises a display field of more than 55 inches. The transparent display device displays images in a transparent state, and the viewer can see not only the image displayed in the display device but also the scene behind the display device.

[0034] The organic light-emitting diode (OLED) is an active light-emitting display device that offers the advantages of light emission, ultra-thinness, wide viewing angle, high brightness, high contrast, low power consumption, and extremely fast response time. Depending on the control method, OLEDs are divided into passive-matrix (PM) and active-matrix (AM) types. AMOLED is a current-controlled device and uses an independent thin-film transistor (TFT) to control each subpixel, allowing each subpixel to be continuously and independently controlled to emit light.A transparent display device that uses AMOLED technology typically divides each pixel into a display area and a non-light-emitting area, with the display area being equipped with a pixel driver circuit and a light-emitting device to achieve image display, and the non-light-emitting area achieving light transmission.

[0035] A deterioration of the properties or an internal short-circuit fault of a thin-film transistor can occur in a circuit of a display device, in a manufacturing process of the thin-film transistor, or in a manufacturing process of an organic light-emitting diode.

[0036] If a thin-film transistor is not driven normally, a pixel or subpixel can become a dark spot because current or voltage is not applied to an organic light-emitting diode (OLED) connected to the thin-film transistor. Alternatively, if a source electrode and a drain electrode of a driver thin-film transistor are short-circuited, the driver thin-film transistor cannot be driven normally, and the voltage applied to the source electrode is applied directly to the drain electrode without switching on and off, thus keeping the subpixel permanently on and resulting in a bright spot.

[0037] Since the bright spot is easily visible to the user's eyes due to its high visibility, it degrades the display quality. Therefore, even if only a single bright spot appears in the display area, the display device is considered defective, leading to the problem that the display device cannot be manufactured as a finished product. In particular, because the dark spot or the bright spot can be seen by the user's eyes in a transparent display device or a large-format top-emission display device, a solution is needed that can avoid or minimize the dark spot or the bright spot.

[0038] In the transparent display device, due to the need to reserve a sufficient non-light-emitting area, the space in the display area for providing a pixel driver circuit is limited, and the circuit wiring in the display area must be minimized.

[0039] At least one embodiment of the disclosure provides a display substrate, and the display substrate comprises a base substrate and a display unit. The display unit is provided on the base substrate and comprises a display area and a non-light-emitting area; the display area comprises a subpixel, and the subpixel comprises a driver transistor and a light-emitting device; the driver transistor is configured to control the magnitude of a driver current flowing through the light-emitting device and comprises a gate electrode, a first pole, and a second pole; wherein the light-emitting device is configured to receive the driver current and is driven by the driver current to emit light, and comprises a first electrode, and the first electrode comprises a first section and a second section spaced apart from each other;The display unit further comprises a connection structure and a first transfer electrode, and the connection structure is connected to the first section of the first electrode and the second section of the first electrode and has a connection section located in the non-light-emitting region; and the first transfer electrode is connected to the first pole of the driver transistor and comprises a section located in the non-light-emitting region, and the connection section in the non-light-emitting region is electrically connected to the section of the first transfer electrode located in the non-light-emitting region.

[0040] For example, Fig. 1A A schematic planar overview of a display substrate provided by an embodiment of the present disclosure. As in Fig. As shown in Figure 1A, the display substrate 10 comprises a base substrate 1 and a display unit P provided on the base substrate, for example, a plurality of display units P, wherein the plurality of display units P are arranged, for example, in an array. Each display unit P comprises a display area 11 and a non-light-emitting area 12, the display area 11 comprising a subpixel, for example, the display unit P comprises a plurality of subpixels arranged in an array, and the array comprises a first row of pixels extending along a first direction D1, and a second row of pixels extending along the first direction D1; the first row of pixels comprises a first subpixel P1 and a second subpixel P2, which are adjacent to each other, and the second row of pixels comprises a third subpixel P3 and a fourth subpixel P4, which are adjacent to each other. Fig. Figure 1A shows the case where the display area 11 of each display unit P comprises the first subpixel P1, the second subpixel P2, the third subpixel P3, and the fourth subpixel P4. Of course, in other embodiments, the display area 11 of each display unit P can comprise more or fewer than four subpixels.

[0041] For example, the first subpixel P1 is a red subpixel (R) that emits red light, the second subpixel P2 is a green subpixel (G) that emits green light, the second subpixel P2 is a white subpixel (W) that emits white light, and the fourth subpixel P4 is a blue subpixel (B) that emits blue light. Of course, the emitting colors of the first subpixel P1, the second subpixel P2, the second subpixel P2, and the fourth subpixel P4 are not limited to the case mentioned above, and the embodiments of the present disclosure are not limited in this respect.

[0042] In some embodiments, the shape of each subpixel can be a rectangle, a rhombus, a pentagon, or a hexagon. In one exemplary embodiment, four subpixels can be arranged horizontally parallel to form an RWBG pixel array. In some other embodiments, the four subpixels can be arranged in a square or rhombus-shaped array, or vertically parallel, which is not limited in the present disclosure.

[0043] Fig. 2A is a schematic diagram of an equivalent circuit of pixel circuits of four subpixels of a Fig. 1A, display unit P. When combining Fig. 1A and Fig. In 2A combined, each subpixel selected from a group consisting of the first subpixel P1, the second subpixel P2, the third subpixel P3, and the fourth subpixel P4 comprises a pixel circuit, and the pixel circuit comprises a driver transistor T1 and a light-emitting device 20; the display area 11 is a light-emitting area used for displaying images; and the non-light-emitting area is an area that does not emit light and is not used for displaying images, and the environment of the non-display side can be seen through the non-light-emitting area on the display side of the display substrate. The driver transistor T1 is configured to control the magnitude of the driver current flowing through the light-emitting device 20 and comprises a gate electrode, a first pole, and a second pole.The light-emitting device 20 is configured to receive the driver current and be driven by the driver current to emit light. For example, the display substrate is an organic light-emitting diode (OLED) display substrate, and the light-emitting device 20 is an OLED.

[0044] Fig. Figure 1B is a block diagram of a display substrate provided by at least one embodiment of the present disclosure. As in Fig. As shown in Figure 1B, for example, each subpixel selected from a group consisting of the first subpixel P1, the second subpixel P2, the third subpixel P3, and the fourth subpixel P4 comprises a pixel circuit that drives the light-emitting device 20 to emit light. The display substrate can further comprise a plurality of scanning lines and a plurality of data lines for providing scanning (control) signals and data signals to the plurality of subpixels, thereby driving the plurality of subpixels. The display substrate can also include a power supply line, a sensing line, etc., if required.

[0045] The pixel circuit comprises a driver sub-circuit for controlling the light-emitting device 20 to emit light, and a detection sub-circuit for detecting the electrical properties of the subpixel in order to implement external compensation. The embodiments of the present disclosure do not restrict the specific structure of the pixel circuit.

[0046] Fig. Figure 1B shows a schematic diagram of a 3T1C pixel circuit used in the display substrate. Depending on requirements, the pixel circuit may also include a compensation circuit, a reset circuit, etc., and the pixel circuit may, for example, also be a 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C circuit. The embodiments of the present disclosure are not limited in this respect.

[0047] As in Fig. 2A and Fig. As shown in Figure 1A, in an exemplary embodiment each display unit P further comprises a first sampling signal line G1, a second sampling signal line G2, a first power supply line vdd, a second power supply line vss, four data signal lines D (in Fig. 2A consists of four data signal lines D, each the first data signal line D1 to the fourth data signal line D4, the first subpixel P1 is connected to the first data signal line D1, the second subpixel P2 is connected to the second data signal line D2, the third subpixel P3 is connected to the third data signal line D3 and the fourth subpixel P4 is connected to the fourth data signal line D4), a detection signal line S and four pixel circuits, each corresponding to the four subpixels P1\P2\P3\P4.

[0048] For example, the first sampling signal line G1 and the second sampling signal line G2 extend along the first direction D1 and are arranged along the second direction D2, with the first direction D1 intersecting the second direction D2; for example, the first direction D1 is perpendicular to the second direction D2. The first power supply line vdd, the data signal lines D1\D2\D3\D4, and the acquisition signal line S run along the second direction D2 and are arranged along the first direction D1.

[0049] For example, four data signal lines D and one capture signal line S are arranged between the first power supply line vdd and the second power supply line vss; two data signal lines D3\D4 of the four data signal lines D1\D2\D3\D4 are located between the capture signal line S and the first power supply line vdd; and the other two data signal lines D1\D2 of the four data signal lines D are located between the capture signal line S and the second power supply line vss. In this way, four data signal lines D1\D2\D3\D4 and one capture signal line S are arranged between the first power supply line vdd and the second power supply line vss to form four subpixels. Similarly, a first power supply line vdd, a second power supply line vss, and four data signal lines D1\D2\D3\D4 are arranged between two capture signal lines S to form four subpixels.

[0050] Fig. 2B- Fig. 2D are signal timing diagrams of a control method for a pixel circuit provided by an embodiment of the present disclosure. With reference to Fig. 2A and Fig. 2B, for example, comprises the pixel circuit of each pixel selected from the group consisting of the first subpixel P1, the second subpixel P2, the third subpixel P3, and the fourth subpixel P4, comprising a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. The first sampling signal line G1 is connected to the gate electrode of the second transistor T2 in each subpixel, and the second sampling signal line G2 is connected to the gate electrode of the third transistor T3 in each subpixel. In each subpixel, the first electrode of the second transistor T2 is electrically connected to the first capacitor electrode of the storage capacitor Cst and the gate electrode of the first transistor T1. The data signal line is connected to the second electrode of the second transistor T2, and the second electrode of the second transistor T2 is configured to receive the data signal GT.and the second transistor T2 is a data transistor and is configured to write the data signal DT to the gate electrode of the first transistor T1 and the storage capacitor Cst in response to the first control signal G1; the first electrode of the first transistor T1 is electrically connected to the second capacitor electrode of the storage capacitor Cst and is configured to be electrically connected to the first electrode of the light-emitting device 20, with the first power supply line VDD being connected to the second electrode of the first transistor T1, the second electrode of the first transistor T1 being configured to receive the first power supply voltage V1 (for example, a high power supply voltage VDD), and the first transistor T1 is a driver transistor and is configuredthat it controls a current to drive the light-emitting device by controlling the voltage of the gate electrode of the first transistor T1; the first electrode of the third transistor T3 is electrically connected to the first electrode of the first transistor T1 and the second capacitor electrode of the storage capacitor Cst; the detection signal line S is connected to the second electrode of the third transistor T3; the second electrode of the third transistor T3 is configured to be connected to the first detection line S in order to be connected to an external detection circuit 11; the third transistor T3 is a detection transistor and is configured to detect the electrical properties of the associated subpixel in response to the second control signal G2.to achieve external compensation; the electrical properties include, for example, the threshold voltage and / or the carrier mobility of the first transistor T1, or the threshold voltage or the driver current, etc., of the light-emitting device. The external detection circuit 11, for example, is a conventional circuit with a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), which are not described in detail in the embodiments of this disclosure.

[0051] Each of the transistors used in the embodiments of this disclosure can be a thin-film transistor, a field-effect transistor, or another switching component with the same properties. In the embodiments of this disclosure, the case where all transistors are thin-film transistors is taken as an example for the purpose of introduction. The source electrode and the drain electrode of the transistor used here can be structurally symmetrical, such that the source electrode and the drain electrode can be structurally indistinguishable. To distinguish the two electrodes of the transistor, with the exception of the gate electrode, in the embodiments of this disclosure one of the two electrodes of the transistor is directly designated as the first electrode and the other electrode of the two electrodes of the transistor as the second electrode.Furthermore, transistors can be divided into N-type and P-type transistors based on their characteristics. If the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0 V, -5 V, -10 V, or another suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5 V, 10 V, or another suitable voltage). If the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5 V, 10 V, or another suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0 V, -5 V, -10 V, or another suitable voltage). It should be noted that the transistor in... Fig. 1B is an N-type transistor used for illustration purposes; however, this does not constitute a limitation of the present disclosure.

[0052] The following describes the operating principle of the in Fig. 2A pixel circuit shown with reference to the one in Fig. 2B- Fig. 2D represented signal timing diagrams described, whereby Fig. 2B represents a signal timing diagram of the pixel switching during a display process and Fig. 2C and Fig. Represent 2D signal timing diagrams of the pixel switching during a capture process.

[0053] For example, in Fig. As shown in Figure 2B, the display process of each frame of an image includes a data writing and reset stage 1 and a light-emitting stage 2. Fig. Figure 2B illustrates the temporal waveforms of the different signals in each stage. One operating cycle of the 3T1C pixel circuit includes: in the data write and reset stage 1, the first control signal G1 and the second control signal G2 are both turn-on signals; the second transistor T2 and the third transistor T3 are turned on; the data signal DT is transferred through the second transistor T2 to the gate electrode of the first transistor T1; a first switch K1 is closed; an analog-to-digital converter writes a reset signal through the first sensing line 130 and the third transistor T3 to the first electrode of the light-emitting device (such as an anode of the OLED); and the first transistor T1 is turned on and generates a driver current to charge the first electrode of the light-emitting device to a working voltage.and in the light-emitting stage 2, the first control signal G1 and the second control signal G2 are both off signals; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains constant, and the first transistor T1 operates in a saturated state with a constant current and drives the light-emitting device to emit light.

[0054] Fig. Figure 2C, for example, shows a signal timing diagram when the pixel circuit detects the threshold voltage. One operating cycle of the 3T1C pixel circuit includes: the first control signal G1 and the second control signal G2 are both turn-on signals; the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted through the second transistor T2 to the gate electrode of the first transistor T1; the first switch K1 is turned off; the analog-to-digital converter writes a reset signal through the first detection line 130 and the third transistor T3 to the first electrode (node ​​S) of the light-emitting device; the first transistor T1 is turned on to charge node S until the first transistor is turned off; and the digital-to-analog converter samples the voltage on the first detection line 130 to obtain the threshold voltage of the first transistor T1.This process can be carried out, for example, when the display device is switched off.

[0055] Fig. Figure 2D shows, for example, a signal timing diagram of the pixel circuit during threshold voltage detection. A working cycle of the 3T1C pixel circuit comprises: in a first stage, the first control signal G1 and the second control signal G2 are both turn-on signals; the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted through the second transistor T2 to the gate electrode of the first transistor T1; the first switch K1 is turned off, and the analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting device through the first detection line 130 and the third transistor T3;In a second stage, the first control signal G1 is a switch-off signal, the second control signal G2 is a switch-on signal, the second transistor T2 is switched off, the third transistor T3 is switched on, and the first switch K1 and a second switch K2 are switched off so that the first sensing line 130 is floating; and due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains constant, the first transistor T1 operates in a saturated state with a constant current and drives the light-emitting device to emit light, and then the digital-to-analog converter samples the voltage on the first sensing line 130 and calculates the carrier mobility of the first transistor T1 in combination with the magnitude of the light-emitting current. This process can be carried out, for example, during the fade-out phases between the display stages.

[0056] The electrical properties of the first transistor T1 can be obtained and a corresponding compensation algorithm can be implemented using the above acquisition.

[0057] As in Fig. As shown in Figure 1B, the display substrate 10 comprises, for example, a data driver circuit 03 and a sampler circuit 04. The data driver circuit 03 is configured to output a data signal, such as the data signal DT mentioned above, as needed (such as an image signal input to the display device); and the pixel circuit of each subpixel is further configured to receive the data signal and apply the data signal to the gate electrode of the first transistor. The sampler circuit 04 is configured to output various sample signals, such as the first control signal G1 and the second control signal G2 mentioned above, and the sampler circuit 04 is, for example, an integrated circuit chip (IC) or a gate driver circuit (GOA) fabricated directly on the display substrate.

[0058] The display substrate 10 also includes, for example, a control circuit 02. The control circuit 02 is configured, for example, to control the data driver circuit 03 for applying data signals and the gate driver circuit for applying sampling signals. An example of the control circuit 02 is a timing control circuit (T-con). The control circuit 02 can be implemented in various forms, e.g., with a processor 021 and a memory 022, where the memory 022 contains executable codes and the processor 021 executes the executable codes to perform the aforementioned acquisition procedure.

[0059] The processor 021, for example, is a central processing unit (CPU) or other forms of processing devices with data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), and the like.

[0060] For example, memory 022 comprises one or more computer program products. These computer program products can include various types of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory includes, for example, main memory (RAM) and / or cache memory, etc. Non-volatile memory includes, for example, ROM, hard disks, flash memory, etc. One or more computer program instructions can be stored in the computer-readable storage medium, and processor 021 can execute these program instructions to perform the desired functions. Various applications and data can also be stored in the computer-readable storage media, such as the electrical parameters determined using the acquisition method mentioned above.

[0061] Fig. 3A is a schematic planar view of a display unit P of a display substrate 10 provided by at least one embodiment of the present disclosure; Fig. 3B is a schematic diagram of a third subpixel P3 in Fig. 3A; Fig. 3C is an enlarged view of part L, which is a connecting structure in Fig. 3B includes; and Fig. 4A is a schematic cross-sectional view along line AA' in Fig. 3B. With reference to Fig. 3A- Fig. 3C and Fig. 4A The light-emitting device 20 comprises a first electrode 2, and the first electrode 2 comprises a first section 21 and a second section 22, which are spaced apart from each other. The display unit P further comprises a connection structure 3 and a first transfer electrode 4. The connection structure 3 is connected to both the first section 21 and the second section 22 of the first electrode 2 and comprises a connection section 30 located in the non-light-emitting region 12; and the first transfer electrode 4 is connected to the first pole T1s of the driver transistor T1 and comprises a section located in the non-light-emitting region 12, and the connection section 30 is electrically connected in the non-light-emitting region 12 to the section of the first transfer electrode 4 located in the non-light-emitting region 12.In the display substrate 10 provided by the embodiment of the present disclosure, several sections of the first electrode 2, such as the first section 21 and the second section 22, are all connected to the first pole T1s of the driver transistor T1 via the connecting section 30 and the first transfer electrode 4, such that an opening area of ​​a subpixel (where the third subpixel P3 is taken as an example) comprises a first partial opening 601 and a second partial opening 602 (as in . Fig. (5K illustrated), and the first partial opening 601 and the second partial opening 602 are the areas corresponding to the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2, respectively. For example, the first section 21 of the first electrode 2 covers the first partial opening 601, and the second section 22 of the first electrode 2 covers the second partial opening 602. Furthermore, the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 are electrically connected in the non-light-emitting area 12 to the connecting section 30, which is located in the non-light-emitting area 12. Then, the connecting section 30 is connected to the first pole T1s of the driver transistor T1 via the section of the first transfer electrode 4, which is located in the display area 11. If a poor display, such asIf a dark spot occurs in one of the two partial openings of the aperture area of ​​the subpixel, the first section or the second section of the first electrode 2, corresponding to the position where the poor display occurs, can be cut off, ensuring that the area where the dark spot occurs does not perform the display function, reducing problems with the dark spot of the subpixel, achieving subpixel repair, improving image quality, and ensuring excellent display performance of the display substrate product.Since the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 are electrically connected to the connecting section 30 located in the non-light-emitting area 12, and then the connecting section 30 is connected to the first pole T1s of the driver transistor T1 through the section of the first transfer electrode 4 located in the display area 11, it is also convenient to provide a through-hole in the non-light-emitting area 12 to connect the connecting section 30 to the first transfer electrode 4.Compared to the solution of connecting both the first section 21 and the second section 22 of the first electrode 2 to the first transfer electrode 4 in the display area 11, because no pixel circuit is provided in the non-light-emitting area 12, in the embodiment of the present disclosure the alignment process of producing the through-hole for connecting the connecting section 30 to the first transfer electrode 4 at the position corresponding to the connecting section 30 in the non-light-emitting area 12 is relatively simple, and the yield of the display substrate can be significantly improved.

[0062] It should be noted that in at least one embodiment of the present disclosure, a longitudinal section vdd1 of the first power supply line vdd and the second power supply line vss are spaced apart in the first direction D1 and are each located at a first edge of the display area 11 in the first direction D1 and at a second edge of the display area 11 opposite the first edge in the first direction D1. The area between an edge of the longitudinal section vdd1 of the first power supply line vdd that is remote from the second power supply line vss and an edge of the second power supply line vss that is remote from the longitudinal section vdd1 of the first power supply line vdd is the display area 11.

[0063] For example, in Fig. As shown in Figure 4A, the light-emitting device is an organic light-emitting diode (OLED) comprising a first electrode 2, a second electrode 24, and a light-emitting layer 23 between the first electrode 2 and the second electrode 24. The first electrode consists, for example, of a material with a high work function, serving as the anode, such as an ITO / Ag / ITO stacked structure, an ITO / Al / ITO stacked structure (sandwich structure), or an ITO / (Al+Ag) / ITO stacked structure (sandwich structure). Of course, the first electrode is not limited to the sandwich structure mentioned above, nor is the material of the first electrode limited to the types mentioned above. The second electrode 24 consists of a material with a low work function, serving as the cathode, such as a semi-transparent metal or a metal alloy, such as an Ag / Mg alloy.For example, the light-emitting device is a top-emission structure, the first electrode 2 is a reflective electrode, and the second electrode 122 is a transmissive or semitransmissive electrode.

[0064] For example, with reference to Fig. 3B- Fig. 3C and Fig. 4A comprises the first transfer electrode 4 and a first transfer section 41, and the first transfer section 41 is located in the display area 11 and is connected to the first terminal of the driver transistor T1. The section of the connecting electrode 4 located in the non-light-emitting area 12 comprises a second transfer section 42, the second transfer section 42 is connected to the first transfer section 41, the connecting section 30 and the second transfer section 42 are located in different layers, and the connecting section 30 is connected to the second transfer section 42 in the non-light-emitting area 12 through the first through-hole V0.

[0065] For example, in Fig. As shown in Figure 4A, the display unit P further comprises a second transfer electrode 5, and the second transfer electrode 5 is located in the non-light-emitting area 12 and is arranged between the connecting section 30 and the second transfer section 42 in a direction perpendicular to the base substrate 1, and the orthographic projection of the second transfer electrode 5 on the base substrate 1 overlaps at least partially with both the orthographic projection of the connecting section 30 on the base substrate 1 and the orthographic projection of the second transfer section 5 on the base substrate 1.The connecting section 30 is connected to the second transfer section 42 by the second transfer electrode 5 to create a segmental connection, thereby reducing the hole depth of the connecting section 30, which is directly connected to the second transfer section 42 by a through hole, and improving the production yield of the display substrate.

[0066] For example, as in Fig. As shown in Figure 4A, the display substrate 10 further comprises a first insulating layer 101, a second insulating layer 102 located on a side of the first insulating layer 101 furthest from the base substrate 1, a third insulating layer 103 located on a side of the second insulating layer 102 furthest from the base substrate 1, a fourth insulating layer 104 located on a side of the second transfer electrode 5 furthest from the third insulating layer 103 in the direction perpendicular to the base substrate 1, and an intermediate insulating layer 105 located on a side of the fourth insulating layer 104 furthest from the third insulating layer 103 in the direction perpendicular to the base substrate 1.The first through-hole V0 includes a first sub-through-hole V01 that penetrates the first insulating layer 101 and the third insulating layer 103, and the second transfer electrode 5 is connected to the second transfer section 42 through the first sub-through-hole V01. The indicator substrate 10 also includes a second sub-through-hole V02 that penetrates the fourth insulating layer 104, and the connecting section 30 is connected to the second transfer electrode 5 through the second sub-through-hole V02, thus achieving the connection between the connecting section 30 and the second transfer section 42 via the multi-stage through-hole.

[0067] For example, the first transfer section 41 and the second transfer section 42 form a continuous structure and are manufactured as a single piece. The material of the first transfer electrode 4 is, for example, a metallic material such as copper, aluminum, chromium, a copper alloy, an aluminum alloy, a chromium alloy, a manganese alloy, etc., but is not limited to the types listed above.

[0068] For example, the display unit P further comprises an intermediate insulating layer 105, wherein the intermediate insulating layer 105 is arranged in the display area 11 and not in the non-light-emitting area 12, and in the direction perpendicular to the base substrate 1, the intermediate insulating layer 105 is arranged between the first electrode 2 and the second transfer electrode 5. As shown in Fig. 4A and Fig. As shown in Figure 5H, the first electrode 2 is electrically connected to the first pole T1s of the driver transistor T1 through an opening O1 that penetrates the interlayer insulating layer 5 in a direction perpendicular to the base substrate 1. The opening O1 is, for example, connected to the second sub-through hole V02, and the first electrode 2 enters the second sub-through hole V02 through the opening O1, which penetrates the interlayer insulating layer 5, to be connected to the second transfer electrode 5. For example, the orthographic projection of the first through-hole on the base substrate 1 is located within the orthographic projection of the aperture O1 on the base substrate 1, i.e., the orthographic projections of the second sub-through-hole V02 and the first sub-through-hole V01 on the base substrate 1 are located within the orthographic projection of the aperture O1 on the base substrate 1.In this way, the first electrode 2 can be electrically connected to the first pole T1s of the driver transistor T1 via the larger opening O1 in the interlayer insulating layer 105 in the non-light-emitting area, which facilitates the connection of the junction section 30 and the second transfer electrode 5 in the non-light-emitting area. Manufacturing the larger opening O1 in the non-light-emitting area requires less complex manufacturing processes and is easy to implement. Furthermore, the manufacturing of the opening O1 exhibits high accuracy and minimal impact on surrounding structures, thus avoiding the problem of low through-hole production yield and significant impact on surrounding structures caused by the limited space available for punching holes in the insulating layer in the display area 11.

[0069] For example, in Fig. As shown in Figure 4A, the interlayer insulating layer 105 is located in the display area 11 and not in the non-light-emitting area 12A, i.e., the interlayer insulating layer 105 does not include any section that lies in the non-light-emitting area 12A.For example, in the production of the interlayer insulating layer 105, a section of a material layer used to form the interlayer insulating layer 105 located in the non-light-emitting region 12A is completely removed by a patterning process, so that the opening O1 is formed in a region of the non-light-emitting region and in the same layer as the interlayer insulating layer 105, that is, the orthographic projection of the opening O1 on the base substrate 1 is located within the non-light-emitting region 12A, and the area of ​​the orthographic projection of the opening O1 on the base substrate 1 is equal to the area of ​​the non-light-emitting region 12A.In this way, by not providing the interlayer insulating layer 105 in the non-light-emitting area, compared to the solution of producing a through-hole in the non-light-emitting area 12A through which the first electrode 2 passes, the manufacturing difficulty of the interlayer insulating layer 105 is further reduced and the manufacturing yield of the indicator substrate is improved.

[0070] For example, the area of ​​the orthographic projection of aperture O1 on the base substrate 1 is larger than the area of ​​the orthographic projection of a subpixel adjacent to aperture O1 on the base substrate 1. For example, with respect to Fig. 4A and Fig. 1, in the arrangement direction of the display area 11 and the non-light-emitting area 12A, the maximum width W1 of the aperture O1 is greater than the maximum width W2 of a subpixel, and here a subpixel P3 adjacent to the aperture O1 is taken as an example.

[0071] In other embodiments, for example, as in Fig. In 4D representation, the orthographic projection of the opening O1 on the base substrate 1 is located within the non-light-emitting area 12A, and the area of ​​the orthographic projection of the opening O1 on the base substrate 1 is smaller than the area of ​​the non-light-emitting area 12A. This means that during the manufacturing process of the interlayer insulating layer 105, a portion of the section located within the non-light-emitting area 12A of the material layer used to form the interlayer insulating layer 105 is removed by a patterning process, thereby forming the opening O1. The opening O1 is a larger through-hole that passes through the interlayer insulating layer 105, and the edge of the opening O1 is at least partially surrounded by the material of the interlayer insulating layer 105. Other features and corresponding technical effects of the in Fig. The embodiments shown in 4D are the same as those in Fig. 4A, see description of Fig. 4A.

[0072] For example, as in Fig. As shown in Figure 4A, the interlayer insulating layer 105 has a defect that forms a height difference between the interlayer insulating layer 105 and the adjacent structure at the transition between the display area 11 and the non-light-emitting area 12A, i.e., there is a stepped structure 001 at the edge of the interlayer insulating layer 105 located near the non-light-emitting area 12, wherein the first electrode 2 covers the stepped structure 001 and thus crosses the stepped structure 001 and extends to the non-light-emitting area 12, and the interlayer insulating layer 105 is not provided on a side of the stepped structure 001 located near the non-light-emitting area 12, so that the connecting section 30 is located in the space on a side of the position of the height difference of the It can be arranged in a stepped structure 001. Compared to the solution,In the present embodiment, where the intermediate insulating layer 105 is arranged in both the display area 11 and the non-light-emitting area 12A, the creation of the through-hole that penetrates the intermediate insulating layer 105 and is used to connect the connection section 30 and the second transfer electrode 5 in the intermediate insulating layer 105 can be avoided. This simplifies the manufacturing process of the display substrate and is of great importance for improving the yield of the display substrate. Since the thickness of the intermediate insulating layer 105 is relatively large in the direction perpendicular to the base substrate 1, for example, the thickness of the intermediate insulating layer 105 in the direction perpendicular to the base substrate 1 is greater than 6000 angstroms in order to fulfill its function as insulation and as a planarizing layer when the through-hole is present,that penetrates the interlayer insulating layer 105 and is used to connect the connection section 30 and the second transfer electrode 5, and the size of this through-hole differs from the size of a through-hole for other purposes in the interlayer insulating layer 105 in a direction parallel to the base substrate, for example, it is required that the size of this through-hole be relatively large in the direction parallel to the base substrate, making it more difficult to meet these different sizes of the various through-holes simultaneously when the different through-holes passing through the interlayer insulating layer 105 are produced by one and the same structuring process, and ensuring the alignment rate of the mask is more difficult, and the thickness of the interlayer insulating layer 105 is greater, making it more difficult toto meet the accuracy of these different dimensions during an etching process. However, the above-mentioned solution of the embodiments of the present disclosure can avoid the production of the through-hole that penetrates the intermediate insulating layer 105 and is used to connect the connecting section 30 and the second transfer electrode 5 in the intermediate insulating layer 105, thereby avoiding the problems mentioned above.

[0073] The material of the intermediate insulating layer 105, for example, is an organic insulating material. Organic insulating materials include, for example, resin materials, acrylic materials, etc., such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc., but are not limited to the types listed above. For example, the intermediate insulating layer 105 is a planar layer.

[0074] The first insulating layer 101, the second insulating layer 102, the third insulating layer 103 and the fourth insulating layer 104 are, for example, inorganic insulating layers consisting of silicon oxides such as silicon oxide, silicon nitride or silicon oxynitride or silicon nitrides or silicon oxynitrides or insulating materials including metal oxynitride such as aluminum oxide, titanium nitride, etc.

[0075] For example, in Fig. As shown in Figure 3A, the display substrate 10 also includes a first signal line G1 / G2 and second signal lines D1-D4, which are provided on the base substrate 1. The first signal line G1 / G2 transmits a sampling signal; for example, the first signal line includes a first sampling signal sub-line G1 and a second sampling signal sub-line G2; the first sampling signal sub-line G1 transmits a first sampling signal, and the second sampling signal sub-line G2 transmits a second sampling signal; for example, the first sampling signal and the second sampling signal can be line-wise sampling signals, for example, the first sampling signal and the second sampling signal are the same sampling signal, and this case can be applied to the above-mentioned Fig. 2B may be referenced; or in other embodiments, the first sampling signal and the second sampling signal are different signals. For example, the second signal lines D1-D4 each carry the data signal DT; the first signal line extends along the first direction D1 as a whole, and the second signal lines D1-D4 extend along the second direction D2, which intersects the first direction D1; and the subpixel further comprises a data write transistor T2, and the data write transistor T2 is configured to transfer the data signal to the driver transistor T1 under the control of the first sampling signal.

[0076] It should be noted that “extend along the first direction D1 as a whole” includes extending essentially along the first direction D1, as long as it extends at least along the first direction D1 as a whole. For example, in some examples, the first signal line extending along the first direction D1 as a whole may contain a certain curved section, or in some examples, an edge of a strip extending along the second direction D2 may not be a smooth line as a whole; for example, the edge of the line may contain ridges or sawtooth edges—in short, as long as the overall tendency to extend is along the first direction D1. The same applies to the description “extend along the second direction D2 as a whole,” and the same applies to the meaning of the extension in a certain direction as a whole mentioned in the present disclosure.

[0077] With reference to Fig. 3B- Fig. 3C comprises the connection structure 3, for example, at least two extension sections, and the at least two extension sections comprise a first extension section 31 and a second extension section 32. The first extension section 31 comprises a first end and a second end opposite the first end of the first extension section 31 and extends from the display area 11 to the non-light-emitting area 12, wherein the first end of the first extension section 31 is connected to the first section 21 of the first electrode 2 and the second end of the first extension section 31 is located in the non-light-emitting area 12; the second extension section 32 comprises a first end and a second end opposite the first end of the second extension section 32 and extends from the display area 11 to the non-light-emitting area 12.The first end of the second extension section 32 is connected to the second section 22 of the first electrode 2, and the second end of the second extension section 32 is located in the non-light-emitting area 12; and the connecting section 30 is connected to the second end of the first extension section 31 and the second end of the second extension section 32. In this way, the connecting section 30 is connected to the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2, respectively, via at least two channels, namely the first extension section 31 and the second extension section 32. If a poor display, such as a dark spot, occurs in an area selected from a group consisting of an area corresponding to the first section 21 of the first electrode 2, the aperture area of ​​the third subpixel P3, and an areaThe area corresponding to the second section 22 of the first electrode 2, which consists of the opening area of ​​the third subpixel P3, can be either the first extension section 31 or the second extension section 32, which corresponds to the area where a poor display, such as a dark spot, occurs. This ensures that the area with the poor display, such as a dark spot, does not perform the display function. The first extension section 31 and the second extension section 32 have the form of a strip extending along the first direction D1, which facilitates clipping, thus simplifying subpixel repair and improving display quality.

[0078] For example, the second end of the first extension section 31 has a first cuttable section 310, and the second end of the second extension section 32 has a second cuttable section 320. There is no conductive layer overlapping the first cuttable section 310 in the direction perpendicular to the base substrate 1 on a side of the first cuttable section 310 close to the base substrate 1 and at a position directly opposite the first cuttable section 310, and there is no conductive layer overlapping the second cuttable section 320 in the direction perpendicular to the base substrate 1 on a side of the second cuttable section 320 close to the base substrate 1 and at a position directly opposite the second cuttable section 320. In this way, if a poor indication, such asa dark spot that occurs in a subpixel, other conductive layers are not damaged during the cutting process of cutting off the first cuttable section 310 or the second cuttable section 320, thus facilitating the cutting process, achieving the repair of the subpixel and improving the display quality.

[0079] For example, as in Fig. The maximum width W is shown in 3C. SPa gap between the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 in the second direction D2 smaller than the maximum width Wc of the connecting section 30 in the second direction D2, to ensure that the connecting section 30 has a sufficient width in the second direction D2 to connect the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2, and to ensure that the distance between the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 should not be too large to take up too much space in order to achieve a display field with high PPI at the same time.

[0080] For example, the first section 21 of the first electrode 2, the second section 22 of the first electrode 2, the first extension section 31, the second extension section 32 and the connecting section 30 form a continuous structure and are formed in one piece to simplify the structure of the display substrate, and the above-mentioned continuous and one-piece structure can be formed by performing an identical patterning process on an identical layer of material, which simplifies the manufacturing process of the display substrate.

[0081] For example, as in Fig. 3A- Fig. As shown in Figure 3B, each subpixel further comprises a first power supply line vdd, wherein the first power supply line vdd is connected to a first voltage terminal VDD and is configured to provide a first power supply voltage for the subpixel, wherein the first power supply line vdd is located in the same layer as the first pole of the driver transistor T1 and comprises a longitudinal section vdd1, and wherein the longitudinal section vdd1 extends as a whole along the second direction D2 and is electrically connected to a subpixel adjacent to the longitudinal section vdd1.For example, the first power supply line vdd further comprises a transverse section vdd2, and the transverse section vdd2 is electrically connected to the longitudinal section vdd1 and extends along the first direction D1 as a whole to be connected to each subpixel of the display unit, thereby providing the first power supply voltage for each subpixel of the display unit. For example, the transverse section vdd2 is in . Fig. 3B is electrically connected to the third subpixel P3 and the fourth subpixel P4, and Fig. Figure 3A further shows another transverse section vdd2, which is connected to the longitudinal section vdd2 and electrically connected to the first subpixel P1 and the second subpixel P2, such that the first supply voltage is delivered from the longitudinal section vdd1 to each subpixel of the display unit. For example, the first extension section 31 and the second extension section 32 extend across the first supply line vdd and the second signal line to the non-light-emitting area 12, to be connected to the link section located in the non-light-emitting area 12.

[0082] For example, regarding Fig. In 3A, the non-light-emitting area 12 and the display area 11 are arranged in the second direction D2, the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 are arranged in the second direction D2, and the extension section 31 and the second extension section 32 both extend along the first direction D1 as a whole. Such an arrangement mode can coordinate the positions of the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 and the position of the non-light-emitting area corresponding to the subpixel in which the first electrode 2 is located, so that it is convenient to separate the first extension section 31 and the second extension section 32 from the first section 21 of the first electrode 2 and the second extension section 32, respectively.to lead out of the second section 22 of the first electrode 2 to the non-light-emitting area 12, and it is advantageous to ensure that the connecting section 30 in the non-light-emitting area 12 is connected to both the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2.

[0083] For example, the non-light-emitting area 12 comprises a first non-light-emitting area 12A and a second non-light-emitting area 12B, wherein the first non-light-emitting area 12A is arranged on a first side of the display area 11 in the first direction D1, and the second non-light-emitting area 12B is arranged on a second side opposite the first side of the display area 11 in the first direction D1; the first subpixel P1 and the third subpixel P3 are adjacent to the first non-light-emitting area 12A, and the second subpixel P2 and the fourth subpixel P4 are adjacent to the first non-light-emitting area 12A;each of the plurality of subpixels is provided with the connection structure 3, and the connection structure 3 is connected to both the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 of a subpixel adjacent to the connection structure 3; the connection section 30, which corresponds to the connection structure 3 of the first subpixel P1, and the connection section 30, which corresponds to the connection structure 3 of the third subpixel P3, are arranged in the first non-light-emitting area 12A;and the connection section 30, which corresponds to the connection structure 3 of the second subpixel P2, and the connection section 30, which corresponds to the connection structure 3 of the fourth subpixel P4, are arranged in the second non-light-emitting area 12B, such that the first electrode of each subpixel of the display unit P comprises a first section and a second section, and the first section of the first electrode and the second section of the first electrode of each subpixel can be connected to the first pole T1s of the driver transistor T1, which is located in the display area 11, via the connection section and the first transfer electrode (or the first transfer electrode and the second transfer electrode) which are located in the non-light-emitting area corresponding to the respective subpixel.

[0084] For example, in Fig. As shown in 3A, the first signal line G1 / G2, which delivers sampling signals to the first subpixel P1, the second subpixel P2, the third subpixel P3 and the fourth subpixel P4, is located in a border area between the first pixel row and the second pixel row, in order to deliver sampling signals to the first pixel row and the second pixel row on both sides of the border area.

[0085] For example, the planar patterns of the first subpixel P1 and the second subpixel P2 are symmetrical with respect to an axis of symmetry extending along the second direction D2, the planar patterns of the third subpixel P3 and the fourth subpixel P4 are symmetrical with respect to the axis of symmetry, and the planar patterns of the first non-light-emitting area 12A and the second non-light-emitting area 12B are symmetrical with respect to the axis of symmetry in order to make reasonable use of space and improve the uniformity of the display substrate, thereby improving the uniformity of the display in the display area and reducing the manufacturing difficulty of the display substrate.

[0086] With reference to Fig. 4A, the display unit P, for example, further comprises a pixel definition layer 6, and the pixel definition layer 6 comprises a first section 61 and a second section 62. The first section 61 is located between the first electrodes 2 of adjacent subpixels to define an opening region 60 of the subpixel, and the light-emitting layer 23 of the light-emitting device 20 is located at least within the opening region 60. The second section 62 is located between the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 to space the first section 21 of the first electrode 2 apart from the second section 22 of the first electrode 2.

[0087] For example, in Fig. As shown in Figure 4A, the orthographic projection of the connection section 30 on the base substrate 1 is located within the orthographic projection of the first section 61 of the pixel definition layer 6 on the base substrate 1, in order to avoid the connection section 30 and the first section 61 of the pixel definition layer 6 occupying independent space, in order to save space and to use the first section 61 of the pixel definition layer 6 to protect the connection section 30.

[0088] For example, the light-emitting device of the display substrate 10, which is provided in some embodiments of the present disclosure, can assume a top-emission structure.

[0089] For example, as in Fig. As shown in Figure 4A, where the third subpixel P3 is taken as an example, each subpixel further comprises a first capacitor C1; the first capacitor C1 comprises a first electrode plate Ca and a second electrode plate Cb; the first electrode plate Ca is electrically connected to the gate electrode T1g of the driver transistor T1 and is provided in the same layer as the gate electrode of the driver transistor T1, for example, the first electrode plate Ca and the gate electrode T1g of the driver transistor T1 form a continuous structure and are formed in one piece; and the orthographic projection of the second electrode plate Cb on the base substrate 1 overlaps at least partially with the orthographic projection of the first electrode plate Ca on the base substrate 1.

[0090] For example, as in Fig. As shown in Figure 4A, taking the third subpixel P3 as an example, the subpixel also includes a second capacitor C2, and the second capacitor C2 includes the first electrode plate Ca and a third plate Cc; the third plate Cc has an overlapping section and a non-overlapping section, the orthographic projection of the overlapping section on the base substrate 1 overlaps with the orthographic projection of the first electrode plate Ca on the base substrate 1, and the orthographic projection of the non-overlapping section on the base substrate 1 does not overlap with the orthographic projection of the first electrode plate Ca on the base substrate 1 and overlaps at least partially with the orthographic projection of the second electrode plate Cb on the base substrate 1. Fig. 4B is a schematic cross-sectional view along line BB' and line CC' in Fig. 3B, as in Fig. As shown in 4B, the non-overlapping section is connected to the second electrode plate Cb through the second through-hole V2, and the third electrode plate Cc also serves as the first transfer section 41, i.e. the first transfer section 41 is electrically connected to the second electrode plate Cb through the second through-hole V2 to simplify the structure and manufacturing process of the display substrate 10.

[0091] For example, as in Fig. As shown in Figure 4B, the second electrode plate Cb is located in the same layer as the first pole T1s of the driver transistor T1. For example, the second electrode plate Cb and the first pole T1s of the driver transistor T1 form a continuous structure and are formed in one piece to achieve the electrical connection between the second electrode plate Cb and the first pole T1s of the driver transistor T1, thereby establishing the electrical connection between the first transfer section 41 and the first pole T1s of the driver transistor T1. Using the third electrode plate Cc as the first transfer section 41 and forming the second electrode plate Cb and the first pole T1s of the driver transistor T1 into a continuous and one-piece structure significantly simplifies the structure and manufacturing process of the display substrate 10.

[0092] For example, as in Fig. As shown in Figure 4B, the first terminal T1s of the driver transistor T1 is connected to an active layer T1a of the driver transistor T1 by a plurality of through-holes to reduce the contact resistance between them; for example, the plurality of through-holes are spaced apart along the second direction D2; for example, the first terminal T1s of the driver transistor T1 is connected to the active layer T1a of the driver transistor T1 by three through-holes V91, V92, and V93, and the through-holes V91, V92, and V93 penetrate both the second insulating layer 102 and the third insulating layer 103. Of course, the number of through-holes is not limited to three but can be designed as required.

[0093] Fig. 5A is a schematic planar view of the first conductive layer of the in Fig. 3A shown display unit; Fig. 5B is a schematic planar view of a first insulating layer of the in Fig. 3A shown display unit; Fig. 5C is a schematic planar view of the semiconductor layer of the in Fig. 3A shown display unit; Fig. 5D is a schematic planar view of the second conductive layer of the in Fig. 3A shown display unit; Fig. 5E is a schematic planar view of the third insulating layer of the in Fig. 3A shown display unit; Fig. 5F is a schematic planar view of the third conducting layer of the in Fig. 3A shown display unit; Fig. 5G is a schematic planar view of a fourth insulating layer of the in Fig. 3A shown display unit; Fig. 5H is a schematic planar view of a fifth insulating layer of the in Fig. 3A; Fig. 5I is a schematic planar view of the fourth conducting layer of the in Fig. 3A display unit shown; and Fig. 5J is a schematic planar view of the fifth conductive layer of the in Fig. 3A shown display unit. As in Fig. 5A- Fig. 5I and in conjunction with Fig. As shown in Figure 4A, the display substrate 10 comprises a first conductive layer 100, a first insulating layer 101, a semiconductor layer 600, a second insulating layer 102, a second conductive layer 200, a third insulating layer 103, a third conductive layer 300, a fourth insulating layer 104, a fifth insulating layer 105, a fourth conductive layer 400 and a fifth conductive layer 500, which are stacked successively on the base substrate 1 along the direction from a position close to the base substrate 1 to a position farther away from the base substrate 1, and the fifth insulating layer 105 is also the aforementioned intermediate insulating layer 105.

[0094] The material of the semiconductor layer 600 includes, for example, a silicon-based material (a-Si, p-Si, etc.), a metal oxide semiconductor (IGZO, ZnO, AZO, IZTO, etc.) and an organic material (sexithiophene, polythiophene, etc.).

[0095] As in Fig. 4A und Fig. 5A- Fig. As shown in Figure 5J, the first conductive layer 100 comprises the first transfer section 41, the second transfer section 42 and the third electrode plate Cc; the semiconductor layer 600 comprises the active layer T1a of the driver transistor T1, the active layer T2a of the data transistor T2 and the active layer T3a of the sensing transistor T3; the second conductive layer 200 comprises the first sampling signal part line G1 and the second sampling signal part line G2, the gate electrode T1g of the driver transistor T1, the gate electrode T2g of the data transistor T2, the gate electrode T3g of the sensing transistor T3, the first electrode plate Ca, the cross section vdd2 of the first power supply line vdd and the auxiliary power supply line vdd3;the auxiliary power supply line vdd3 extends along the second direction D2, corresponding to the longitudinal section vdd1 of the first power supply line vdd, and is electrically connected to the longitudinal section vdd1 of the first power supply line vdd by a plurality of through holes V4 that penetrate the third insulating layer 103 in order to be connected in parallel with the longitudinal section vdd1 of the first power supply line vdd in order to achieve the effect of reducing the resistance of the first power supply line vdd; furthermore, as in ; Fig. As shown in Figure 5D, the auxiliary power supply line vdd3 is electrically connected to the transverse section vdd2, so that the transverse section vdd2 is electrically connected to the longitudinal section vdd1. For example, the auxiliary power supply line vdd3 and the transverse section vdd2 are provided in the same layer, and both are located in the second conductive layer 200. For example, the auxiliary power supply line vdd3 and the transverse section vdd2 form a continuous structure and are formed in one piece. The third conductive layer 300 comprises the first pole T1s and the second pole T1d of the driver transistor T1, the first pole T2s and the second pole T2d of the data transistor T2, the first pole T3s and the second pole T3d of the detection transistor T3, the data line D1\D2\D3\D4, the detection signal line S, and the longitudinal section vdd1 of the first power supply line vdd. Fig. 4A and Fig. 5H shows that the above-mentioned intermediate insulating layer 105 is only provided in the display area 11, and that there is no intermediate insulating layer 105 in the non-light-emitting area 12.

[0096] With reference to Fig. 4A and Fig. For example, both the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 are electrically connected to the first pole T1s of the driver transistor T1 and each comprises a first electrode sublayer 2a, a second electrode sublayer 2b, and a third electrode sublayer 2c, which are stacked on top of each other in the direction perpendicular to the base substrate 1, from a position close to the base substrate 1 to a position farther away from the base substrate 1. The fourth conductive layer 400 comprises the connecting section 30, the first extension section 31, the second extension section 32, the first electrode sublayer 2a of the first section 21, and the first electrode sublayer 2a of the second section 22. The fifth conductive layer 500 comprises the third electrode sublayer 2c of the first section 21 and the third electrode sublayer 2c of the second section 22.For example, the display substrate 10 further comprises a sixth conductive layer, the sixth conductive layer is located between the fourth conductive layer 400 and the fifth conductive layer 500 in the direction perpendicular to the base substrate 1, and the sixth conductive layer comprises the second electrode sublayer 2b of the first section 21 and the second electrode sublayer 2b of the second section 22.

[0097] Fig. 4C is a schematic cross-sectional view along the line DD' in Fig. 3A. With reference to Fig. 5A and Fig. 4C comprises the first conductive layer 100 and an intermediate connection section 43, which is located, for example, at the boundary between the first and second pixel rows. The second terminal T3d of the sensing transistor T3 is connected to the active layer T3a of the sensing transistor T3 through the intermediate connection hole V33, which passes through the third insulating layer 103, and is connected to the intermediate connection section 43 through the second connection hole V32, which passes through the third insulating layer 103 and the first insulating layer 101; and the sensing signal line S is connected to the intermediate connection section 43 through the first connection hole V31, which passes through the third insulating layer 103 and the first insulating layer 101, to establish the connection between the sensing signal line S and the second terminal T3d of the sensing transistor T3.Furthermore, the second pole T3d' of the sensing transistor of the fourth subpixel P4 is connected to the active layer T3a' of the sensing transistor of the fourth subpixel P4 through the through-hole V35, which passes through the third insulating layer 103, and is connected to the intermediate connection section 43 through the through-hole V34, which passes through the third insulating layer 103 and the first insulating layer 101, so that the second pole T3d of the sensing transistor of the third subpixel P3 and the second pole T3d' of the sensing transistor of the fourth subpixel P4 are connected to the same sensing signal line S through the same intermediate connection section 43, which simplifies the construction and manufacturing process of the display substrate 10.

[0098] For example, as in Fig. 4C and Fig. As shown in Figure 5C, for example, the second pole T3d of the sensing transistor T3 of the first subpixel P1 (i.e., the upper subpixel below) and the second pole T3d of the sensing transistor T3 of the third subpixel P3 (i.e., the lower subpixel below) form a continuous and one-piece electrode, the active layer T3a of the sensing transistor T3 of the first subpixel P1 and the active layer T3a of the sensing transistor T3 of the third subpixel P3 form a continuous and one-piece active layer IAL, and the continuous and one-piece electrode is electrically connected to the continuous and one-piece active layer IAL through the through-hole V33.

[0099] For example, in Fig. As shown in Figure 4A, the third electrode plate Cc is located on the side of the first electrode plate Ca that is closest to the base substrate 1.

[0100] With reference to Fig. 4A and Fig. For example, in 5A, the display substrate 10 further comprises a light-shielding layer 7, and the light-shielding layer 7 is located on the side of the semiconductor layer 200 closest to the base substrate 1. The orthographic projection of the active pattern (i.e., the active layer T1a or channel region) of the driver transistor T1 on the base substrate 1 is located within the orthographic projection of the light-shielding layer 7 on the base substrate 1, so that the light-shielding layer 7 is used to shield the peak light from the side of the active pattern of the driver transistor T1 furthest from the base substrate 1, in order to prevent the peak light from entering the channel region of the driver transistor T1, thereby preventing the light from degrading the performance of the driver transistor T1.For example, the light-emitting device 20 is a top-emission type, and the light emitted by the light-emitting layer 23 is emitted from the side of the light-emitting device 20 furthest from the base substrate 1. Of course, the light-emitting device 20 can also emit from below, and the light emitted by the light-emitting layer 23 is emitted through the base substrate 1. For example, the light-shielding layer 7 also serves as the first transfer section 41; that is, the light-shielding layer 7 and the first transfer section 41 are the same structure to simplify the structure and manufacturing process of the display substrate 10.

[0101] At least one embodiment of the present disclosure further provides a method for operating a display substrate that is applicable to each of the display substrates 10 provided by the embodiments of the present disclosure. Referring to Fig. 3C comprises the operating procedure: cutting off a section of the interconnect structure 3 of the display substrate 10, which is located in the non-light-emitting area, in order to separate the interconnect structure 3 from one of the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2. Here, "separating" means that the interconnect structure 3 is no longer electrically connected to one of the first section 21 and the second section 22; for example, one of the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 is separated from the interconnect section 30 of the interconnect structure 3, which is located in the non-light-emitting area 12. In this way, taking the third subpixel P3 as an example, if a poor display, such as...If a dark spot occurs in an area selected from a group consisting, for example, of an area corresponding to the first section 21 of the first electrode 2, the opening area of ​​the subpixel, and an area corresponding to the second section 22 of the first electrode 2, the opening area of ​​the subpixel, when a poor display, such as a dark spot, occurs in the area corresponding to the first section 21 of the first electrode 2, the first section 21 of the first electrode 2 can be disconnected from the connection structure 3, so that the area with the poor display, such as a dark spot, does not perform the display function in order to repair the subpixel and improve the display quality.

[0102] For example, on the side of the interconnection structure 3 located near the base substrate 1, no conductive layer overlaps with the cut-off portion of the interconnection structure 3 in the direction perpendicular to the base substrate 1. Similarly, on the side of the first cuttable section 310 located near the base substrate 1, no conductive layer overlaps with the first cuttable section 310 in the direction perpendicular to the base substrate 1, and on the side of the second cuttable section 320 located near the base substrate 1, no conductive layer overlaps with the second cuttable section 320 in the direction perpendicular to the base substrate 1. In this case, the method for operating the indicator substrate involves cutting off one of the first cuttable section 310 and one of the second cuttable section 320 to separate one of the first section 21 of the first electrode 2 and one of the second section 22 of the first electrode 2 from the interconnection section 30.In this way, other conductive layers are not damaged during the cutting process when cutting off the first cuttable section 310 or the second cuttable section 320, thus facilitating the cutting process, thereby achieving subpixel repair and improving display quality. For example, the first cuttable section 310 or the second cuttable section 320 is cut off by a laser irradiation process to form a notch (not shown in the figures). For example, the notch separates the first cuttable section 310 or the second cuttable section 320 into two sections spaced apart in the first direction D1. One section is connected to the first section of the first electrode or the second section of the first electrode, and the other section is connected to the connecting section 30.

[0103] At least one embodiment of the present disclosure further provides a display substrate, wherein the display substrate comprises a base substrate, a display unit, a scanning signal line, and a longitudinal signal line. The display unit is provided on the base substrate and comprises a display area and a non-light-emitting area; the display area comprises a subpixel, the subpixel comprises a driver transistor and a light-emitting device, the driver transistor is configured to control the magnitude of a driver current flowing through the light-emitting device, and the light-emitting device is configured to receive the driver current and be driven by the driver current to emit light; the scanning signal line is provided on the base substrate and extends as a whole along a first direction.The transmission line runs through the non-light-emitting area and the display area and transmits a scanning signal; the longitudinal signal line is provided on the base substrate and is located in the display area and extends along a second direction that intersects the first direction as a whole; and the scanning signal line comprises at least one outer ring segment, and each of the at least one outer ring segment comprises a first conductive line and a second conductive line. The first conductive line extends along the first direction as a whole and extends from the non-light-emitting area to the display area; the second conductive line extends along the first direction as a whole,extends from the non-light-emitting region to the display region and is spaced apart in the second direction from the first conductive line; both the first conductive line and the second conductive line overlap with the longitudinal signal line in a direction perpendicular to the base substrate; and the scanning signal line comprises a body section that extends as a whole along the first direction, and both the first conductive line and the second conductive line are electrically connected to the body section. In the display substrate, the first conductive line and the second conductive line transmit the same scanning signal, and the first conductive line and the second conductive line of the at least one outer ring section extend from the non-light-emitting region to the display region.to overlap with the longitudinal signal line. In this way, the at least one outer ring section can effectively reduce the load (or resistance) of the scanning signal line while avoiding excessive overlap with the longitudinal signal line. Furthermore, the first and second conductive lines of the at least one outer ring section extend from the non-light-emitting area to the display area to overlap with the longitudinal signal line, which is located at the edge of the display area closest to the non-light-emitting area, in a direction perpendicular to the base substrate. Thus, if a problem such as a short circuit occurs at the overlap between the longitudinal signal line and a line selected from a group consisting of the first and second conductive lines of the same outer ring section, the short-circuited line selected from the group canwhich consists of the first conductive line and the second conductive line, are cut off to cause the short-circuited line to stop working, to prevent the display effect of the display unit on which the short-circuited line is located from being affected, and to achieve pixel repair of the display unit.

[0104] For example, Fig. 6A a schematic enlarged view of part A including the at least one outer ring section in Fig. 3A. With reference to Fig. 3A, Fig. 6A and Fig. 5D includes the display substrate 10 and a longitudinal signal line provided on the base substrate 1 and arranged in the display area 11, extending as a whole along the second direction D2, which intersects the first direction D1. The longitudinal signal line includes, for example, the aforementioned first power supply line vdd, the second power supply line vss, the data lines D1-D4, the sensing line S, a connecting line (described below), and the like. In the Fig. 3A and Fig. In the embodiments shown in Figure 6A, the first scanning signal sub-line G1, which extends as a whole along the first direction D1, transmits the first scanning signal and comprises a first outer ring section R1. The aforementioned at least one outer ring section comprises the first outer ring section R1, which in turn comprises a first conductive line R11 and a second conductive line R12. The first conductive line R11 of the first outer ring section R1 extends as a whole along the first direction D1 and from the non-light-emitting area 12A to the display area 11. The second conductive line R12 of the first outer ring section R1 extends as a whole along the first direction D1, from the non-light-emitting area 12A to the display area 11, and is spaced apart from the first conductive line R11 of the first outer ring section R1 in the second direction D2.The first sampling signal sub-line G1 comprises a first body section G10, which extends along the first direction D1 as a whole, and the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R1 are both connected to the first body section G10, so that the first conductive line R11 of the first outer ring section R1, the second conductive line R12 of the first outer ring section R1 and the first body section G10 transmit the first sampling signal.

[0105] As mentioned above, the display substrate 10 includes the first power supply line vdd, and the first power supply line vdd is connected to the first voltage terminal and configured to supply the first power supply voltage to the subpixels, and includes the longitudinal section vdd1, which extends along the second direction D2 as a whole. As in Fig. As shown in Figure 6A, the longitudinal signal line comprises the longitudinal section vdd1 of the first power supply line vdd, and both the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R1 overlap with the longitudinal section vdd1 of the first power supply line vdd in the direction perpendicular to the base substrate 1. In this way, the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R1 both extend from the non-light-emitting area 12A to the display area 11, so that the first conductive line R11 and the second conductive line R12 can overlap with the longitudinal signal line, such as the first power supply line vdd, in the direction perpendicular to the base substrate 1.which is located at an edge of the display area 11 close to the non-light-emitting area 12A. Thus, the first outer ring section R1 can effectively reduce the load (or resistance) of the first sampling signal sub-line G1 and avoid excessive overlap with the longitudinal section vdd1, and there are only two overlapping sections between the first sampling signal sub-line G1 and the longitudinal section vdd1. If a problem such as a short circuit occurs on the overlapping section between the longitudinal section vdd1 and a line selected from a group consisting of the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R1, the one line selected from the group consisting of the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R1 that is short-circuited,can be cut off, for example, the one conductor selected from the group consisting of the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R1, which is short-circuited, at the position of the first side or the second side that are opposite each other in the first direction D1, of the longitudinal section vdd1, so that the cut conductive line ceases to function in order to avoid impairing the display effect of the display unit P, where the one that is short-circuited is located, and to achieve pixel repair of the display unit P; and the one selected from the group consisting of the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R, which is not cut off,continues to provide the first sampling signal for the multitude of subpixels P1-P4 of the display unit P, in order to allow the multitude of subpixels P1-P4 of the display unit P to operate normally and to reduce the effects of the aforementioned short-circuit problem on the display effect.

[0106] For example, the longitudinal signal line further includes a data signal line DT, and the data signal line transmits a data signal DT; the first sampling signal sub-line G1 is configured to supply a first sampling signal to the data write transistor T2, for example, the first sampling signal sub-line G1 supplies the first sampling signal to the plurality of subpixels P1-P4. In the Fig. In the embodiment shown in Figure 6A, for example, the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R1 overlap with the first data signal line D1 in the direction perpendicular to the base substrate 1. Of course, in other embodiments, the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R1 can overlap with the second data signal line D2 in the direction perpendicular to the base substrate 1, or overlap with the third data signal line D3 in the direction perpendicular to the base substrate 1, or overlap with the fourth data signal line D4 in the direction perpendicular to the base substrate 1.In other embodiments, for example, the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R1 can also overlap with a plurality of data signal lines of the display unit P, which can be designed as required.

[0107] For example, the non-light-emitting area of ​​the display unit P comprises a first non-light-emitting area 12A and a second non-light-emitting area 12B, wherein the first non-light-emitting area 12A is located on the first side of the display area 11 in the first direction D1, and the second non-light-emitting area 12B is located on the second side, opposite the first side, of the display area 11 in the first direction D1; and the first scanning signal sub-line G1 passes sequentially through the first non-light-emitting area 12A, the display area 11, and the second non-light-emitting area 12B. The first body section G10 comprises a first section G101 located in the first non-light-emitting area 12A and a second section G102 located in the second non-light-emitting area 12B;and the first sampling signal sub-line G1 further comprises a first branch section and a second branch section. The first branch section is connected to the first section G101 of the first body section G10 and the second section G102 of the first body section G10 and comprises the first conductive line R11 of the first outer ring section R1; the first conductive line R11 of the first outer ring section R1 is located on the first side of the first body section G10 in the second direction D2, and the first conductive line R11 of the first outer ring section R1 is electrically connected to the first body section G10; wherein the second branch section is connected to the first section G101 of the first body section G10 and the second section G102 of the first body section G10 and comprises the second conductive line R12 of the first outer ring section R1;and the second conductive line R12 of the first outer ring section R1 is arranged on the second side, opposite the first side, of the first body section G10 in the second direction D2, and the second conductive line R12 of the first outer ring section R1 is connected to the first body section G10 to correspond to the first pixel row and the second pixel row, which are arranged along the second direction D2, in order to make adequate use of the space.

[0108] For example, as in Fig. 6A and Fig. As shown in 5D, the first sampling signal sub-line G1 further comprises a second outer ring section R2, and the aforementioned at least one outer ring section comprises the second outer ring section R2. The first conductive line R21 of the second outer ring section R2 and the second conductive line R22 of the second outer ring section R1 are both connected to the first body section G10. The longitudinal signal line comprises a second power supply line vss, and the second power supply line vss is connected to a second voltage terminal, configured to supply a second power supply voltage, different from the first power supply voltage, to the subpixel.and extends along the second direction D2; and the first conductive line R21 of the second outer ring section R2 and the second conductive line R22 of the second outer ring section R2 overlap with the second power supply line vss in the direction perpendicular to the base substrate 1. In this way, the second outer ring section R2 can further reduce the load (or resistance) of the first sampling signal sub-line G1, while avoiding excessive overlap with the second power supply line vss, and there are only two overlapping sections between the second outer ring section R2 and the second power supply line vss. If a problem such as a short circuit occurs at the overlapping section between the longitudinal section vdd1 and a line selected from the group consisting of the first conductive line R21 of the second outer ring section R2 and the second conductive line R22 of the second outer ring section R2,The one conductor selected from the group consisting of the first conductive line R21 of the second outer ring section R2 and the second conductive line R22 of the second outer ring section R2, which is short-circuited, can be cut off, for example, the one conductor selected from the group consisting of the first conductive line R21 of the second outer ring section R2 and the second conductive line R22 of the second outer ring section R2, which is short-circuited, can be cut off at the position of the first side or the second side that are opposite each other in the first direction D1, the second power supply line vss can be cut off, so that the cut conductive line stops working, in order to avoid affecting the display effect of the display unit P where the cut conductive line is located, and to achieve pixel repair of the display unit P; and the one,which is selected from the group consisting of the first conductive line R21 of the second outer ring section R2 and the second conductive line R22 of the second outer ring section R2, which is not cut off, continues to provide the first sampling signal for the multitude of subpixels P1-P4 of the display unit P, in order to allow the multitude of subpixels P1-P4 of the display unit P to operate normally and to reduce the effects of the aforementioned short-circuit problem on the display effect.

[0109] The first power supply voltage is, for example, a high power supply voltage VDD, and the second power supply voltage is, for example, a low power supply voltage VSS.

[0110] For example, in Fig. 6A and Fig. As shown in Figure 5D, the second outer ring section R2 and the first outer ring section R1 are spaced apart from each other in the first direction D1. Since the signal lines between the second outer ring section R2 and the first outer ring section R1 are relatively close together in the embodiments of the present disclosure, this technical scheme can avoid the problem of the formation of many short circuits and the reduction in manufacturing yield that arises from the overlap of the second outer ring section R2 and the first outer ring section R1 with too many signal lines extending along the second direction D2.Of course, the lengths of the second outer ring section R2 and the first outer ring section R1 in the first direction D1 can be designed according to the various layout structures in such a way as to determine which signal lines extending along the second direction D2 overlap with the second outer ring section R2 and the first outer ring section R1 in the direction perpendicular to the base substrate 1, and the embodiments of the present disclosure are not limited in this aspect.

[0111] For example, in Fig. 6A and Fig. As shown in 5D, the first conductive line R11 of the first outer ring section R1 and the second conductive line R12 of the first outer ring section R1 extend from the first non-light-emitting area 12A to the display area 11, and the first conductive line R21 of the second outer ring section R2 and the second conductive line R22 of the second outer ring section R2 extend from the second non-light-emitting area 12B to the display area 11. The first scanning signal sub-line G1 further comprises an intermediate connection section G103.The first outer ring section R1 and the second outer ring section R2 are both closed rings, and the first section G101 of the first body section G10, the first outer ring section R1, the intermediate connecting section G103, the second outer ring section R2, and the second section G102 of the first body section G10 are connected sequentially to achieve that the first section G101 of the first body section G10, the first outer ring section R1, the intermediate connecting section G103, the second outer ring section R2, and the second section G102 of the first body section G10 transmit the first sampling signal along the first direction D1.

[0112] For example, as in Fig. 6A and Fig. In 5D representation, the first outer ring section R1 and the second outer ring section R2 are symmetrical with respect to an axis of symmetry extending along the second direction D2, so that the display unit P and the pixel arrangement are more uniform and the display effect of the entire display area is relatively uniform.

[0113] For example, the first section of the first body section G10, the first outer ring section R1, the intermediate connecting section G103, the second outer ring section R2 and the second section of the first body section G10 form a continuous structure and are formed in one piece (i.e. a one-piece structure) to simplify the structure and manufacturing process of the display substrate 10.

[0114] For example, in Fig. 6A and Fig. As shown in Figure 5D, the first conductive line R11 of the first outer ring section R1 has a first end and a second end that are opposite each other in the first direction D1, and the second conductive line R12 of the first outer ring section R1 has a first end and a second end that are opposite each other in the first direction D1; the first outer ring section R2 further comprises a third connecting line R13 and a fourth connecting line R14; the third connecting line R13 is arranged in the first non-light-emitting area 12A, extends along the second direction D2 and connects the first end of the first conductive line R11 and the first end of the second conductive line R12;and the fourth connecting line R14 is arranged in the display area 11, extends along the second direction D2 and connects the second end of the first conductive line R11 and the second end of the second conductive line R12, so that the first outer ring section R1 forms a closed ring. The same applies to the second outer ring section R2.

[0115] For example, the longitudinal section vdd1 of the first power supply line vdd is located at the first edge of the display area 11 in the first direction D1, and the second power supply line vss is located at the second edge, opposite the first edge, of the display area 11 in the first direction D1. Thus, the first conductive line R11 and the second conductive line R12 of the first outer ring section R1 extend from the first non-light-emitting area 12A to the display area 11, so that they overlap with the longitudinal section vdd1 of the first power supply line vdd, and the first conductive line R21 and the second conductive line R22 of the second outer ring section R2 extend from the second non-light-emitting area 12B to the display area 11, so that they overlap with the second power supply line vss.

[0116] For example, as in Fig. 6A and Fig. As shown in Figure 5D, the sampling signal line, as mentioned above, further comprises the second sampling signal sub-line G2, and the second sampling signal sub-line G2 extends along the first direction D1 as a whole, is spaced apart from the first sampling signal sub-line in the second direction D2, and carries the second sampling signal, which is different from the first sampling signal; the second sampling signal sub-line G2 comprises a third outer ring section R3, and the aforementioned at least one outer ring section comprises the third outer ring section R3; wherein the second sampling signal sub-line G2 comprises a second body section G20, which extends along the first direction D1 as a whole,and the first conductive line R31 of the third outer ring section R3 and the second conductive line R32 of the third outer ring section R3 are both connected to the second body section G20; and the first conductive line R31 of the third outer ring section R3 and the second conductive line R32 of the third outer ring section R3 both overlap with the longitudinal section vdd1 of the first power supply line vdd and the second power supply line vss in the direction perpendicular to the base substrate 1. Thus, the third outer ring section R3 can effectively reduce the load (or resistance) of the second sampling signal sub-line G2, while avoiding excessive overlap between the third outer ring section R3 and the longitudinal section vdd1 or the second power supply line vss.and there are only two overlapping sections between the third outer ring section R3 and the longitudinal section vdd1 or the second power supply line vss. If a problem such as a short circuit occurs on the overlapping section between the longitudinal section vdd1 or the second power supply line vss and a line selected from the group consisting of the first conductor R31 of the third outer ring section R3 and the second conductor R32 of the third outer ring section R3, the short-circuited line selected from the group consisting of the first conductor R31 of the third outer ring section R3 and the second conductor R32 of the third outer ring section R3 can be cut off, for example, the line selected from the group consisting of the first conductor R31 of the third outer ring section R3 and the second conductor R32 of the third outer ring section R3,which is short-circuited, at the position of the first side or the second side that are opposite each other in the first direction D1, of the longitudinal section vdd1 or the second power supply line vss, so that the cut conductive line ceases to operate in order to avoid affecting the display effect of the display unit P where the cut conductive line is located, and to achieve pixel repair of the display unit P; and the one selected from the group consisting of the first conductive line R31 of the third outer ring section R3 and the second conductive line R32 of the third outer ring section R3, which is not cut, continues to provide the first sampling signal for the plurality of subpixels P1-P4 of the display unit P,to allow the multitude of subpixels P1-P4 of the display unit P to function normally and to reduce the effects of the aforementioned short-circuit problem on the display effect.

[0117] For example, if a short circuit occurs at position PA where the third data signal line D3 connects to the first conductive line R31 of the third outer ring section R3 in Fig. If a short circuit occurs (6A), the first conductive line R31 of the third outer ring section R3 can be cut at position PA1 on the first side of the third data signal line D3 in the first direction D1, or the first conductive line R31 of the third outer ring section R3 can be cut at position PA2 on the second side of the third data signal line D3 in the first direction D1, so that the first conductive line R31 of the third outer ring section R3 no longer carries current, thus eliminating the short circuit occurring at position PA, and the uncut second conductive line R32 of the third outer ring section R3 provides the second sampling signal for subpixels of the display unit P. The repair procedure for each longitudinal signal line is similar and is not described individually.

[0118] For example, as in Fig. 6A and Fig. As shown in 5D, the first conductive line R31 of the third outer ring section R3 and the second conductive line R32 of the third outer ring section R3 each extend from the first non-light-emitting area 12A to the display area 11 and then extend to the second non-light-emitting area 12B.This means that the first conductive line R31 of the third outer ring section R3 and the second conductive line R32 of the third outer ring section R3 run successively through the first non-light-emitting area 12A, the display area 11 and the second non-light-emitting area 12B and penetrate the entire display area 11 in the first direction D1, so that the first conductive line R31 of the third outer ring section R3 and the second conductive line R32 of the third outer ring section R3 can overlap with all longitudinal signal lines in the display area 1, which extend along the second direction D2 as a whole, in the direction perpendicular to the base substrate 1, and for all longitudinal signal lines the pixel repair mentioned above can be solved in the event of a short circuit.

[0119] For example, the second body section G20 comprises a first section located in the first non-light-emitting region 12A and a second section located in the second non-light-emitting region 12B; and the second sampling signal sub-line G2 comprises a third branch section and a fourth branch section. The third branch section is connected to the first section of the second body section G20 and the second section of the second body section G20 and comprises the first conductive line R31 of the third outer ring section R3; the first conductive line R31 of the third outer ring section R3 is located on the first side of the second body section G20 in the second direction D2, and the first conductive line R31 of the third outer ring section R3 is electrically connected to the second body section G20;the fourth branching section is connected to the first section of the second body section G20 and the second section of the second body section G20 and includes the second conductive line R32 of the third outer ring section R3; and the second conductive line R32 of the third outer ring section R3 is arranged on the second side, opposite the first side, of the second body section G20 in the second direction D2, and the second conductive line R32 of the third outer ring section R3 is electrically connected to the second body section G20 to correspond to the first pixel row and the second pixel row, which are arranged along the second direction D2 in order to make adequate use of space, so that the second sampling signal sub-line G2 can be used to supply the second sampling signal to the first pixel row and the second pixel row.;

[0120] For example, as in Fig. As shown in Figure 6A, the first conductive line R31 of the third outer ring section R3 and the second conductive line R32 of the third outer ring section R3 both overlap with the data signal line in the direction perpendicular to the base substrate 1, overlap with the longitudinal section vdd1 of the first power supply line vdd in the direction perpendicular to the base substrate 1 and overlap with the second power supply line vss in the direction perpendicular to the base substrate 1.The data signal lines include, for example, a first data line D1, which delivers a data signal DT to the first subpixel P1, a second data line D2, which delivers a data signal DT to the second subpixel P2, a third data line D3, which delivers a data signal DT to the third subpixel P3, and a fourth data line D4, which delivers a data signal DT to the fourth subpixel P4; and the first data line D1, the second data line D2, the third data line D3, and the fourth data line D4 are spaced apart in the first direction D1. For example, the first conductive line R31 of the third outer ring section R3 and the second conductive line R32 of the third outer ring section R3 are both connected to the data signal lines D1-D4 of the plurality of subpixels P1-P4 of the display unit P.In this way, for each pixel selected from a group consisting of the data signal lines D1-D4, the longitudinal section vdd1 of the first power supply line vdd and the second power supply line vss, the repair can be carried out if a short circuit mentioned above occurs at the overlapping position of the third outer ring section R3 and the respective signal line.

[0121] For example, the longitudinal signal line further includes a capture signal line S, and the capture signal line S carries a capture signal. The subpixel further includes a capture transistor T3, the second capture signal subline G2 is configured to supply a second capture signal to the capture transistor T3, and the capture transistor T3 is configured to use the capture signal to capture the electrical characteristics of the subpixel under the control of the second capture signal to achieve external compensation. As in Fig. As shown in Figure 6A, for example, the first conductive line R31 of the third outer ring section R3 and the second conductive line R32 of the third outer ring section R3 both overlap with the detection signal line S in the direction perpendicular to the base substrate 1. Consequently, the pixel repair mentioned above can also be implemented for the detection signal line S if a short circuit occurs at the overlapping position of the detection signal line S and the third outer ring section R3.

[0122] For example, the first sampling signal sub-line G1 is configured to supply the first sampling signal to a data transistor T2 of the third subpixel P3 and a data transistor T2 of the fourth subpixel P4; the first conductive line R31 of the third outer ring section R3 supplies the second sampling signal to a sensing transistor T3 of the first subpixel P1 and a sensing transistor T3 of the second subpixel P2; and the second conductive line R32 of the third outer ring section R3 supplies the second sampling signal to a sensing transistor T3 of the third subpixel P3 and a sensing transistor T3 of the fourth subpixel P4. Both the first conductive line R31 and the second conductive line of the third outer ring section R3 overlap with the first data line D1, the second data line D2, the third data line D3, and the fourth data line D4 in the direction perpendicular to the base substrate 1.

[0123] For example, as in Fig. As shown in Figure 6A, for example, the sections of the first conductive line R31 of the third outer ring section R3, which overlap with the channel areas of the detection transistors T3 of the third subpixel P3 and the fourth subpixel P4, form the gate electrode T3g-3 of the detection transistor T3 of the third subpixel P3 and the gate electrode T3g-4 of the detection transistor T3 of the fourth subpixel P4, and the sections of the second conductive line R32 of the third outer ring section R3, which overlap with the channel areas of the detection transistor T3 of the first subpixel P1 and the second subpixel P2, form the gate electrode T3g-1 of the detection transistor T3 of the first subpixel P1 and the gate electrode T3g-2 of the detection transistor T3 of the second subpixel P2.

[0124] Referring to Fig. In 5D, the first sampling signal sub-line G1 and the second sampling signal sub-line G2 are located in the same layer, for example, in the second conductive layer 200. Therefore, the outer ring sections, such as the first outer ring section R1, the second outer ring section R2, and the third outer ring section R3, are all located in the same conductive layer, for example, all in the second conductive layer 200.

[0125] With reference to Fig. 6A and Fig. 5D, the area of ​​the ring shape of the third outer ring section R3 is larger than the area of ​​the ring shape of the first outer ring section R1 and larger than the area of ​​the ring shape of the second outer ring section R2. For example, the length of the third outer ring section R3 in the first direction D1 is greater than the length of the second outer ring section R2 in the first direction D1 and greater than the length of the first outer ring section R1 in the first direction D1, and the width of the third outer ring section R3 in the second direction D2 is greater than the width of the second outer ring section R2 in the second direction D2 and greater than the width of the first outer ring section R1 in the second direction D2.Along the first direction D1, the third outer ring section R3 extends into the display area 11 from the non-light-emitting area 12A of a display unit located on the first side of the display area 11, and penetrates the display area 11 along the first direction D1 and then extends into the second non-light-emitting area 12B located on the second side of the display area 11, while the first outer ring section R1 and the second outer ring section R2 do not traverse the entire display area 11 along the first direction.

[0126] For example, as in Fig. As shown in Figure 6A, the section of the intermediate connection section G103 of the first sampling signal part line G1, which overlaps with the channel area of ​​the data transistor T2 of the third subpixel P3, forms the gate electrode T2g-3 of the data transistor T2 of the third subpixel P3, and the section of the intermediate connection section G103 of the first sampling signal part line G1, which overlaps with the channel area of ​​the data transistor T2 of the fourth subpixel P4, forms the gate electrode T2g-4 of the data transistor T2 of the fourth subpixel P4.

[0127] For example, as in Fig. 6A and Fig. As shown in Figure 5F, the display unit P further comprises an auxiliary sampling line G3, a first connecting line CL1 and a second connecting line CL2, and the auxiliary sampling line G3 extends along the first direction D1; the first connecting line CL1 is connected to the auxiliary sampling line G3 and the first sampling signal sub-line G1; the second connecting line CL2 is spaced from the first connecting line CL1 in the second direction D2 and is connected to the auxiliary sampling line G3 and the first sampling signal sub-line G1; the auxiliary sampling line G3 is configured to supply the first sampling signal to the data transistor T2 of the first subpixel P1 and the data transistor T2 of the second subpixel P2;and the first conductive line R31 of the third outer ring section R3 and the second conductive line R32 of the third outer ring section R3 both overlap with the first connecting line CL1 and the second connecting line CL2 in the direction perpendicular to the base substrate 1. In this way, the pixel repair mentioned above can be implemented for both the first connecting line CL1 and the second connecting line CL2 in the event of a short circuit at the overlapping position of both the first connecting line CL1 and the second connecting line CL2 and the third outer ring section R3.

[0128] For example, as in Fig. As shown in 5D, the first sampling signal line G1 and the auxiliary sampling line G3 are located in the same layer as the first pole of the driver transistor and are both situated in the second conductive layer 200. The first connecting line CL1 and the second connecting line CL2 are located in the third conductive layer 300 and are situated in a different layer than the first sampling signal line G1.

[0129] For example, as in Fig. As shown in Figure 5F, the auxiliary scanning line G3 has a first end and a second end that are opposite each other in the first direction D1; and the first connecting line CL1 is connected to the first end of the auxiliary scanning line G3 and the first outer ring section R1, and the second connecting line CL2 is connected to the second end of the auxiliary scanning line G3 and the second outer ring section R2.

[0130] For example, regarding Fig. 5E- Fig. 5F and Fig. 6A, for example, the first end of the auxiliary scanning line G3 is connected to the first end of the first connecting line CL1 through a through-hole V71 that passes through the third insulating layer 103, and the second end of the first connecting line CL1 is connected to the first scanning signal sub-line G1 through a through-hole V61 that passes through the third insulating layer 103; the second end of the auxiliary scanning line G3 is connected to the first end of the second connecting line CL2 through a through-hole V72 that passes through the third insulating layer 103, and the second end of the second connecting line CL2 is connected to the first scanning signal sub-line G1 through a through-hole V62 that passes through the third insulating layer 103.For example, the second end of the first connecting line CL1 is connected to the second outer ring section R2 through the through hole V61, and the second end of the second connecting line CL2 is connected to the second outer ring section R2 through the through hole V62.

[0131] For example, the number of outer ring sections contained in the second sampling signal sub-line G2 is less than the number of outer ring sections contained in the first sampling signal sub-line G1. For example, the number of outer ring sections contained in the second sampling signal sub-line G2 is 1, i.e., the number of third outer ring sections R3 is 1; the number of outer ring sections contained in the first sampling signal sub-line G1 is 2, i.e., one first outer ring section R1 and one second outer ring section R2. The first sampling signal sub-line G1 contains more outer ring sections, which is practical for providing the outer ring sections at multiple locations and flexibly meets the requirements of multiple locations where the outer ring sections need to be provided, e.g.,Two outer ring sections, each provided at two positions in a display unit, are connected to the first and second ends of the auxiliary scanning line G3. Furthermore, the second scanning signal section G2 comprises fewer outer ring sections, thus meeting the requirements for the second scanning signal section G2 to overlap with various longitudinal signal lines. This avoids the need for a large number of outer ring sections, simplifying the structure of the display substrate and reducing manufacturing difficulties. This is crucial for improving the manufacturing yield of the display substrate, especially for a display substrate with a complex structure and high resolution.

[0132] For example, Fig. 6B a schematic enlarged view of part B, which contains at least one inner ring section in Fig. 3A includes. With reference to Fig. 5D and Fig. In 6B, the transverse section vdd2 of the first power supply line vdd comprises an inner ring section R4, and the inner ring section R4 comprises a third conductive line R41 and a fourth conductive line R42. The third conductive line R41 extends along the first direction D1 as a whole and is located in the display area 11; the fourth conductive line R42 extends along the first direction D1 as a whole, is located in the display area 11, and is spaced from the third conductive line R41 in the second direction D2. The third conductive line R41 and the fourth conductive line R42 both overlap with at least a portion of the longitudinal signal line in the direction perpendicular to the base substrate 1 and supply the same first power supply voltage to the plurality of subpixels of the display unit P.

[0133] For example, the transverse section vdd2 of the first power supply line vdd is provided in the same layer as the first sampling signal sub-line G1 and the second sampling signal sub-line G2, is provided in a different layer than the longitudinal section vdd1 of the first power supply line vdd and is electrically connected to the longitudinal section vdd1 through a through-hole (in particular as above).

[0134] For example, as in Fig. As shown in Figure 6B, the third conductive line R41 and the fourth conductive line R42 both overlap with at least a portion of the data signal lines of the display unit P in the direction perpendicular to the base substrate 1. For example, the third conductive line R41 and the fourth conductive line R42 both overlap with the third data signal line D3 and the fourth data signal line D4 in the direction perpendicular to the base substrate 1. Therefore, if a short circuit occurs at the positions of the third data signal line D3 or the fourth data signal line D4 that overlap with the third conductive line R41 or the fourth conductive line R42, pixel repair can be achieved. For example, if a short circuit occurs at position PO of the fourth data signal line D4 in Fig. If a fault occurs in line 6B, which overlaps with the third conductive line R41, the third conductive line R41 can be cut at position p1 on the first side of the fourth data signal line D4 in the first direction D1, or the third conductive line R41 can be cut at position p2 on the second side of the fourth data signal line D4 in the first direction D1, so that the third conductive line R41 no longer carries current, thereby eliminating the short circuit at position PO, and the fourth conductive line R42, which is not cut, provides the second power supply voltage for subpixels of the display unit P. The repair procedure for each longitudinal signal line is similar to the one described above and is not described individually.

[0135] Of course, in other embodiments, the third conductive line R41 and the fourth conductive line R42 can overlap with each data signal line of the data signal lines D1-D4 of the display unit P in the direction perpendicular to the base substrate 1. Therefore, if a short circuit occurs at the positions of the data signal lines D1-D4 that overlap with the third conductive line R41 and the fourth conductive line R42, pixel repair can be achieved.

[0136] For example, as in Fig. As shown in Figure 6B, both the third conductive line R41 and the fourth conductive line R42 overlap with the detection signal line S in the direction perpendicular to the base substrate 1. Thus, the pixel repair mentioned above can also be implemented for both the third data signal line D3 and the fourth data signal line D4 if a short circuit occurs at the overlapping positions between the third data signal line D3 or the fourth data signal line D4 and the detection signal line S.

[0137] For example, the detection signal line S is located between the third data line D3 and the fourth data line D4 and borders both the third data line D3 and the fourth data line D4. Both the third conductive line R41 and the fourth conductive line R42 overlap with the third data line D3, the fourth data line D4, and the detection signal line S in a direction perpendicular to the base substrate 1. In this way, by using a ring structure, which is the inner ring section R4, to overlap with a multitude of longitudinal signal lines at a position where the longitudinal signal lines are densely arranged, the pixel repair mentioned above, when a short circuit occurs, can also be implemented for the third data signal line D3, the fourth data signal line D4, and the detection signal line S.

[0138] Fig. 5K is a schematic planar view of a pixel definition layer of the in Fig. 3A shown display unit. For example, the pixel definition layer 6 exposes at least part of the outer ring section. With reference to Fig. 3A, Fig. 5K and Fig. 6A exposes, for example, part of the first outer ring section R1 and part of the second outer ring section R2 to the pixel definition layer 6.

[0139] For example, regarding Fig. 3A, Fig. 3C, Fig. 5K and Fig. 6A comprises the pixel definition layer 6, a section of which is located in the non-light-emitting area 12A; the section of the pixel definition layer 6 located in the non-light-emitting area 12A includes a groove 63 recessed away from the display area; and the orthographic projection of the connection section 30 on the base substrate 1 lies at least partially within the orthographic projection of the groove 63 on the base substrate 1; the groove 63 has an edge 631 facing the connection section 30, and a space lies between an edge of the connection section 30 that is away from the display area 11 in the first direction D1 and the edge 631 of the groove 63. That is, the edge 631 of the groove 63 is located on a side of the edge 301 of the connection section 30 that is away from the display area 11.

[0140] At least one embodiment of the present disclosure further provides a method for operating a display substrate that is applicable to each of the display substrates 10 provided by the embodiments of the present disclosure. The method for operating the display substrate 1 comprises: cutting off a section located in the display area 11 from a group consisting of the first conducting line and the second conducting line of the same outer ring section. For example, the same outer ring section can be any one selected from a group consisting of the aforementioned first outer ring section R1, the second outer ring section R2, and the third outer ring section R3.

[0141] For example, in the direction perpendicular to the base substrate 1, no conductive layer overlaps with a conductor selected from the group consisting of the first and second conductive conductors of the same outer ring section on the side of a truncated section closest to the base substrate 1. This overlap occurs when, for example, as mentioned above, a short circuit occurs at position PA, where the third data signal line D3 overlaps with the first conductive line R31 of the third outer ring section R3 in Fig. 6A overlaps, the first conductive line R31 of the third outer ring section R3 can be at position PA1 or position PA2 in Fig. 6A is cut off. In this way, if the aforementioned poor display, such as a short circuit in which a subpixel occurs, other conductive layers are not damaged during the cutting process of removing a conductor selected from the group consisting of the first and second conductive conductors of the same outer ring section, thus facilitating the cutting process, achieving subpixel repair, and improving display quality. For other outer ring sections or inner ring sections, the processing procedure for performing subpixel repair is similar and is not described individually.

[0142] For example, one of the first and second conducting lines of the same outer ring section is cut off by a laser irradiation process to form a notch (not shown in the figures).

[0143] At least one embodiment of the present disclosure further provides a display substrate, and the display substrate comprises a base substrate and a display unit. The display unit is provided on the base substrate and comprises a display area and a non-light-emitting area; the display area comprises a subpixel, and the subpixel comprises a driver transistor and a light-emitting device; the driver transistor is configured to control the magnitude of a driver current flowing through the light-emitting device and comprises a gate electrode, a first pole, and a second pole; the light-emitting device is configured to receive the driver current and is driven by the driver current to emit light, and comprises a first electrode;wherein the first electrode comprises a first section and a second section spaced apart from each other, and the first section and the second section are connected to the first pole of the driver transistor and each comprise a first electrode sublayer and a second electrode sublayer stacked on top of each other in a direction perpendicular to the base substrate along a direction from near the base substrate to away from the base substrate; the first electrode sublayer of the first section has a first edge close to the second section, the second electrode sublayer of the first section has a second edge close to the second section and the first edge is located on a side of the second edge away from the second section;the first electrode sublayer of the second section has a third edge located close to the first section, the second electrode sublayer of the second section has a fourth edge located close to the first section, and the third edge is located on a side of the fourth edge furthest from the first section.

[0144] For example, Fig. 7 another schematic cross-sectional view along line AA' in Fig. 3B, Fig. 8A is a schematic enlarged view of part C in Fig. 7, and Fig. 9 is a schematic planar view of the in Fig. Part C shown in 8A. As in Fig. 7- Fig. As shown in Figure 9, the first electrode 2 in the display substrate 10 comprises a first section 21 and a second section 22, which are spaced apart from each other, with the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 being connected to the first pole T1s of the driver transistor T1 (see the description of Figure 9). Fig. 4A for the specific connection mode), and the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 each comprise a first electrode sublayer 2a and a second electrode sublayer 2b, which are stacked successively in the direction perpendicular to the base substrate 1 and along the direction from a position near the base substrate 1 to a position remote from the base substrate 1. The first electrode sublayer 2a of the first section 21 of the first electrode 2 has a first edge 2a-1 near the second section 22 of the first electrode 2, and the second electrode sublayer 2b of the first section 21 of the first electrode 2 has a second edge 2b-1 near the second section 22 of the first electrode 2.and the first edge 2a-1 is located on a side of the second edge 2b-1 away from the second section 22 of the first electrode 2; the first electrode sublayer 2a of the second section 22 of the first electrode 2 has a third edge 2a-2 near the first section 21 of the first electrode 2, the second electrode sublayer 2b of the second section 22 of the first electrode 2 has a fourth edge 2b-2 near the first section 21 of the first electrode 2, and the third edge 2a-2 is located on a side of the fourth edge 2b-2 away from the first section 21 of the first electrode 2. That is, in the display substrate, the edges of the first electrode sublayer 2a of the first section 21 of the first electrode 2 (like an anode) and the first electrode sublayer 2a of the second section 22 of the first electrode 2 are located close to each other.Each is notched relative to the edges of the second electrode sublayer of the first section 21 and the second electrode sublayer of the second section 22, which are located close to each other. In this way, after the first electrode sublayer 2a of the first section 21 and the first electrode sublayer 2a of the second section 22 have been formed, when the second electrode sublayer 2b of the first section 21 and the second electrode sublayer 2b of the second section 22 are formed by a structuring process, it can be prevented that the second electrode sublayer 2b of the first section 21 is in contact with the second electrode sublayer 2b of the second section 22 due to an excessive distance.and the second electrode sublayer 2b of the second section 22 can be prevented from coming into contact with the first electrode sublayer 2a of the first section 21, thus reducing the structuring difficulty and improving the fabrication yield of the display substrate. If the design of the edges of the first section 21 and the second section 22 of the display substrate, which is in , Fig. If the design shown in Figure 8A and provided by the embodiment of the present disclosure is not adopted, the distance between the second electrode sublayer 2b of the first section 21 and the second electrode sublayer 2b of the second section 22 must be increased, which reduces the size of the opening area 60 of the pixel definition layer 6. Therefore, the design of the edges of the first section 21 and the second section 22 of the display substrate, which is shown in Figure 8A, can be increased. Fig. 8A is shown and is provided by the embodiment of the present disclosure, further increasing the aperture ratio of the subpixel.

[0145] In some embodiments, for example, the orthographic projection of the first electrode sublayer 2a of the first section 21 of the first electrode 2 on the base substrate 1 is located within the orthographic projection of the second electrode sublayer 2b of the first section 21 of the first electrode 2 on the base substrate 1, and the area of ​​the orthographic projection of the first electrode sublayer 2a of the first section 21 of the first electrode 2 on the base substrate 1 is smaller than the area of ​​the orthographic projection of the second electrode sublayer 2b of the first section 21 of the first electrode 2 on the base substrate 1;and the orthographic projection of the first electrode sublayer 2a of the second section 22 of the first electrode 2 on the base substrate 1 is arranged within the orthographic projection of the second electrode sublayer 2b of the second section 22 of the first electrode 2 on the base substrate 1, and the area of ​​the orthographic projection of the first electrode sublayer 2a of the second section 22 of the first electrode 2 on the base substrate is smaller than the area of ​​the orthographic projection of the second electrode sublayer 2b of the second section 22 of the first electrode 2 on the base substrate 1, in order to further reduce the risk of contact between the electrode sublayers spaced apart from each other in the ideal state mentioned above.

[0146] For example, as in Fig. 7- Fig. As shown in Figure 9, the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 each further comprise a third electrode sublayer 2c, wherein the third electrode sublayer 2c of the first section 21 of the first electrode 2 is stacked on the second electrode sublayer 2b of the first section 21 of the first electrode 2 in the direction perpendicular to the base substrate 1 and is located on a side of the second electrode sublayer 2b of the first section 21 of the first electrode 2 that is away from the base substrate 1.and the third electrode sublayer 2c of the second section 22 of the first electrode 2 is stacked on the second electrode sublayer 2b of the second section 22 of the first electrode 2 in a direction perpendicular to the base substrate 1 and is arranged on a side of the second electrode sublayer 2b of the second section 22 of the first electrode 2 furthest from the base substrate 1; the third electrode sublayer 2c of the first section 21 of the first electrode 2 has a fifth edge 2c-1 near the second section 22 of the first electrode 2 and the first edge 2a-1 is arranged on a side of the fifth edge 2c-1 furthest from the second section 22 of the first electrode 2; and the third electrode sublayer 2c of the second section 22 of the first electrode 2 has a sixth edge 2c-2 near the first section 21 of the first electrode 2,and the third edge 2a-2 is located on a side of the sixth edge 2c-2 furthest from the first section 21 of the first electrode 2. That is, the edge of the first electrode sublayer 2a of the first section 21 near the second section 22 is further notched relative to the edge of the third electrode sublayer 2c of the first section 21 near the second section 22, and the edge of the first electrode sublayer 2a of the second section 22 near the first section 21 is further notched relative to the edge of the third electrode sublayer 2c of the second section 22 near the first section 21, so that contact between the third electrode sublayer 2c of the first section 21 and the first electrode sublayer 2a of the second section 22 is prevented.and that the third electrode sublayer 2c of the second section 22 is in contact with the first electrode sublayer 2a of the first section 21. Furthermore, if the display substrate is constructed as in , Fig. If the embodiment shown in Figure 8A of the present disclosure, in which the first edge 2a-1 is further from the second section 22 than the fifth edge 2c-1 and the third edge 2a-2 is further from the first section 21 than the sixth edge 2c-2, is not adopted, the distance between the third electrode sublayer 2c of the first section 21 and the third electrode sublayer 2c of the second section 22 must be increased, thereby reducing the size of the opening area 60 of the pixel definition layer 6. Therefore, the design of the edges of the first section 21 and the second section 22 of the display substrate, which is shown in Figure 8A, increases the distance between the third electrode sublayer 2c of the first section 21 and the third electrode sublayer 2c of the second section 22, which is shown in Figure 8A, increases the size of the opening area 60 of the pixel definition layer 6. Fig. 8A is shown and is provided by the embodiment of the present disclosure, further the aperture ratio of the subpixel.

[0147] For example, the orthographic projection of the first electrode sublayer 2a of the first section 21 of the first electrode 2 on the base substrate 1 is located within the orthographic projection of the third electrode sublayer 2c of the first section 21 of the first electrode 2 on the base substrate 1, and the area of ​​the orthographic projection of the first electrode sublayer 2a of the first section 21 of the first electrode 2 on the base substrate 1 is smaller than the area of ​​the orthographic projection of the third electrode sublayer 2c of the first section 21 of the first electrode 2 on the base substrate 1;and the orthographic projection of the first electrode sublayer 2a of the second section 22 of the first electrode 2 on the base substrate 1 is located within the orthographic projection of the third electrode sublayer 2c of the second section 22 of the first electrode 2 on the base substrate 1, and the area of ​​the orthographic projection of the first electrode sublayer 2a of the second section 22 of the first electrode 2 on the base substrate is smaller than the area of ​​the orthographic projection of the third electrode sublayer 2c of the second section 22 of the first electrode 2 on the base substrate 1, in order to further reduce the risk of contact between the electrode sublayers spaced apart from each other in the ideal state mentioned above.

[0148] For example, in Fig. As shown in 8A, the second edge 2b-1 is notched relative to the fifth edge 2c-1, i.e., the second edge 2b-1 is located on a side of the fifth edge 2c-1 furthest from the second section 22; and the fourth edge 2b-2 is indented relative to the sixth edge 2c-2, i.e.,The fourth edge 2b-2 is located on a side of the sixth edge 2c-2 furthest from the first section 21, in order to further reduce the risk of the second electrode sublayer 2b of the first section 21 coming into contact with the second electrode sublayer 2b of the second section 22, the risk of the second electrode sublayer 2b of the first section 21 coming into contact with the first electrode sublayer 2a of the second section 22, the risk of the second electrode sublayer 2b of the second section 22 coming into contact with the first electrode sublayer 2a of the first section 21, and the risk of the third electrode sublayer 2c of the second section 22 coming into contact with the first electrode sublayer 2a of the first section 21. Other features and technical effects of . Fig. 8B are the same as those in Fig. 8A embodiment shown.

[0149] For example, in the Fig. In the embodiment shown in Figure 8B, for example, the second electrode sublayer 2b of the first section 21, the third electrode sublayer 2c of the first section 21, the second electrode sublayer 2b of the second section 22, and the third electrode sublayer 2c of the second section are formed by the same structuring process using the same mask, which is formed, for example, by an etching process such as a wet etching process, in order to simplify the manufacturing process of the display substrate 10; and the material of the second electrode sublayer 2b differs from the material of the third electrode sublayer 2c, such that the second electrode sublayer 2b and the third electrode sublayer 2c have different etch rates, thereby facilitating the manufacturing process of the display substrate 10. Fig. The structure shown in section 8B will be obtained. 8B.

[0150] The structuring process in the present disclosure includes, for example, a photolithography process, and of course other structuring processes can also be used.

[0151] For example, the material of the first electrode sublayer 2a of the first section 21 and the material of the first electrode sublayer 2a of the second section 22 are each a transparent conductive material; the material of the second electrode sublayer 2b of the first section 21 and the material of the second electrode sublayer 2b of the second section 22 are each a metallic material; and the material of the third electrode sublayer 2c of the first section 21 and the material of the third electrode sublayer 2c of the second section 22 are each a transparent conductive material. The material of the second electrode sublayer 2b can, for example, include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and an alloy material combined with the aforementioned metals.For example, the material of the first electrode sublayer 2a and the material of the third electrode sublayer 2c are each a conductive metal oxide material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc. Of course, the materials of the first electrode sublayer 2a, the second electrode sublayer 2b, and the third electrode sublayer 2c are not limited to the types listed above, and the embodiments of the present disclosure are not limited in this respect.

[0152] For example, in the Fig. In the embodiment shown in Figure 8A, the orthographic projection of the second electrode sublayer 2b of the first section 21 of the first electrode 2 on the base substrate 1 is arranged with the orthographic projection of the third electrode sublayer 2c of the first section 21 of the first electrode 2 on the base substrate 1, and the orthographic projection of the second electrode sublayer 2b of the second section 22 of the first electrode 2 on the base substrate 1 is arranged within the orthographic projection of the third electrode sublayer 2c of the second section 22 of the first electrode 2 on the base substrate 1.That is, each edge of the second electrode sublayer 2b of the first section 21 is pressed into the corresponding edge of the third electrode sublayer 2c of the first section 21, and each edge of the second electrode sublayer 2b of the second section 22 is pressed into the corresponding edge of the third electrode sublayer 2c of the second section 22.

[0153] For example, in Fig. As shown in Figure 8A, the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 are arranged in the longitudinal direction, the first edge 2a-1 is spaced from the second edge 2b-1 by a first distance d1 in the longitudinal direction, the third edge 2a-2 is spaced from the fourth edge 2b-2 by a second distance d2 in the longitudinal direction, and the first distance d1 is substantially equal to the second distance d2.

[0154] For example, the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 are arranged in the longitudinal direction, the first edge 2a-1 is spaced from the second edge 2b-1 by the first distance d1 in the longitudinal direction, and the third edge 2a-2 is spaced from the fourth edge 2b-2 by the second distance d2 in the longitudinal direction. The range of the first distance d1 is 1 µm-1.5 µm, and the range of the second distance d2 is 1 µm-1.5 µm, to effectively prevent the second electrode sublayer 2b of the first section 21 from coming into contact with the second electrode sublayer 2b of the second section 22, to prevent the second electrode sublayer 2b of the first section 21 from coming into contact with the first electrode sublayer 2a of the second section 22, and to prevent the second electrode sublayer 2b of the second section 22 from coming into contact with the first electrode sublayer 2a of the first section 21.

[0155] For example, a third distance d3 between the first edge 2a-1 and the third edge 2a-2 is larger than a fourth distance d4 between the first edge 2b-1 and the fourth edge 2b-2. For example, the third distance d3 between the first edge 2a-1 and the third edge 2a-2 is not less than 6 µm, or the fourth distance d4 between the second edge 2b-1 and the fourth edge 2b-2 is not less than 4 µm, in order to effectively prevent the second electrode sublayer 2b of the first section 21 from coming into contact with the second electrode sublayer 2b of the second section 22, to prevent the second electrode sublayer 2b of the first section 21 from coming into contact with the first electrode sublayer 2a of the second section 22, and to prevent the second electrode sublayer 2b of the second section 22 from coming into contact with the first electrode sublayer 2a of the first section 21 due to an insufficient distance.

[0156] Alternatively, in some other embodiments, such as in Fig. As shown in Figure 8B, the fifth edge 2c-1 is essentially flush with the second edge 2b-1, and the sixth edge 2c-2 is essentially flush with the fourth edge 2b-2, so that while simultaneously reducing the risk of contact between the electrode sublayers, which are ideally spaced apart, and reducing the manufacturing difficulties, the manufacturing difficulties of the display substrate 10 are also reduced. For example, the second electrode sublayer 2b of the first section 21, the third electrode sublayer 2c of the first section 21, the second electrode sublayer 2b of the second section 22, and the third electrode sublayer 2c of the second section 22 are formed by the same structuring process using the same mask to simplify the manufacturing process of the display substrate 10. For example, in the fabrication of the display substrate 10, after the first conductive layer 100,The first insulating layer 101, the semiconductor layer 600, the second insulating layer 102, the second conductive layer 200, the third insulating layer 103, the third conductive layer 300, the fourth insulating layer 104, and the fifth insulating layer 105 are stacked on the base substrate 1, a first conductive material layer covering the fifth insulating layer 105 is formed, and a first mask is used to perform a first structuring process on the first conductive material layer to form the first electrode sublayer 2a of the first section 21 and the second electrode sublayer 2b of the first section 21; then a second conductive material layer is formed to cover the first electrode sublayer 2a of the first section 21 and the second electrode sublayer 2b of the first section 21, and a third conductive material layer is formed in this way.that it is arranged on a side of the second conductive material layer furthest from the base substrate 1, and the third conductive material layer and the second conductive material layer are stacked in the direction perpendicular to the base substrate 1; then a second mask is used to carry out a second structuring process on the second conductive material layer and the third conductive material layer to form the second electrode sublayer 2b of the first section 21, the third electrode sublayer 2c of the first section 21, the second electrode sublayer 2b of the second section 22, and the third electrode sublayer 2c of the second section 22; in this way, the fifth edge 2c-1 is substantially flush with the second edge 2b-1, and the sixth edge 2c-2 is substantially flush with the fourth edge 2b-2,which simplifies the manufacturing process of the display substrate 10 and reduces the manufacturing difficulties of the display substrate 10.

[0157] It should be noted that the aforementioned "essentially flush" is not limited to being absolutely flush. Since the materials forming the first conductive layer and the second conductive layer of the second electrode sublayer 2b and the third electrode sublayer 2c are different, there is, for example, a certain deviation distance between the fifth edge 2c-1 and the second edge 2b-1. If this deviation distance is within 5% of the size of the third electrode sublayer 2c of the first section 21 in this direction, or within 5% of the size of the second electrode sublayer 2b of the first section 21 in this direction, then the fifth edge 2c-1 can be understood to be essentially flush with the second edge 2b-1. The same applies to the sixth edge 2c-2, which is essentially flush with the fourth edge 2b-2.

[0158] For example, the orthographic projection of the second electrode sublayer 2b of the first section 21 of the first electrode 2 on the base substrate 1 substantially overlaps with the orthographic projection of the third electrode sublayer 2c of the first section 21 of the first electrode 2 on the base substrate 1, and the orthographic projection of the second electrode sublayer 2b of the second section 22 of the first electrode 2 on the base substrate 1 substantially overlaps with the orthographic projection of the third electrode sublayer 2c of the second section 22 of the first electrode 2 on the base substrate 1.Similar to the "essentially flush" mentioned above, "essentially overlapping" here also refers to the fact that if there is a deviation between two projections that essentially overlap in a certain direction, and if the deviation is within 5% of the size of the second electrode sublayer 2b of the first section 21 in that direction, then the orthographic projection of the second electrode sublayer 2b of the first section 21 of the first electrode 2 on the base substrate 1 essentially overlaps with the orthographic projection of the third electrode sublayer 2c of the first section 21 of the first electrode 2 on the base substrate 1.The same applies if the orthographic projection of the second electrode sublayer 2b of the second section 22 of the first electrode 2 on the base substrate 1 substantially overlaps with the orthographic projection of the third electrode sublayer 2b of the second section 22 of the first electrode 2 on the base substrate 1.

[0159] For example, in the display substrate provided by at least one embodiment of the present disclosure, orthographic projections of the channel regions of all transistors of the subpixel on the base substrate 1 are located within the orthographic projection of the first electrode 2 on the base substrate 1, and the channel regions of all transistors of the subpixel are located on the side of the first electrode 2 closest to the base substrate 1.For example, in each subpixel, the orthographic projections of the channel region of the driver transistor T1, the channel region of the data transistor T2, and the channel region of the sensing transistor T3 on the base substrate 1 are all located within the orthographic projection of the first electrode 2 on the base substrate 1, and the channel regions of the driver transistor T1, the data transistor T2, and the sensing transistor T3 are located on the side of the first electrode 2 closest to the base substrate 1. In this way, the channel regions of all transistors in the subpixel are shielded from light by the first electrode 2, and the peak light from the side of the transistor's channel region furthest from the base substrate 1 is also shielded by the first electrode 2.

[0160] The light-emitting device 20 further comprises a light-emitting layer 23, the light-emitting layer 23 is located on the side of the first electrode 2 furthest from the base substrate 1, the first electrode 2 is a reflective electrode, and the light emitted by the light-emitting layer 23 is emitted from the side of the first electrode 2 furthest from the base substrate 1.

[0161] For example, as in Fig. 3A- Fig. As shown in Figure 3B, in the display substrate 10 provided by at least one embodiment, in each subpixel (such as P1-P4) the orthographic projection of the channel area of ​​the driver transistor T1 on the base substrate 1 lies within the orthographic projection of the second section 22 of the first electrode 2 on the base substrate 1; the orthographic projection of the channel area of ​​the data write transistor T2 on the base substrate 1 and the orthographic projection of the channel area of ​​the sensing transistor T3 on the base substrate 1 both lie within the orthographic projection of the first section 21 of the first electrode 2 on the base substrate 1, so that in the case where the four subpixels P1-P4 of a display unit P are substantially symmetrical in the first direction D1 or the second direction D2 (most devices are symmetrical, and the whole is symmetrical, it is not necessary to(that each layer and each device is symmetrical), the first section and the second section of the first electrode of each subpixel are appropriately aligned with the position of the channel area of ​​each transistor of the corresponding subpixel, and appropriate space utilization and arrangement are achieved to minimize the area of ​​the display area, which is of great importance for the transparent display device that adopts the display substrate and can take into account the area of ​​the non-light-emitting area while fulfilling the requirement to use the display area for displaying images; it can also better accommodate the function of seeing through the surrounding image through the non-light-emitting area.

[0162] Fig. Figure 10 is a schematic diagram of an arrangement of a plurality of subpixels of a display unit P provided by an embodiment of the present disclosure. For example, as in Fig. As shown in Figure 10, the length of a subpixel in the second direction D2 is greater than the width of the subpixel in the first direction D1, the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 are arranged in the second direction D2, and the area of ​​the orthographic projection of the first subpixel P1 on the base substrate 1 and the area of ​​the orthographic projection of the third subpixel P3 on the base substrate 1 are both larger than the area of ​​the orthographic projection of the second subpixel P2 on the base substrate 1 and the area of ​​the orthographic projection of the fourth subpixel P4 on the base substrate 1.In this way, the first subpixel P1 and the third subpixel P3 are arranged with a larger size along the longitudinal direction and are located in the same column of subpixels, so that the subpixels in the display area 11 can be arranged sensibly in order to prevent the display area 11 from taking up too much space, which does not affect the space of the non-light-emitting area 12.For example, the area of ​​the orthographic projection of the first subpixel P1 on the base substrate 1 is larger than the area of ​​the orthographic projection of the third subpixel P3 on the base substrate 1, the area of ​​the orthographic projection of the second subpixel P2 on the base substrate 1, and the area of ​​the orthographic projection of the fourth subpixel P4 on the base substrate 1, so that the larger subpixels are arranged in the same row, and it is easy to arrange four subpixels regularly in a display unit P using the limited area of ​​the display area 11.

[0163] For example, the first subpixel P1 emits red (R) light, the second subpixel P2 blue (B) light, the third subpixel P3 white (W) light and the fourth subpixel P4 green (G) light, to compensate for the difference in lifetime of light-emitting layers emitting different colors of light by ensuring that subpixels with different area sizes correspond to the respective light-emitting colors.

[0164] At least one embodiment of the present disclosure further provides a display substrate, and the display substrate comprises a base substrate and a display unit provided on the base substrate. The display unit comprises a display area and a non-light-emitting area, the display area comprises a subpixel, the subpixel comprises a driver transistor and a light-emitting device, the driver transistor is configured to control the magnitude of a driver current flowing through the light-emitting device, and the light-emitting device is configured to receive the driver current and be driven by the driver current to emit light;The light-emitting device comprises a common electrode, and the common electrode is connected to a common voltage terminal. The display unit comprises an auxiliary electrode lead, a first auxiliary electrode, and an auxiliary insulating layer. The auxiliary electrode lead comprises a longitudinal section located in the display area and a transverse section located at least partially in the non-light-emitting area, and the transverse section is connected to the longitudinal section; the first auxiliary electrode is located in the non-light-emitting area and is electrically connected to the common electrode; the auxiliary insulating layer comprises a first auxiliary through-hole located in the non-light-emitting area and exposing at least part of the transverse section, and the first auxiliary electrode is connected to the transverse section through the first auxiliary through-hole.wherein the transverse section, the first auxiliary electrode, and the first auxiliary through-hole form an auxiliary unit, and the display unit comprises a plurality of auxiliary units; the transverse section of the auxiliary electrode conductor extends along a first direction, the longitudinal section of the auxiliary electrode conductor extends along a second direction intersecting the first direction, and the plurality of auxiliary units are spaced apart in the second direction. In the display substrate, the resistance of the original common electrode is reduced by electrically connecting the first auxiliary electrode in parallel with the common electrode in the non-light-emitting region.

[0165] For example, Fig. 11A a schematic planar local view of a first auxiliary unit H1 of the in Fig. 3A shown display unit, and Fig. 11B is a schematic cross-sectional view along line EE' in Fig. 11A. With reference to Fig. 3A and Fig. 11A- Fig. 11B comprises the light-emitting device 20 in the display substrate provided by at least one embodiment of the present disclosure, a common electrode, and the common electrode is connected to a common voltage terminal. The common electrode is, for example, a second electrode 24 (hereinafter referred to as common electrode 24), for example, a common cathode. The display unit P comprises an auxiliary electrode lead 8, a first auxiliary electrode 91, and an auxiliary insulating layer 104. The auxiliary electrode lead 8 is located, for example, in the third conductive layer 300; therefore, Fig. 11A-11B and Fig. 5F are combined. The auxiliary electrode lead 8 comprises a longitudinal section 81 located in the display area 11 and a transverse section 821 located at least partially in the non-light-emitting area 12, and the transverse section 821 is connected to the longitudinal section 81. For example, the transverse section 821 and the longitudinal section 81 form a continuous structure and are formed in one piece. The transverse section 821 of the auxiliary electrode lead 8 extends, for example, along the first direction D1, and the longitudinal section 81 of the auxiliary electrode lead 8 extends along the second direction D2, which intersects the first direction D1. The first auxiliary electrode 91 is located in the non-light-emitting area 12 and is electrically connected to the common electrode 24;and the auxiliary insulating layer 104 includes a first auxiliary through-hole V001, which is located in the non-light-emitting region 12 and exposes at least part of the transverse section 821, and the first auxiliary electrode 91 is connected to the transverse section 821 through the first auxiliary through-hole V001. That is, the transverse section 821 is connected to the common electrode 24 via the first auxiliary electrode 91 by means of the first auxiliary through-hole V001. In this way, the first auxiliary electrode 91 is electrically connected to the transverse section 821 of the auxiliary electrode line 8 through the first auxiliary through-hole V001 in the non-light-emitting area 12, by providing the first auxiliary through-hole V001 and the first auxiliary electrode 91 in the non-light-emitting area 12 and by guiding the transverse section 821 from the display area 11 to the non-light-emitting area 12;and the first auxiliary electrode 91 is also electrically connected to the common electrode 24, so that the transverse section 821 of the auxiliary electrode lead 8 is electrically connected to the common electrode 24 in the non-light-emitting area 12, thereby adding the first auxiliary electrode 91 and the auxiliary electrode lead 8, which are electrically connected to the common electrode 24, in parallel, so that the space of the display area 11 is not occupied, while the resistance of the original common electrode is reduced, and the non-light-emitting area 12 is fully utilized with sufficient space to accommodate the first auxiliary electrode 91, the first auxiliary through-hole V001 and the transverse section 821 of the auxiliary electrode lead 8.

[0166] The auxiliary electrode line 8 is, for example, the second power supply line Vss mentioned above. For the description of the display area 11 and the non-light-emitting area 12, please refer to the previous description.

[0167] For example, the auxiliary insulating layer 104 and the fourth insulating layer 104 are provided in the same layer and are made of the same material and are formed by carrying out the same patterning process on the same film layer, and the same patterning process is, for example, a photolithography process which includes an exposure process, a development process and other processes.

[0168] For example, the intermediate insulating layer 105 and the fifth insulating layer are in the same layer and made of the same material and are formed by the same structuring process on the same film layer, and the same structuring process is, for example, a photolithography process which includes exposure, development and other processes.

[0169] As in Fig. As shown in Figure 11B, the first auxiliary electrode 91 comprises, for example, a first conductive sublayer 901, a first stacked section 91a, and a second stacked section 91b. The first conductive sublayer 901 is connected to the transverse section 821 via the first auxiliary through-hole V001;The first stacked section 91a is electrically connected to the first conductive sublayer 901 and is stacked in the direction perpendicular to the base substrate 1. It is located on a side of the first conductive sublayer 901 furthest from the base substrate 1 and comprises a first stacked layer 911 and a second stacked layer 912, which are stacked together in the direction perpendicular to the base substrate. The second stacked layer 912 is located on a side of the first stacked layer 911 furthest from the base substrate 1 and is connected to the common electrode 24. The first stacked section 91a is located at an end of the first auxiliary electrode 91 that is closest to the display area 11 and is directly connected to the structure in the display area 11.The second stacked layer 912, for example, is directly connected to the common electrode 24, without any other electrodes or structures between the two. The second stacked section 91b is stacked on the first conductive sublayer 901 in a direction perpendicular to the base substrate 1, is located on the side of the first conductive sublayer 901 furthest from the base substrate 1, and is located on a side of the first stacked section 91a furthest from the base substrate 1; wherein the second stacked section 91b is electrically connected to the first stacked section 91a through the first conductive sublayer 901, for example, the second stacked section 91b is in direct contact with the first conductive sublayer 901 and the second stacked section 91b is in direct contact with the first stacked section 91a;For example, the surface of the second stacked section 91b and the surface of the first conductive sublayer 901 are in direct contact with each other and are stacked in the direction perpendicular to the base substrate 1, and the surface of the second stacked section 91b and the surface of the first stacked section 91a are in direct contact with each other and are stacked in the direction perpendicular to the base substrate 1. In addition, the second stacked section 91b comprises a third stacked layer 913 and a fourth stacked layer 914, which are stacked together in the direction perpendicular to the base substrate 1;the third stacked layer 913 and the first stacked layer 911 are made of the same material, are provided in the same layer and are spaced apart from each other in the direction parallel to the base substrate 1, and the fourth stacked layer 914 and the second stacked layer 912 are made of the same material, are provided in the same layer and are spaced apart from each other in the direction parallel to the base substrate.

[0170] For example, the third stacked layer 913 and the first stacked layer 911 are formed by the same process. This same process may be the same structuring process, and the structuring process may involve, for example, using an evaporation mask to perform evaporation to form the third stacked layer 913 and the first stacked layer 911; or the structuring process may involve, for example, using a mask to perform exposure, development, etching, and other processes. Alternatively, the same process may, for example, not involve a structuring process but only a deposition or vapor deposition process, so that the third stacked layer 913 is naturally separated from the first stacked layer 911 (as described below), thereby simplifying the manufacturing process of the display substrate.

[0171] Similarly, for example, the fourth stacked layer 914 and the second stacked layer 912 are formed by the same process. This same process may be the same structuring process, and the structuring process may include, for example, the use of a vapor deposition mask to perform a vapor deposition to form the fourth stacked layer 914 and the second stacked layer 912; or the structuring process may include, for example, the use of a mask to perform an exposure process, a development process, an etching process, and other processes. Alternatively, the same process may, for example, not include a structuring process but only a deposition or vapor deposition process, so that the fourth stacked layer 914 is naturally separated from the second stacked layer 912 (as described below), thereby simplifying the manufacturing process of the display substrate.

[0172] For example, in Fig. As shown in Figure 11B, the second stacked layer 912 is connected to the common electrode 24 and is in direct contact with the first conductive sublayer 901; for example, the second stacked layer 912 is in contact with the first conductive sublayer 901 in a first region TP1. For example, the first stacked layer 911 is in contact with the first conductive sublayer 901; and the second stacked layer 912 comprises an upper section covering an upper surface of the first stacked layer 911 located away from the base substrate 1, and a side section covering a side surface of the first stacked layer 911 that intersects with the upper surface of the first stacked layer 911, and the side section is in contact with the first conductive sublayer 901.That is, the first region TP1 is located at an edge of the second stacked layer 912 near the second stacked section 91b, the side section of the second stacked layer 912 is also an edge section (a section of the second stacked layer 912 that is located in the first region TP1) of the second stacked layer 912 near the second stacked section 91b, and the edge section of the second stacked layer 912 is in direct contact with the first conductive sublayer 901.

[0173] For example, in Fig. As shown in Figure 11B, the second stacked layer 912 covers the upper surface of the first stacked layer 911 away from the base substrate 1 and covers the side surface of the first stacked layer 911 that intersects the upper surface of the first stacked layer 911, and the edge section of the second stacked layer 912 located near the second stacked section 91b covers at least the side surface of the first stacked layer 911, i.e., covers an edge of the first stacked layer 911 located near the second stacked section 91b, so that the edge section of the second stacked layer 912 near the second stacked section 91b is able to be in direct contact with the first conductive sublayer 901.

[0174] As in Fig. As shown in Figure 11B, the second stacked section 91b, for example, comprises a fifth stacked layer 915 and a sixth stacked layer 916. The fifth stacked layer 915 is located between the first conductive sublayer 901 and the third stacked layer 913; the sixth stacked layer 916 is located between the fifth stacked layer 915 and the third stacked layer 913; The fifth stacked layer 915 and the sixth stacked layer 916 are stacked on the first conductive sublayer 901, the third stacked layer 913 and the fourth stacked layer 914 in the direction perpendicular to the base substrate 1 and are electrically connected to each other, and the fifth stacked layer 915 and the sixth stacked layer 916 are both spaced apart from the first stacked layer 911 and the second stacked layer 912 in the direction parallel to the base substrate 1, that is, the third stacked layer 913,The fourth stacked layer 914, the fifth stacked layer 915, and the sixth stacked layer 916 are all spaced from the first stacked layer 911 and the second stacked layer 912 in the direction parallel to the base substrate 1. For example, the orthographic projection of the sixth stacked layer 916 on the base substrate 1 includes a central region CR and an edge region PR surrounding the central region CR, and the orthographic projection of the fifth stacked layer 915 on the base substrate 1 overlaps the central region CR but does not overlap the edge region PR. The orthographic projection of the first region TP1 on the base substrate 1 lies at least partially within the orthographic projection of the edge region PR on the base substrate 1. In this way, a plurality of conductive layers are stacked to form the second stacked section 91b, which is advantageous,to better reduce the resistance of the original common electrode. For example, see , Fig. 4A, the light-emitting device 20 comprises the aforementioned first electrode 2 and the light-emitting layer 23, which are located in the display area 11. The light-emitting layer 23 is arranged between the first electrode 2 and the common electrode 24. The first electrode 2 comprises a first electrode sublayer 2a, a second electrode sublayer 2b, and a third electrode sublayer 2c, which are stacked successively in a direction perpendicular to the base substrate 1 and along a direction from near to away from the base substrate 1. For example, the first conductive sublayer 901 of the first auxiliary electrode 91 and the first electrode sublayer 2a are made of the same material and are provided in the same layer; the first stacked layer 911 and the light-emitting layer 23 are made of the same material.are provided in the same layer and form a continuous and one-piece structure; the second stacked layer 912 and the common electrode 24 are made of the same material, are provided in the same layer and form a continuous and one-piece structure; the third stacked layer 913 and the light-emitting layer 23 consist of the same material and are provided in the same layer; the fourth stacked layer 914,The second stacked layer 912 and the common electrode 24 are made of the same material and are located in the same layer; the fifth stacked layer 915 and the second electrode sublayer 2b are made of the same material and are located in the same layer; and the sixth stacked layer 916 and the third electrode sublayer 2c are made of the same material and are located in the same layer. In this way, the first conductive sublayer 901 and the first electrode sublayer 2a of the first auxiliary electrode 91 can be formed by the same process; the first stacked layer 911, the light-emitting layer 23, and the third stacked layer 913 can be formed by the same process; the fourth stacked layer 914, the second stacked layer 912, and the common electrode 24 can be formed by the same process.The fifth stacked layer 915 and the second electrode sublayer 2b can be formed by the same process, and the sixth stacked layer 916 and the third electrode sublayer 2c can be formed by the same process. The “same process” here can refer to the explanation mentioned above. In this way, each layer structure of the first auxiliary electrode 91 can be formed using the processes corresponding to the various functional layers in the display area 11 mentioned above, without additional film layer fabrication or patterning processes for providing the first auxiliary electrode 91.

[0175] For example, during the production of the display substrate in Fig. As shown in Figure 11B, the fifth stacked layer 915 and the sixth stacked layer 916 are formed by the same structuring process using the same mask, for example using an etching process such as a wet etching process, to simplify the manufacturing process of the display substrate;Furthermore, since the materials of the fifth stacked layer 915 and the sixth stacked layer 916 are different, the material of the fifth stacked layer 915 and the material of the sixth stacked layer 916 are each the same as the material of the second electrode sublayer 2b and the material of the third electrode sublayer 2c, and reference can be made to the previous description of the material of the second electrode sublayer 2b and the material of the third electrode sublayer 2c, so that the fifth stacked layer 915 and the sixth stacked layer 916 have different etch rates and the fifth stacked layer 915 shrinks inwards relative to the sixth stacked layer 916, as in ; Fig. Figure 11B shows that the orthographic projection of the fifth stacked layer 915 on the base substrate 1 overlaps with the central area CR and does not overlap with the edge area PR. After the formation of the fifth stacked layer 915 and the sixth stacked layer 916, the steps for the formation of the first stacked layer 911, the light-emitting layer 23, the third stacked layer 913, the fourth stacked layer 914, and the second stacked layer 912 are carried out sequentially.

[0176] In the process for forming the first stacked layer 911, the light-emitting layer 23 and the third stacked layer 913 on a side of the sixth stacked layer 916 away from the base substrate 1, for example, the first stacked layer 911, the light-emitting layer 23 and the third stacked layer 913 are formed by a vapor deposition process, and the first stacked layer 911 and the light-emitting layer 23 can be formed into a single-piece structure.Due to the presence of the fifth stacked layer 915 and the sixth stacked layer 916, these layers have a specific thickness. This results in a segment difference between the upper surface of the sixth stacked layer 916, located away from the base substrate 1, and the upper surface of the first conductive sublayer 901, also located away from the base substrate 1. Consequently, the third stacked layer 913 and the first stacked layer 911 can be separated from each other due to this segment difference. Furthermore, there is a segment difference between the upper surface of the third stacked layer 913, located away from the base substrate 1, and the upper surface of the first stacked layer 911, also located away from the base substrate 1.

[0177] Next, in the process for forming the fourth stacked layer 914, the second stacked layer 912, and the common electrode 24, for example, the fourth stacked layer 914, the second stacked layer 912, and the common electrode 24 are formed by a deposition process, and the second stacked layer 912 and the common electrode 24 can be formed into a single-piece structure. Due to the segment difference between the upper surface of the third stacked layer 913, as seen from the base substrate 1, and the upper surface of the first stacked layer 911, as seen from the base substrate 1, the fourth stacked layer 914 and the second stacked layer 912 can be separated from each other; furthermore, because the fifth stacked layer 915 shrinks inwards relative to the sixth stacked layer 916, i.e.,The orthographic projection of the fifth stacked layer 915 on the base substrate 1 overlaps with the central region CR and does not overlap with the edge region PR; therefore, the second stacked layer 912 is in contact with the first conductive sublayer 901 in the first region TP1, and the orthographic projection of the first region TP1 on the base substrate 1 is at least partially located within the orthographic projection of the edge region PR on the base substrate 1.

[0178] In this way, the common electrode 24 can be connected to the first conductive sublayer 901, so that the first auxiliary electrode 91 can be connected electrically in parallel to the common electrode 24 to reduce the resistance of the original common electrode 24.

[0179] For example, the sum of the thickness of the fifth stacked layer 915 in the direction perpendicular to the base substrate 1 and the thickness of the sixth stacked layer 916 in the direction perpendicular to the base substrate 1 is greater than or equal to 6000 Angstroms, such that the fifth stacked layer 915 has sufficient thickness to form a sufficient segment difference between the upper surface of the sixth stacked layer 916, located away from the base substrate 1, and the upper surface of the first conductive sublayer 901, located away from the base substrate 1, to continue to ensure the reliability that the third stacked layer 913 and the first stacked layer 911 can be separated from each other due to the segment difference, and the reliability that the fourth stacked layer 914 and the second stacked layer 912 can be separated from each other.

[0180] As in Fig. As shown in Figure 11B, the first auxiliary electrode 91, for example, comprises a third stacked section 91c.The third stacked section 91c is stacked on the first conductive sublayer 901 in the direction perpendicular to the base substrate 1, is located on the side of the first conductive sublayer 901 furthest from the base substrate 1, is electrically connected to the first stacked section 91a and the second stacked section 91b through the first conductive sublayer 901 and comprises a seventh stacked layer 917 and an eighth stacked layer 918 stacked together in the direction perpendicular to the base substrate 1, wherein the seventh stacked layer 917 and the third stacked layer 913 are provided in the same layer and are spaced apart from each other in the direction parallel to the base substrate 1, and the eighth stacked layer 918 and the fourth stacked layer 914 are provided in the same layer and are spaced apart from each other in the direction parallel to the base substrate 1.

[0181] For example, the eighth stacked layer 918 is in direct contact with the first conductive sublayer 901. Similarly, the eighth stacked layer 918 is in direct contact with the first conductive sublayer 901 in a second region TP2, and the orthographic projection of the second region TP2 on the base substrate 1 lies at least partially within the orthographic projection of the edge region PR on the base substrate 1. As in the case of the first region TP1, the eighth stacked layer 918 covers the upper surface of the seventh stacked layer 917 furthest from the base substrate 1 and the side surface of the seventh stacked layer 917 that intersects the upper surface of the seventh stacked layer 917, and the edge section of the eighth stacked layer 918 located near the second stacked section 91b covers at least the side surface of the seventh stacked layer. 917, i.e.covers an edge of the seventh stacked layer 917 located near the second stacked section 91b, so that the edge section of the eighth stacked layer 918 located near the second stacked section 91b is able to be in direct contact with the first conductive sublayer 901.

[0182] For example, the seventh stacked layer 917, the third stacked layer 913, and the light-emitting layer 23 are made of the same material and located in the same layer, and the eighth stacked layer 918, the fourth stacked layer 914, and the second stacked layer 912 are made of the same material and located in the same layer. In this way, the seventh stacked layer 917, the third stacked layer 913, and the light-emitting layer 23 can be formed by the same process, and the eighth stacked layer 918 and the fourth stacked layer 914 can be formed by the same process. The “same process” here refers to the explanation mentioned above.Similar to the formation of the structure in the first area TP1, in the process of forming the seventh stacked layer 917, the third stacked layer 913 and the light-emitting layer 23 using the same process, the segment difference formed by the fifth stacked layer 915 and the sixth stacked layer 916 can cause the seventh stacked layer 917 to be separated from the third stacked layer 913, and in the process of forming the eighth stacked layer 918, the fourth stacked layer 914 and the second stacked layer 912 using the same process, the eighth stacked layer 918 is separated from the fourth stacked layer 914.

[0183] Fig. Figure 11C is a schematic planar view showing the positional relationship of the second stacked layer, the fourth stacked layer, the fifth stacked layer, and the eighth stacked layer in Fig. 11B shows. With reference to Fig. 11B and Fig. For example, in 11C, the second stacked layer 912 and the eighth stacked layer 918 form a continuous and one-piece structure, and the continuous and one-piece structure includes an edge section that surrounds the second stacked section 91b, and the edge section is in direct contact with the first conductive sublayer 901, that is, the first conductive sublayer 901 is in direct contact with the continuous and one-piece structure formed by the second stacked layer 912 and the eighth stacked layer 918 in a circumferential area that surrounds the entire second stacked section 91b, so that the first conductive sublayer 901 is connected to the continuous and one-piece structure by the second stacked layer 912 and the eighth stacked layer 918 at a multitude of positions, thereby ensuring reliability.that the first conductive sublayer 901 is electrically connected to the common electrode 24. The first region TP1 and the second region TP2 are each two sections of the circumferential region located on two opposite sides of the second stacked section 91b, and two positions of the first region TP1 and the second region TP2 are shown as an example in , Fig. 11B is taken to introduce how the first conductive sublayer 901 is electrically connected to the common electrode 24.

[0184] For example, in Fig. 11A and Fig. As shown in Figure 11B, the interlayer insulating layer 105 of the display substrate is located on the side of the auxiliary insulating layer 104 furthest from the base substrate 1, an edge of the interlayer insulating layer 105 is located in the non-light-emitting region 12, and part of the first conductive sublayer 901 covers the interlayer insulating layer 105; the first region TP1 is located within the orthographic projection of the interlayer insulating layer 105 onto the base substrate 1, i.e.The edge section of the second stacked layer 912 is in contact with the first conductive sublayer 901 on the interlayer insulating layer 105 to reduce the segment difference between the second stacked layer 912 (which forms a continuous and one-piece structure with the common electrode 24) and the first conductive sublayer 901 on the pixel definition layer 6 in the direction perpendicular to the base substrate 1 by using the thickness of the interlayer insulating layer 105, and to prevent the second stacked layer 912 from being broken, thereby ensuring the reliability of the connection between the second stacked layer 912 and the first conductive sublayer 901 in the first region TP1.

[0185] For example, in Fig. As shown in Figure 11B, the second area TP2 is located on a side of the orthographic projection of the interlayer insulating layer 105 on the base substrate 1 that is remote from the display area 11. The transition of layers such as the fifth stacked layer 915 reduces the segment difference between the first conductive sublayer 901 and the eighth stacked layer 918, and there is no need to extend the thicker interlayer insulating layer 105 to the first auxiliary through-hole V001, thus preventing the thicker interlayer insulating layer 105 from interfering with the connection of the individual layers at the first auxiliary through-hole V001.

[0186] For example, the transverse section 821, the first auxiliary electrode 91 and the first auxiliary through-hole V001, which are in Fig. Figure 11B shows an auxiliary unit, and the display unit P comprises a plurality of auxiliary units. A plurality of auxiliary units are spaced apart in the second direction D2.

[0187] For example, the multitude of auxiliary units spaced apart in the second direction D2 are all located in the non-light-emitting area 12 and have the same or different distances from the display area 11 in the first direction D1.

[0188] For example, the multitude of auxiliary units includes a first auxiliary unit H1 and a second auxiliary unit H2; the specific structures of the first auxiliary unit H1 and the second auxiliary unit H2 are similar; the first auxiliary unit H1 and the second auxiliary unit H2 are both auxiliary units, as in Fig. 11B shown above, but the specific positions of the first auxiliary unit H1 and the second auxiliary unit H2 are different.

[0189] For example, in Fig. As shown in 3A, the multitude of auxiliary units comprises a first auxiliary unit H1 and a second auxiliary unit H2, wherein both the first auxiliary unit H1 and the second auxiliary unit H2 are located in the non-light-emitting area 12 and the first auxiliary unit H1 and the second auxiliary unit H2 have different distances from the display area 11 in the first direction D1.

[0190] Fig. 12A is a schematic planar local view of the second auxiliary unit H2 of the in Fig. 3A shown display unit, and Fig. 12B is a schematic cross-sectional view along line FF' in Fig. 12A.

[0191] The second auxiliary unit H2 differs from the first auxiliary unit H1 as follows. As in Fig. 12A and Fig. As shown in Figure 12B, the distance between a first auxiliary through-hole V002 of the second auxiliary unit H2 and the display area 11 in the first direction D1 is greater than the distance between a first auxiliary through-hole V001 of the first auxiliary unit H1 and the display area 11 in the first direction D1, i.e., with reference to Fig. 3A, Fig. 12A and Fig. 12B is the distance between an edge of the first auxiliary through-hole V002 of the second auxiliary unit H2 near the display area 11 and an edge of the second power supply line vss near the non-light-emitting area 12B greater than the distance between an edge of the first auxiliary through-hole V001 of the first auxiliary unit H1 near the display area 11 and the edge of the second power supply line vss near the non-light-emitting area 12B.Therefore, the second auxiliary unit H2 and the first auxiliary unit H1 are offset in the second direction D2, which is advantageous for the use of a limited space, especially in the case where the area of ​​each display unit in a high PPI (pixels per inch) display substrate is smaller and it is necessary to use a limited area to arrange a large number of auxiliary units, ensuring that the second auxiliary unit H2 and the first auxiliary unit H1 are offset in the second direction D2, which allows the large number of auxiliary units to better adapt to the arrangement of the lines nearby.

[0192] In Fig. 5G and Fig. For example, in 12A, the planar shape of the first auxiliary through-hole V002 of the second auxiliary unit H2 is a trapezoid, in order to increase the contact area between the first conductive sublayer 901 and the transverse section 821. Of course, the planar shape of the first auxiliary through-hole V002 can also be circular, rectangular, etc.

[0193] For example, as in Fig. 12A and Fig. As shown in Figure 12B, the length of the transverse section 821 of the second auxiliary unit H2 in the first direction D1 is greater than the length of the transverse section 821 of the first auxiliary unit H1 in the first direction D1, in order to ensure that the through-hole of the second auxiliary unit H2 is located further away from the display area 22.

[0194] For example, a display unit P comprises at least three first auxiliary units H1, the number of second auxiliary units H2 is greater than or equal to one, and in the second direction D2 there is at least one second auxiliary unit H2 between the at least three first auxiliary units H1. As in Fig. As shown in Figure 3A, a display unit P comprises, for example, three first auxiliary units H1 and one second auxiliary unit H2, with the second auxiliary unit H2 being located between the three first auxiliary units H1. Of course, in other embodiments, the number of first auxiliary units H1 and second auxiliary units H2 in each display unit can also be designed according to the size of the display substrate and the requirement to reduce the resistance of the original common electrode. The present disclosure does not limit the number of first auxiliary units H1 and second auxiliary units H2.

[0195] Table 1 below is a table of the relationship between an auxiliary unit and the common electrode voltage drop, and Table 1 illustrates the influence of providing an auxiliary unit on the common electrode voltage drop. Table 1: Relationship between an auxiliary device and the voltage drop of the common electrode Widerstand einer Hilfseinheit / Ω 2000 20000 200000 4000000 17500000 Spannungsabfall der gemeinsamen Elektrode / V 1.336 1.427 2.338 3.029 8.339

[0196] As in Fig. As shown in Figure 12B, for example, the first stacked layer 911 of the first stacked section 91a of the second auxiliary unit H2 includes an inter-hole SP, and the second stacked layer 912 of the first stacked section 91a is electrically connected to the first conductive sublayer 901 of the second auxiliary unit H2 via the inter-hole SP. That is, as shown in Fig. As shown in Figure 12B, the first stacked layer 911 of the first stacked section 91a of the second auxiliary unit H2 comprises a first section 911a located near the display area 11 and a second section 911b located away from the display area 11, and the intervening through-hole SP, which exposes the first conductive sublayer 901 of the second auxiliary unit H2, is located between the first section 911a of the first stacked layer 911 and the second section 911b of the first stacked layer 911 to ensure that the first section 911a of the first stacked layer 911 is at least partially separated from the second section 911b of the first stacked layer 911; the second stacked layer 912 is electrically connected to the first conductive sublayer 901 of the second auxiliary unit H2 through the intervening through-hole SP.which further increases the contact area between the first conductive sublayer 901 and the second stacked layer 912; in addition to achieving the electrical connection between the common electrode 24 and the first conductive sublayer 901 in the first region TP1 and the second region TP2, the electrical connection between the common electrode 24 and the first conductive sublayer 901 is also achieved through the intermediate through-hole SP, thereby further ensuring the reliability of the electrical connection between the common electrode 24 and the first conductive sublayer 901 and ensuring that the first auxiliary electrode 91 of the second auxiliary unit H2 is electrically connected in parallel with the common electrode 24,to reduce the resistance of the original common electrode 24. Furthermore, since the distance between the first auxiliary through-hole V002 of the second auxiliary unit H2 and the display area 11 in the first direction D1 is greater than the distance between the first auxiliary through-hole V001 of the first auxiliary unit H1 and the display area 11 in the first direction D1, and the length of the transverse section 821 of the second auxiliary unit H2 in the first direction D1 is greater than the length of the transverse section 821 of the first auxiliary unit H1 in the first direction D1, the above-mentioned construction therefore provides sufficient space for the intermediate through-hole SP.

[0197] For example, the intermediate hole SP in Fig. 12B is formed by laser drilling, i.e. the first stacked layer 911 is drilled through with a laser, exposing the first conductive sublayer 901, and the first auxiliary through-hole V002 of the second auxiliary unit H2 is far from the display area 11 in the first direction D1, providing sufficient space for carrying out the laser drilling to avoid damage to other structures near the intermediate through-hole SP due to overly dense wiring.

[0198] For example, the distance from the first auxiliary through-hole V002 of the second auxiliary unit H2 to the display area 11 in the first direction D1 is at least twice as large as the distance from the first auxiliary through-hole V001 of the first auxiliary unit H1 to the display area 11 in the first direction D1, in order to provide sufficient space for the provision of the intermediate through-hole SP, to provide sufficient space for laser drilling and to avoid damage to other structures near the intermediate through-hole SP due to overly dense wiring.

[0199] Other structures of the second auxiliary unit H2, which are in Fig. Figure 12B shows, for example, the second stacked layer 912, which is connected to the common electrode 24, the first stacked layer 911, the third stacked layer 913, ..., the eighth stacked layer 918, etc., are all the same as those in Fig. 11B shown, it can refer to the description in Fig. 11B are referred to, and will not be repeated here.

[0200] For example, the area of ​​the planar shape of the first auxiliary through-hole V001 of the second auxiliary unit H2 is larger than the area of ​​the planar shape of the first auxiliary through-hole V001 of the first auxiliary unit H1, i.e., the area of ​​the orthographic projection of the first auxiliary through-hole V001 of the second auxiliary unit H2 on the base substrate 1 is larger than the area of ​​the orthographic projection of the first auxiliary through-hole V001 of the first auxiliary unit H1 on the base substrate 1. This is because the second auxiliary unit H2 is farther from the display area 11, and the transverse section 821 of the second auxiliary unit is longer, so the transverse section 821 has a greater resistance.Therefore, the area of ​​the first auxiliary through-hole V001 of the second auxiliary unit H2 is larger in order to reduce the resistance of the entire structure formed by connecting the first auxiliary electrode 91 with the transverse section 821 through the first auxiliary through-hole V001 of the second auxiliary unit H2, thereby reducing the resistance of the entire second auxiliary unit H2.

[0201] For example, a display unit P comprises at least two first auxiliary units H1, and the number of second auxiliary units H2 is greater than or equal to one in order to reduce the resistance of the original common electrode more effectively. For example, a display unit P comprises at least three first auxiliary units H1, and in the second direction D2, at least one second auxiliary unit H2 is located between any two first auxiliary units of the at least three first auxiliary units H1 in order to arrange the positions of the auxiliary units at different distances from the display area 11 in a display unit P in a meaningful way, to fully utilize the limited space, and additionally to reduce the resistance of the original common electrode more effectively.

[0202] For example, regarding Fig. 3A, in a display unit P, the at least two first auxiliary units H1 comprise the No. 1 first auxiliary unit H1, the No. 2 first auxiliary unit H1, and the No. 3 first auxiliary unit H1; the No. 1 first auxiliary unit H1 and the No. 2 first auxiliary unit H1 are located in the second subpixel P2, and the No. 3 auxiliary unit H1 and the second auxiliary unit H2 are located in the fourth subpixel P4. In this way, the auxiliary units are arranged along the entire display unit P in the second direction D2, the resistance of the original common electrode is reduced in a relatively balanced manner at each position, and the display uniformity of the display substrate is improved.

[0203] For example, in Fig. As shown in Figure 3A, the No. 1 first auxiliary unit H1 and the No. 2 first auxiliary unit H1 are each arranged on two opposite sides of the connection section 30 of the second subpixel P2 in the second direction D2, and the No. 3 first auxiliary unit H1 and the second auxiliary unit H2 are each arranged on two opposite sides of the connection section 30 of the fourth subpixel P4 in the second direction D2 in order to coincide with the position of the connection section 30 and to fully utilize the empty area on the opposite sides of the connection section 30 in the second direction D2 in order to provide the first auxiliary unit H1 as much as possible.

[0204] For example, as in Fig. As shown in Figure 3A, the second auxiliary unit H2 is arranged in the second direction D2 on a side of the connection section 30 of the fourth subpixel P4 that is close to the connection of the fourth subpixel P4 and the second subpixel P2; alternatively, in other embodiments, the second auxiliary unit H2 can also be arranged on a side of the connection section 30 of the fourth subpixel P4 that is far from the connection of the fourth subpixel P4 and the second subpixel P2.

[0205] With reference to Fig. 11B, Fig. 3A, Fig. 3C and Fig. For example, in 4A, the area of ​​the planar shape of the first auxiliary through-hole V001 of the first auxiliary unit H1 is larger than the area of ​​the planar shape of the first through-hole V0. Since the structure provided in the first auxiliary through-hole V001 of the first auxiliary unit H1 is relatively complex and serves to reduce the resistance of the original common electrode, the area of ​​the first auxiliary through-hole V001 of the first auxiliary unit H1 is larger than the area of ​​an ordinary through-hole such as the first through-hole V0, which helps to fully ensure the reliability of the connection between the first auxiliary electrode 91 and the transverse section 821 through the first auxiliary through-hole V001 of the second auxiliary unit H2.

[0206] Fig. 13A is a schematic planar local view of the third auxiliary unit H3 of the in Fig. 3A shown display unit, and Fig. 13B is a schematic cross-sectional view along the line GG' in Fig. 13A.

[0207] With reference to Fig. 3A and Fig. 13A- Fig. In Figure 13B, the display unit P includes, for example, a second auxiliary electrode 92, and the second auxiliary electrode 92 is located in the display area 11 and is electrically connected to the common electrode 24. The auxiliary insulating layer 104 further includes a second auxiliary through-hole V003, which is located in the display area 11 and exposes at least part of the longitudinal section 81 of the auxiliary electrode lead 8, and the second auxiliary electrode 92 is connected to the longitudinal section 81 of the auxiliary electrode lead 8 through the second auxiliary through-hole V003. That is, the longitudinal section 81 of the auxiliary electrode lead 8 is connected to the common electrode 24 via the second auxiliary electrode 92 by means of the second auxiliary through-hole V003.In this way, in addition to providing the first auxiliary through-hole V001 and the first auxiliary electrode 91 in the non-light-emitting area 12, the second auxiliary through-hole V003 and the second auxiliary electrode 92 in the display area 11 electrically connect the second auxiliary electrode 92 in parallel with the common electrode 2 in order to further reduce the resistance of the original common electrode 24; and the auxiliary insulating layer 104 is the existing fourth insulating layer 104 in the display area 11, so that providing the second auxiliary through-hole V003 does not occupy any additional area of ​​the display area 11, which is advantageous for providing the second auxiliary electrode 92 while utilizing the limited space.

[0208] For example, in Fig. As shown in Figure 13B, the orthographic projection of the first conductive sublayer 901 on the base substrate 1 lies within the orthographic projection of the longitudinal section 81 of the auxiliary electrode lead 8 on the base substrate 1. Therefore, the first conductive sublayer 901 does not occupy any additional area of ​​the display area 11, which is advantageous for saving space, especially with a display substrate with a high PPI (pixels per inch) the area of ​​each display unit is smaller, so it is particularly important to utilize the limited space to provide the second auxiliary electrode 92.

[0209] As in Fig. As shown in Figure 13B, the second auxiliary electrode 92 comprises, for example, a second conductive sublayer 902, a first stacked section 92a, and a second stacked section 92b. The second conductive sublayer 902 is connected to the longitudinal section 81 of the auxiliary electrode lead 8 through the second auxiliary through-hole V003; the first stacked section 92a is electrically connected to the second conductive sublayer 902 of the second auxiliary electrode 92 and is stacked in the direction perpendicular to the base substrate 1, is located on a side of the second conductive sublayer 902 of the second auxiliary electrode 92 away from the base substrate 1, and comprises a first stacked layer 912 and a second stacked layer 922, which are stacked together in the direction perpendicular to the base substrate 1.and the second stacked layer 922 of the second auxiliary electrode 92 is located on a side of the first stacked layer 921 of the second auxiliary electrode 92 furthest from the base substrate 1 and is connected to the common electrode 24; the second stacked section 92b is stacked on the second conductive sublayer 902 of the second auxiliary electrode 92 in a direction perpendicular to the base substrate 1, is located on the side of the second conductive sublayer 902 of the second auxiliary electrode 92 furthest from the base substrate 1, and the second stacked section 92b is located on a side of the first stacked section 92a of the second auxiliary electrode 92 furthest from the base substrate 1, is electrically connected to the first stacked section 92a of the second auxiliary electrode 92 by the second conductive sublayer 902 and comprises a third stacked layer 923 and a fourth stacked layer 924,which are stacked together in a direction perpendicular to the base substrate 1. The third stacked layer 923 of the second auxiliary electrode 92 and the first stacked layer 921 of the second auxiliary electrode 92 are made of the same material, provided in the same layer and spaced apart from each other in a direction parallel to the base substrate 1, and the fourth stacked layer 924 of the second auxiliary electrode 92 and the second stacked layer 922 of the second auxiliary electrode 92 are made of the same material, provided in the same layer and spaced apart from each other in a direction parallel to the base substrate 1.

[0210] In Fig. In 13B, for example, the third stacked layer 923 and the first stacked layer 921 are formed by the same process. This same process may be a structuring process, and the structuring process may include, for example, the use of an evaporation mask to perform evaporation to form the third stacked layer 923 and the first stacked layer 921; or the structuring process may include, for example, the use of a mask to perform an exposure process, a development process, an etching process, and other processes. Alternatively, the same process may, for example, not include a structuring process but only a deposition process or an evaporation process, so that the third stacked layer 923 is naturally separated from the first stacked layer 921 (as described below), thereby simplifying the manufacturing process of the display substrate.

[0211] Similarly, for example in Fig. 13B The fourth stacked layer 924 and the second stacked layer 922 are formed by the same process. The same process can be the same structuring process, and the structuring process includes, for example, the use of an evaporation mask to perform evaporation to form the fourth stacked layer 924 and the second stacked layer 922; or the structuring process includes, for example, the use of a mask to perform an exposure process, a development process, an etching process, and other processes. Alternatively, the same process may, for example, not include a structuring process but only a deposition process or an evaporation process, such that the fourth stacked layer 924 is naturally separated from the second stacked layer 922 (as described below), thereby simplifying the manufacturing process of the display substrate.

[0212] For example, in Fig. As shown in Figure 13B, the second stacked layer 922 of the second auxiliary electrode 92 is connected to the common electrode 24 and is in direct contact with the second conductive sublayer 902 of the second auxiliary electrode 92. For example, the second stacked layer 922 in the first region TP1 is in contact with the first conductive sublayer 901.For example, the first stacked layer 921 of the second auxiliary electrode 92 is in contact with the first conductive sublayer 901; and the second stacked layer 922 of the second auxiliary electrode 92 comprises an upper section covering an upper surface of the first stacked layer 921 of the second auxiliary electrode 92 away from the base substrate 1, and a side section covering a side surface of the first stacked layer 911 of the second auxiliary electrode 92 that intersects with the upper surface of the first stacked layer 921, and the side section of the second auxiliary electrode 92 is in contact with the second conductive sublayer 902.That is, the first region TP1 is located at an edge of the second stacked layer 922 near the second stacked section 92b, the side section of the second stacked layer 922 is also an edge section (a section of the second stacked layer 922 that is located in the first region TP1) of the second stacked layer 922 near the second stacked section 92b, and the edge section of the second stacked layer 922 is in direct contact with the second conductive sublayer 902.

[0213] For example, as in Fig. As shown in Figure 13B, the second stacked layer 922 covers the upper surface of the first stacked layer 921, which is remote from the base substrate 1, and the side surface that intersects the upper surface of the first stacked layer 921, and the edge section of the second stacked layer 922 located near the second stacked section 92b covers at least the side surface of the first stacked layer 921, i.e., an edge of the first stacked layer 921 located near the second stacked section 92b, so that the edge section of the second stacked layer 922 located near the second stacked section 92b is able to be in direct contact with the second conductive sublayer 902.

[0214] As in Fig. As shown in Figure 13B, the second stacked section 92b, for example, comprises a fifth stacked layer 925 and a sixth stacked layer 926. The fifth stacked layer 925 is located between the second conductive sublayer 902 and the third stacked layer 923; the sixth stacked layer 926 is located between the fifth stacked layer 925 and the third stacked layer 923; The fifth stacked layer 925 and the sixth stacked layer 926 are stacked on the second conductive sublayer 902, the third stacked layer 923 and the fourth stacked layer 924 in the direction perpendicular to the base substrate 1 and are electrically connected to each other, and the fifth stacked layer 925 and the sixth stacked layer 926 are both spaced apart from the first stacked layer 921 and the second stacked layer 922 in the direction parallel to the base substrate 1, that is, the third stacked layer 923,The fourth stacked layer 924, the fifth stacked layer 925, and the sixth stacked layer 926 are all spaced from the first stacked layer 921 and the second stacked layer 922 in the direction parallel to the base substrate 1. For example, the orthographic projection of the sixth stacked layer 926 on the base substrate 1 includes a central region CR and an edge region PR surrounding the central region CR, and the orthographic projection of the fifth stacked layer 925 on the base substrate 1 overlaps the central region CR but does not overlap the edge region PR. The orthographic projection of the first region TP1 on the base substrate 1 lies at least partially within the orthographic projection of the edge region PR on the base substrate 1. In this way, a plurality of conductive layers are stacked together to form the second stacked section 92b, which is advantageous,to better reduce the resistance of the original common electrode. For example, see , Fig. 4A, the light-emitting device 20 comprises the aforementioned first electrode 2 and the light-emitting layer 23, which are located in the display area 11. The light-emitting layer 23 is arranged between the first electrode 2 and the common electrode 24. The first electrode 2 comprises a first electrode sublayer 2a, a second electrode sublayer 2a, a second electrode sublayer 2b, and a third electrode sublayer 2c, which are stacked one on top of the other in a direction perpendicular to the base substrate 1 and along a direction from a position close to the base substrate 1 to a position remote from the base substrate 1. For example, the second conductive sublayer 902 of the first auxiliary electrode 92 and the first electrode sublayer 2a are made of the same material and in the same layer. The first stacked layer 921 and the light-emitting layer 23 form a continuous and one-piece structure.The second stacked layer 922 and the common electrode 24 form a continuous and single-piece structure; the third stacked layer 923 and the light-emitting layer 23 are made of the same material and are located in the same layer; the fourth stacked layer 924, the second stacked layer 922, and the common electrode 24 are made of the same material and are located in the same layer; the fifth stacked layer 925 and the second electrode sublayer 2b are made of the same material and are located in the same layer; and the sixth stacked layer 926 and the third electrode sublayer 2c are made of the same material and are located in the same layer. In this way, the second conductive sublayer 902 of the first auxiliary electrode 92 and the first electrode sublayer 2a can be formed by the same process, as can the first stacked layer 921.The light-emitting layer 23 and the third stacked layer 923 can be formed by the same process; the fourth stacked layer 924, the second stacked layer 922, and the common electrode 24 can be formed by the same process; the fifth stacked layer 925 and the second electrode sublayer 2b can be formed by the same process; and the sixth stacked layer 926 and the third electrode sublayer 2c can be formed by the same process. The “same process” here can refer to the explanation mentioned above. In this way, each layer structure of the first auxiliary electrode 92 can be formed using the processes corresponding to the various functional layers in the display area 11 mentioned above, without adding an additional film layer fabrication process or a patterning process to provide the first auxiliary electrode 92.

[0215] For example, in the production of the in Fig. As shown in Figure 13B, the fifth stacked layer 925 and the sixth stacked layer 926 are formed by the same structuring process using the same mask, for example using an etching process such as a wet etching process, to simplify the manufacturing process of the display substrate;Furthermore, since the materials of the fifth stacked layer 925 and the sixth stacked layer 926 are different, the material of the fifth stacked layer 925 and the material of the sixth stacked layer 926 are each the same as the material of the second electrode sublayer 2b and the material of the third electrode sublayer 2c, and reference can be made to the previous description of the material of the second electrode sublayer 2b and the material of the third electrode sublayer 2c, so that the etch rates of the formation of the fifth stacked layer 925 and the sixth stacked layer 926 in the etching process are different and the fifth stacked layer 925 shrinks inwards relative to the sixth stacked layer 926, as in ; Fig. As shown in Figure 13B, the orthographic projection of the fifth stacked layer 925 on the base substrate 1 overlaps with the central area CR and does not overlap with the edge area PR. After the formation of the fifth stacked layer 925 and the sixth stacked layer 926, the steps for the formation of the first stacked layer 921, the light-emitting layer 23, the third stacked layer 923, the fourth stacked layer 924, and the second stacked layer 922 are carried out successively.

[0216] In the process for forming the first stacked layer 921, the light-emitting layer 23 and the third stacked layer 923 on a side of the sixth stacked layer 926 away from the base substrate 1, for example, the first stacked layer 921, the light-emitting layer 23 and the third stacked layer 923 are formed by a vapor deposition process, and the first stacked layer 921 and the light-emitting layer 23 can be formed into a continuous and one-piece structure.Due to the presence of the fifth stacked layer 925 and the sixth stacked layer 926, these layers have a specific thickness. This results in a segment difference between the upper surface of the sixth stacked layer 926, located away from the base substrate 1, and the upper surface of the second conductive sublayer 902, also located away from the base substrate 1. Consequently, the third stacked layer 923 and the first stacked layer 921 can be separated from each other due to this segment difference. Furthermore, there is a segment difference between the upper surface of the third stacked layer 923, located away from the base substrate 1, and the upper surface of the first stacked layer 921, also located away from the base substrate 1.

[0217] Next, in the process for forming the fourth stacked layer 924, the second stacked layer 922, and the common electrode 24, for example, the fourth stacked layer 924, the second stacked layer 922, and the common electrode 24 are formed by a deposition process, and the second stacked layer 922 and the common electrode 24 can be formed into a continuous and one-piece structure. Due to the segment difference between the upper surface of the third stacked layer 923, as seen from the base substrate 1, and the upper surface of the first stacked layer 921, as seen from the base substrate 1, the fourth stacked layer 924 and the second stacked layer 922 can be separated from each other; furthermore, because the fifth stacked layer 925 shrinks inwards relative to the sixth stacked layer 926, i.e.,The orthographic projection of the fifth stacked layer 925 on the base substrate 1 overlaps with the central region CR and does not overlap with the edge region PR; therefore, the second stacked layer 922 is in contact with the second conductive sublayer 902 in the first region TP1, and the orthographic projection of the first region TP1 on the base substrate 1 is at least partially located within the orthographic projection of the edge region PR on the base substrate 1.

[0218] In this way, the common electrode 24 can be connected to the second conductive sublayer 902, so that the first auxiliary electrode 92 can be electrically connected in parallel with the common electrode 24 to reduce the resistance of the original common electrode 24.

[0219] For example, as in Fig. As shown in Figure 13B, the sum of the thickness of the fifth stacked layer 925 in the direction perpendicular to the base substrate 1 and the thickness of the sixth stacked layer 926 in the direction perpendicular to the base substrate 1 is greater than or equal to 6000 Angstroms, such that the fifth stacked layer 925 has a sufficient thickness to form a sufficient segment difference between the upper surface of the sixth stacked layer 926, which is away from the base substrate 1, and the upper surface of the second conductive sublayer 902, which is away from the base substrate 1, to continue to ensure the reliability that the third stacked layer 923 and the first stacked layer 921 can be separated from each other due to the segment difference, and the reliability that the fourth stacked layer 924 and the second stacked layer 922 can be separated from each other.

[0220] As in Fig. As shown in 13B, the first auxiliary electrode 92, for example, comprises a third stacked section 92c.The third stacked section 92c is stacked on the second conductive sublayer 902 in the direction perpendicular to the base substrate 1, is located on the side of the second conductive sublayer 902 furthest from the base substrate 1, is electrically connected to the first stacked section 92a and the second stacked section 92b through the second conductive sublayer 902, and comprises a seventh stacked layer 927 and an eighth stacked layer 928, which are stacked together in the direction perpendicular to the base substrate 1, wherein the seventh stacked layer 927 and the third stacked layer 923 are in the same layer and spaced apart in the direction parallel to the base substrate 1, and the eighth stacked layer 928 and the fourth stacked layer 924 are in the same layer and spaced apart in the direction parallel to the base substrate 1.

[0221] For example, the eighth stacked layer 928 is in direct contact with the second conductive sublayer 902. Similarly, the eighth stacked layer 928 is in direct contact with the first conductive sublayer 90 in a second region TP2, and the orthographic projection of the second region TP2 on the base substrate 1 lies at least partially within the orthographic projection of the edge region PR on the base substrate 1. As in the case of the first region TP1, the eighth stacked layer 928 covers the upper surface of the seventh stacked layer 927 furthest from the base substrate 1 and the side surface that intersects the upper surface of the seventh stacked layer 927, and the edge section of the eighth stacked layer 928 located near the second stacked section 92b covers at least the side surface of the seventh stacked layer 927.an edge of the seventh stacked layer 927 near the second stacked section 92b is covered, so that the edge section of the eighth stacked layer 928 near the second stacked section 92b is able to be in direct contact with the second conductive sublayer 902.

[0222] For example, the seventh stacked layer 927, the third stacked layer 923, and the light-emitting layer 23 are made of the same material and are located in the same layer, and the eighth stacked layer 928, the fourth stacked layer 924, and the second stacked layer 922 are made of the same material and are located in the same layer. In this way, the seventh stacked layer 927, the third stacked layer 923, and the light-emitting layer 23 can be formed by the same process, and the eighth stacked layer 928 and the fourth stacked layer 924 are formed by the same process. The “same process” here can refer to the explanation mentioned above.Similar to the formation of the structure in the first area TP1, in the process of forming the seventh stacked layer 927, the third stacked layer 923 and the light-emitting layer 23 using the same process, the segment difference formed by the fifth stacked layer 925 and the sixth stacked layer 926 can cause the seventh stacked layer 927 to be separated from the third stacked layer 923, and in the process of forming the eighth stacked layer 928, the fourth stacked layer 924 and the second stacked layer 922 using the same process, the eighth stacked layer 928 is separated from the fourth stacked layer 924.

[0223] With reference to Fig. 13B and Fig. 5H is the interlayer insulating layer 105, for example, the fifth insulating layer 105, i.e., the interlayer insulating layer 105 and the fifth insulating layer 105 are located in the same layer and are made of the same material. The fifth insulating layer 105 includes a third auxiliary through-hole V004, and the orthographic projection of the third auxiliary through-hole V004 on the base substrate 1 is located within the orthographic projection of the longitudinal section 81 of the auxiliary electrode lead 8 on the base substrate 1. The second auxiliary through-hole V003 of the second auxiliary unit H2 is connected to the third auxiliary through-hole V004, and the third auxiliary through-hole V004 exposes the second auxiliary through-hole V003.For example, part of the first stacked section 92a of the second auxiliary unit H2 is located in the third auxiliary passage opening V004, and the first area TP1 is located in the third auxiliary passage opening V004; the second stacked section 92b of the second auxiliary unit H2 is located in the third auxiliary passage opening V004; part of the third stacked section 92c of the second auxiliary unit H2 is located in the third auxiliary passage opening V004; and the second conductive sublayer 902 is located at least partially in the third auxiliary passage opening V004, and the second area TP2 is located in the third auxiliary passage opening V004.

[0224] Fig. Figure 14A is a schematic diagram of a portion of layers, including a pixel definition layer and a first electrode, which is shown in Fig. 3A display unit shown; and Fig. Figure 14B is a schematic enlarged view of part P0, which is enclosed by a dashed box in Fig. 14A is displayed, whereby Fig. 14B more layers than in Fig. 14A includes the layers in Fig. Include 3A.

[0225] With reference to Fig. 14A- Fig. 14B and Fig. 5K defines the pixel definition layer 6, the aperture area 60, the aperture area 60 comprises a plurality of pixel apertures located in the display area 111, the plurality of pixel apertures correspond one-to-one to the plurality of subpixels, and the plurality of pixel apertures are the aperture areas of the plurality of subpixels. For example, in each of the plurality of subpixels, the orthographic projection of the pixel aperture on the base substrate 1 is located within the orthographic projection of the first electrode 2 on the base substrate 1. Two adjacent subpixels under the plurality of subpixels of the display unit P are each an upper subpixel and a lower subpixel, and the direction perpendicular to an arrangement direction of the upper subpixel and the lower subpixel is a reference direction.For example, the reference direction is the first direction D1 mentioned above, and the arrangement direction of the upper and lower subpixels is the second direction D2 mentioned above. The following describes, as an example, the case in which the first subpixel P1 serves as the upper subpixel and the third subpixel P3 as the lower subpixel. In the present embodiment, the second subpixel P2 can also serve as the upper subelectrode and the fourth subpixel P4 as the lower subelectrode. Alternatively, in some other embodiments, the upper and lower subpixels can also be arranged along the first direction D1 or along any direction, and the embodiments of the present disclosure impose no restrictions regarding the position and arrangement direction of the upper and lower subpixels.

[0226] With reference to Fig. 14A- Fig. 14B comprises a first electrode 2 of the first subpixel P1, a first edge u21a located near the third subpixel P3, and a second edge u21b that intersects the first edge u21a of the first electrode 2 and is located on a first side of the first edge u21a of the first electrode 2 in the first direction D1, and an opening area of ​​the first subpixel P1 comprising a first edge u61a located near the third subpixel P3 and a second edge u61b that intersects the first edge u61a of the opening area and is located on a first side of the first edge u61a of the opening area in the first direction D1.The distance between the first edge u21a of the first electrode 2 of the first subpixel P1 and the first edge u61a of the aperture area of ​​the first subpixel P1 is a first distance d1, the distance between the second edge u21b of the first electrode 2 of the first subpixel P1 and the second edge u61b of the aperture area of ​​the first subpixel P1 is a second distance d2, and the first distance d1 is greater than the second distance d2, so that in the first subpixel P1 in the first direction D1 the first edge u21a of the first electrode 2 projects further beyond the corresponding edge of the aperture area of ​​the corresponding subpixel in the arrangement direction of the two adjacent subpixels, to ensure that the first electrode 2 of the first subpixel P1 can cover a larger area in the boundary region between the first subpixel P1 and the third subpixel P3 in the second direction D2.Therefore, in the case where the transistor of the pixel circuit is located in the border region between the first subpixel P1 and the third subpixel P3 (e.g., the detection transistor T3 of the first subpixel P1 is located at least partially in the border region), if part of the first electrode 2 lies in the border region, a section of the first electrode 2 of the first subpixel P1 near the border region between the first subpixel P1 and the third subpixel P3 can completely cover at least part of the channel area of ​​the transistor that is located in the border region, thus preventing the performance of the transistor from being affected by light irradiation on the channel area.

[0227] For example, the first distance d1 is the average distance in the first direction D1. For example, the first edge u21a of the first electrode 2 of the first subpixel P1 is essentially parallel to the first edge u61a of the aperture area 60 of the first subpixel P1, and the second edge u21b of the first electrode 2 of the first subpixel P1 is essentially parallel to the second edge u61b of the aperture area 60 of the first subpixel P1. The term "essentially parallel" is not limited to the case of absolute parallelism; each edge of the first electrode of each subpixel and each edge of the aperture area of ​​each subpixel in the present disclosure are not limited to straight line segments, and these edges may contain curved sections, as long as the distance relation mentioned above is satisfied at every position along the first direction D1.

[0228] For example, regarding Fig. 14A- Fig. 14B, the first electrode 2 in each of the plurality of subpixels comprises a first section 21 and a second section 22 spaced apart in the second direction D2, wherein the first section 21 of the first electrode 2 and the second section 22 of the first electrode 2 are connected to the first electrode of the driver transistor, the opening area of ​​the subpixel comprises a first partial opening 601 and a second partial opening 602, the first section 21 of the first electrode 2 covers the first partial opening 601 and the second section 22 of the first electrode 2 covers the second partial opening 602.

[0229] The non-light-emitting area 12A and the display area 11 are arranged in the first direction D1 and are located next to the first subpixel P1 and the third subpixel P3.In the case where an edge of the first section 21 of the first electrode 2 of the first subpixel P1 near the third subpixel P3 serves as the first edge u21a of the first electrode 2 of the first subpixel P1, an edge that intersects with the first edge u21a and lies near the non-light-emitting region 12A of the first section 21 of the first electrode 2 of the first subpixel P1 serves as the second edge u21b of the first electrode 2 of the first subpixel P1, an edge of the first partial aperture 601 of the first subpixel P1 near the third subpixel P3 serves as the first edge u61a of the first partial aperture 601 of the first subpixel P1, and an edge of the first partial aperture 601 of the first subpixel P1 near the non-light-emitting region 12A serves as the second edge u61b serves the aperture area 60 of the first subpixel P1.

[0230] For example, regarding Fig. 14A- Fig. 14B, in the first subpixel P1, the orthographic projection of the channel region T3a of the sensing transistor T3 on the base substrate 1 is located within the orthographic projection of the first electrode 2 on the base substrate 1, for example, the orthographic projection of the channel region T3a of the sensing transistor T3 is located within the orthographic projection of the first section 21 of the first electrode 2 on the base substrate 1; and the first edge u21a of the first electrode 2 of the first subpixel P1 is located on a side of the channel region C3 of the sensing transistor T3 of the first subpixel P1 in the second direction D2 that is close to the third subpixel P3, i.e.The first edge u21a of the first electrode 2 of the first subpixel P1 is located on the outside of channel region C3 of the sensing transistor T3 of the first subpixel P1, to better ensure that the first electrode 2 of the first subpixel P1 can cover at least a portion of channel region C3 of the sensing transistor T3, which is located in the boundary region between the first subpixel P1 and the third subpixel P3. In the third subpixel P3, the first edge d21a of the first electrode 2 of the third subpixel P3 is located on a side of channel region C3 of the sensing transistor T3 of the third subpixel P3 that is close to the first subpixel P1 in the second direction D2, i.e., the first edge d21a of the first electrode 2 of the third subpixel P3 is arranged on the outside of the channel area C3 of the sensing transistor T3 of the third subpixel P3 to better ensure that the first electrode 2 of the third subpixel P3 can cover at least part of the channel area C3 of the sensing transistor T3, which is located in the boundary region between the first subpixel P1 and the third subpixel P3.

[0231] For example, the first pole T3s of the sensing transistor T3 of the first subpixel P1 is located on a side of the second pole T3d away from the third subpixel P3, and the first pole T3s of the sensing transistor T3 of the third subpixel P3 is located on a side of the second pole T3d of the sensing transistor T3 away from the upper sub-electrode;and in the second direction D2, the distance between the first pole T3s of the sensing transistor T3 of the first subpixel P1 and the first pole T3s of the sensing transistor T3 of the third subpixel P3 is smaller than the length of the opening area of ​​the first subpixel P1 in the second direction D2 and smaller than the length of the opening area of ​​the third subpixel P3 in the second direction D2, to ensure that the sensing transistor T3 is located near the boundary between the first subpixel P1 and the third subpixel P3, which is advantageous for reducing the distance between adjacent subpixels in the second direction D2, thereby making the layout of the pixel array more compact and achieving a high PPI.

[0232] It should be noted that the length of the aperture area of ​​the first subpixel P1 in the second direction D2 refers to the length of the first aperture area 601 of the first subpixel P1 in the second direction D2, and the length of the aperture area of ​​the third subpixel P3 in the second direction D2 refers to the length of the first aperture area 601 of the third subpixel P3 in the second direction D2.

[0233] For example, in at least one embodiment, the distance between the first pole T3s of the sensing transistor T3 of the first subpixel P1 and the first pole T3s of the sensing transistor T3 of the third subpixel P3 is less than 1 / 2 the width of the aperture area 60 in order to effectively reduce the distance between adjacent subpixels in the second direction D2, thereby making the layout of the pixel array more compact and achieving a high PPI.

[0234] With reference to Fig. 14A- Fig. 14B and the previous Fig. 6A, for example, the second sampling signal sub-line G2 comprises a ring section, i.e., the third outer ring section R3, wherein a section of the third outer ring section R3 overlapping with the active layer T3a of the sensing transistor T3 of the first subpixel P1 in the direction perpendicular to the base substrate 1, and a section of the third outer ring section R3 overlapping with the active layer T3a of the sensing transistor T3 of the third subpixel P3 in the direction perpendicular to the base substrate 1, respectively, form the gate electrode of the sensing transistor T3 of the first subpixel P1 and the gate electrode of the sensing transistor T3 of the third subpixel P3; and the orthographic projection of the third outer ring section R3 onto the base substrate 1 forms an annular region.and the orthographic projection of the second pole T3d of the sensing transistor T3 of the first subpixel P1 on the base substrate 1 and the orthographic projection of the second pole T3d of the sensing transistor T3 of the third subpixel P3 on the base substrate 1 are both arranged within the annular area, so that the limited space is used effectively to design the positional relationship between the third outer ring section R3 and both the first pole T3s and the second pole T3d of the two sensing transistors T3, which are at least partially located in the boundary area, so that the channel area of ​​the sensing transistor T3 can be covered by the first electrode of the subpixel in which the sensing transistor T3 is located, while achieving a compact structural design, thus taking into account both the performance of the sensing transistor T3 and the improvement of the PPI.

[0235] For example, a first electrode 2 of the third subpixel P3 includes a first edge d21a near the first subpixel P1 and a second edge d21b that intersects the first edge d21a of the first electrode 2 and is located near the non-light-emitting region 12A; an aperture region of the third subpixel P3 includes a first edge d61a near the first subpixel P1 and a second edge d61b that intersects the first edge d61a of the aperture region and is located near the non-light-emitting region 12A; The distance between the first edge d21a of the first electrode 2 of the third subpixel P3 and the first edge d61a of the aperture area of ​​the third subpixel P3 is a third distance d3, the distance between the second edge d21b of the first electrode 2 of the third subpixel P3 and the second edge d61b of the aperture area of ​​the third subpixel P3 is a fourth distance d4,and the third distance d3 is larger than the fourth distance d4, so that in the third subpixel P3, compared to the case in the first direction D1, the first edge of the first electrode 2 lies further beyond the corresponding edges of the opening region of the respective subpixel in the arrangement direction of two adjacent subpixels (as in the second direction D2), to ensure that the first electrode 2 of the third subpixel P3 can cover a larger area in the boundary region between the first subpixel P1 and the third subpixel P3 in the second direction D2. Therefore, in the case where the transistor of the pixel circuit is provided in the boundary region between the first subpixel P1 and the third subpixel P3 (for example, the sensing transistor T3 of the third subpixel P3), the section of the first electrode 2 of the third subpixel P3 near the boundary region between the first subpixel P1 and the third subpixel P3 can cover the channel region of the transistor,which is located in the border area, can be completely covered, thus preventing the transistor's performance from being affected by light exposure to the channel area.

[0236] Here, the edge of the first section 21 of the first electrode 2 of the third subpixel P3 near the first subpixel P1 serves as the first edge d21a of the first electrode 2 of the third subpixel P3, the edge that intersects with the first edge d21a and lies near the non-light-emitting region 12A of the first section 21 of the first electrode 2 of the third subpixel P3 serves as the second edge d21b of the first electrode 2 of the third subpixel P3, the edge of the first partial aperture 601 of the third subpixel P3 near the first subpixel P1 serves as the first edge d61a of the aperture area of ​​the third subpixel P3, and the edge that intersects with the first edge d61a and lies near the non-light-emitting region 12A of the first partial aperture 601 of the third Subpixel P3 serves as the second edge d61b of the opening area of ​​the third subpixel P3.

[0237] For example, as in Fig. As shown in Figure 14B, the first electrode 2 of the first subpixel P1 further comprises a fourth edge u21d opposite the second edge u21b of the first electrode 2, and the aperture area of ​​the first subpixel P1, like the first partial aperture 601, further comprises a fourth edge u61d opposite the second edge u61b of the aperture area. In some embodiments, for example, the first distance d1 is greater than the distance between the fourth edge u21d of the first electrode 2 of the first subpixel P1 and the fourth edge u61d of the aperture area of ​​the first subpixel P1, to ensure that the channel area of ​​the sensing transistor T3 of the first subpixel P1, which lies at least partially at the boundary, is covered and shielded by the first electrode. In some embodiments, the same may apply to the third subpixel P3, i.e.,The first electrode 2 of the third subpixel P1 further has a fourth edge d21d opposite the second edge d21b of the first electrode 2, and the aperture area of ​​the third subpixel P3, like the first partial aperture 601, further has a fourth edge d61d opposite the second edge d61b of the aperture area. For example, in some embodiments, the third distance d3 is greater than the distance between the fourth edge d21d of the first electrode 2 of the third subpixel P3 and the fourth edge d61d of the aperture area of ​​the third subpixel P3, in order to ensure that the channel area of ​​the detection transistor T3 of the third subpixel P3, which lies at least partially in the boundary region, is covered and shielded by the first electrode.

[0238] With reference to Fig. 14B, Fig. 3A and Fig. For example, in the first subpixel P1, the first pole T3s of the sensing transistor T3 is electrically connected to the active layer T3a of the sensing transistor T3 via an upper through-hole V51; and in the third subpixel P3, the first pole T3s of the sensing transistor T3 is electrically connected to the active layer T3a of the sensing transistor T3 via a lower through-hole V52. Referring to Fig. 14B and Fig. 4C The orthographic projection of the first edge u21a of the first electrode 2 of the first subpixel P1 on the base substrate 1 overlaps at least partially with the orthographic projection of the edge of the interpass hole V33 on the base substrate 1, located away from the third subpixel P3 in the second direction D2. This means that the first electrode 2 of the first subpixel P1 extends along the second direction D2 to the edge of the interpass hole V33 located away from the third subpixel P3 in the second direction D2. Furthermore, the orthographic projection of the first edge d21a of the first electrode 2 of the third subpixel P3 on the base substrate 1 overlaps at least partially with the orthographic projection of the edge of the interpass hole V33 on the base substrate 1, located away from the first subpixel P1 in the second direction D2.The first electrode 2 of the third subpixel P3 extends along the second direction D2 to the edge of the through-hole V33 located away from the first subpixel P1 in the second direction D2. This ensures that the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3 each cover the bordering channel area C3 of the sensing transistor T3 of the corresponding subpixel. Furthermore, it ensures sufficient space between the first electrode 2 of the first subpixel P1 and the second electrode 2 of the third subpixel P3, and that the edge of the first electrode is aligned with the edge of the through-hole, thereby reducing manufacturing difficulty and improving the manufacturing yield of the display substrate.

[0239] For example, as in Fig. As shown in Figure 14B, the continuous and one-piece electrode IAL traverses a space between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3 along the second direction D2, and two ends of the continuous and one-piece electrode IAL, which are opposite each other in the second direction D2, are located on two sides of the space between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3 in the second direction D2.

[0240] For example, in Fig. 14B, Fig. 5B and Fig. As shown in Figure 5E, the interconnection section 43 is located on the side of the active layer T3a of the sensing transistor T3 that is close to the base substrate 1; for example, the interconnection section 43 is located in the first conductive layer 100, as shown in Figure 5E. Fig. 5A is shown; furthermore, the orthographic projection of the intermediate connection section 43 on the base substrate 1 is at least partially within the orthographic projection of the space between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3 on the base substrate 1; and the sensing signal line S is connected to the intermediate connection section 43 through the first connection through-hole V31, and the active layer IAL, which is continuous and one-piece, is connected to the intermediate connection section 43 through the second connection through-hole V32.The first interconnection through-hole V1 and the second interconnection through-hole V3, corresponding to the intermediate interconnection section 43, are provided in the space between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3, and the first interconnection through-hole V31, the second interconnection through-hole V32 and the intermediate through-hole V33, which are located in the boundary region between the adjacent upper subpixel and the lower subpixel in the pixel array, are neatly arranged so that the edge of the first electrode is aligned with the edge of the through-hole, thereby reducing the manufacturing difficulties and improving the manufacturing yield of the display substrate.

[0241] For example, as in Fig. As shown in Figure 14B, the orthographic projection of the first edge u21a of the first electrode 2 of the first subpixel P1 on the base substrate 1 overlaps at least partially with both the orthographic projection of an edge that is away from the third subpixel P3 in the second direction D2, of the first connecting hole V31 on the base substrate 1 and with the orthographic projection of an edge that is away from the third subpixel P3 in the second direction D2, of the second connecting hole V32; and the orthographic projection of the first edge d21a of the first electrode 2 of the third subpixel P3 on the base substrate 1 overlaps at least partially both with the orthographic projection of the edge that is away from the first subpixel P1 in the second direction D2, of the second connecting through hole V32 on the base substrate 1 and with the orthographic projection of the edge,the first electrode 2 of the first subpixel P1 extends along the second direction D2 to the edge of the first connection through V31 that is farther from the lower subpixel and extends to the edge of the second connection through V32 that is farther from the lower subpixel. The first electrode 2 of the third subpixel P3 extends along the second direction D2 to the edge of the first connection through V31 that is farther from the upper subpixel in the second direction D2 and extends to the edge of the second connection through V32 that is farther from the upper subpixel in the second direction D2. In this way, the intermediate through V33, the first connection through V31 and the second connection through V32,Those located in the border area between the adjacent upper subpixel and the lower subpixel in the pixel arrangement are neatly arranged, thereby reducing manufacturing difficulties and improving the manufacturing yield of the display substrate.

[0242] For example, as in Fig. As shown in Figure 14B, the third distance d3 and the first distance d1 are both greater than the width in the second direction D2 of the space between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3. The width in the second direction D2 of the space between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3 refers to the distance between the first edge u21a of the first electrode 2 of the first subpixel P1 and the first edge d21a of the first electrode 2 of the third subpixel P3; for example, the distance is the average value of the distances between the two at different positions along the first direction D1.Therefore, it can be ensured that the third distance d3 and the first distance d1 are sufficiently large, thus ensuring that the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3 can completely cover the channel area C3 of the detection transistor T3 of the first subpixel P1 and the channel area C3 of the detection transistor T3 of the third subpixel P3, respectively.

[0243] For example, as in Fig. As shown in Figure 14B, the first electrode 2 of the first subpixel P1 still has a third edge u22c located away from the third subpixel P3, and the first partial aperture 601 of the first subpixel P1 still has a third edge u62c located away from the third subpixel P3. The distance between the third edge u22c of the first electrode 2 of the first subpixel P1 and the third edge u62c of the first partial aperture 601 of the first subpixel P1 is a fifth distance d5, and the first distance d1 is greater than the fifth distance d5. In each subpixel, for example, in the first subpixel P1, the orthographic projections of the driver transistor T1 and the data write transistor T2 on the base substrate 1 are located within the orthographic projection of the aperture area of ​​the subpixel in which the driver transistor T1 is located, on the base substrate.For example, the orthographic projections of the driver transistor T1 and the data write transistor T2 of the first subpixel P1 on the base substrate 1 lie within the orthographic projections of the second aperture 602 and the first aperture 601 of the first subpixel P1 on the base substrate 1,and the orthographic projections of the driver transistor T1 and the data write transistor T2 of the third subpixel P3 on the base substrate 1 each lie within the orthographic projection of the second aperture 602 of the third subpixel P3 and the orthographic projection of the first aperture 601 of the third subpixel P3 on the base substrate 1; and in the first subpixel P1, the distance between the channel area C1 of the driver transistor T1 and the third edge u62c of the second partial aperture 602 is greater than the distance between the channel area C3 of the sensing transistor T3 and the first edge u61a of the first partial aperture 601. Therefore, the channel area C1 of the driver transistor T1 is covered and shielded by the corresponding first electrode, and the first distance d1, which is greater than the fifth distance d5, can further ensure,that the channel area C3 of the detection transistor T3 of the first subpixel P1 is covered and shielded by the corresponding first electrode.

[0244] Here, an edge of the second section 22 of the first electrode 2 of the first subpixel P1, which is away from the third subpixel P3, serves as the third edge u22c of the first electrode 2 of the first subpixel P1, and an edge of the second partial aperture 602 of the first subpixel P1, which is away from the third subpixel P3, serves as the third edge u62c of the aperture area of ​​the first subpixel P1.

[0245] For example, the distance between the third edge of the first electrode 2 of the third subpixel P3, located away from the first subpixel P1, and the third edge of aperture area 60 of the third subpixel P3, located away from the first subpixel P1, is a sixth distance d6, and the third distance d3 is greater than the sixth distance d6. Furthermore, in the third subpixel P1, the distance between the channel area C1 of the driver transistor T1 and the third edge d62c of the second partial aperture 602 is greater than the distance between the channel area C3 of the sensing transistor T3 and the first edge d61a of the first partial aperture 601.Therefore, the channel area C1 of the driver transistor T1 is covered and shielded by the corresponding first electrode, and the third distance d3 is larger than the sixth distance d6, which further ensures that the channel area C3 of the sensing transistor T3 of the third subpixel P3 is covered and shielded by the corresponding first electrode.

[0246] Here, an edge of the second section 22 of the first electrode 2 of the third subpixel P3, located away from the first subpixel P1, serves as the third edge d22c of the first electrode 2 of the third subpixel P3, and the edge of the second partial aperture 602 of the third subpixel P3, located away from the first subpixel P1, serves as the third edge d62c of the aperture area of ​​the third subpixel P3.

[0247] Referring to Fig. 5C and Fig. In 14B, for example, the orthographic projection of the data write transistor T2 on the base substrate 1 is also located within the orthographic projection of the opening region on the base substrate 1, so that the orthographic projection of the channel region C2 of the data write transistor T2 on the base substrate 1 lies within the orthographic projection of the opening region on the base substrate 1 and is also covered and shielded by the first electrode. Therefore, the orthographic projections of the channel regions of all transistors of the pixel circuit on the base substrate are all located within the orthographic projections of the first electrodes of the respective subpixels in which they are located on the base substrate. For example, in Fig. 5C and Fig. 14B, in each subpixel of the plurality of subpixels, the orthographic projection of the channel area C1 of the driver transistor T1 on the base substrate 1 is arranged within the orthographic projection of the second section 22 of the first electrode 2 on the base substrate 1; and the orthographic projection of the channel area C2 of the data write transistor on the base substrate 1 is located within the orthographic projection of the first section 21 of the first electrode 2 on the base substrate 1 and is located on the side of the orthographic projection of the channel area C3 of the sensing transistor T3 on the base substrate 1 that is close to the second section 22 of the first electrode 2.

[0248] For example, at least part of the orthographic projection of the detection transistor T3 on the base substrate 1 is located outside the orthographic projection of the opening region on the base substrate 1; for example, at least part of the orthographic projection of the second pole T3d of the detection transistor T3 on the base substrate 1 is located outside the orthographic projection of the opening region on the base substrate 1.In such a design, the first electrode does not need to be too large, while fulfilling the requirement that the first electrode covers and shields the channel areas of all transistors in the pixel circuit of the subpixel in which the first electrode is located, thus ensuring the space between the first electrode of the first subpixel P1 and the first electrode of the third subpixel P3 adjacent to the first subpixel P1, and ensuring that a portion of the sensing transistor T3, which is not necessarily shielded, is located in the space between the first electrode of the first subpixel P1 and the first electrode of the third subpixel P3 adjacent to the first subpixel P1, in order to fully utilize the limited space and achieve a high PPI.

[0249] For example, regarding Fig. 14A- Fig. 14B, the area of ​​the aperture of the third subpixel P3 is larger than the area of ​​the aperture 60 of the first subpixel P1, and the third distance d3 is larger than the first distance d1. For example, the area of ​​the first partial aperture 601 of the third subpixel P3 is larger than the area of ​​the first partial aperture 601 of the first subpixel P1; or the sum of the areas of the first partial aperture 601 and the second partial aperture 602 of the third subpixel P3 is larger than the sum of the areas of the first partial aperture 601 and the second partial aperture 602 of the first subpixel P1.For example, the first subpixel P1 emits red light, the third subpixel P3 emits white light, and the third distance d3 is larger than the first distance d1 to ensure that in both the first subpixel P1 and the third subpixel P3, which is adjacent to the first subpixel P1, the first electrode can block the channel area of ​​the detection transistor located in the boundary area between the first subpixel P1 and the third subpixel P3.

[0250] It should be noted that the embodiment mentioned above introduces each edge of the first electrode of a subpixel and each edge of the opening area of ​​a subpixel by assuming, for example, that the first electrode of a subpixel comprises the first section and the second section, which are spaced apart from each other. However, the embodiments of the present disclosure are not limited to this case; in other embodiments, the first electrode of the subpixel may be a continuous and one-piece structure or may comprise more than two spaced-apart sections. In all cases, the first electrode, the second edge, the third edge, and the fourth edge are determined by considering the entire first electrode as a single, unified structure.

[0251] As in Fig. As shown in Figure 15, at least one embodiment of the present disclosure further provides a display device 1000. As shown in Figure 15, at least one embodiment of the present disclosure further provides a display device 1000. Fig. As shown in Figure 15, the display device 1000 comprises one of the display substrates 10 provided by the embodiments of this disclosure. The display device 1000 can, for example, be a device with a display function, such as a display device with organic light-emitting diodes, a display device with quantum dot light-emitting diodes, etc., or other types of devices. The embodiments of this disclosure do not limit this aspect.

[0252] The structure, function and technical effects of the display device provided by the embodiments of the present disclosure can refer to the corresponding descriptions of the display substrate 10 provided by the embodiments of the present disclosure, and details are not described again here.

[0253] For example, the display device 1000 provided by at least one embodiment of the present disclosure can be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook, a digital photo frame, a navigation device, etc., and the embodiments of the present disclosure are not limited in this respect.

[0254] The above descriptions are only exemplary embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure, and the scope of protection of the present disclosure is determined by the attached claims.

Claims

[1] A display substrate comprising: a base substrate; and a display unit located on the base substrate and comprising a display region and a non-light-emitting region, wherein the display region comprises a subpixel, the subpixel comprises a drive transistor and a light-emitting device, the drive transistor is configured to control the magnitude of a drive current flowing through the light-emitting device, and the light-emitting device is configured to receive the drive current and be driven by the drive current to emit light; the light-emitting device comprises a first electrode and a common electrode, and the common electrode is connected to a common voltage terminal; the display unit includes: an auxiliary electrode line comprising a longitudinal portion located in the display region and a transverse portion located at least partially in the non-light-emitting region, the transverse portion being connected to the longitudinal portion; a first auxiliary electrode located in the non-light-emitting region and electrically connected to the common electrode; and an auxiliary insulating layer comprising a first auxiliary via hole located in the non-light-emitting region and exposing at least a part of the transverse portion, wherein the first auxiliary electrode is connected to the transverse portion through the first auxiliary via hole; the transverse portion, the first auxiliary electrode, and the first auxiliary through-hole form an auxiliary unit, and the display unit comprises a plurality of auxiliary units; the transverse portion of the auxiliary electrode line extends along a first direction, the longitudinal portion of the auxiliary electrode line extends along a second direction intersecting the first direction, and the plurality of auxiliary units are spaced apart in the second direction. [2] The display substrate according to claim 1, wherein the plurality of auxiliary units comprise a first auxiliary unit and a second auxiliary unit, and the first auxiliary unit and the second auxiliary unit are each the one auxiliary unit; and a distance between a first auxiliary through-hole of the second auxiliary unit and the display area in the first direction is greater than a distance between a first auxiliary through-hole of the first auxiliary unit and the display area in the first direction. [3] The display substrate according to claim 2, wherein a length of the transverse portion of the second auxiliary unit in the first direction is greater than a length of the transverse portion of the first auxiliary unit in the first direction. [4] The display substrate according to claim 3, wherein the first auxiliary electrode comprises: a first conductive sublayer connected to the transverse section through the first auxiliary via hole; a first stacked portion electrically connected to the first conductive sub-layer and stacked with the first conductive sub-layer in a direction perpendicular to the base substrate, located on a side of the first conductive sub-layer remote from the base substrate, and comprising a first stacked layer and a second stacked layer stacked with each other in the direction perpendicular to the base substrate, wherein the second stacked layer is located on a side of the first stacked layer remote from the base substrate and is connected to the common electrode; and a second stacked portion stacked with the first conductive sub-layer in the direction perpendicular to the base substrate, located on the side of the first conductive sub-layer remote from the base substrate, and located on a side of the first stacked portion remote from the base substrate, electrically connected to the first stacked portion through the first conductive sub-layer, and comprising a third stacked layer and a fourth stacked layer stacked with each other in the direction perpendicular to the base substrate, wherein the third stacked layer, the first stacked layer, and a light-emitting layer of the light-emitting device located in the display region are made of the same material, in the same layer, and spaced from each other in a direction parallel to the base substrate, and the fourth stacked layer,the second stacked layer and the common electrode of the light-emitting device located in the display region are spaced apart from each other in the same layer and in the direction parallel to the base substrate; and, the first stacked layer of the first stacked portion of the second auxiliary unit comprises an intermediate via hole, and the second stacked layer of the first stacked portion of the second auxiliary unit is electrically connected to the first conductive sub-layer of the second auxiliary unit through the intermediate via hole. [5] The display substrate according to claim 1, wherein an area of a planar shape of a first auxiliary through-hole of the second auxiliary unit is larger than an area of a planar shape of a first auxiliary through-hole of the first auxiliary unit. [6] The display substrate according to claim 2, wherein a display unit comprises at least two first auxiliary units and the number of second auxiliary units is greater than or equal to one. [7] The display substrate according to claim 6, wherein said one display unit comprises at least three first auxiliary units, and in said second direction at least one second auxiliary unit is located between said at least three first auxiliary units. [8] The display substrate according to claim 6 or 7, wherein the display unit comprises a plurality of sub-pixels arranged in an array, and the array comprises a first pixel row extending along the first direction and a second pixel row extending along the first direction; the first pixel row comprises a first subpixel and a second subpixel arranged adjacent to each other, and the second pixel row comprises a third subpixel and a fourth subpixel arranged adjacent to each other; in a display unit, the at least two first auxiliary units comprise No. 1 first auxiliary unit, No. 2 first auxiliary unit and No. 3 first auxiliary unit; and the No. 1 first auxiliary unit and the No. 2 first auxiliary unit are located in the second subpixel, and the No. 3 auxiliary unit and the second auxiliary unit are located in the fourth subpixel. [9] A display substrate according to claim 8, wherein each subpixel of the display unit comprises: a connection structure electrically connecting a first portion of the first electrode and a second portion of the first electrode and including a connection portion located in the non-light-emitting region; and a first transfer electrode electrically connected to a first terminal of the driver transistor and including a portion located in the non-light-emitting region, wherein the connecting portion in the non-light-emitting region is electrically connected to the portion of the first transfer electrode located in the non-light-emitting region; the first transfer electrode includes: a first transfer portion located in the display region and electrically connected to the first terminal of the driver transistor, wherein a portion of the first transfer electrode located in the non-light-emitting region is a second transfer portion of the first transfer electrode, the second transfer portion is electrically connected to the first transfer portion, the connecting portion and the second transfer portion are each located in different layers, and the connecting portion in the non-light-emitting region is electrically connected to the second transfer portion through a first through-hole; and the No. 1 first auxiliary unit and the No. 2 first auxiliary unit are each located on two opposite sides of the connecting portion of the second sub-pixel in the second direction, and the No. 3 first auxiliary unit and the second auxiliary unit are each located on two opposite sides of the connecting portion of the fourth sub-pixel in the second direction. [10] The display substrate according to claim 9, wherein, in the second direction, the second auxiliary unit is located on a side of the connecting portion of the fourth subpixel close to a junction of the fourth subpixel and the second subpixel; or, in the second direction, the second auxiliary unit is located on a side of the connecting portion of the fourth subpixel remote from the junction of the fourth subpixel and the second subpixel. [11] The display substrate according to any one of claims 8 to 10, wherein an area of a planar shape of the first auxiliary through-hole of the first auxiliary unit is larger than an area of a planar shape of the first through-hole. [12] A display substrate according to any one of claims 1 to 11, wherein in an auxiliary unit of the at least one auxiliary unit, the first auxiliary electrode comprises: a first conductive sublayer connected to the transverse section through the first auxiliary via hole; a first stacked portion electrically connected to the first conductive sub-layer and stacked with the first conductive sub-layer in a direction perpendicular to the base substrate, located on a side of the first conductive sub-layer remote from the base substrate, and comprising a first stacked layer and a second stacked layer stacked with each other in the direction perpendicular to the base substrate, wherein the second stacked layer is located on a side of the first stacked layer remote from the base substrate and is connected to the common electrode; and a second stacked section stacked with the first conductive sub-layer in the direction perpendicular to the base substrate, located on the side of the first conductive sub-layer remote from the base substrate, and located on a side of the first stacked section remote from the base substrate, electrically connected to the first stacked section through the first conductive sub-layer, and comprising a third stacked layer and a fourth stacked layer stacked with each other in the direction perpendicular to the base substrate, wherein the third stacked layer and the first stacked layer are made of the same material, in the same layer, and spaced from each other in a direction parallel to the base substrate, and the fourth stacked layer and the second stacked layer are made of the same material,in the same layer and spaced apart in the direction parallel to the base substrate. [13] The display substrate according to claim 12, wherein the second stacked layer is electrically connected to the common electrode and is in contact with the first conductive sub-layer; the first stacked layer is in contact with the first conductive sub-layer; and the second stacked layer includes a top portion covering an upper surface of the first stacked layer remote from the base substrate, and a side portion covering a side surface of the first stacked layer that intersects with the upper surface of the first stacked layer, and the side portion is in contact with the first conductive sub-layer. [14] The display substrate according to claim 13, wherein the second stacked portion further comprises: a fifth stacked layer located between the first conductive sublayer and the third stacked layer; and a sixth stacked layer located between the fifth stacked layer and the third stacked layer, wherein the fifth stacked layer and the sixth stacked layer are stacked with the first conductive sub-layer, the third stacked layer, and the fourth stacked layer in a direction perpendicular to the base substrate and are electrically connected to each other, and both the fifth stacked layer and the sixth stacked layer are spaced from the first stacked layer and the second stacked layer in a direction parallel to the base substrate; an orthographic projection of the sixth stacked layer on the base substrate comprises a central region and an edge region surrounding the central region, and an orthographic projection of the fifth stacked layer on the base substrate overlaps with the central region and does not overlap with the edge region; and the second stacked layer is in contact with the first conductive sublayer in a first region and an orthographic projection of the first region on the base substrate lies at least partially within an orthographic projection of the edge region on the base substrate. [15] The display substrate according to claim 14, wherein the light-emitting device further comprises a first electrode and a light-emitting layer located in the display region, the light-emitting layer being interposed between the first electrode and the common electrode, and the first electrode comprises a first electrode sub-layer, a second electrode sub-layer, and a third electrode sub-layer sequentially stacked in the direction perpendicular to the base substrate and along a direction from a position close to the base substrate to a position away from the base substrate;and the first conductive sublayer of the first auxiliary electrode and the first electrode sublayer are made of the same material and in the same layer, the first stacked layer and the light-emitting layer form a continuous and integral structure, the second stacked layer and the common electrode form a continuous and integral structure, the third stacked layer and the light-emitting layer are made of the same material and in the same layer, the fourth stacked layer, the second stacked layer, and the common electrode are made of the same material and in the same layer, the fifth stacked layer and the second electrode sublayer are made of the same material and in the same layer, and the sixth stacked layer and the third electrode sublayer are made of the same material and in the same layer.; [16] A display substrate according to any one of claims 1 to 15, wherein the display unit further comprises: a second auxiliary electrode located in the display area and electrically connected to the common electrode; and the auxiliary insulating layer further comprises a second auxiliary via hole located in the display region and exposing at least a part of the longitudinal portion of the auxiliary electrode line, and the second auxiliary electrode is connected to the longitudinal portion of the auxiliary electrode line through the second auxiliary via hole. [17] The display substrate according to claim 16, wherein the second auxiliary electrode comprises: a second conductive sublayer connected to the longitudinal portion of the auxiliary electrode line through the second auxiliary through-hole; a first stacked portion electrically connected to the second conductive sub-layer of the second auxiliary electrode and stacked in a direction perpendicular to the base substrate, located on a side of the second conductive sub-layer of the second auxiliary electrode remote from the base substrate, and comprising a first stacked layer and a second stacked layer stacked on top of each other in the direction perpendicular to the base substrate, wherein the second stacked layer of the second auxiliary electrode is arranged on a side of the first stacked layer of the second auxiliary electrode remote from the base substrate and is connected to the common electrode; and a second stacked portion stacked on the second conductive sub-layer of the second auxiliary electrode in the direction perpendicular to the base substrate, located on the side of the second conductive sub-layer of the second auxiliary electrode remote from the base substrate and located on a side of the first stacked portion of the second auxiliary electrode remote from the base substrate, electrically connected to the first stacked portion of the second auxiliary electrode through the second conductive sub-layer, and comprising a third stacked layer and a fourth stacked layer stacked together in the direction perpendicular to the base substrate, wherein the third stacked layer of the second auxiliary electrode and the first stacked layer of the second auxiliary electrode are made of the same material, in the same layer, and spaced apart from each other in a direction parallel to the base substrate,and the fourth stacked layer of the second auxiliary electrode and the second stacked layer of the second auxiliary electrode are made of the same material, in the same layer, and spaced apart from each other in the direction parallel to the base substrate. [18] The display substrate according to claim 17, wherein the second stacked layer of the second auxiliary electrode is connected to the common electrode and is in contact with the second conductive sub-layer of the second auxiliary electrode. [19] The display substrate according to any one of claims 1 to 15, wherein the transverse portion of the auxiliary electrode line extends along a first direction and the longitudinal portion of the auxiliary electrode line extends along a second direction intersecting with the first direction; the display substrate further comprises: a first power supply line connected to a first voltage terminal and configured to supply a first power supply voltage different from a common voltage to the subpixel, and including a longitudinal portion extending along the second direction as a whole, wherein the longitudinal portion of the first power supply line and the longitudinal portion of the auxiliary electrode line are spaced apart in the first direction and are respectively located at a first edge of the display area in the first direction and at a second edge, opposite to the first edge, of the display area in the first direction; and a region between an edge of the longitudinal section of the first power supply line remote from the longitudinal section of the auxiliary electrode line and an edge of the longitudinal section of the auxiliary electrode line remote from the longitudinal section of the first power supply line is the display region. [20] A display device comprising the display substrate according to any one of claims 1 to 15.

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