Semiconductor device and power conversion device

Abstract

In a semiconductor device (100) that drives and controls a semiconductor element (10), a current control unit (1) is provided to supply a current with a pulse shape between a control terminal (G) and a negative electrode terminal (S) of the semiconductor element (10). A peak detection circuit (5) detects a peak value of a voltage between the control terminal (G) or the negative electrode terminal (S) and a reference potential during a current supply period through the current control unit (1). A temperature estimation unit (7) calculates an estimated temperature of the semiconductor element based on an output voltage of the peak detection circuit (5), which is sampled by a voltage detection unit (6).The time control unit (3) causes the current control unit (1) to operate in order to provide the current supply period during at least one of the following: an on period after which the semiconductor element switches to the on state; and an off period after which the semiconductor element switches to the off state.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor device and a power conversion device. STATE OF THE ART

[0002] In a power converter that uses a power semiconductor element, such as an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET), an increase in the density of the current flowing through the power semiconductor element has been propagated for miniaturization.

[0003] Increasing the current density, however, increases the energy loss of the power semiconductor element and leads to a temperature rise within the element. The power semiconductor element has a maximum permissible operating temperature, determined by the properties of its semiconductor materials and other factors. If the temperature exceeds this maximum, thermal drift can occur, potentially leading to its destruction. For this reason, temperature management has become increasingly important in power semiconductors in recent years.

[0004] For managing the temperature of the power semiconductor element described above, a method is known in which a temperature sensor, such as a thermistor, is attached to a fin or the like for cooling the power semiconductor element in order to indirectly estimate the temperature of the power semiconductor element. However, since the thermal time constant between the power semiconductor element and the fin is generally large, this method may not be able to measure rapid changes in the temperature of the power semiconductor element due to a load change within a short time.

[0005] One of the methods for solving this problem is disclosed in Japanese patent application no. 2020-72569 (PTL1). In this method, information indicating a relationship between a change in the gate voltage over time during a switching operation of the semiconductor device and the temperature of a power semiconductor element is stored in advance, and the temperature of the power semiconductor element is estimated from the point in time at which the gate voltage increases. LIST OF CAPLETS PATENT LITERATURE

[0006] PTL 1: Japanese Disclosure Document No. 2020-72569 BRIEF DESCRIPTION OF THE INVENTIONAL PROBLEM

[0007] However, the technique disclosed in PTL1 requires a high-precision measurement mechanism and a high-speed processor to measure the time it takes for the gate voltage to rise, and by providing such a measurement mechanism, a miniaturization of the power module can be limited.

[0008] The present disclosure was made in view of the aforementioned problems, and one objective of the present disclosure is to provide a semiconductor device that drives and controls a power semiconductor element and has the function of estimating a temperature of the power semiconductor element without requiring a high-accuracy measuring mechanism and a high-speed processor. SOLUTION TO THE PROBLEM

[0009] According to one aspect of the present disclosure, a semiconductor device that drives and controls a semiconductor element includes a driver circuit, a current control unit, a timing control unit, a peak detection circuit, a voltage detection unit, and a temperature estimation unit. The semiconductor element has a positive electrode terminal, a negative electrode terminal, and a control terminal, wherein a drive voltage is applied to the control terminal to control a current flowing between the positive and negative electrode terminals. The driver circuit supplies the drive voltage to the control terminal to switch the semiconductor element between an on state and an off state. The current control unit is provided to conduct a current with a pulse shape between the control terminal and the negative electrode terminal.The timing unit controls the point in time when current is supplied by the current control unit. The peak detection circuit outputs a peak value of an input voltage, where the input voltage is a potential difference of the control terminal or the negative electrode terminal with respect to a reference potential during a current supply period by the current control unit. The voltage detection unit samples an output voltage of the peak detection circuit. The temperature estimation unit calculates an estimated temperature of the semiconductor element based on a detection voltage by the voltage detection unit. The timing unit causes the current control unit to operate to provide the current supply period during at least one of the following: an on-period, after which the semiconductor element transitions to the on-state; and an off-period, after which the semiconductor element transitions to the off-state. ADVANTAGEOUS EFFECTS OF THE INVENTION

[0010] According to the present disclosure, it is possible to provide a semiconductor device capable of estimating the temperature of a semiconductor element without a high-speed measuring mechanism and a high-speed processor, based on a peak value of a voltage between a control terminal or a negative electrode terminal and a reference potential when a current is supplied between the control terminal and the negative electrode terminal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A is a configuration diagram illustrating an example of a power module according to a first embodiment. Fig. 1B is a circuit diagram that shows a configuration example for a power control unit in Fig. 1A illustrates. Fig. 2A is a circuit diagram that shows a first example of a connection position of the in Fig. 1B describes the illustrated power control unit. Fig. 2B is a circuit diagram that shows a second example of the connection position of the in Fig. 1B describes the illustrated power control unit. Fig. Figure 3 is a configuration diagram showing a modification of the power module in Fig. 1A illustrates. Fig. 4 is a circuit diagram that shows a configuration example for a Fig. 1A describes an illustrated peak detection circuit. Fig. Figure 5 is a time diagram for describing a temperature estimation method by a semiconductor device according to the first embodiment. Fig. Figure 6 is a circuit diagram describing a configuration of a peak detection circuit according to a modification of the first embodiment. Fig. Figure 7 is a time diagram for describing a temperature estimation method by a semiconductor device according to the modification of the first embodiment. Fig. Figure 8 is a circuit diagram that describes a first configuration example for a peak detection circuit according to a second embodiment. Fig. Figure 9 is a circuit diagram describing a second configuration example for the peak detection circuit according to the second embodiment. Fig. Figure 10 is a time diagram for describing a temperature estimation method by a semiconductor device according to a third embodiment. Fig. Figure 11 is a configuration diagram illustrating an example of a power module according to a fourth embodiment. Fig. Figure 12 is a time diagram describing a method for estimating the thermal resistance and thermal impedance by a semiconductor device according to the fourth embodiment. Fig. Figure 13 is a flowchart describing a process for calculating the thermal resistance and thermal impedance of the semiconductor device according to the fourth embodiment. Fig. Figure 14 is a block diagram illustrating a configuration of a power conversion system in which a power conversion device according to the present embodiment is used with a semiconductor element mounted thereon. DESCRIPTION OF EXECUTION FORMS

[0011] Embodiments of the present disclosure are described in more detail below with reference to the drawings. In the following description, the same reference numerals are used for identical or corresponding parts in the drawings, and their descriptions are not repeated. First embodiment.

[0012] Fig. Figure 1A is a configuration diagram illustrating an example of a power module 101 according to a first embodiment. Fig. 1B is a circuit diagram that shows a configuration example for a current control unit 1 in Fig. Figure 1A illustrates the configuration of the power module 101. The configuration is described below with reference to... Fig. 1A and Fig. 1B described.

[0013] As in Fig. As illustrated in Figure 1A, the power module 101 includes a power semiconductor element 10 and a semiconductor device 100 that drives and controls the power semiconductor element 10. The semiconductor device 100 controls the switching of the power semiconductor element 10 and measures the element temperature of the power semiconductor element 10.

[0014] The power semiconductor element 10 includes a positive electrode terminal (drain) D, a negative electrode terminal (source) S, and a control terminal (gate) G. A main current Imt, which flows between the positive electrode terminal D and the negative electrode terminal S, is controlled by a drive voltage applied to the control terminal G.

[0015] The power semiconductor element 10 can be any type of MOSFET, IGBT, metal-semiconductor field-effect transistor (MESFET), bipolar transistor, or the like. A case where the power semiconductor element 10 is a MOSFET is described below as an example. Materials such as SiC, GaN, Ga₂O₃, diamond, or the like can be used for the power semiconductor element 10.

[0016] The semiconductor device 100 includes a gate drive unit 4, a current control unit 1, a gate wiring unit 2, a timing control unit 3, a peak detection unit 5, a voltage detection unit 6, and a temperature estimation unit 7. Here, the gate drive unit 4 includes a driver circuit 42 as a drive control unit, which is connected to and drives the power semiconductor element 10, and a main control unit 41, which controls the driver circuit 42.

[0017] The control terminal G of the power semiconductor element 10 is connected to the driver circuit 42 via the resistor element 21, which is provided in a gate wiring unit 2. The gate wiring unit 2 provides a series of loop wires that connect the control terminal G and the negative electrode terminal S of the power semiconductor element 10 to the driver circuit 42. In the example from Fig. 1A the resistor element 21 is connected between the driver circuit 42 and the control terminal G of the power semiconductor element 10.

[0018] The current control unit 1 is connected to the driver circuit 42 and, through the driver circuit 42, supplies current to a path formed between the control terminal G and the negative electrode terminal S of the power semiconductor element 10. As shown in Fig. As illustrated in Figure 1B, the current control unit 1 includes a pulse current supply 20 for supplying a pulsed current. More precisely, the pulse current supply 20 includes, for example, a current supply 11 that supplies a constant current and a current control switch 12 that is connected in parallel to the current supply 11. The current control switch 12 is switched on or off by the time control unit 3 in response to a switch control signal 31.

[0019] When the current control switch 12 is switched from on to off, the pulse current supply 20 begins to output current, and when the current control switch 12 is switched from off to on, the pulse current supply 20 stops outputting current. In this way, the output current of the current control unit 1 is pulse-controlled in response to the switching on and off of the current control switch 12.

[0020] Various types of commonly known current sources can be used as the current supply 11. For example, a bipolar transistor, a current mirror, or a current supply provided at the output side of a constant voltage source with a resistor can be used. Additionally, depending on the circuit configuration, the current supply 11 can be a current source that delivers a current or a current sink that receives a current. A switching element that operates at a relatively high speed, for example, a MOSFET, can be used as the current control switch 12. If measurement accuracy is required, an ultrafast device, such as a high electron mobility transistor (HEMT) made of GaN, can be used as the current control switch 12.

[0021] As in Fig. As illustrated in Figure 1B, one end of each of the power supply 11 and the current control switch 12 is connected to a reference potential node 90, which applies a reference potential. Here, the reference potential is, for example, a control ground of the driver circuit 42 or a power supply voltage of the driver circuit 42.

[0022] The other end of each from the power supply 11 and the current control switch 12 is electrically connected directly or indirectly to the control terminal G or the negative electrode terminal S of the power semiconductor element 10. If it is connected indirectly, the other end of each from the power supply 11 and the current control switch 12 is connected to the control terminal G (Gate) or the negative electrode terminal S (Source) of the power semiconductor element 10 via a semiconductor switching element or a resistor, which is another electronic component mounted on the driver circuit 42.

[0023] Fig. 2A and Fig. 2B illustrate circuit diagrams that describe a first and a second example of a connection position of the current control unit 1.

[0024] In particular, illustrates Fig. 2A is a configuration example in which the other end described above (the side not connected to the reference potential node 90) of each of the power supply 11 and the current control switch 12 is electrically connected to the negative electrode terminal S of the power semiconductor element 10. Fig. 2A the current control unit 1 is connected to a position where the current control unit 1 supplies the current from the side of the negative electrode terminal S of the power semiconductor element 10.

[0025] On the other hand, it illustrates Fig. 2B is a configuration example in which the other end of each of the power supply 11 and the current control switch 12 described above is electrically connected to the control terminal G of the power semiconductor element 10. Fig. 2B, the current control unit 1 is indirectly connected to the control terminal G via the driver circuit 42, thus connecting the current control unit 1 to a position where the current control unit 1 supplies the current from the side of the control terminal G of the power semiconductor element 10. A case in which the other end of each of the current supply 11 and the current control switch 12 is electrically connected to the negative electrode terminal S of the power semiconductor element 10 ( Fig. 2A), is described below as an example.

[0026] With renewed reference to Fig. 1A The timing unit 3 outputs a switch control signal 31 to control the current control switch 12 of the current control unit 1 based on a command 412 from the main control unit 41 of the gate driver unit 4. As described above, the main control unit 41 controls the driver circuit 42 and the timing unit 3. For example, a functional device such as a microprocessor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA) is used as the main control unit 41.

[0027] Although the timing control unit 3 and the gate control unit 4 are in Fig. To explicitly distinguish between the components 1A for the purpose of description, the timing control unit 3 can be contained within the main control unit 41. Furthermore, the driver circuit 42 and the timing control unit 3 can be mounted on the same substrate, or the main control unit 41, the driver circuit 42, the timing control unit 3, and the current control unit 1 can be mounted together on the same substrate.

[0028] The peak detection circuit 5 is connected to the driver circuit 42 to detect a voltage (voltage between terminals) between both ends of the power supply 11. A configuration example of the peak detection circuit 5 is described below.

[0029] The voltage detection unit 6 detects an output voltage of the peak detection circuit 5. The temperature estimation unit 7 calculates an estimated temperature of the power semiconductor element 10 from an output voltage value of the peak detection circuit 5 at a given time, based on the detection value of the voltage detection unit 6 and control information 32 from the timing control unit 3. For example, the temperature estimation unit 7 calculates a resistance value of the power semiconductor element 10 from the output voltage value described above, as described below. Furthermore, the temperature estimation unit 7 generates temperature information 71, which includes the estimated temperature.The estimated temperature is obtained by converting the newly measured resistance value of the power semiconductor element 10 into a temperature by comparison with conversion data that provide a relationship between resistance values ​​and element temperatures, which are predetermined on the basis of the measured values ​​from preliminary experiments on an actual machine.

[0030] Temperature information 71 is fed back into the main control unit 41. If the temperature exceeds a predetermined value, the main control unit 41 can change a drive pattern to reduce the loss of the power semiconductor element and can also output warning information to a host system. Although the main control unit 41 and the temperature estimator 7 are in Fig. 1A, which are illustrated as separate components for the purpose of description, may contain the function of the temperature estimation unit 7 in the main control unit 41.

[0031] Fig. Figure 3 is a configuration diagram showing a modification of the power module 101 in Fig. 1A illustrates this. The in Fig. The illustrated performance module 101 differs from the performance module 101 in 3. Fig. 1A because the resistive element 21 in the gate wiring section 2 is connected to a wire (source wire) connected to the negative electrode terminal S, and not to a wire (gate wire) connected to the control terminal G. In this case as well, the resistive element 21 causes a voltage drop in the gate wiring section 2 according to the current flowing between the control terminal G and the negative electrode terminal S. The other configurations in Fig. 3 are the same as those in Fig. 1A, and thus the same or corresponding parts are identified by the same reference numerals, and their description is not repeated. Although the resistive element 21 in each of the Fig. 1A and Fig. As is clearly illustrated outside the power semiconductor element 10 in Figure 3, a gate resistor may not be provided outside the power semiconductor element 10 depending on the application. [Temperature estimation method for power semiconductor element]

[0032] A method for estimating the temperature of the power semiconductor element 10 by the semiconductor device 100 in Fig. 1A is described in more detail below. Fig. Figure 4 illustrates a configuration example of the peak detection circuit 5 in Fig. 1A. Fig. Figure 5 illustrates a time diagram to describe a temperature estimation method by the semiconductor device 100, in which the Fig. 4 illustrated peak detection circuit 5 is arranged.

[0033] As in Fig. As illustrated in Figure 4, the peak detection circuit 5 can, for example, be configured by a detection circuit with a diode 51, a capacitor 52, and a discharge switch 53. The diode 51 is connected between an input node Nx and a node Ny, with a direction from input node Nx to node Ny being a forward direction. The capacitor 52 is connected between node Ny and a node Ns. The potential of node Ns is also referred to as Vss. Node Ns has the same potential as that of the reference potential node 90. Fig. 1B and the like, and an input voltage Vx of the peak detection circuit 5 corresponds to a potential difference of node Nx with respect to node Ns, i.e. a potential difference of the control terminal G or the negative electrode terminal S with respect to the reference potential.

[0034] The discharge switch 53 is connected in parallel with the capacitor 52 and is switched on and off by the timing unit 3 in response to a switch control signal 35. The discharge switch 53 can, for example, be configured with a MOSFET with a small leakage current to keep the potential of node Ny in an off state.

[0035] As described above, the peak detection circuit 5 is connected to receive the voltage (voltage between terminals) between both ends of the power supply 11. Therefore, when the current control unit 1 is connected in the manner described above, the voltage between the terminals is measured. Fig. 2A is connected, the input node Nx and the node Ns of the peak detection circuit 5 are directly or indirectly connected to the negative electrode terminal S of the power semiconductor element 10 and the reference potential node 90. That is, the input node Nx is electrically connected to the negative electrode terminal S of the power semiconductor element 10. On the other hand, if the current control unit 1 is connected in the manner from Fig. Since 2B is connected, the input node Nx and the node Ns of the peak detection circuit 5 are directly or indirectly connected to the control terminal G of the power semiconductor element 10 and the reference potential node 90. That is, the input node Nx is electrically connected to the control terminal G of the power semiconductor element 10.

[0036] If the voltage at input node Nx is higher than the voltage at node Ny, the input voltage Vx is passed to node Ny in the peak detection circuit 5 and held by capacitor 52. Conversely, if the voltage at input node Nx is lower than the voltage at node Ny, the input voltage Vx is not passed to node Ny, and thus capacitor 52 holds and outputs a peak value of a voltage previously passed through diode 51.

[0037] In Fig. 4 corresponds to the input node Nx as an example of the “first node”, the node Ny as an example of the “second node” and the diode 51 as an example of the “first diode”.

[0038] The voltage detection unit 6 samples and detects a voltage (Vdet) across capacitor 52, i.e., the output voltage of the peak detection circuit 5. In the following description, the voltage across capacitor 52, which corresponds to the input voltage of the voltage detection unit 6, is also referred to as a detection voltage Vdet. When the discharge switch 53 is in the on state, the detection voltage Vdet is cleared (Vdet = Vss).

[0039] The temperature estimation method using the semiconductor device 100 ( Fig. 1A) according to the first embodiment, with reference to Fig. 5 described. In Fig. Figure 5 displays waveforms up to time t2, voltage waveforms and signal waveforms during a normal switching operation where no temperature measurement is performed, and displays waveforms after time t2, voltage waveforms and signal waveforms where a temperature measurement is performed along with the switching operation. First, the operation of the semiconductor device 100 during a normal switching operation is described. (How the semiconductor device works during normal operation)

[0040] The driver circuit 42 outputs a positive potential Vcc, which is higher than a threshold voltage, and a potential Vee (normally a negative potential or zero potential) that is less than or equal to the threshold voltage, to control the power semiconductor element 10. Specifically, based on a driver input signal 411 from the main control unit 41, the driver circuit 42 applies a positive potential Vcc or a negative or zero potential Vee as a gate voltage to the control terminal G of the power semiconductor element 10. As a result, the driver circuit 42 switches the power semiconductor element 10 between the on and off states.

[0041] During normal operation, the timing control unit 3 controls the current control switch 12 of the current control unit 1 so that it is always in the on state. Therefore, if an enhancement-type element, such as an n-type MOSFET, is used as the current control switch 12, a constant high (H) logic signal is fed in as the switch control signal 31 of the current control switch 12. If a depletion-type element, such as a p-type MOSFET, is used as the current control switch 12, a constant low (L) logic signal is fed in as the switch control signal 31.

[0042] In particular, with reference to Fig. 5, that when the driver input signal 411 changes from a low level to a high level at time t0 during a switch-on process to the driver circuit 42, the positive potential Vcc is applied to the control terminal G of the power semiconductor element 10, causing the gate voltage Vgs to rise. At time t0x, after a rise period with a time constant that depends on the resistance value of the resistor element 21 and the element capacitance of the power semiconductor element 10, the gate voltage Vgs reaches the positive potential Vcc.

[0043] At this point, the gate current supplied by the driver circuit 42 to the power semiconductor element 10 flows directly to the reference potential node 90 via the current control switch 12. Additionally, the current from the power supply 11 also flows to the reference potential node 90 via the current control switch 12 and is not supplied to the driver circuit 42. It should be noted that a Miller period is observed during the rise period between time t0 and time t0x, in which the gate voltage Vgs has a constant value.

[0044] In the event of a turn-off process, the driver input signal 411 changes from a high (H) level to a low (L) level at time t1. As a result, a negative or zero potential Vee is applied to the control terminal G of the power semiconductor element 10, causing the gate voltage Vgs to drop. At time t1x, after a fall-off period similar to the turn-on process, the gate voltage Vgs reaches a negative or zero potential Vee. As in the turn-on process, the gate current flows through the current control switch 12 to the reference potential node 90. The current from the power supply 11 flows through the current control switch 12 to the reference potential node 90 and is not supplied to the driver circuit 42. It should be noted that the Miller cycle is also observed during the fall-off period from time t1 to t1x. (Temperature measurement during a single period)

[0045] Next, the operation of semiconductor device 100 during temperature measurement is described. The temperature is measured over a period in which the gate voltage is stable, except for the rising and falling periods. The stable period includes a period in which the gate voltage is stable at a positive potential Vcc (hereinafter referred to as the "on period") and a period in which the gate voltage is stable at a negative or zero potential Vee (hereinafter referred to as the "off period").

[0046] First, a temperature measurement during the one-period is described. With reference to Fig. At time t2, the driver input signal 411 changes from a low level to a high level, corresponding to a switch-on command time. The switch control signals 31 and 35 are switched from a high level to a low level at time t3 after a specific delay period from time t2. This delay time can be easily set as a time constant of the resistance value of the resistor element 21 and the capacitance of the power semiconductor element 10, or longer.

[0047] If the delay time is short, a gate drive current from the driver circuit 42 also affects the detection voltage of the voltage detection unit 6, which impacts the accuracy of the temperature measurement. If, on the other hand, the delay time is long, the time t4 at which the switch control signal 31 returns to the high level is close to the time t5 at which the switch-off process begins. Consequently, a gate drive current from the driver circuit 42 also affects the detection voltage of the voltage detection unit 6, which impacts the accuracy of the temperature measurement.

[0048] When the switch control signal 31 is switched to the L level (time t3), the current control switch 12 is opened. Fig. 1B is switched off. Consequently, the current from the power supply 11 does not flow to the reference potential node 90, but to the power semiconductor element 10. That is, the current control unit 1 supplies the current between the control terminal G and the negative electrode terminal S. During this current supply period, the input voltage Vx to the peak detection circuit 5 is expressed by the following expression (1). [Expression 1] Vx(t−t3)=(Rg+Rgint)⋅lg+t−t3cdieIg|t≥t3

[0049] In expression (1), Vx(t - t3) represents the input voltage of the peak detection circuit 5 at time t after time t3. gintThis is a value of a gate resistance (gate internal resistance) in the power semiconductor element 10. The gate internal resistance is generated by a material, such as polysilicon, on the power semiconductor element 10. Alternatively, the gate internal resistance includes a parasitic resistance due to a gate wiring pattern on the power semiconductor element 10.

[0050] R g In expression (1), the resistance across the driver circuit 42 and the value of the resistive element 21 represent a different resistance component than the resistance caused by the power semiconductor element 10 itself. Normally, R g provided by a resistor externally attached to the power semiconductor element 10, which makes the selection of resistance values ​​and temperature characteristics relatively simple. C die represents a capacity value that is determined by the gate side (in the case of Fig. 2A) or the source page (in the case of Fig. 2B) of the power semiconductor element 10 is considered. I g represents a supply current from the power supply 11.

[0051] In the power control unit 1 ( Fig. 1B and the like) when the current control switch 12 is switched off, current is fed from the power supply 11 to the power semiconductor element 10. As a result, the input voltage Vx according to expression (1) is fed into the peak detection circuit 5.

[0052] In particular, a constant voltage V0 = (R is initially applied g + R gint ) · I ggenerated by multiplying the total value of the gate internal resistance of the power semiconductor element 10, the resistor element 21 and the resistance at the driver circuit 42 by the value of the current supplied by the power supply 11, as represented by the first term on the right-hand side of expression (1).

[0053] Furthermore, after time t3, when the current control switch 12 is switched off, the input voltage Vx increases due to the charging of the parasitic capacitance of the power semiconductor element 10 according to (t - t3) · I g / C die , as represented by the second term on the right-hand side of expression (1). If the parasitic capacity C die is constant and the current I gSince the current supply 11 has a constant value, the input voltage Vx of the peak detection circuit 5 increases linearly. Because the change in the input voltage Vx is transmitted to the capacitor 52 via node Ny during the process of the input voltage Vx increasing, the detection voltage Vdet of the voltage detection unit 6 changes equivalently to the input voltage Vx after time t3 (Vdet = Vx).

[0054] When the switch control signal 31 is returned from the L level to the H level at time t4, the current control switch 12 in the current control unit 1 is turned on, so that current flows from the power supply 11 to the reference potential node 90. Simultaneously, an electrical charge stored in the parasitic capacitance of the power semiconductor element 10 is also discharged. When the current control switch 12 is turned on, the voltage of the power supply 11 between the terminals becomes zero. Therefore, the input voltage Vx of the peak detection circuit 5 becomes zero at time t4 (Vx = 0).

[0055] On the other hand, the switch control signal 35 is held at the low level, and thus the discharge switch 53 in the peak detection circuit 5 is held in the off state. Therefore, after time t4, the detection voltage Vdet of the voltage detection unit 6 is held at the voltage value at time t3.

[0056] If the switch control signal 35 changes from the L level to the H level at time t4x, the discharge switch 53 in the peak detection circuit 5 ( Fig. 4) switched on, and thus the voltage of capacitor 52 becomes zero. In response, the detection voltage Vdet of the voltage detection unit 6 changes to zero (Vdet = 0). It should be noted that the time t4x can also be synchronized with a switch-off command time described below, at which the driver input signal 411 changes from the high level to the low level.

[0057] As a result, during a temperature measurement during the one-period, an input voltage Vx(t4) described below is measured by the voltage detection unit 6 as a detection voltage Vdet during one period from time t4 to t4x. [Expression 2] Vx(t4)=(Rg+Rgint)⋅Ig+t4−t3cdie⋅Ig|t4≥t3

[0058] If current I ghas a constant value and a time difference between time t3 and t4 (i.e., a length of the current supply period) is constant, is a value obtained by subtracting the second term on the right-hand side, which corresponds to the charging voltage of the parasitic capacitance, from Vx(t4), i.e., V0 = (R g + R int ) · I g in the first term on the right-hand side, is obtained from the resistance value (R g + R int ) dependent. It should be noted that the temperature dependence of the parasitic capacitance is usually low and therefore the charging voltage of the parasitic capacitance can be considered a constant value.

[0059] Therefore, the resistance value (R) g + R gint ) using a voltage value V1 of the detection voltage Vdet at time t4, the time difference between time t3 and t4 and a known I g, which corresponds to the output current of the power supply 11, can be calculated.

[0060] Here, each of the resistance values ​​R g and R gint a temperature dependence is observed. If each of the resistance values ​​R g and R gint exhibiting a linear temperature dependence, the resistance values ​​R g (T) and R gint at temperature T as R g (T) ≈ R g 0 · (1 + K1 · T) and R gint (T) ≈ R gint 0 · (1 + K2 · T) represented using a temperature coefficient K.

[0061] If the temperature dependence of the resistance R g , apart from the gate internal resistance of the power semiconductor element 10, is sufficiently smaller than the temperature dependence of the gate internal resistance R gint of the power semiconductor element 10, i.e., when ΔR g < ΔR gint(K1 < K2) for a difference in resistance values ​​caused by the temperature T represents the temperature dependence of the resistance value (R). g + R gint ) represents the temperature dependence of the gate internal resistance of the power semiconductor element 10. As described above, K1 < K2 can be achieved by selecting the resistor element (e.g., resistor element 21) attached externally to the power semiconductor element 10 with a resistance value R g to be provided, achieved.

[0062] Therefore, the estimated temperature of the power semiconductor element 10 can be calculated by using the resistance value (R) obtained by the calculation described above. g + R gint) is compared with calibration data that represent the relationship between resistance values ​​and temperatures and were recorded in advance. The calibration data described above can be acquired, for example, by measuring the resistance value (R). g + R gint ) is obtained in a similar manner to that described above when the power module 101 is installed in a thermostatic bath and the element temperature of the power semiconductor element 10 is changed from the outside.

[0063] If it is difficult to acquire calibration data, a rate of change (temperature coefficient K2) of the gate internal resistance value R is used. gint Information about the temperature is captured in advance, indicating the relationship between temperatures and resistance values ​​of the power semiconductor element 10, and the calculation is performed using the calculated resistance value (R). g + R gint) and the temperature coefficient K2 (K2 > K1), which were recorded in advance, were carried out, which allows the temperature of the power semiconductor element 10 to be calculated.

[0064] In a case where each of the output currents (I g ) the current supply 11 and the time difference between time t3 and t4 (length of the current supply period by the current control unit 1) is kept constant, only the resistance value (R) g + R gint ) as a variable in response to the temperature change of the power semiconductor element 10 at the detection voltage Vdet. Therefore, the information specifying the relationship between temperatures and resistance values ​​of the power semiconductor element 10 can also be preset to calculate the estimated temperature directly from the detection voltage Vdet or V0, which is extracted from the detection voltage Vdet without specifying the resistance value (R). g + R gintto calculate. (Temperature measurement during off-period)

[0065] Next, the temperature measurement during the off-time is described. Fig. 5 switches when the driver input signal 411 switches from the high level to the low level at time t5, which corresponds to the turn-off command time, the switch control signal 31 switches from the high level to the low level at time t6, after a certain delay period has elapsed from time t5. As described above, this delay time can be easily set as a time constant of the resistance element 21 and the capacitance of the power semiconductor element 10, determined by the resistance value, or longer.

[0066] When the switch control signal 31 changes from the H level to the L level at time t6, the current control switch 12 of the current control unit 1 ( Fig. 1B and the like) are switched off. Consequently, the current from the power supply 11 does not flow to the reference potential node 90, but to the power semiconductor element 10. That is, the current control unit 1 supplies the current between the control terminal G and the negative electrode terminal S, and the current supply period is provided during the off period.

[0067] When the current control switch 12 is switched off and current is fed from the power supply 11 to the power semiconductor element 10, the input voltage Vx of the peak detection circuit 5 changes according to the preceding expression (1). Note that time t3 in expression (1) is replaced by time t6.

[0068] Thus, similar to the situation described above after time t3, in the current supply period provided after time t6, the input voltage Vx of the peak detection circuit 5 and the detection voltage Vdet of the voltage detection unit 6 are also a sum of the constantly generated voltage V0 = (R g + R gint ) · I g and (t - t6) · I g / C die , which is the charging voltage of the parasitic capacitance of the power semiconductor element 10, and increases due to the charging of the parasitic capacitance with an elapsed time from time t6. That is, the behavior of the input voltage Vx and the detection voltage Vdet after time t6 is the same as after time t3.

[0069] Similar to the measurement during the one-period, when the switch control signal 31 changes from the L level to the H level at time t7, the current control switch 12 in the current control unit 1 is turned on, and thus the input voltage Vx of the peak detection circuit 5 becomes zero (Vx = 0). On the other hand, the discharge switch 53 in the peak detection circuit 5 is held off until time t7x, at which the switch control signal 31 changes from the L level to the H level. Therefore, after time t7, the detection voltage Vdet of the voltage detection unit 6 is held at the voltage value at time t7.

[0070] Therefore, the resistance value (R) g + R gint ), as described in relation to the one-period, using a voltage value V2 of the detection voltage Vdet from time t7 to t7x, a time difference between time t6 and t7 (length of the current supply period) and a known I g, which corresponds to the output current of the power supply 11, can also be calculated in the off period.

[0071] As described above, the semiconductor device 100 can be designed such that the temperature dependence of the resistance value R g , which is not the gate internal resistance of the power semiconductor element 10, sufficiently smaller than the temperature dependence of the gate internal resistance value R gint of the power semiconductor element 10, the estimated temperature of the power semiconductor element 10 by comparing the resistance value (R) g + R gint ), which is obtained by calculation, using calibration data that represent the relationship between resistance values ​​and pre-recorded temperatures. Alternatively, as described above, the temperature of the power semiconductor element 10 can also be calculated using the temperature coefficient K2 (K2 > K1) of the gate internal resistance value R.gint , which was obtained in advance, and the calculated resistance value (R) g + R gint ) will be calculated.

[0072] Furthermore, as described in relation to the one-period, in a case where each of the output current (I) g ) the current supply 11 and the time difference between time t6 and t7 (length of the current supply period by the current control unit 1) is kept constant, the estimated temperature can also be calculated directly from the detection voltage Vdet or V0, which is extracted from the detection voltage Vdet, without the resistance value (R g + R gint to calculate.

[0073] In the example from Fig. 5. The time at which the switch control signal 31 shifts from the high level to the low level (the time at which current is supplied from power supply 11) is synchronized with the time at which the switch control signal 35 shifts from the high level to the low level (corresponding to the time at which voltage detection begins). However, a certain time difference between these times can also be provided.

[0074] Furthermore, as in Fig. Figure 5 illustrates that the length of time t3 to t4x and the length of time t6 to t7x (i.e., the length of the current supply period) required for temperature measurement during the on-period and off-period are obtained by subtracting the period length required for the on / off switching of the current control switch 12 and the period length required for the on / off switching of the discharge switch 53 from the length of the on-period or off-period during the circuit and can be set, for example, to approximately several microseconds to several hundred microseconds. [Effect of the first embodiment]

[0075] As described above, the power module 101 according to the embodiment measures a peak voltage between the control terminal G or the negative electrode terminal S and the reference potential node 90 when current I gCurrent is injected from the power supply 11 into a path between the control terminal G and the negative electrode terminal S during the on-period or off-period of the power semiconductor element 10, enabling it to stably estimate the temperature of the power semiconductor element 10. The time for the start of the current injection can be determined as a time after the elapsed delay time from the rise or fall time of the driver voltage, where the delay time is simply set as a time constant of the gate resistance and the element capacitance, or a time longer than or equal to the time constant. Modification of the first embodiment.

[0076] One modification of the first embodiment describes a modification of a configuration of the peak detection circuit 5.

[0077] Fig. Figure 6 is a circuit diagram describing a configuration for a peak detection circuit 5 according to the modification of the first embodiment. In the modification of the first embodiment, the peak detection circuit 5 has the following features: Fig. 6 illustrated configuration in the semiconductor device 100 in Fig. 1A up.

[0078] As in Fig. Figure 6 illustrates that in the peak detection circuit 5, according to the modification of the first embodiment, the discharge switch 53 is configured in the circuit configuration shown in Figure 6. Fig. 4 is replaced by a resistance element 54. That is, in the modification of the first embodiment, an on / off control of the discharge switch 53 is unnecessary, which leads to the simplified configuration of the peak detection circuit 5.

[0079] Fig. Figure 7 is a time diagram for describing a temperature estimation method by a semiconductor device according to the modification of the first embodiment.

[0080] With reference to Fig. 7 In the modification of the first embodiment, a voltage waveform of the capacitor 52 in the peak detection circuit 5 changes, and thus a waveform of the detection voltage Vdet of the voltage detection unit 6 changes from that in the first embodiment ( Fig. 5) Since the other signal waveforms and voltage waveforms in Fig. 7 like those in Fig. Since there are 5, the detailed description of each will not be repeated.

[0081] In Fig. 7. The capacitor 52 is discharged by the resistive element 54 from time t4 during the on-period and from time t7 during the off-period, whereby the current control switch 12 of the current control unit 1 is switched off in response to the switching control signal 31. As a result, the detection voltage Vdet gradually decreases according to an RC time constant determined by a capacitance value of the capacitor 52 and a resistance value of the resistive element 54.

[0082] In the modification of the first embodiment, the time of sampling the voltage value for calculating the resistance value (R) g + R gint ) in relation to the in Fig. 7. The detection voltage Vdet is set as illustrated, so that the elapsed time from time t4 or t7 is constant.

[0083] As a result, the influence of the discharge of capacitor 52 can be eliminated and a change in the voltage V0 = (R g+ R gint ) · I g The voltage caused by the temperature change of the power semiconductor element 10 can be extracted. It should be noted that the voltage detection unit 6 in the first embodiment ( Fig. 5) preferably detect voltage values ​​V1 and V2 by sampling the detection voltage Vdet simultaneously with or immediately after time t4 or t7.

[0084] Thus, in the modification of the first embodiment, in which the peak detection circuit 5 has the simplified configuration, the temperature of the power semiconductor element 10 can also be kept stable during the on-period or the off-period of the power semiconductor element 10, similar to the first embodiment.

[0085] It should be noted that the RC time constant described above in the peak detection circuit 5 must be set such that the capacitor 52 is discharged within one period (e.g., half a switching cycle) that is defined by a switching cycle (period length from time t0 to t2 in Fig. 7) of the power semiconductor element 10 is determined. For example, the capacitor 52 and the resistor element 54 are preferably designed such that the discharge of the capacitor 52 is completed in several microseconds to several hundred microseconds.

[0086] In contrast, in the peak detection circuit 5 according to the first embodiment, the detection voltage Vdet is kept constant after times t4 and t7. Therefore, it can be expected that a simple detector, which is slow with respect to its response time, can be used to construct the voltage detection unit 6 more economically than the modification of the first embodiment. Second embodiment.

[0087] A second embodiment describes a further modification of the configuration of the peak detection circuit 5.

[0088] Fig. Figure 8 is a circuit diagram that describes a first configuration example for a peak detection circuit according to the second embodiment.

[0089] As in Fig. Figure 8 illustrates that the peak detection circuit 5, according to the first configuration example of the second embodiment, includes in addition to the one shown in Fig. The configuration illustrated in Figure 4 also includes an operational amplifier 55. The operational amplifier 55 is connected between the input node Nx and the diode 51 (anode).

[0090] The operating amplifier 55 is connected via a voltage follower connection and transmits the voltage of the input node Nx to the anode of the diode 51. Therefore, the input voltage Vx, which is the same as in the first embodiment, is applied to the diode 51. Consequently, the detection voltage Vdet through the voltage detection unit 6 is the same as in the first embodiment, and the temperature of the power semiconductor element 10 can be maintained stably during the on-period or off-period of the power semiconductor element 10 using the same method as in the first embodiment.

[0091] In the circuit configuration in Fig. 4. A portion of the current flows from the current control unit 1, i.e., the supply current (I). g Current from the power supply 11 flows between the input node Nx and the node Ns, which are connected in parallel to the power supply 11, and is used to charge the capacitor 52. Therefore, the accuracy of the temperature estimation may deteriorate due to an error corresponding to the current flowing through the peak detection circuit 5 when the temperature is estimated using the relationship in expression (1) above.

[0092] In contrast, in the circuit configuration in Fig. 8 An input stage with a high impedance is connected to the input node Nx, which prevents the supply current from the power supply 11 from flowing through the peak detection circuit 5. By using an active element, such as an operational amplifier 55, which has a high input impedance in the input stage, to increase the input impedance of the peak detection circuit 5, as described above, almost all of the supply current from the power supply 11 can be directed through the power semiconductor element 10. That is, the operational amplifier 55 corresponds to an example of an "impedance conversion circuit".

[0093] As a result, in the semiconductor device which includes the tip detection circuit according to the first configuration example of the second embodiment, an error in the temperature calculated according to the ratio of expression (1) can be reduced and the accuracy of estimating the temperature of the power semiconductor element 10 can be improved.

[0094] Fig. Figure 9 is a circuit diagram describing a second configuration example for the peak detection circuit according to the second embodiment.

[0095] As in Fig. As illustrated in Figure 9, the peak detection circuit 5 according to the second configuration example of the second embodiment further includes a diode 56 with the same properties as those of diode 51 and an operating amplifier 58 in addition to the one shown in Figure 9. Fig. 8 illustrated configurations (first configuration example).

[0096] Diode 56 is inserted into a feedback path of the operating amplifier 55, which is connected via a voltage follower connection, and thus causes a voltage drop corresponding to that of diode 51. A negative bias voltage (V-) for stable contact of diode 56 in the circuit can be applied to the cathode of diode 56 via a resistor. Diode 56 corresponds to an example of a "second diode".

[0097] With such a configuration, the influence of the voltage drop caused by diode 51 can be eliminated, and the difference between the voltage of node Ny and the output voltage of the operating amplifier 55 (i.e., the voltage of input node Nx) can be reduced. Consequently, the difference between the detection voltage Vdet by the voltage detection unit 6 and the input voltage Vx of the peak detection circuit 5 can be decreased, and thus the accuracy of estimating the temperature of the power semiconductor element 10 can be further improved.

[0098] The operational amplifier 58 is connected between node Ny and the voltage detection unit 6. The operational amplifier 58 is connected via a voltage follower connection and outputs a voltage corresponding to the voltage of node Ny to the voltage detection unit 6 as the detection voltage Vdet. By arranging the operational amplifier 58, the output impedance of the peak detection circuit 5 decreases. Consequently, higher voltage detection accuracy is expected in the voltage detection unit 6. Furthermore, since it is possible to prevent the potential of node Ny from changing due to the influence of the voltage detection unit 6, higher detection accuracy of the detection voltage Vdet can also be achieved from this perspective.

[0099] It should be noted that the operating amplifier 58 is located in the Fig. Figure 8 illustrates that the first configuration example can also be additionally connected between node Ny and the voltage detection unit 6. Furthermore, the operational amplifier 58 corresponds to an example of an "impedance conversion circuit".

[0100] As described above, by using the peak detection circuit according to the second embodiment, the voltage change caused by the temperature change of the power semiconductor element 10 is reflected more clearly in the detection voltage Vdet, and thus the accuracy of estimating the temperature of the power semiconductor element 10 can be further improved. In the configuration examples in the Fig. 8 and Fig. 9 the discharge switch 53 can be used similarly to in Fig. 6 (modification of the first embodiment) can also be replaced by a resistance element 54. Third embodiment.

[0101] A third embodiment describes a modification of the on / off control of the current control switch 12 of the current control unit 1. The first embodiment describes the example in which an off period of the current control switch 12 is provided during each of the on and off periods as a period in which the gate voltage of the power semiconductor element 10 is stable, except for the rise and fall periods. In the third embodiment, however, a plurality of off periods of the current control switch 12 are provided.

[0102] Fig. Figure 10 is a time diagram for describing a temperature estimation method by a semiconductor device according to the third embodiment. Fig. 10 provides a plurality of off-periods of the current control switch 12, i.e., a plurality of current supply periods through the current supply 11, during the off-period of the power semiconductor element 10.

[0103] In the example from Fig. A temperature measurement is performed during the off-period after time t5, during which the power semiconductor element 10 is switched off. Specifically, similar to what is described in Fig. 5, over a period from time t6 to time t7 after the elapse of a certain delay period from time t5, which corresponds to the switch-off command time, the switch control signal 31 is set to the L level and a current supply period is provided by the current control unit 1. As described in the first embodiment, during this current supply period, the current is supplied from the current supply 11 to the power semiconductor element 10 via the gate wiring unit 2, so that the input voltage Vx of the peak detection circuit 5 increases according to the preceding expression (1).

[0104] At time t7, the switch control signal 31 changes from the L level to the H level. During one H-level period of the switch control signal 31, the current control switch 12 in the current control unit 1 is turned on, and both ends of the current supply 11 have the same potential, thus the input voltage Vx becomes zero (Vx = 0).

[0105] After time t7, a low-level period of the switch control signal 31 is again provided for a period from time t8 to t9. Furthermore, at time t9, the switch control signal 31 changes from the low level to the high level, and then the low-level period of the switch control signal 31 is provided again for a period from time t10 to t11.

[0106] During the low-level period of the switch control signal 31 over each of the period from time t8 to t9 and the period from time t10 to t11, the input voltage Vx of the peak detection circuit 5 rises according to the preceding expression (1) similarly to the period from time t6 to t7.

[0107] As described above, the example from Fig. 10 the multitude of low-level periods of the switch control signal 31, such as the periods from time t6 to t7, from time t8 to t9, from time t10 to t11, ..., from time tk-1 to tk, i.e., the multitude of current supply periods provided by the current control unit 1 by switching off the current control switch 12 during the off period. The durations of the low-level periods of the switch control signal 31 are set to be equal to each other. Therefore, the behavior (the waveform) of the input voltage Vx is the same in each of the low-level periods of the switch control signal 31. Therefore, the input voltage Vx has the same voltage value V2 at the end of each of the low-level periods of the switch control signal 31.

[0108] Also in the Fig. Figure 5 illustrates peak detection circuit 5. When the diode 51 is taken out of the line during the off period of the discharge switch 53, the voltage of node Ny actually decreases gradually due to a leakage current of the discharge switch 53 or the like. Fig. Section 10 also highlights a slight decrease in the detection voltage Vdet, which is caused by the gradual decay. For example, Vx becomes zero (Vx = 0) after time t7 and diode 51 is removed from the line, causing the detection voltage Vdet of V2 to gradually decrease.

[0109] Since the low-level period of the switch control signal 31 is provided over the period from time t8 to t9, the input voltage Vx rises similarly to the period from time t6 to t7. Consequently, when the input voltage Vx again becomes higher than the voltage (detection voltage Vdet) of node Ny, the diode 51 is switched on and the detection voltage Vdet can return to V2 at approximately time t7.

[0110] As described above, according to the third embodiment, by repeatedly switching the current control switch 12 on and off and repeatedly providing the multitude of current supply periods, the damping of the output voltage of the peak detection circuit 5, i.e., the detection voltage Vdet of the voltage detection unit 6, can be eliminated. Consequently, a simple detector, which is slow with respect to its response time, can be used as the voltage detection unit 6. It should be noted that this process of switching the current control switch 12 on and off can be repeated over the entire period in which the gate voltage of the power semiconductor element 10 is stable, with the exception of the rise and fall periods, i.e., during the entire off period and the entire on period.

[0111] To simplify the description, Fig. 10 The example where the off-period of the current control switch 12 (current supply period by the current control unit 1) is not provided during the on-period and no temperature measurement is performed. However, a temperature measurement can be performed during both the on-period and the off-period, and a plurality of off-periods of the current control switch 12 (current supply periods by the current supply 11) can be provided in at least one of the temperature measurements.

[0112] Furthermore, in the third embodiment, the reaction delay of the peak detection circuit 5 can also be reduced by repeatedly switching the current control switch 12 on and off several times. In particular, in the Fig. Figure 6 illustrates that the response speed of the peak detection circuit 5 is limited by the RC time constant determined by the capacitor 52 and the resistor 54. If the input voltage Vx does not have enough pulses, the peak value of the input voltage Vx can be higher than the output voltage (detection voltage Vdet) of the peak detection circuit 5. To address this, a variety of pulse waveforms can be provided as the input voltage Vx by repeatedly switching the current control switch 12 on and off, as in the third embodiment. This allows the peak detection circuit 5 to accurately reflect the peak value of the input voltage Vx in the detection voltage Vdet.

[0113] It should be noted that the off-period of the current control switch 12 may not be exactly the same in some cases due to the influence of jitter or similar factors in the control system. If the off-period varies, a change factor other than the temperature of the power semiconductor element 10 is included in the peak value of the input voltage Vx, which raises concerns about a potential impairment of the temperature estimation accuracy. Even in such a case, by providing the off-period of the current control switch 12—that is, the period for measuring the input voltage Vx—within an off-period or on-period, as in the third embodiment, the influence of any error caused by jitter can be averaged out. Consequently, the impairment of the temperature estimation accuracy can be prevented. Fourth embodiment.

[0114] A fourth embodiment describes an example in which the calculated value of the estimated temperature of the power semiconductor element 10, which is calculated in each of the first to third embodiments, is used to calculate a steady-state thermal resistance or a transient thermal resistance of the power semiconductor element 10.

[0115] When calculating the steady-state thermal resistance, the power semiconductor element 10 must be in a thermally steady state (thermal equilibrium). This steady state can be achieved, for example, by passing a specific DC current through the power semiconductor element 10 to generate a specific power loss, as in a power cycle test, which is one of the general reliability tests for power semiconductor elements.

[0116] Alternatively, a pseudo-thermal equilibrium can also be generated by continuously switching the power semiconductor element 10 to control the current flowing through it to a fixed amount. For example, a pseudo-thermal equilibrium can be generated by controlling the current of each power semiconductor element to a fixed amount in a configuration where four power semiconductor elements are used to control one direction of current, such as a full-bridge circuit, or in a configuration where an inductive load or a resistive load is connected to a half-bridge circuit containing two power semiconductor elements.

[0117] Fig. Figure 11 is a configuration diagram illustrating an example of a power module according to the fourth embodiment.

[0118] As in Fig. As illustrated in Figure 11, a power module 103 according to the fourth embodiment further includes a main current detection unit 81 for measuring the main current Imt and a main voltage detection unit 82 for detecting a main voltage (drain-source voltage) Vmt of the power semiconductor element 10 in addition to the configuration of the power module 101 or 102 ( Fig. 1A, Fig. 3) according to the first embodiment. The main current Imt measured by the main current detection unit 81 and the main voltage Vmt detected by the main voltage detection unit 82 are input into the main control unit 41. Thus, the main control unit 41 can calculate a power loss generated in the power semiconductor element 10 using a product of the main voltage Vmt and the main current Imt.

[0119] Fig. Figure 12 is a time diagram describing a method for estimating the thermal resistance and thermal impedance of a semiconductor device according to the fourth embodiment. A Fig. The 12 illustrated control process can, for example, be carried out by the main control unit 41.

[0120] With reference to Fig. 12. The power semiconductor element 10 is switched several times until time t5, so that the thermal equilibrium state described above is established. Then, after time t5, the power semiconductor element 10 is held in the off state.

[0121] During the off-period of the power semiconductor element 10, Vmt is generated and Imt = 0. Conversely, during the on-period of the power semiconductor element 10, Imt is generated, and a finite resistance (on-resistance) is generated in the power semiconductor element 10. Therefore, during the on-period, a power loss (conduction loss) of Pls = Vmt · Imt occurs due to the on-resistance described above. Furthermore, during this period, a period occurs during switching on and off in which Vmt · Imt is not zero, and a power loss (switching loss) of Pls = Vmt · Imt occurs. Due to these power losses, the temperature Tj of the power semiconductor element 10 increases.

[0122] Since the current does not flow through the power semiconductor element 10 after time t5, the temperature Tj of the power semiconductor element 10 gradually decreases according to a thermal impedance between the power semiconductor element 10 and a cooler (not shown) and the cooling capacity of the cooler.

[0123] A time constant for the temperature change at this point in time can be easily estimated from the thermal resistance and thermal capacitance of a heat dissipation path of the power semiconductor element 10. Generally, the time constant described above is approximately several dozen to several hundred microseconds near the power semiconductor element 10. This value is generally close to or longer than the switching cycle of the power semiconductor element 10. In the first to third embodiments described so far, the temperature of the power semiconductor element 10 is assumed to be estimated during the on / off process, and thus the temperature change of the power semiconductor element 10 during the temperature measurement is almost negligible.

[0124] In contrast, in the fourth embodiment, the temperature change of the power semiconductor element 10, which is kept in the off state for a long time, is measured using the method described in the third embodiment, whereby a thermal resistance and a thermal impedance of the power semiconductor element 10 are measured.

[0125] In particular, the current control switch 12 is repeatedly switched on and off, so that a multitude of L-level periods (i.e., current supply periods), each having a predetermined length, are present in the switch control signal 31 after time t6, similar to in Fig. 10 is provided. As described in the first to third embodiments, in each off-period of the current control switch 12 an input voltage Vx, which reflects the temperature Tj at that time, is generated by the current supply from the current control unit 1 (current supply 11).

[0126] Therefore, by detecting the peak value of the input voltage Vx from the detection voltage Vdet for each current supply period in which the current control switch 12 is off, the estimated temperature (the estimated value of Tj) of the power semiconductor element 10 can be calculated at any given time. In the example from Fig. 12 N (N: an integer greater than or equal to 2) temperature measurements are carried out during a period from the first L-level period (from time t6 to t7) to the N-th L-level period (from time tn - 1 to tn).

[0127] Since the power semiconductor element 10 is held in the off state after time t5, it gradually cools down. Therefore, the peak values ​​of the input voltage Vx and the detection voltage Vdet gradually decrease in response to the temperature change of the power semiconductor element 10. To calculate the temperature decrease Tj based on the decrease in the detection voltage Vdet, the peak detection circuit 5 must have a response time that can reflect the decrease in the peak value of the input voltage Vx caused by the decrease in the temperature of the power semiconductor element 10 in the detection voltage Vdet. Therefore, the response time constant of the peak detection circuit 5 is preferably shorter than the thermal time constant of the power semiconductor element 10.

[0128] Fig. Figure 13 is a flowchart describing a process for calculating the thermal resistance and thermal impedance of the semiconductor device according to the fourth embodiment. A Fig. The illustrated series of processes is carried out, for example, by the main control unit 41.

[0129] The main control unit 41 performs the processing at step (hereinafter simply referred to as "S") 110 to S150 when the power semiconductor element 10 is in the thermal equilibrium state described above. Fig. 12. Processing at S110 to S150 is carried out before time t5.

[0130] The main control unit 41 detects the main voltage Vmt (instantaneous value) of the power semiconductor element 10 at S110, which is measured by the main voltage detection unit 82, and detects the main current Imt (instantaneous value) of the power semiconductor element 10 at S120, which is measured by the main current detection unit 81. Since the main voltage Vmt detected at S110 and the main current Imt detected at S120 are measured at the same time, the main control unit 41 calculates the power loss Pls (instantaneous value) generated in the power semiconductor element 10 at S130 from a multiplication of the main voltage Vmt and the main current Imt.

[0131] Until the thermal resistance is calculated, the main control unit 41 determines NO at S140. If the main control unit 41 determines NO at S140, it then performs the processing at S150 to calculate the power loss Plsc for each switching cycle of the power semiconductor element 10. Specifically, the power loss Plsc for each switching cycle is calculated by summing the power loss Pls, which is calculated at S130 within each switching cycle. At S150, the summed value is cleared at the end or beginning of each switching cycle.

[0132] In the example from Fig. 12. A determination of YES at S140 occurs at time t5. Until a YES determination is made at S140, the processing at S110 to S150 is repeated. At S150, a moving average value of power loss Plsc over the last X cycles (X: a predetermined integer greater than or equal to 2) can also be obtained.

[0133] If a determination of JA occurs at S140, the main control unit 41 moves the process to S160 and begins calculating the thermal resistance. At S160, the main control unit 41 determines the power P (W), which is used to calculate a thermal resistance Rth. For example, the power P could be a power loss Plsc in the immediately preceding switching cycle calculated at S150, or the latest moving average of the power loss Plsc if a determination of JA occurs at S140.

[0134] As with reference to Fig. As described in section 12, the main control unit 41 calculates the estimated temperature (the estimated value of Tj) of the power semiconductor element 10 for each L-level period (equal length) of the switch control signal 31 from the detection voltage Vdet, which is obtained as the peak value of the input voltage Vx. Here, as described in section 12, the temperature of the power semiconductor element 10 is calculated from the detection voltage Vdet, which is obtained as the peak value of the input voltage Vx. Fig. 12 described, assuming that a total of N temperature measurements are carried out.

[0135] In S170, the main control unit 41 performs the i-th (i: a natural number from 1 to N) temperature measurement and calculates an estimated temperature T(i) from the detection voltage Vdet at that time. Fig. 12, if i = 1, an estimated temperature T(1) of the power semiconductor element 10 is calculated at time t6 to t7.

[0136] If i ≥ 2, the thermal resistance Rth = ΔT / P at S180 is calculated using a temperature change ΔT(i) = T(i) - T(1) and power P determined at S160. At S180, a thermal resistance Rth(i) is calculated at the i-th temperature measurement (i ≥ 2).

[0137] At S190, the main control unit 41 determines whether the number of measurements i fulfills a predetermined end condition (N). Until the measurement end condition is fulfilled (NO at S190), the thermal resistance Rth(i) calculated at S180 is recorded at S195. Therefore, if the number of measurements i has been reached and the measurement end condition is fulfilled (YES at S190), thermal resistances Rth(2) to Rth(N) have already been recorded. It should be noted that the measurement end condition at S190 can be determined based on the number of measurements or based on the length of time elapsed since a YES determination at S140.

[0138] If the measurement end condition is met (YES at S190), the main control unit 41 can calculate the thermal impedance Zth of the power semiconductor element 10, which includes the cooling system, using the thermal resistances (here Rth(2) to Rth(N)) that were calculated up to that point in response to the time-dependent change in the temperature Tj of the power semiconductor element 10. As described above, the main control unit 41 performs the calculation in Fig. 13 illustrated the control process, which can form an example of a “unit for calculating thermal resistance”.

[0139] To calculate the thermal impedance, it is necessary to adjust the measurement condition at S190 to ensure sufficient cooling time for the power semiconductor element 10. Although the required cooling time depends on the thermal time constant of the power semiconductor element 10's cooling system, it is generally on the order of several seconds to several hundred seconds. Integrating a cooling time of this magnitude into the normal operating mode of a general power electronics device is challenging. However, by using current control or a system shutdown time in an inverter system to keep a power semiconductor element switched off for a certain period, for example, the off state of the power semiconductor element 10 can be maintained for a relatively long period, and the Fig. The process for calculating thermal impedance is illustrated in section 13.

[0140] As described above, according to the fourth embodiment, the thermal resistance Rth of the power semiconductor element 10 can be calculated using the temperature estimation method for the power semiconductor element 10 described in the first to third embodiments. Furthermore, if the off-period (cooling period) of the power semiconductor element 10 can be ensured for temperature measurement, the thermal impedance Zth of the power semiconductor element 10, which includes the cooling system, can be calculated. Fifth embodiment.

[0141] In a fifth embodiment, the power modules 101 to 103 according to the first to fourth embodiments described above are used in a power conversion device. The fifth embodiment describes a case in which the present disclosure is used in a three-phase inverter, although the present disclosure is not limited to a specific power conversion device.

[0142] Fig. Figure 14 is a block diagram illustrating a configuration of a power conversion system in which the power conversion device is used according to the embodiment.

[0143] The in Fig. Figure 14 illustrates a power conversion system comprising a power supply 120, a power conversion device 110, and a load 130. The power supply 120 is a DC power supply and provides DC power to the power conversion device 110. The power supply 120 can be of any type. For example, the power supply 120 can be a DC system, a solar cell, and a storage battery, or it can consist of a rectifier circuit or an AC / DC converter connected to an AC system. Alternatively, the power supply 120 can consist of a DC / DC converter that converts a DC power output from the DC system into a predetermined power level.

[0144] The power conversion device 110 is a three-phase inverter connected between the power supply 120 and the load 130. It converts the DC power supplied by the power supply 120 into AC power and supplies AC power to the load 130. As shown in Fig. As illustrated in Figure 14, the power conversion device 110 includes a main conversion circuit 111 that converts DC power to AC power and delivers the AC power, and a control circuit 112 that outputs a control signal to the main conversion circuit 111 for controlling the main conversion circuit 111.

[0145] Consumer 130 is a three-phase electric motor driven by AC power supplied by the power conversion device 110. Consumer 130 is not limited to a specific application; it is an electric motor that can be attached to various electrical devices, such as an electric motor for a hybrid vehicle, an electric vehicle, a rail vehicle, an elevator, or an air conditioning system.

[0146] The power conversion device 110 is described in detail below. The main conversion circuit 111 includes a switching element and a freewheeling diode (not illustrated), converts DC power supplied by the power supply 120 into AC power by switching the switching element, and supplies the AC power to the load 130. Although there are various specific circuit structures of the main conversion circuit 111, according to the present embodiment, the main conversion circuit 111 can be a two-stage, three-phase full-bridge circuit comprising six switching elements and six freewheeling diodes connected antiparallel to the respective switching elements. At least one of the switching elements of the main conversion circuit 111 is the power semiconductor element 10, which is included in the power module 101 according to one of the first to fourth embodiments described above.The six switching elements are connected in pairs in series to form an upper and a lower arm, and each of the upper and lower arms forms each phase (U-phase, V-phase, W-phase) of the full bridge circuit. The output terminals of the upper and lower arms, i.e., the three output terminals of the main conversion circuit 111, are connected to the load 130.

[0147] Furthermore, as described in the preceding first to fourth embodiments, the semiconductor device 100 (not illustrated), which controls each switching element, is integrated into the power modules 101 to 103, the main conversion circuit 111 includes the semiconductor device 100. The semiconductor device 100 generates a control signal for controlling the switching elements of the main conversion circuit 111 and supplies the control signal to the control electrodes of the switching elements of the main conversion circuit 111. In particular, the control circuit outputs to the control electrode of each switching element a control signal to switch the switching element on and a control signal to switch the switching element off according to a control signal from the control circuit 112, which will be described later.When the switching element is held in an ON state, the control signal is a voltage signal (ON signal) that is greater than or equal to a threshold voltage of the switching element, and when the switching element is held in an OFF state, the control signal is a voltage signal (OFF signal) that is less than or equal to the threshold voltage of the switching element.

[0148] The control circuit 112 controls the switching elements of the main conversion circuit 111 so that the desired power is supplied to the load 130. Specifically, the control circuit 112 calculates a time (on-time) for each switching element of the main conversion circuit 111 to be switched on, based on the power to be supplied to the load 130. For example, the control circuit 112 can control the main conversion circuit 111 by means of pulse width modulation (PWM), which modulates the on-time of the switching element according to the output voltage. The control circuit 112 then outputs a control command (control signal) to the semiconductor device 100 included in the main conversion circuit 111, so that at any given time the on signal is output to the switching element to be switched on and the off signal is output to the switching element to be switched off.The semiconductor device 100 outputs the on signal or the off signal as a control signal to the control electrode of each switching element according to the control signal.

[0149] In the power conversion device according to the present embodiment, any one of the power modules 101 to 103 according to the first to fourth embodiments is used as power module 101, which forms the main conversion circuit 111, thereby improving the reliability of the power conversion device based on the temperature measurement result of the power semiconductor element.

[0150] The present embodiment describes an example in which the present disclosure is used with a two-stage, three-phase inverter. However, the present disclosure is not limited to this and can be used with various power conversion devices. In the present embodiment, the two-stage power conversion device has been described. However, a three-stage or more-stage power conversion device can also be used, or the present disclosure can be used with a single-phase inverter when power is supplied to a single-phase load. In a case where power is supplied to a DC load or the like, the present disclosure can also be used with a DC / DC converter or an AC / DC converter.

[0151] Furthermore, the power conversion device in which the present disclosure is used is not limited to the one described above, which is used for an electric motor serving as a consumer, and can, for example, be used as a power supply device for an electrical discharge machine, a laser beam machine, an induction heater, or a contactless power supply system. In addition, the power conversion device in which the present disclosure is used can also be used as a network protection device for a photovoltaic generation system, a power storage system, or the like.

[0152] In conjunction with the multitude of embodiments described above, for the purpose of confirmation, a combination of features described in the multitude of embodiments described above, including a combination not mentioned in the description, may also originally be provided within the scope if there is no inconsistency or contradiction.

[0153] It is understood that the embodiments disclosed in this document are in every respect illustrative and not limiting. The scope of this disclosure is defined by the content of the claims and not by the above description, and is intended to include any modification that lies within the scope and meaning of the claims. REFERENCE MARK LIST

[0154] 1 Current control unit; 2 Gate wiring unit; 3 Timing control unit; 4 Gate drive unit; 5 Peak detection circuit; 6 Voltage detection unit; 7 Temperature estimation unit; 10 Power semiconductor element; 11 Power supply; 12 Current control switch; 20 Pulsed power supply; 21, 54 Resistor element; 31, 35 Switch control signal; 32 Control information; 41 Main control unit; 42 Driver circuit; 51, 56 Diode; 52 Capacitor; 53 Discharge switch; 55, 58 Operating amplifier; 71 Temperature information; 81 Main current detection unit; 82 Main voltage detection unit; 90 Reference potential node; 100 Semiconductor device; 101 to 103 Power module; 110 Power conversion device; 111 Main conversion circuit; 112 Control circuit; 120 Power supply; 130 Consumer; 411 Driver input signal; 412 Command; D Positive electrode terminal; G Control terminal; Imt Main current (power semiconductor element); Ns, Nx, Ny nodes; S Negative electrode terminal; Vdet Detection voltage;Vgs Gate voltage; Vmt Main voltage (power semiconductor element); Vx Input voltage (peak detection circuit). QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2020-72569

[0006]

Claims

[1] Semiconductor device that drives and controls a semiconductor element, wherein the semiconductor element has a positive electrode terminal, a negative electrode terminal and a control terminal, wherein a drive voltage for controlling a main current flowing between the positive electrode terminal and the negative electrode terminal is applied to the control terminal, wherein the semiconductor device comprises: a driver circuit for supplying the drive voltage to the control terminal to switch the semiconductor element between an on state and an off state; a current control unit provided to conduct a current having a pulse shape between the control terminal and the negative electrode terminal; a timing control unit for controlling a timing of supply of the current by the current control unit; a peak detection circuit for outputting a peak value of an input voltage, the input voltage being a potential difference of the control terminal or the negative electrode terminal with respect to a reference potential in a current supply period by the current control unit; a voltage detection unit for sampling an output voltage of the peak detection circuit; and a temperature estimation unit for calculating an estimated temperature of the semiconductor element based on a detection voltage by the voltage detection unit, wherein the timing control unit causes the power control unit to operate to provide the power supply period during at least one of the following: an on-period after which the semiconductor element changes to the on-state; and an off period after which the semiconductor element switches to the off state. [2] A semiconductor device according to claim 1, wherein the peak detection circuit includes: a first diode having an anode connected to a first node, the first node being electrically connected to the control terminal or the negative electrode terminal; a capacitor connected between a second node connected to a cathode of the first diode and a node supplying the reference potential; and a discharge switch element or a discharge resistor to discharge the capacitor. [3] A semiconductor device according to claim 2, wherein the peak detection circuit further includes an impedance conversion circuit arranged according to at least one of: between the first node and the anode of the first diode; and between the second node and the voltage detection unit. [4] A semiconductor device according to claim 3, wherein the peak detection circuit includes, as the impedance conversion circuit, an operational amplifier connected in a manner of a voltage follower connection between the first node and the anode of the first diode, and the peak detection circuit further includes a second diode inserted into and connected to a feedback path of the voltage follower connection and causing a voltage drop equal to that of the first diode. [5] A semiconductor device according to any one of claims 1 to 4, wherein the timing control unit provides a plurality of power supply periods during at least one of the on-period and the off-period. [6] A semiconductor device according to any one of claims 1 to 5, wherein the timing unit repeatedly provides a plurality of current supply periods within a thermal resistance measuring period in which the semiconductor element is kept off, and the semiconductor device further comprises: a main current detection unit for detecting the main current of the semiconductor element; a main voltage detection unit for detecting a main voltage between the positive electrode terminal and the negative electrode terminal of the semiconductor element; and a thermal resistance calculating unit for calculating a power loss for each switching cycle occurring in the semiconductor element before the thermal resistance measuring period, and calculating a thermal resistance of the semiconductor element based on the calculated power loss and a change in the estimated temperature calculated for each of the plurality of power supply periods. [7] A semiconductor device according to any one of claims 1 to 6, wherein the current control unit is arranged at a position where the current is supplied from the negative electrode terminal side of the semiconductor element. [8] A semiconductor device according to any one of claims 1 to 6, wherein the current control unit is arranged at a position where the current is supplied from the control terminal side of the semiconductor element. [9] A semiconductor device according to any one of claims 1 to 8, wherein the current having a pulse shape has a predetermined amplitude, the power supply period is provided to have a predetermined time duration, and the temperature estimation unit calculates the estimated temperature using a resistance value determined from the detection voltage and the amplitude of the current in the current supply period, and information indicating a predetermined relationship between a temperature of the semiconductor element and the resistance value. [10] Power conversion device comprising: a main conversion circuit comprising the semiconductor device according to any one of claims 1 to 9 and a semiconductor element driven and controlled by the semiconductor device, the main conversion circuit converting and outputting input electrical power, and a control circuit for outputting a control signal for controlling power conversion by the main conversion circuit to the main conversion circuit.

Images