INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD

Abstract

An information processing device (1) comprises an acquisition unit (11) for acquiring a net list of an electrical circuit, and a processing unit (12) for extracting a component name list and a wiring name list from the net list, and creating a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, and a combination list containing an extracted component name obtained by extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list,and output the updated component name list and combination list.,

Description

FIELD OF TECHNOLOGYThe present disclosure relates to an information processing apparatus and an information processing method.BACKGROUND TO THE PRIOR ARTCircuit diagram data indicating an electric circuit designed by computer aided design (CAD) is data including information regarding components and connection information regarding wiring between the components. For example, in Patent Literature 1, a technique of searching circuit diagram data of electric circuits having similar configurations in a database in which circuit diagram data is registered is explained using a circuit matrix in which the electric circuits are represented by a matrix.REFERENCE LISTPATENT LITERATUREPatent Literature 1: JP 2007-128383 ASUMMARY OF THE INVENTIONTECHNICAL PROBLEMA graph network representing an electric circuit by nodes and edges (edges) is created from list information extracted from an electric circuit network list. The list information is information on the components and wirings included in the electric circuit, including a component name list and a wiring name list. In the component name list, the component names of the components included in the electric circuit are set. In the wiring name list, the wiring names of wirings connecting the components are set.The wirings whose wiring names are set in the wiring name list include ground wirings, input wirings, and output wirings in the electric circuit. On the other hand, in the component name list, only component names of circuit components having structural features are set, and elements that give masses, inputs, and outputs aMerkmal that do not have structural features are not included. Accordingly, for conventional list information, it is necessary to define various types of masses, a plurality of inputs, and a plurality of outputs by wiring.On the other hand, for conventional list information, if the circuit has a unique ground or input and output, unless a specific mechanism is provided for each circuit, the ground or input and output cannot be distinguished as different circuit information. An input of a circuit component comprises, for example, a power supply unit or a power supply for the circuit component and further comprises an input for an external signal. As described above, there are various inputs of circuit components, and definition by only wiring names leads to ambiguity in both cases. Therefore, it is difficult to separate both from each other only by the graphene sheet after the electric circuit is converted to the graphene sheet.In order to separate both from each other, information on the number of components or the order of description is necessary on the graph network, and this is usable only when the number of input ports is determined in advance. In a case where the graph network is created without the above information by using list information in which the definitions of ground, input, and output in the circuit components are not appropriate, information deterioration may occur in the graph network. When the information degradation occurs, the original shift map cannot be recovered from the graph network.Incidentally, in the conventional technique described in Patent Literature 1, when a circuit matrix is created from list information in which the definitions of ground, input, and output are not appropriate, information deterioration is expected to occur in the circuit matrix as described above. In this case, even when the circuit matrix is used, there is a possibility that circuit diagram data of similar electric circuits cannot be accurately searched.The present disclosure solves the above problem, and an object of the present disclosure is to provide an information processing apparatus and an information processing method capable of providing list information in which information deterioration caused by conversion of an electric circuit to a graphene network can be suppressed.SOLUTION OF PROBLEMAn information processing apparatus according to the present disclosure includes an acquisition unit to acquire a netlist of an electric circuit, and a processing unit to extract a component name list and a wiring name list from the netlist, and to generate a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, and a combination list including an extracted component name obtained by extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list, and outputting the updated component name list and the combination list.ADVANTAGEOUS EFFECTS OF THE INVENTIONAccording to the present disclosure, a component name list and a wiring name list are extracted from the electric circuit netlist, and a component name list that is updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, a wiring name list that is updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, and a combination list that includes an extracted component name that is obtained by extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list are created, and the updated component name list and the combination list are output. In this way, the information processing apparatus according to the present disclosure outputs the list information in which the ground, the input, and the output in the electric circuit are defined as circuit components, so that it is possible to provide the list information in which information degradation caused by the conversion of the electric circuit to the graphene network can be suppressed.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a block diagram illustrating a configuration example of an information processing apparatus according to a first embodiment. FIG. 2 is a schematic diagram illustrating an example (1) of an electric circuit and a graph network according to the first embodiment. FIG. 3 is a schematic diagram illustrating an example (2) of the electric circuit and the graphene mesh according to the first embodiment. FIGS. 4A and 4B are block diagrams illustrating a hardware configuration for implementing the functions of the information processing apparatus according to the first embodiment. FIG. 5 is a flowchart illustrating an information processing method according to the first embodiment. FIG. 6 is a circuit diagram illustrating an example (1) of an electric circuit. FIG. 7 is a circuit diagram illustrating an example (2) of an electric circuit. FIG. 8 is a circuit diagram illustrating an example (3) of an electric circuit. FIG. 9 is a schematic diagram illustrating a graph network in which nodes are connected by edges. FIG. 10 is a schematic diagram illustrating a graph network in which nodes are connected via wiring nodes. FIG. 11 is a flowchart illustrating data input processing (1) to the graph network in the first embodiment. FIG. 12 is a flowchart illustrating data input processing (2) to the graph network in the first embodiment. FIG. 13 is a flowchart illustrating data input processing ( 3) to the graph network in the first embodiment. FIG. 14 is a graph illustrating an example (1) of a calculation result of inference accuracy by the information processing apparatus according to the first embodiment. FIG. 15 is a graph illustrating an example (2) of a calculation result of inference accuracy by the information processing apparatus according to the first embodiment. FIG. 16 is a block diagram illustrating a configuration example of an information processing apparatus according to a second embodiment. FIG. 17 is a flowchart illustrating an information processing method according to the second embodiment. FIG. 18 is a circuit diagram illustrating an example (4) of an electric circuit. FIG. 19 is a circuit diagram illustrating an example (5) of an electric circuit. FIG. 20 is a schematic diagram illustrating an example (1) of an electric circuit and a graph network according to the second embodiment. FIG. 21 is a schematic diagram illustrating an example (2) of an electric circuit and a graph network according to the second embodiment. FIG. 22 is a schematic diagram illustrating an example (3) of an electric circuit and a graph network according to the second embodiment. FIG. 23 is a graph illustrating an example of a calculation result of inference accuracy by the information processing apparatus according to the second embodiment.DESCRIPTION OF THE EMBODIMENTSFirst EmbodimentFIG. 1 is a block diagram illustrating a configuration example of an information processing apparatus 1 according to a first embodiment. In FIG. 1, an information processing device 1 acquires a netlist of an electric circuit and provides list information in which information deterioration in a graph network of the electric circuit can be suppressed by using the acquired netlist. The graph network of the electric circuit is information representing the electric circuit having a node representing a component and an edge representing a wiring line. The graph network also includes information indicating a feature amount of the node and a feature amount of the edge.In the construction of an electric circuit, a circuit diagram of the electric circuit is designed from a circuit design CAD, information indicating the circuit diagram is passed to a circuit board design CAD, and a circuit board circuit pattern is designed from the circuit board design CAD. The information indicating the circuit diagram passed from the circuit design CAD to the circuit board design CAD is the netlist of the electrical circuit. For example, the information processing device 1 acquires the netlist from the circuit design CAD and outputs the netlist including the list information created using the acquired netlist to a computer on which the circuit board design CAD is installed. In the computer, a printed circuit pattern is designed for the circuit diagram indicated by the input netlist by means of the printed circuit design CAD.The circuit diagram indicated by the netlist includes information indicating a passive component, an active component, an I / O component, and wiring in the electrical circuit. The passive component is a component such as a coil, a capacitor, a resistor, or a diode. The active component is a component such as a power supply, a processor, a random access memory, or a field programmable gate array (FPGA). The I / O component is, for example, an inter-board connector, a power supply connector, and a communication connector. The wiring is a wiring for connecting the above-mentioned components.The power supply itself is not included in the circuit diagram because the circuit diagram shows an electric circuit that operates when power is supplied from the outside or when a control signal of Ethernet (registered trademark) or the like or an analog signal acquired from a sensor is input. The power supply unit is a battery or an accumulator or a commercially available energy source.Note that in the following, it is assumed that at least one ground wiring, an input wiring, and an output wiring are connected to one or more circuit components in the circuit diagram. In addition, the circuit diagram indicated in the netlist does not necessarily need to be in operation, and may be in the middle of the design stage, or may be obtained by extracting only a circuit part that implements some functions of the entire circuit.Although several dozens of types of printing methods such as the TELESIS format, the PADS format and the SCICARDIS format are known in the netlist, each format contains information on the components included in the electrical circuit and the wiring connecting the components. Generally, a circuit diagram includes a ground wiring, an input wiring, and an output wiring. However, there may be no input wiring or output wiring in a circuit diagram that handles electromagnetic waves, heat, or the like that are input or output without wiring. Note that in a case where an electromagnetic wave or heat is converted into an electric signal and an electric signal is converted into an electromagnetic wave or heat, the circuit diagram includes an input wiring through which the electric signal converted from the electromagnetic wave or heat propagates and an output signal through which the electric signal to be converted into an electromagnetic wave or heat propagates. The netlist also contains information about this wiring.In addition, the netlist includes a component name list and a wiring name list. In the component name list, all component names in the netlist are specified. In the wiring name list, all the wiring names in the netlist are set. Also, in the wiring name list, wiring names indicating a ground wiring, an input wiring, and an output wiring in the electric circuit are set, but in the component name list, information indicating a ground, an input, and an output is not set, and only a circuit component having a structural feature such as a semiconductor element (hereinafter, simply referred to as a semiconductor) or a capacitor is set. Thus, even if there are plural types of masses, inputs and outputs in the electric circuit, they cannot be distinguished from the component name list.In this case, in the wiring name list, the ground wiring, the input wiring, and the output wiring must be further classified and defined according to the type of the ground, the input, and the output. For example, when there are a plurality of mass, input, and output types in a certain component, it is necessary to define a plurality of wiring types classified according to the mass, input, and output types also between this component and a component to be connected, and a wiring name list becomes complicated. When an electric circuit is converted into a graph network using list information including a complicated wiring name list, there is a high possibility that information deterioration occurs in the graph network.On the other hand, the information processing device 1 adds component names indicating a ground terminal, an input terminal, and an output terminal to the component name list, and removes the wiring names indicating the ground wiring, the input wiring, and the output wiring from the wiring name list. Then, the information processing device 1 extracts a component name corresponding to the wiring name in the wiring name list from the component names in the component name list, creates a combination list including the extracted component name, and outputs list information including the component name list and the combination list. In this way, in the information processing apparatus 1, even if there are a plurality of ground, input and output types in the electric circuit, they can be defined as individual components. Therefore, it is possible to provide list information in which information deterioration in the graph network of the electric circuit can be suppressed without complicating the list information as is the case in defining a plurality of types of wiring.As illustrated in FIG. 1, the information processing apparatus 1 includes an acquisition unit 11 and a processing unit 12.The acquisition unit 11 executes a first process of acquiring a netlist of the electric circuit. For example, the information processing apparatus 1 is connected to a computer equipped with a circuit design CAD, and the acquisition unit 11 acquires a netlist created using the circuit design CAD from the computer.Moreover, the acquisition unit 11 may acquire a circuit diagram model of an electric circuit that operates in a circuit simulator and convert the circuit diagram indicated by the circuit diagram model into a netlist.That is, the acquisition of the netlist by the acquisition unit 11 includes the acquisition of the netlist by conversion of the shift schedule.The processing unit 12 extracts the component name list and the wiring name list from the netlist, and creates a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, and a combination list including an extracted component name obtained by extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list, and outputs the updated component name list and the combination list. In addition, the processing unit 12 outputs the updated component name list and the combination list in which a component name is replaced with a unique identification number common to each of features of components.Specifically, the processing unit 12 executes a second process to a sixth process.The second process is a process of extracting the component name list and the wiring name list from the netlist acquired by the acquisition unit 11.The third process is a process of adding component names indicating a ground terminal, an input terminal, and an output terminal to the component name list.The fourth process is a process of removing wiring names indicating ground wirings, input wirings, and output wirings from the wiring name list.The fifth process is a process of extracting a component name corresponding to a wiring name in the wiring name list subjected to the fourth process from the component names in the component name list subjected to the third process and creating a combination list including the extracted component name.The sixth process is a process of replacing the component name in the component name list subjected to the third process with the component name in the combination list obtained in the fifth process with a unique identification number common to each of the features of the component, and outputting list information including the component name list and the combination list in which the component name has been replaced with the identification number.FIG. 2 is a schematic diagram illustrating an example (1) of an electric circuit and a graph network, wherein the left diagram of FIG. 2 shows an example of an electric circuit, and the upper and lower diagrams on the right side show a graph network of the electric circuit on the left side. The electric circuit illustrated in FIG. 2 is a circuit including a power supply V, a semiconductor X, an inductance L, a capacitor C, and a resistor R. In the electric circuit, the power supply V, a single terminal of the semiconductor X, the capacitor C, and the resistor R are connected to the ground GND.The power supply V itself is not included in a circuit diagram of an electric circuit that operates with electric power supplied (registered) from the power supply V. Thus, in a netlist representing the circuit diagram, an input terminal powered by the power supply is not set as a circuit component. Moreover, in the component name list included in the power list, electric circuit components such as the semiconductor X, the inductance L, the capacitor C, and the resistor R are set with a functional structure, but a power input or a ground GND without a functional structure is not set.When the component name list in which the power input and the ground GND are not set is used, the graph network on the lower right side is created. In the graph network on the lower right side, there is a node of the semiconductor X, a node of the inductor L, a node of the capacitor C, and a node of the resistor R, but no node of a network input from the power supply V and no node of the ground GND. In the graph network on the lower right side, the power input from the power supply V and the ground GND are defined as wirings.In the electric circuit on the left side, for example, power is supplied (registered) from the power supply V to one terminal of the semiconductor C. Thus, in the graphene mesh on the lower right side, the thick line wiring connected to the node of the semiconductor X is input wiring with respect to the power input from the power supply V.Further, in the electric circuit on the left side, the semiconductor X, the capacitor C, and the resistor R are connected to the ground GND.As indicated by white lines, the ground GND is defined as, for example, a ground wiring between the semiconductor X and the capacitor C, a ground wiring between the semiconductor X and the resistor R, and a ground wiring between the capacitor C and the resistor R. That is, when the power input and the ground GND are not set in the component name list, four types of wirings indicating the power input from the power supply V and the ground GND are defined in the power list.When the original electric circuit can be specified using the netlist obtained by the inverse conversion of the converted graph net to the netlist after the conversion of the netlist of the electric circuit to the graph net, it is determined that there is no information degradation in the graph net.In general, there is no invertibility between the conversion from the netlist to the graph network and the inverse conversion from the graph network to the netlist, and the netlist after the inverse conversion may not be a netlist that can be calculated by the circuit simulator.Thus, the information degradation of the graph network is determined by inputting the graph network to the graph neural network and training the graph neural network to derive the original electrical circuit without performing an inverse conversion from the graph network to the netlist. In the determination of information deterioration using the graph neural network, the process of inverse converting the netlist from the graph network is not performed, so that there is an effect that the above problem does not occur. However, the graph neural network has a problem that the inference results vary. In this case, it is possible to suppress the influence of the variation in the inference results from being small by training the graph neural network having a common network structure a plurality of times and confirming the variation in the inference results by the graph neural network of the trained model.As described above, the determination of the information deterioration using the graphene neural network is an excellent determination method that can achieve a more stable result than in a case where inverse conversion from the graphene network to the netlist is performed.In this case, the graph neural network is a machine learning model (AI) that infers an electric circuit corresponding to a graph network when the graph network is input.If the graph neural network has high accuracy in inferencing the original electric circuit, it is determined that there is little information degradation that occurs when the electric circuit netlist is converted to the graph network.In a case where there are a plurality of types of ground GNDs, inputs, and outputs in an electric circuit, in a graph network obtained by converting a netlist of the electric circuit, the ground GNDs and wirings indicating the inputs and the outputs are classified and defined according to the types of the ground GNDs, the inputs, and the outputs. These wirings are defined under complicated conditions including a relationship to a connected component in addition to information on a classified type. Therefore, the graph neural network needs to be trained including a complicated condition for each wiring, and the inference accuracy with which the graph neural network infers the original electric circuit decreases.On the other hand, the information processing device 1 adds component names indicating the ground terminal, the input terminal, and the output terminal to the component name list included in the electric circuit netlist on the left side, and removes the wiring names indicating the ground wiring, the input wiring, and the output wiring from the wiring name list included in the netlist. Then, the information processing device 1 extracts a component name corresponding to the wiring name in the wiring name list from the component names in the component name list, creates a combination list including the extracted component name, and outputs the component name list and the combination list.In the component name list and the combination list, the power input of the power supply V and the ground GND in the electric circuit on the left side are set as components. Thus, the netlist including the component name list and the combination list is converted to the graphical network on the upper right side. In the graph network, on the lower right side, in addition to the node of the semiconductor X, the node of the inductor L, the node of the capacitor C, and the node of the resistor R, a node of a power input from the power supply V, and a node of the ground GND are set.Since the power input from the power supply V and the ground GND are defined as components, the wiring related to the power input from the power supply V to the semiconductor X in the graphene network on the upper right side does not need to be classified into types of input wirings and is defined as connection between nodes.In addition, the ground GND does not need to be classified into types of ground wiring, and is defined as a connection between nodes. That is, in the graph network on the upper right side, all the wirings in the original electric circuit are defined by one type of wiring between the nodes.Thus, a plurality of types of ground GNDs, inputs, and outputs included in the electric circuit can be distinguished as components. That is, the graph neural network can train the masses GNDs, the inputs, and the outputs in the electric circuit as components, and the accuracy with which the graph neural network interferes with the original electric circuit is improved.FIG. 3 is a schematic diagram illustrating an example (2) of an electric circuit and a graph network, wherein a left diagram of FIG. 3 shows an example of an electric circuit, and the upper and lower diagrams on the right side show a graph network of the electric circuit on the left side. The electric circuit illustrated in FIG. 3 is a circuit including a power supply V, a semiconductor X, an inductance L, a capacitor C, and a resistor R. When the component name list in which the ground GND is not fixed in the electric circuit on the left side is used, the electric circuit is converted to the graph network on the lower right side.In the graph network on the lower right side, a network input node of the power supply V, a node of the semiconductor X, a node of the inductor L, a node of the capacitor C, and a node of the resistor R are set, and the ground GND is defined as a ground wiring set between the nodes, as indicated by a white line. Generally, since there are many components connected to the ground GND among the components included in the electric circuit, considerably many ground connections for the ground GND need to be defined depending on circuit scale. In addition, an output node is a voltage across resistor R.This time, in the circuit diagram illustrated in FIG. 3, the power supply V serving as an input node and the resistor R constituting a load of an output node are described for convenience, but in a regular circuit diagram in the electrical construction, the power supply V or the resistor R is not described and expressed as an open end.Moreover, in the graph network on the lower right side, six ground wirings are set for the ground GND, but five more wirings are set for connection from nodes other than the ground GND. That is, it is necessary to define 11 wirings in the netlist in total.On the other hand, the information processing device 1 provides list information in which the ground GND is set as a component. This list information may be converted into a graph network on the upper right side. In the graph network, on the upper right side shown in FIG. 3, in addition to the network input node of the power supply V, the node of the semiconductor X, the node of the inductor L, the node of the capacitor C, and the node of the resistor, a node of the ground GND is set.Note that the semiconductor includes not only a semiconductor having a function such as a transistor, a diode, a metal oxide semiconductor field effect transistor (MOSFET), or an insulated gate bipolar transistor (IGBT), but also a scaled-up integrated circuit such as an IC or an LSI, e.g., a CPU, a GPU, a random access memory, or an ASIC.In the first embodiment, since a node including a scaled-up integrated circuit in which an internal circuit element is unknown (black box) can be defined, all the semiconductors can be handled in a similar manner. Even if an internal circuit element is known, in a circuit that handles a signal of a band other than a high frequency or a frequency to which a semiconductor is aligned, a result of the circuit calculation often does not agree with an actual measurement due to the influence of parasitic capacitance, residual inductance, residual resistance, or the like, that is, the circuit is not an equivalent circuit. Thus, even if an internal circuit element can be specified, it is often useless, and the present embodiment, which can be treated as a black box, has a special effect.However, even if a circuit element within an integrated circuit is unknown, attribute information of the integrated circuit itself such as a CPU or a memory can be acquired in many cases, and therefore it is desirable to input the attribute information of the integrated circuit as attribute information of the semiconductor node.Note that the attribute information is, for example, information obtained by combining various types of information described in specifications (also referred to as a specification sheet), such as a manufacturer, a type of a component, a model number of the component, a product lot, the number of terminals of the component, a frequency of an input signal for the component, a voltage of the input signal, a current of the input signal, a power of the input signal, a frequency of an output signal of the component, a voltage of the output signal, a current of the output signal, and a power or dimension of the output signal.By defining the ground GND as a component in the graph network on the upper right side, it is sufficient if nine wirings are set between nine nodes. Thus, only nine wirings in total need to be defined in the netlist, and the number of wirings to be defined in the netlist can be reduced as compared with a case where the ground GND is not defined as a component. By reducing the number of wirings, the amount of calculation can be reduced, and even a computer or edge computing which does not have high calculation power can handle a scaled-up circuit.Next, a hardware configuration for implementing the functions of the information processing apparatus 1 will be described.The information processing device 1 is, for example, a computer connected to an information network.The computer may be a server or client that may be connected to a cloud or the like via an information network, or a self-contained computer that is not connected to the information network. Moreover, it may be a computer used in a closed network environment at a factory, referred to as edge computing.In addition, the information processing device 1 may be a smartphone, a tablet terminal, a personal computer (PC), or a microcomputer.The information processing device 1 may be a device that uses an information processing service offered as a service (SaaS) in the form of software. That is, a dedicated application for providing the information processing service in the first embodiment is executed by the server to which the information processing device 1 is connected via the information network, and the information processing device 1 can receive the provision of the information processing service via the web browser without installing the dedicated application.The functions of the acquisition unit 11 and the processing unit 12 included in the information processing apparatus 1 are realized by a processing circuit. That is, the information processing apparatus 1 includes a processing circuit for executing the processing of steps ST 1 to ST 9 illustrated in FIG. 5. The processing circuit may be dedicated hardware or a central processing unit (CPU) that executes a program stored in a work memory.FIG. 4A is a block diagram showing hardware components that realize the functions of the information processing apparatus 1. In FIG. 4A, an input interface 100, an output interface 101, and a processing circuit 102 are connected to each other via a bus wiring. FIG. 4B is a block diagram showing a hardware configuration for executing software for implementing the functions of the information processing apparatus 1. In FIG. 4B, an input interface 100, an output interface 101, a processor 103, and a working memory 104 are connected to each other via a bus wiring. In FIGS. 4A and 4B, for example, the input interface 100 is an interface that forwards the netlist acquired from the information processing device 1. The output interface 101 is an interface that forwards list information output from the information processing device 1 to an external device.In a case where the processing circuit is a dedicated hardware processing circuit 102 as illustrated in FIG. 4A, the processing circuit 102 corresponds to, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a combination thereof.The functions of the acquisition unit 11 and the processing unit 12 included in the information processing apparatus 1 may be implemented by separate processing circuits, or these functions may be collectively implemented by a single processing circuit.In a case where the processing circuit is the processor 103 illustrated in FIG. 4B, the functions of the acquisition unit 11 and the processing unit 12 included in the information processing apparatus 1 are implemented by software, firmware, or a combination of software and firmware. Note that the software or the firmware is described as a program and stored in the work memory 104.The processor 103 reads and executes the program stored in the work memory 104, thereby executing the functions of the acquisition unit 11 and the processing unit 12 included in the information processing apparatus 1.The information processing apparatus 1 includes, for example, a work memory 104 for storing a program which, when executed by the processor 103, results in execution of the processing of steps ST 1 to ST 9 illustrated in FIG. 5. These programs cause a computer to execute the operations or methods executed by the acquisition unit 11 and the processing unit 12. The storage 104 may be a computer-readable storage medium storing a program that causes a computer to function as the acquisition unit 11 and the processing unit 12.The memory 104 corresponds to, for example, a nonvolatile or volatile semiconductor memory such as a random access memory (RAM), a read only memory (ROM), a flash memory, an erasable programmable read only memory (EPROM), or an electrically EPROM (EEPROM), a magnetic disk, a flexible disk, an optical disk, a compact disc, a mini disk, or a DVD.A part of the functions of the acquisition unit 11 and the processing unit 12 included in the information processing apparatus 1 may be implemented by dedicated hardware, and another part thereof may be implemented by software or firmware. For example, the function of the acquisition unit 11 may be implemented by the processing circuit 102 that is dedicated hardware, and the function of the processing unit 12 may be implemented by the processor 103 that reads and executes a program stored in the memory 104. As described above, the processing circuit may implement the above-mentioned functions by hardware, software, firmware, or a combination thereof.The program executed by the processor 103 may be received by a system (comport) such as the world wide web (WWW) that interconnects a plurality of pieces of hardware via one or both of a wired and wireless connection.In addition, when the information processing device 1 trains a graph neural network to be described later, the information processing device 1 may transmit and receive the parameters obtained by the training, particularly a weighting matrix in the neural network, into the system.The information processing device 1 may function as a training device that performs machine learning.Note that the training device may be a device with general-purpose hardware that is distinguished by parallel calculations, such as a graphics processing unit (GPU), in addition to the CPU. In addition, the information processing apparatus 1 may include a plurality of computers connected to each other via a communication port.In the following description, the information processing apparatus 1 performs both the training and the inference, but training and inference may be performed by separate apparatuses that operate independently of each other. In this case, one of these devices may be the information processing device 1, or both may be the information processing device 1.Moreover, the information processing device 1 may be a device that provides a plurality of virtual hardware environments in a single hardware, and virtually handles individual pieces of virtual hardware as individual pieces of hardware.Next, an operation of the information processing apparatus 1 according to the first embodiment will be described.FIG. 5 is a flowchart illustrating the information processing method according to the first embodiment, and shows a sequence of operations performed by the information processing apparatus 1.First, the acquisition unit 11 acquires a netlist (step ST 1). For example, the acquisition unit 11 reads a circuit diagram model from the work memory 104 shown in FIG. 4B, and converts a circuit diagram indicated by the circuit diagram model into a netlist. As the notation form of the netlist, there is one in which a wiring name is described after a component name. For example, there are formats such as Telesis, PADS, Allegro, Express PCB, Intergraph, and Scicards.Moreover, as the notation form of the netlist, there is a form in which the component name is described after the wiring name. For example, Calay, Mentor or Vectron.Moreover, the notation form of the netlist also includes a form in which a component name and a wiring name are described simultaneously. For example, there are computer vision, algorex, multiwire, and the like.In each notation method, the ground, input and output are defined as wiring. The following netlist represents a netlist related to an electrical circuit for operating a switched mode power supply in the Telesis format. $PACKAGES lt3489! LT3489; U1 ind! 2.2u; L1 schottky! 1N5818; D1 cap! 20u; C1 res! 28.7K; R1 res! 5.23K; R2 cap!.001u; C2 $NET N002; U1.1 U1.7 N003; U1.2 R1.2 R2.1 IN; U1.3 U1.6 L1.1.0; U1.4 C1.2 R2.2 C2.2 N001; U1.5 L1.2 D1.1 N004; U1.8 C2.1 OUT; D1.2 C1.1 R1.1 $ENDThe processing unit 12 extracts a component name list from the netlist (step ST 2- 1) and extracts a wiring name list from the netlist (step ST 2- 2). For example, the processing unit 12 stores all the component names included in the netlist in the component name list, and stores all the wiring names included in the netlist in the wiring name list.Note that either the processing of step ST 2- 1 or the processing of step ST 2- 2 may be executed first, or may be executed simultaneously.In the component name list, components having structural features such as semiconductors or capacitors are stored, but not a ground terminal, an input terminal, and an output terminal. On the other hand, the wiring name list includes a ground wiring, an input wiring, and an output wiring, which are a part of the wiring.The processing unit 12 adds the ground wiring, the input wiring, and the output wiring included in the netlist to the component name list as a ground terminal, an input terminal, and an output terminal (step ST 3- 1). The processing unit 12 removes the ground wiring, the input wiring, and the output wiring (step ST 3- 2). Thus, information indicating the ground terminal, the input terminal, and the output terminal remains in the component name list as component information, so that it is possible to suppress information deterioration when the electric circuit is converted to the graph network using the list information including the component name list.Note that either the processing of step ST 3- 1 or the processing of step ST 3- 2 may be executed first, or may be executed simultaneously.The line following "$PACKAGE" in the above netlist stands for a component name, and the line following "$NET" stands for a wiring name. The component name "U 1, L 1, D 1, C 1, R 1, R 2, C 2" extracted from the netlist is the component name list.The wiring name "N002, N003, IN, 0, N001, N004, OUT" extracted from the netlist is the wiring name list. The input wiring is defined as "IN" and the output wiring is defined as "OUT". In some netlists, no names for input and output may be defined, but all netlists include corresponding wirings corresponding to an input and an output of an electric circuit. "0" is a wiring name indicative of a ground wiring and always present on, for example, a substrate on which a semiconductor is mounted.Note that in this case, N001, N002, N003, and N004 are wiring names mechanically assigned from CAD to wirings that the designer did not give wiring names in a targeted manner.The processing unit 12 adds the one ground (GND), one input (IN), and one output (OUT) to the component name list. The component name list to which the ground (GND), the input (IN), and the output (OUT) are added is, for example, "U 1, L 1, D 1, C 1, R 1, R 2, C 2, GND, IN, OUT". The ground (GND), the input (IN), and the output (OUT) have no structural features unlike the circuit components, and therefore are not set in the component name list, but the processing unit 12 processes the ground (GND), the input (IN), and the output (OUT) as circuit components.In the netlist, the number of the ground (GND), the input (IN), or the output (OUT) need not be one, but may be a plurality. For example, the ground may be divided into a system ground and a frame ground, and depending on the electric circuit, both may be connected by a capacitor, a resistor, an inductive part, or the like. These masses may be defined as different masses.The electric circuit includes not only a power supply terminal connected to a commercially available power supply or a battery, but also a plurality of types of input terminals such as an input terminal for an external signal.Moreover, the electric circuit includes, for example, a plurality of output terminals such as an output terminal for outputting a signal indicating the rotational speed of a rotating machine, in addition to an output terminal for outputting a signal connected to the rotating machine such as a motor.The processing unit 12 removes the ground wiring ( 0), the input wiring (IN), and the output wiring (OUT) from the wiring name list. The list of the wiring names is "N002, N003, N001, N004". Thereby, ground, inputs and outputs can be defined as components and not as wirings, which can reduce the information deterioration in conversion from an electric circuit to a graph network.For example, when the same electric circuit is represented with "PADS", another notation form of the netlist, the following results, and in this case, the component name list and the wiring name list can be similarly created.Note that in any notation form of the netlist, the electrical circuit is not constructed without a component and wiring, such that the component name list and the wiring name list can always be created. *PART* U1 LT3489 L1 2.2u D1 1N5818 C1 20u R1 28.7K R2 5.23K C2.001u *NET* *SIGNAL*N002 U1.1 U1.7 *SIGNAL*N003 U1.2 R1.2 R2.1 *SIGNAL *IN U1.3 U1.6 L1.1 *SIGNAL*0 U1.4 C1.2 R2.2 C2.2 *SIGNAL*N001 U1.5 L1.2 D1.1 *SIGNAL*N004 U1.8 C2.1 *SIGNAL*OUT D1.2 C1.1 R1.1 *END*Next, the processing unit 12 extracts a component name corresponding to a wiring name in the wiring name list from the component names in the component name list, and creates a combination list including the extracted component name (step ST 4). For example, the processing unit 12 extracts, from the netlist, the component names in the component name list corresponding to the wiring names in the wiring name list in the order of the list, and creates a combination list with the extracted component names. Here, the processing unit 12 includes the ground terminal, the input terminal, and the output terminal that have been added to the component name list in the combination list.Note that the "component name corresponding to the wiring name" is a component name indicating a component to which the wiring indicated by the wiring name is connected.By including the ground terminal in the combination list, the information amount of the combination list can be reduced. Generally, many components in an electrical circuit are connected to the ground GND. For example, in a case where N components are connected to the ground GND, the combination list includes N combinations of the ground GND and the components.Note that when the ground GND is not defined, it is necessary to make the number of combinations of the ground GND and the components proportional to the square of N.Since the electric circuit is constructed only when the components are connected by wiring, the combination list can always be prepared as long as the electric circuit operates normally.FIG. 6 is a circuit diagram illustrating an example (1) of the electric circuit. A netlist of the electrical circuit shown in FIG. 6 is as follows. #Component #Verdrahtung(1); IN,A(2); A,B(3); B,C,D(4); D,OUT GND; A,B,CThe component name list extracted from the netlist is obtained by adding "IN", "OUT", and "GND" to "A, B, C, D, IN, OUT, GND". The wiring name list becomes "(1), (2), (3), (4)" by removing "IN", "OUT", and "GND".In a netlist in which a wiring connected to a ground terminal is not defined, a wiring is provided between the ground and a component, and a name is given to the wiring.That is, in the netlist of the electric circuit illustrated in FIG. 6, for example, the ground is represented by "G", and the component names are connected so as to give the wiring names "G-A", "G-B", and "G-C". Thus, the wiring name list is "(1), (2), (3), (4), G-A, G-B, G-C".In the component name list "A, B, C, D, IN, OUT, GND", the component names corresponding to the wiring names in the wiring name list "(1), (2), (3), (4), G-A, G-B, G-C" are extracted one by one from the netlist to obtain the following combination list.(1); IN, A(2); A, B(3); B,C,D(4); D, OUTG-A; GND,AG-B; GND,BG-C; GND,CSubsequently, the processing unit 12 determines whether or not there are three or more component names corresponding to a wiring name among the component names in the combination list (step ST 5). Here, when it is determined that less than three component names correspond to a single wiring name in the combination list (step ST 5; NO), the processing unit 12 replaces the component name in the combination list with the identification number (step ST 6).On the other hand, when it is determined that three or more component names correspond to a single wiring name in the combination list (step ST 5; YES), the processing unit 12 divides it into a combination of two component names (step ST 7). For example, when a component name that a certain wiring name carries, that is, a component name corresponding to a wiring name is [capacitor, coil, resistor], the processing unit 12 divides the component name into three combinations of [capacitor, coil], [coil, resistor], and [resistor, capacitor]. Similarly, in a case where the component name is [capacitor, coil, resistor, semiconductor], the processing unit 12 divides the component name into six combinations of [capacitor, coil], [capacitor, resistor], [capacitor, semiconductor], [coil, resistor], [coil, semiconductor], and [resistor, semiconductor].The processing unit 12 adds the combinations obtained by dividing into combinations of two component names each to the list, and removes the combination having three or more component names from the combination list before dividing. However, this processing is processing for creating an adjacence matrix in the graph network, and cannot be divided as long as the adjacence matrix can be created directly from the combination list.For example, since (3); B, C, D in the netlist corresponds to a combination of three or more component names, the processing unit 12 divides them into (B, C), (C, D), and (D, B). This results in the following combination list for the circuit diagram shown in FIG. 6.(1); (IN,A)(2); (A,B)(3); (B, C), (C, D), (D, B)(4); (D, OUT)G-A; (GND,A)G-B; (GND,B)G-C; (GND,C)FIG. 7 is a circuit diagram illustrating an example (2) of the electric circuit. The circuit diagram shown in Figure 7 is the following netlist. #Component #Verdrahtung '; IN,A'; A,D'; C,D,E (4A); E,F (5A); F,OUT GND; A,C,EThe component name list included in the netlist is "A, C, D, E, F, GND, IN, OUT", and the wiring name list is "(1A), (2A), (3A), (4A), (5A), G-A, G-C, G-E". The processing unit 12 extracts the component name corresponding to each wiring name in the wiring name list from the netlist to prepare the following combination list.(1A); IN,A(2A); A, D(3A); C, D, E(4A); E, F(5A); F, OUTG-A; GND,AG-C; GND,BG-E; GND,ESubsequently, in a case where each combination list includes three or more component names, the processing unit 12 decomposes the component names. For example, the processing unit 12 creates the following combination list by dividing the combination "(3A); C, D, E" into combinations of two component names each.(1A); (IN, A)(2A); (A,D)(3A); (C,D),(D,E),(E,C)(4A); (E,F)(5A); (F, OUT)G-A; (GND,A)G-C; (GND,B)G-E; (GND,E)Heretofore, in the description, it has been assumed that component names other than the same component do not match, but in a case where the same component name is used for a circuit component having a different function, the processing unit 12 changes the component name.Conversely, the processing unit 12 changes the component name when different component names are used for the same circuit component. When the number of component names is large and it is difficult to unify the component names, it is easy to unify the component names by using the model number of the individual component manufacturers.The processing unit 12 defines a common unique identification number for each component type or component model number indicated by each component name in the component name list (step ST 8), and replaces each component number in the component name list with an identification number (step ST 9).The processing unit 12 replaces each component name included in the component name list and the combination list with an identification number. The component name list thus obtained and the combination list are output as list information.By using the list information including the component name list and the combination list in which the component name is replaced with the identification number, the circuit information can be expressed by numerical values, and the information deterioration of the graph network is reduced as described above, so that the original electric circuit can be created by using the graph network.Moreover, the identification number may be defined for each component type that is a feature of the component.The type of the component can be expressed by information such as capacitor, coil, power supply IC, or diode. Depending on the classification method, there are about 100 or fewer types of components. Thus, the number of types of components is relatively small. For example, the processing unit 12 replaces the component name by using the serial number set for each component type as an identification number.Moreover, the identification number may be defined for each model number of the component.In a case where the number of components used in the electric circuit is limited, the identification number for each model number of the component is relatively small. In this case, by using the identification number defined by the model number of the component, information deterioration in converting the list information into the graph network can be prevented.In step ST 8, the processing unit 12 defines an identification number according to the following method, and assigns the defined identification number to a component name.The component name list related to the electric circuit shown in FIG. 6 is "A, B, C, D, IN, OUT, GND" as described above, and the component name list related to the electric circuit shown in FIG. 7 is "A, C, D, E, F, GND, IN, OUT" as described above.The processing unit 12 combines these component name lists into a component name list "A, A, B, C, C, D, D, E, F, GND, GND, IN, IN, OUT, OUT". The component name list includes a plurality of equal component names.The processing unit 12 removes the duplicate of component names to prepare a component name list "A, B, C, D, E, F, GND, IN, OUT".Subsequently, the processing unit 12 allocates identification numbers such that each component in the component name list has different identification numbers. When a natural number is used as the identification number, the component name list in which the component name is replaced with the identification number is as follows. Note that the identification number is not necessarily a consecutive number, but may be a letter or a symbol.A→1B→2C→3D→4E→5F→6GND→7IN→8OUT→9The order may be arbitrarily changed, wherein the identification number of the component name "GND" is "0", the identification number of the component name "IN" is "1", and the identification number of the component name "OUT" is "2".In addition, the identification number may be a number corresponding to a circuit constant of the component, a model number of the component, a manufacturer of the component, or a withstand voltage of the component. For example, components having the same function as a power supply, a work memory, and a CPU are assigned the same identification number.For example, when an isolated power supply and a non-isolated power supply in the switching power supply are separated from each other, the isolated power supply is assigned the same identification number and the non-isolated power supply is assigned the same identification number.Moreover, the same identification number can be assigned for operations such as boosting, attenuating, or raising and lowering.In addition, an identification number may be assigned depending on a circuit constant of a passive element.For example, a capacitor having a capacitance of 1.0 μF may be assigned the same identification number, and the same identification number may be assigned to a capacitor having a capacitance in a range of 1.0 μF to 3.3 μF.In addition, the definition of the identification number may be changed according to the user's request.Moreover, each model number set for a component by a component manufacturer may be assigned an identification number.The method of defining the identification number may be changed depending on the electric circuit to be handled.For example, when the component name is replaced with the identification number for each component type (capacitor, coil, resistor, semiconductor, and the like), the component name list related to the electric circuit illustrated in FIG. 6 becomes "1, 2, 3, 4, 7, 8, 9", and the combination list becomes "(8, 1), (1, 2), (2, 3), (3, 4), (4, 2), (4, 9), (7.1), (7.2), (7, 3)".Moreover, the component name list related to the electric circuit shown in FIG. 7 is "1, 3, 4, 5, 6, 7, 8, 9", and the combination list is "(8, 1), (1, 4), (3, 4), (4, 5), (5, 3), (5, 6), (6, 9), (7.1), (7.2), (7.5)".The processing unit 12 repeats the above-described sequence of processes, thus creating a component name list and a combination list for all the circuit plans. Since the definition of the identification number is arbitrary, the use of the circuit can be changed depending on the purpose of use of the circuit by determining the identification number according to the feature of the component of interest. For example, in the difficulty of predicting the component type, although the model number is redundant information that can be used as the identification number, if the manufacturer of the component is used as the identification number, there is a possibility that the information is insufficient and correct prediction cannot be made. Therefore, it is necessary to select the identification number according to the purpose of use, and when the identification number is properly selected, the amount of calculation in predicting the component type is small, and prediction accuracy can be improved.In addition, a plurality of identification numbers may be assigned to a single component name.For example, identification numbers corresponding to the model number of the component, the type of the component, and the circuit constant of the component can be assigned. In this case, the list of component names of the electric circuit illustrated in FIG. 7 is, for example, "(1,3,0), (3,3,7), (4,5,3), (5,2,0), (6,8,1), (7,1,0), (8,1,0), (9,1,0)".Since the component types "IN", "OUT", and "GND" as component names are wirings, the identification number is defined as "1", and the components represented by the identification number "1" assigned to one semiconductor, the identification number "5" assigned to another semiconductor, and the component names "IN", "OUT", and "GND" are input terminals, output terminals, and ground and have no circuit constant. In this case, the identification number is defined as "0", for example.For example, a circuit constant may also be provided in the semiconductor to take into account the characteristics in the semiconductor, or different identification numbers may be assigned for the component types labeled "IN", "OUT", and "GND".The method for assigning the identification number may be any method provided that the method is based on a common rule for the circuits.The identification number only needs to be a real number and is not necessarily a natural number.The circuit constant of the component may be directly input as the identification number.Thus, the circuit constant used in a general circuit ranges from a maximum number f (femto) to several 100 G (giga) and about 10 potentiated to 20.Moreover, a small value may be rounded or changed to another value due to a calculation error. In order to avoid these, a function including logarithmization may be used as a circuit constant. The function is, for example, f(x)=log10(x)+15 Here, +15 is -log10(f=1 femto). In this way, f(x) can be converted into a real number equal to or greater than 0. In addition, in order to prevent it from becoming 0 when 1 fis included and it is not possible to determine which component is included, log 10(x)+16 or log 10(x)+15+(minimum amount of more than 0 and less than 1) may be used. For convenience, the case where the basis of logarithmation is 10 has also been described, but the basis does not need to be 10.In this case, since there are many cases where the component constant is sufficient with an accuracy of one place or less, the identification number can be defined by rounding up the value as follows.1f→1,10f→2,100f→3,1n→4,10n→5,100n→6,1u→7,10u→8,100u→9,1m→10, 10m→11,100m→12,1→13,10→14,100→15,1k→16,10k→17,100k→18,1M→1 9,10M→20,100M→21,1G→22,10G→23,100G→24.By the above-described sequence of processes, the circuit diagram can be converted into a netlist, and the netlist can be converted into a component name list and a combination list. By using the component name list and the combination list, a graph network in graph theory can be created.The graph network can be used for searching for similar circuits, which is difficult with a netlist.For example, the processing unit 12 may search for a semiconductor, a capacitor, a coil, ground, and a semiconductor loop path by sequentially searching for adjacent matrices created using the combination list. Specifically, in an electric circuit using a specific circuit component, the identification numbers of the components constituting the circuit are sequentially searched.The processing unit 12 refers to, for example, a database including a semiconductor as a disturbance source and a terminal number of the semiconductor, performs a search process of continuously searching for adjacent components from the electric circuit under a condition that the same component having a terminal corresponding to the terminal number as the starting point is not passed twice or more, and extracts a current loop representing the semiconductor, and ends the search process.Specifically, with the semiconductor to be searched connected as a search start point, the processing of searching for one or more adjacent components from the start point and searching for one or more circuit components adjacent to the components is continuously performed. However, the search is performed on the condition that a component other than the semiconductor which is the start point of the search is not passed twice or more. In this way, it is possible to avoid the search for a physical phenomenon in which the current returns to the original state or the current stops halfway.The processing unit 12 terminates the search process when it terminates at a terminal other than the terminal serving as a start point of the search among the semiconductors serving as search start points.The path that arises from this search process is referred to above as a "current loop.". That is, the above processing corresponds to the processing of extracting a current loop path in the current law, the Kirchhoff's law (Kirchhoff's first law).The terminal may be any terminal. For example, in a differential line, although the number of ground terminals is the largest, each terminal of the differential signal is a start point and the opposite terminal is an end point.For example, it is possible to detect extraction of a noise filter or the like based on an algorithm, or it is possible to estimate the impedance of a propagation path through which the current can flow and predict through which current loop the current most easily flows out of the circuit.In this way, the processing unit 12 may extract features of the semiconductor to be searched and features of the current loop indicating the semiconductor from one or more electrical circuits including one or more semiconductors, and search for a semiconductor similar to the semiconductor to be searched based on the extracted features of the semiconductor and the features of the current loop.In addition, the processing unit 12 may determine whether a component indicating a noise filter is present in the current loop. As an example, a case will be described in which a path returning from a power input terminal of a semiconductor to a ground terminal of the semiconductor via a ground capacitor (Y capacitor) and the ground is detected. In the present embodiment, the ground capacitor and the ground are defined as nodes of the graphene mesh. Thus, the path can be detected by determining the presence or absence of a path from the node (semiconductor) to be the start to the same node as the start via two nodes. For this detection, if all current loops passing through the two nodes are extracted, and a single node of the extracted current loops is a capacitor and the other node is ground, a current loop including a noise filter may be extracted.Moreover, in the information processing apparatus 1, a database having a model number serving as a disturbance countermeasure component is created in advance. By confirming whether or not the extracted capacitor is included in the database, the processing unit 12 may determine that a noise filter is present in the current loop when the extracted capacitor is included.In order to limit the number of nodes that can be considered as sources of interference and reduce the amount of calculation, a database including model numbers of circuit components that can be considered as sources of interference is created in the information processing apparatus 1 in advance. The search targets can be reduced by the processing unit 12 setting only an applicable node as a search starting point.Although the example of the ground capacitor has been described in the above description, a T-type filter, a π-type filter, or the like may be similarly extracted.In addition, the presence or absence of connections between arbitrary components can be confirmed similarly.Moreover, it is possible to predict, from the attribute information carried by each node, a frequency characteristic such as an impedance, a current, or a voltage drop between the components, or a time waveform.The processing unit 12 may extract a similar circuit by creating a current loop for each terminal of the semiconductor and analyzing the circuit components through which the current loop passes. By the above search processing, the processing unit 12 can search for a noise filter circuit or the like without depending on the number of components or the number of wirings in the electric circuit, the number of ground or input / output terminals, or the like. In this way, a search error can be reduced by searching for a path adjacent to the semiconductor, an input connector, or an output connector that serves as a noise source and is provided with the noise filter.Note that since the semiconductor serves as a disturbance source, a model number of a component can be extracted as text data from the netlist. Moreover, inputs and outputs in the circuit diagram are often described as input symbols and output symbols, but may also be referred to as input connectors and output connectors to which the model numbers of the connectors are assigned. In this way, the above-described database in which a semiconductor, a disturbance countermeasure component, an input connector, or an output connector serving as a disturbance source is registered is prepared, and only text data is extracted by referring to the database, whereby omission of the search can be suppressed.In addition to searching for the noise source or the noise filter, a node and an edge are provided with a resistance component or a delay component, so that the processing unit 12 can calculate the impedance between two components and estimate a path through which the current flows most strongly or a path through which the pulse signal arrives earliest.In a case where the electric circuit has a plurality of components connected in parallel to a wiring, the number of combinations of components in the combination list increases in the processing so far. FIG. 8 is a circuit diagram illustrating an example (3) of the electric circuit. The electric circuit illustrated in FIG. 8 is a circuit in which a wiring Line 1 is connected between an input terminal IN and an output terminal OUT, and a capacitor C 1, a capacitor C 2, and a resistor R are connected in parallel to the wiring Line 1. The information processing device 1 that handles the ground, input, and output as components creates list information in which the electric circuit is converted to the graph network illustrated in FIG. 9 below.FIG. 9 is a schematic diagram illustrating a graph network in which nodes are connected by edges. In the graph network shown in FIG. 9, the components of the electric circuit shown in FIG. 8 are represented by nodes, and these components are connected by edges. The information processing device 1 generates list information that handles ground, input, and output as components. Thus, the list information created by the information processing device 1 is converted into a graph network in which, for example, a semiconductor X, a capacitor C 1, a capacitor C 2, a resistor R, and an output terminal OUT are represented as nodes, and all the nodes are connected by edges. In FIG. 9, the description of a node indicating the input terminal IN and a node indicating the ground is omitted for simplicity.Note that the graph network has a feature that a component name is a node, and a node adjacent to any node is a node having a component name.When the electric circuit has a plurality of components connected in parallel to a single wiring, the combination of the components corresponding to each other in the combination list increases approximately in proportion to the square of the number of components connected in parallel to the wiring. In FIG. 9, since three components (capacitor C 1, capacitor C 2, and resistor R) are connected in parallel to a single wiring Line 1, nine combinations are obtained which are the square of 3. For example, there is a scaled-up circuit in which 10 or more bypass capacitors are connected in parallel to a wiring. Such a circuit increases the number of combinations considerably. For this reason, the amount of calculation required for the current loop search increases exponentially, and the search time also increases.Note that, also in the graph network illustrated in FIG. 9, when searching for all current loops originating from a specific component name node, an exhaustive search for nodes is possible, so that the condition is satisfied that a node that has been traversed once is not traversed twice. However, in a case where the component name nodes are adjacent to each other, as explained above, it is necessary to include a number of components approximately proportional to the square of the number of components connected in parallel to a single wiring line. For example, as illustrated in FIG. 9, in the case of three components connected in parallel, it is difficult to calculate a path returning to a node having the same component name as the starting point via a node corresponding to each component name of the three components.Accordingly, the information processing apparatus 1 can create a combination list including wiring names and component names in order to suppress an increase in the number of combinations of component names for a scaled-up circuit in which a plurality of components are connected in parallel to a single wiring as described above. The processing unit 12 extracts, for example, a component name list and a wiring name list from the electric circuit netlist, and creates a component name list that is updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, a wiring name list that is updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, and a combination list that includes an extracted component name obtained by extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list and a wiring name corresponding to the extracted component name, and outputs the updated component name list and combination list.FIG. 10 is a schematic diagram illustrating a graph network in which nodes are connected via wiring nodes. As illustrated in FIG. 10, the processing unit 12 extracts a combination of a component name corresponding to a component connected by a wiring indicated by each wiring name in the wiring name list and each wiring name as a combination list. The graph network converted from the list information has the characteristics that a component name and a wiring name are represented by nodes, and a node adjacent to a node having an arbitrary component name is a node of a wiring name. Thus, the number of combinations can be set to a number proportional to the first power of the number of components.Also in the graph network shown in FIG. 10, when searching for all current loops originating from a specific component name node, an exhaustive search for nodes is also possible, so that the condition is satisfied that a node which has been traversed once is not traversed twice.On the other hand, in the graph network, the component name node and the wiring name node are adjacent to each other, and a route returning to the starting point via four wiring name nodes and three component name nodes is searched instead of via nodes representing three circuit components (capacitor C1, capacitor C2, and resistor R). However, since the wiring connected to each node is linearly proportional, the amount of calculation required for the search does not become exponentially large.As an example of the experiment, when a current loop of a scaled-up circuit having 1,000 or more components was searched in the same computer environment, it took 10 minutes when the component name nodes in the graph network were adjacent to each other, while the search was completed within 1 second when the component name node and the wiring name node were adjacent to each other. Also in this example, a particularly large effect can be obtained in the current loop search.However, in a case where the component name node and the wiring name node are adjacent to each other, compared to a case where the component name nodes are adjacent to each other, it is preferable in a case where the number of components connected in parallel to a single wiring is large, but it is disadvantageous in a case where the number of components connected in parallel is small because the number of the wiring name nodes increases.It is therefore desirable to selectively apply the two methods according to the scale of the circuit or the number of components connected in parallel to a single wiring. For example, if a current loop of a circuit with about 100 components is sought, it is often better to use a graph network with adjacent component names.Note that, regardless of whether the wiring name node is included or not, paths having the same loop path and opposite directions can be obtained in both the above-described methods. Thus, only a single path may remain and the other path may be removed during post processing. However, in a case where the current direction is known and the graph is a directed graph, only a single path is extracted, so that the post-processing may not be performed.The processing unit 12 may replace an element corresponding to a passive circuit in the feature amount matrix with a function value calculated by replacing a circuit constant of a component in a function including logarithmization.In a component having a circuit constant, by changing an element corresponding to a passive circuit in a feature amount matrix with a function value obtained by applying a function including logarithmization to the circuit constant, conversion to a graph network including the circuit constant may be performed.The component having a circuit constant is a resistor, a capacitor, or an inductor, but may be a small signal circuit such as an operational amplifier. Components other than resistors, capacitors and inductors may also be circuit components having circuit constants as long as they can be converted into components composed of resistors, capacitors and inductors under certain conditions.Components with physical dimensions also have parasitic components such as stray capacitance, residual inductance or residual resistance. Thus, the processing unit 12 decomposes a component having a parasitic component into components having only two or more resistors, capacitors, or inductors. The division can be made by predicting an equivalent circuit from the impedance measurement and determining a circuit constant of the equivalent circuit. Thus, a circuit having complicated component characteristics can also be expressed by a graph network.A circuit constant of a component having only one characteristic is assigned to a component name in the component name list. Since the circuit constants often have a width of 20 or more digits from 1p to 1G, the circuit constants can be logarithmically multiplied, except in specific examples. By applying logarithmization to the circuit constant, it is possible to prevent, for example, a capacitor of 1 pF from being subject to a calculation error.The processing unit 12 may perform both or one of normalization and standardization of the function value.For example, normalization is performed to a result obtained by performing logarithmation to a circuit constant.When a graph network is input into a graph neural network, an activation function in the graph neural network responds to a real number of 0 to 1.Normalization is performed on the result of performing logarithmization on the circuit constant, and bijection is performed on a real number equal to or greater than 0 and equal to or less than 1 or greater than 0 and equal to or less than 1, whereby the result of performing logarithmization on the circuit constant can be assigned to an activation function of the real number.Standardization may be performed on a result of performing logarithmization on the circuit constant.For example, in a distribution of the result of performing logarithmization on the circuit constant of the capacitor used for the electric circuit, when there are many capacitors of 100 μF or less and there is even a capacitor such as 100 F, the distribution of the result of performing logarithmization varies on the circuit constant, and the difference as the result of performing logarithmization on the circuit constant for each capacitor is estimated to be small.Thus, by standardization of the result of logarithmizing the circuit constant, it is possible to reduce the variation in distribution.Further, since the range of circuit constants is different for each type of circuit component, different normalization or standardization can also be performed for each type of circuit component. For example, while a capacitor of 100 F falls within the large category of the capacitors, a resistor of 100 Ω belongs within a small category of the resistor, so that the area becomes large. For example, in the case of a capacitor, the distribution is adjusted so that 1 μF is located at the center, and in the case of a resistor, the distribution is adjusted so that 100 Ω is located at the center, thereby reducing the round off error and improving the accuracy of estimation of the result of performing logarithmization to that of the circuit constant.Moreover, the processing unit 12 may perform standardization after normalization to the result of performing logarithmization to the circuit constant, or perform normalization after normalization. Both effects are achieved by this combination of normalization and standardization.A circuit component having no circuit constant does not become information by assigning it the same numerical value as "0" or "1" as an identification number. Thus, a feature amount list created by additional information can be expressed by a matrix.For example, in the case of a capacitor or a coil, the capacitor or the coil can be classified by a circuit constant and has two terminals, so that no information deterioration occurs when the graphene sheet is converted into an electric circuit.On the other hand, in a case where two or more semiconductors are included in a single electric circuit and two or more semiconductors of the same model number are included, information deterioration occurs when conversion from a graph network to an electric circuit is performed. In this way, additional information indicating that they are different components may be added to the component name list for the semiconductor.For example, a real number greater than 0 and equal to or less than 1 is divided by the number of semiconductors, and different real numbers are assigned to the respective semiconductors as additional information.When two semiconductors having the same model number are present in an electric circuit, different real numbers are assigned, such as assignment of 0.3 to one semiconductor and assignment of 0.6 to the other semiconductor.In addition, when only a component in an electric circuit is known to be a semiconductor, and the electric circuit is a circuit having 10 semiconductors, 0.1 to 1.0 may be assigned in increments of 0.1 as additional information.Note that the additional information only needs to have different numerical values, and real numbers can be assigned in any order.Note that, when the identification number is not used, the processing unit 12 may directly output the component name list and the combination list as list information without replacing the component name with the identification number.Modification 1In the information processing device 1 according to Modification 1, the processing unit 12 uses the graph network to train a graph neural network by using the component name list as a node in the graph network, the wiring name list as an edge in the graph network, and the combination list as an adjacence matrix in the graph network.Training of the graph neural network is unsupervised learning when a dataset of training data includes only nodes and edges.On the other hand, in a case where correct response data can be obtained by circuit simulation or experiment, the processing unit 12 trains the graph neural network using nodes, edges, and the correct response data as a data set of training data.Moreover, the processing unit 12 trains the graph neural network by incorporating attribute information of an edge (edge attribute) such as the frequency characteristics of an edge.Moreover, the processing unit 12 trains the graph neural network by using the characteristics of a component for each circuit constant or for each semiconductor as attribute information of a node (node attribute).FIG. 11 is a flowchart illustrating a data input processing example (1) to the graph network in the first embodiment. Assuming that the number of the electric circuits is n, n netlists corresponding to the number of the electric circuits can be generated, and thus the processing unit 12 sets the n netlists as processing targets (step ST 1A). The processing unit 12 sets "1" as the parameter i (step ST 2A).The processing unit 12 sets the value of the parameter i to the function g[i]=[[node], [edge]] (step ST 3A). The processing unit 12 extracts the component name list and the wiring name list from the i-th netlist acquired by the acquisition unit 11.The processing unit 12 reads the component name list extracted from the i-th netlist as a node of the graph network, and reads the wiring name list as an edge of the graph network (step ST 4A). The processing unit 12 sets a node and an edge related to the ith netlist as a single record, and stores the record in a storage area such as the working memory 104 in association with the function g[i] (step STSA).The processing unit 12 determines whether or not the parameter i is equal to or less than n (step ST 6A). If the parameter i is equal to or less than n (step ST 6A; YES), the processing unit 12 adds "1" to the parameter i (step ST 7A), and returns to the processing of step ST 4A.On the other hand, when it is determined that the parameter i is larger than n (step ST 6A; NO), the processing unit 12 outputs data sets respectively associated with g[ 1] to g[n] (step ST 8A).The nodes are a matrix of (number of components of each circuit+ground terminal+input terminal+output terminal)×(number of feature amounts of the nodes). In the electric circuit illustrated in FIG. 6, the nodes are, for example, a matrix of 7×1. Note that although the input terminal and the output terminal have been described as a single electric circuit, it is sufficient if the input terminal and the output terminal have one or more terminals, and in this case, the column of the matrix becomes large.Moreover, the number of feature amounts of the nodes may be input as one-hot, and in this case, when the number of feature amounts of the nodes is M (for example, as in the electric circuit illustrated in FIG. 6, M=4, when a capacitor, a coil, a first semiconductor, and a second semiconductor are included as component types), the nodes have a matrix of 7×M. The edges are a matrix of 2 x (the number of edges). Here, "2" multiplied by (the number of edges) means any two components in the component name list, and the edge is a matrix indicating that these two components are connected by the number of edges.Note that in a case where the direction of the current is known, a directed graph may be used. In the directed graph, when the order in which the current of the components in the combination list flows is expressed as (1, 2), for example, this means by definition the directions from 1 to 2 or the directions from 2 to 1. When bidirectional edges are considered, in a case where the omnidirectional graph is a matrix of 2×(the number of edges), the matrix in the directional graph is a maximum matrix of 4 x (the number of edges).In the case of the electric circuit shown in FIG. 6, since the number of combinations in the combination list is nine (8, 1), (1, 2), (2, 3), (3, 4), (4, 2), (4, 9), (7.1), (7.2), and (7.3), the number of nodes is a 2×109matrix. An element of this matrix is an identification number included as a node in the component name list. That is, a component included in a particular circuit does not form an edge with a component in another circuit.In the graph neural network, the individual circuits may be processed in sequence, but may be parallelized by using dedicated hardware such as a GPU.In particular, when the number of circuits increases to several 1,000 or more, it is desirable to process the circuits together from the viewpoint of the calculation speed or the calculation efficiency, instead of calculating the individual circuits in order. Combinations of nodes and edges, which can be stored in the working memory overall or at a specific point in time, are thus input together.Since there is no correct response data in this example, unsupervised learning is performed.FIG. 12 is a flowchart illustrating a data input processing example (2) to the graph network in the first embodiment. Assuming that the number of the electric circuits is n, n netlists equal to the number of the electric circuits can be generated, and thus the processing unit 12 sets the n netlists as processing targets (step ST 1B). The processing unit 12 sets "1" as the parameter i (step ST 2B).The processing unit 12 sets the value of the parameter i to the function g[i]=[[node], [edge], [correct response data]] (step ST 3B). The processing unit 12 extracts the component name list and the wiring name list from the i-th netlist acquired by the acquisition unit 11 and acquires correct response data obtained in advance.The processing unit 12 reads the component name list extracted from the i-th netlist as a node of the graph network, reads the wiring name list as an edge of the graph network, and further reads correct response data (step ST 4B). The processing unit 12 sets the node, the edge, and the correct response data relating to the ith netlist, and stores the data in a storage area such as the working memory 104 in correspondence with the function g[i] (step ST 5B).The processing unit 12 determines whether or not the parameter i is equal to or less than n (step ST 6B). If the parameter i is equal to or less than n (step ST 6B; YES), the processing unit 12 adds "1" to the parameter i (step ST 7B), and returns to the processing of step ST 4B.On the other hand, when it is determined that the parameter i is larger than n (step ST 6B; NO), the processing unit 12 outputs data sets respectively associated with g[ 1] to g[n] (step ST 8B).FIG. 13 is a flowchart illustrating a data input processing example (3) to the graph network in the first embodiment. Assuming that the number of the electric circuits is n, n netlists equal to the number of the electric circuits can be generated, and thus the processing unit 12 sets the n netlists as processing targets (step ST 1C). The processing unit 12 sets "1" as the parameter i (step ST 2C).The processing unit 12 sets the value of the parameter i to the function g[i]=[[node], [edge], [edge attribute], [correct response data]] (step ST 3C). The processing unit 12 extracts the component name list and the wiring name list from the i-th netlist acquired by the acquisition unit 11, and acquires the attribute of the edge and the correct response data obtained in advance.The processing unit 12 reads the component name list extracted from the i-th netlist as a node of the graph network, reads the wiring name list as an edge of the graph network, and further reads an attribute of the edge of correct response data (step ST 4C). The processing unit 12 sets the node, the edge, the edge attribute, and the correct response data relating to the ith netlist as a data set, and stores it in a storage area such as the working memory 104 in association with the function g[i] (step ST 5C).The processing unit 12 determines whether or not the parameter i is equal to or less than n (step ST 6C). If the parameter i is equal to or less than n (step ST 6C; YES), the processing unit 12 adds "1" to the parameter i (step ST 7C), and returns to the processing of step ST 4C.On the other hand, when it is determined that the parameter i is larger than n (step ST 6C; NO), the processing unit 12 outputs data sets respectively associated with g[ 1] to g[n] (step ST 8C).The data set obtained as described above can be used for self-supervised learning, which is one of clustering, autoencoder, and contrasting learning. Clustering may be used for classification of node types or for classification of edge types.The autoencoder is training a graph neural network to obtain the same output data as the input data after passing through the graph neural network. In the autoencoder, a plurality of circuits may be abstracted and carried.For example, even if the self-supervised learning is similar to clustering, all input data may be classified, and similar circuits may be classified into any number of sets.These are examples, and it is also possible to predict the presence or absence of an edge between nodes, or predict the presence or absence of a node by combining a plurality of technologies.Note that a neural network that handles data of an electric circuit as a graph network is known as well as a graph neural network, a convolutional graph neural network, an attention graph network, and the like.For example, depending on a characteristic of the data or a characteristic of the correct response data, any network suitable for a scaled-up model that is distinguished and sparse (sparse) in an edge-created adjacence matrix may be used.The processing unit 12 trains the graph neural network by using the type of the circuit diagram as correct response data, and using it as teacher data, and using, for example, 3,362 types of example circuits handled by the circuit simulator as training data.The example circuit includes nine types of circuits for operating a semiconductor, namely, circuits (89), reference circuits (59), ADC circuits (27), DAC circuits (29), comparator circuits (40), filter circuits (25), power supply circuits (2272), and operational amplifier circuits (665).The processing unit 12 trains a graph neural network to classify electric circuits using a dataset obtained by combining a graph network and the circuit classification data assigned to each of the plurality of electric circuits as training data, and inputs a graph network not used for the training to the graph neural network, thereby classifying the electric circuits.For example, training of a graph neural network that solves a classification problem of classifying electric circuits into the nine types is performed. Here, 2,300 pieces of data acquired at random were set as training data, and the remaining 897 pieces of data were set as test data that are not used for training. The graph neural network of the training result was randomly classified, and the distribution of the classification problem between the training data and the test data was similar. In addition, the same training data and test data were used for the calculations of all the graphene neural networks described in the embodiments.Note that under the above-mentioned conditions, the node of the component constant or the component model number is not used, and each node represents only an identification number for each component type such as a semiconductor, a capacitor, or an inductor.This is intended to prevent classification of a circuit based on the model number because the circuit classification problem is expected to be predicted based on the connection information between the circuit components, but if the model number of the component is included in the data, classification based on the model number is possible.Also, for the edge, only information for connecting each identification number was input. Since the omnidirectional graph does not consider the direction of current at this time, the adjacence matrix becomes a symmetric matrix at this time.FIG. 14 is a graph illustrating an example (1) of a calculation result of inference accuracy by the information processing apparatus 1 according to the first embodiment. In FIG. 11, the horizontal axis represents the number of iterations (periods) when the graph neural network is trained using the training data and the parameter of the graph neural network is updated. The vertical axis indicates the inference accuracy of the test data that was not used for the training by the trained graph neural network.As shown in FIG. 11, the inference accuracy for the test data improves as the number of iterations increases, and the maximum inference accuracy is 96.26% in 4,000 iterations.Note that the graph neural network used for calculating the inference result illustrated in FIG. 14 includes a combination of 6 hidden layers and a rectified linear unit (ReLU), and the feature amounts obtained by the graph neural network and the ReLU are classified into any of nine types of outputs in two fully connected layers.Moreover, cross entropy was used as a loss function and adaptive torque estimation (adam) was used as an optimization function. The batch size was set to 500, and the graph neural network was trained so that the loss function is close to 0.As described above, the inference accuracy of the trained graph neural network was about 90% when the graph neural network was trained only according to the type of the component and the connection relationship of the individual components.Note that when the circuits indicated in the test data were classified as 77% of people from the graph network, regardless of being power supply circuits, the accuracy of the human inference was about 50%.From this result, it is understood that the inference accuracy based on the present technique is significantly higher than that of a person.FIG. 15 is a graph illustrating an example (2) of the calculation result of the inference accuracy by the information processing apparatus 1 according to the first embodiment, and illustrates a result of training the graph neural network by a passive element, which is a node used for calculating the inference result of FIG. 14, to which a component constant is assigned as training data. The resistance element is, for example, a resistor, a capacitor, or a coil. Since a dynamic range that a value of a passive element can take is large, logarithmization of a base 10 has been made with respect to an identification number corresponding to the type of the passive element, normalization has been performed to make it equal to or greater than 0 and equal to or less than 1, and the value is input as a real number.For example, in a case where the node information is (C1, 0.33 μF) and (L2, 10 μH), if the identification numbers of C1 are 1 and the identification numbers of L2 are 2, the processing unit 12 converts them into (1, -6, 48) and (2, -5, 00), respectively. After all the conversions are completed, the processing unit 12 performs normalization processing using the maximum value and the minimum value, and inputs the normalized value as node information to the graph neural network. Information on the type of an active element (semiconductor) (for a power supply circuit, an operational amplifier circuit or the like) has not been input because it coincides with the correct response data, and the component information of the active element has been set to 0.However, the component information of the active circuit need not be 0, but appropriate component information may be selected.Moreover, GND, IN and OUT were set to 0 in the same manner as in the active element.It was confirmed that the inference accuracy for the test data at the same number of iterations is 98.90% when the inference calculation is performed without changing the conditions different from the conditions in the calculation of FIG. 14.By training the graph neural network by the processing unit 12, it is possible to classify the circuit type only based on the link information. Note that common identification numbers are assigned to the semiconductor elements. When the type of the semiconductor element is the identification number, it agrees with the type of the circuit, and thus the inference accuracy becomes high without the link information having to be trained. Thus, information carried by the semiconductor element is discarded, and information other than the semiconductor element is not included. The processing unit 12 thus updates the component names in the component name list and the combination list with the identification numbers assigned to the respective component names.Modification 2The processing unit 12 may generate a new graph network by simultaneously training the generative network and the identification network in a generative adventitial network, using, as training data, a data set obtained by combining the graph network and the correct response data of characteristics of a plurality of electric circuits respectively added to the electric circuits, and inputting data indicating characteristics similar to the correct response data to the generative network. By combining a graph neural network with a generative adventitial network, circuit plans can be generated or generated from circuit specifications such as desired output signal shapes.The processing unit 12 simultaneously trains a generative network that is a neural network on the side that generates a circuit (generator) and an identification network that is a neural network on the side that determines a circuit (discriminator) in the generative adversarial network. Then, the processing unit 12 trains the graph neural network to increase the power on the generation side and reduce the difference between a circuit serving as teacher data or the output of the circuit and a circuit on the generation side or the output of the circuit. In this way, input data can be generated from the correct response data. That is, when a requested design request is set as correct response data, input data satisfying the correct response data, i.e., a combination of a node and an edge, can be generated.Moreover, not only the output signal but also a plurality of pieces of data such as heat generation or component cost can be used as correct response data to cause the generative adventrial network to be trained.In this case, it is possible to generate a circuit that simultaneously optimizes the signal waveform flowing through each edge, the heat generation at each node, the power at each node, the cost of the entire circuit, or the like.Moreover, since the circuit can be designed in a short time, it is possible to already check the required specifications or the cost in the first design phase.In order to generate a certain waveform at a node that is a circuit component, a node whose characteristic or type is unknown may be specified, the characteristic or type of the component may be predicted, and the waveform may be optimized.Prediction of a characteristic of a component may be realized by generating a node attribute in the graph neural network in the generative adventitial network.The prediction of the component type can be realized by a technique of classifying nodes in the graph neural network.Moreover, a part of the type of the node representing the correct response data of the training data is set as a black box, and the graph neural network is caused to predict the type of the node as self-supervised learning. This also allows prediction of the type of node using the trained graph neural network.Moreover, the information processing device 1 can train a graph neural network by using data for which the calculation of a scaled-up shift pattern has been completed and predicting a voltage or a frequency characteristic of a voltage applied to the component using the trained graph neural network.This can be realized by an existing technology for generating attribute information of a node in the graph neural network in the generative adventitial network. However, since it should not violate Kirchhoff's law, which is a physical limitation, it may be implemented by a limited generative adventrial network.Alternatively, a part of the voltage or the frequency characteristic of the voltage, which is the correct response data of the training data, is set as a black box, and the graph neural network is caused to train to predict the voltage or the frequency characteristic of the voltage as self-supervised learning. This also enables the prediction of the voltage or the frequency characteristic of the voltage with the aid of the trained neural graph network.Moreover, the information processing apparatus 1 can make a circuit depending on a design purpose by predicting connection between existing nodes to generate a certain waveform for an edge to be wiring in the circuit.This corresponds to edge prediction (link prediction) in a graph neural network, and after a graph network is created based on the present embodiment, prediction can be performed with an existing technique using the graph neural network.Alternatively, a part of the presence or absence of an edge between nodes representing the correct response data of the training data is set as a black box, and the graph neural network is caused to train to predict the presence or absence of an edge between nodes as self-supervised learning. Thus, it is also possible to predict the presence or absence of an edge between nodes of an unknown circuit (graph network) with the aid of a trained graph neural network.For example, with the aid of the graph neural network, it is also possible to predict a current to be applied to a component and the frequency characteristic of the current by using the graph neural network trained with the aid of calculated results for a scaled-up circuit diagram for which circuit simulation is difficult.Specifically, similarly to the above-described case of generating the node attribute in the generative adventrial network, the processing unit 12 assigns, to the node, as training data, a record obtained by combining the graph network and the correct response data, which is a matrix including the feature amount obtained by assigning a voltage or a frequency characteristic of a voltage to each node in the graph network as an element of the node attribute. Then, as a generative adventrial network for predicting the voltage or the frequency characteristic of the voltage, a relationship between a graph network generated from a circuit diagram and the voltage or the frequency characteristic of the voltage may be trained by a graph neural network, and the graph neural network may be used for predicting the voltage or the frequency characteristic of the voltage at a part of or all nodes in the graph network that is not used for the training.The generative adventrial network includes a generative network that hide a calculated result as training data and predicts the voltage or frequency characteristic of the voltage, and an identification network that identifies the correctness of the generated prediction. In the generative adventitial network, the generative network and the identification network are trained simultaneously to reduce a difference between the identification result and a calculated result that is training data.Alternatively, a part of a stream and a frequency characteristic of a stream, which are the correct response data of the training data, is set as a black box, and the graph neural network is caused to train to predict the stream and the frequency characteristic of the stream as self-supervised learning. This also enables prediction of the current and frequency characteristic of the current of an unknown circuit (graph network) using the trained graph neural network.Moreover, the processing unit 12 may train the graph neural network to predict a component type using a dataset obtained by combining the graph network and data including a component type corresponding to the respective nodes in the graph network as training data, and predicts a component type that is a part or all of the nodes in the graph network that is not used for the training using the graph neural network. It is a matter of constructing a graph network in which input data of a graph neural network is constructed from a circuit diagram and training data in which the output data is set as a type of a component corresponding to a node and performs supervised training using the training data as teacher data. This makes it possible to predict the type of the component to be used for any graph network based on the trained graph neural network.Moreover, the processing unit 12 may train the graph neural network to predict a stream or a frequency characteristic of a stream at the edge using a data set obtained by combining the graph network and correct response data that is a matrix having a feature amount indicating the stream or the frequency characteristic of the stream at each edge of the graph network as an element as training data, and predict the stream or the frequency characteristic of the stream at a part or all edges of the graph network that is not used for the training using the graph neural network.This is to create a graph network in which the input data of the graph neural network is created from a circuit, and training data in which the output data is set as a current or a frequency characteristic of a current corresponding to an edge, and perform supervised learning using the training data as teacher data. This enables prediction of the current or frequency characteristic of the current in any graph network using the trained graph neural network.Moreover, in a case where there is sufficient training data, it is possible to predict a current or frequency characteristic of a current in an arbitrary graph network using an generative adventitial network, self-supervised learning, or the like, similarly to the above-described case of generating the node attribute in the generative adventitial network. Prediction of a current or frequency characteristic of a current in any graph network may be performed using methods such as supervised learning, generative adversarial network, or self-supervised learning.Here, the supervised learning is a data set with few labeling errors, and it is effective when bias and variance of the entire data set are small. A generative adventrial network is effective when the dataset is large and a solution is required as a solution to an inverse problem, for example when optimizing the entire circuit is performed. The self-supervised learning is effective in a case where it is difficult to assign label, a case where there are many label errors, or a case where more computational resources are available due to a large amount of computation.Moreover, a result of the graph neural network obtained by self-supervised learning, that is, a weighting matrix obtained by training may be subjected to transfer learning or fine tuning, and used in combination with, for example, supervised learning, which poses a problem with an insufficient dataset. As described above, the information processing apparatus 1 can change the structure or the training method of the graph neural network, the manner in which the teacher data is given, and the like, depending on the given condition or the obtained result.Moreover, the processing unit 12 may train the graph neural network for predicting the performance or a frequency characteristic of the performance in at least one node or edge using a dataset obtained by combining the graph network and correct response data, which is a matrix having a feature amount indicating the performance or the frequency characteristic of the performance in at least a part or all of nodes or edges included in the graph network as an element, as training data, and predict the performance or the frequency characteristic of the performance in at least one of a part or all of nodes or edges included in the graph network not used for the training, using the graph neural network.Also in this case, the supervised learning of a graph neural network is performed with an input as a graph network and an output as power or a frequency characteristic of the power. The power or frequency characteristic of the power may be inferred from the unknown input of the trained graph neural network obtained as a result.In addition, the input is a graph network, the power or the frequency characteristic of the power is predicted by the generative network, and the graph neural network is trained so as to reduce the difference between the prediction result and the correct response data in the identification network. The power or frequency characteristic of the power may be inferred from the unknown input of the trained graph neural network obtained as a result.Moreover, self-supervised learning of the graph neural network is performed in which an input is a graph network, and an output is trained to hide a part of the power or a frequency characteristic of the power and predict a hidden value. The power or frequency characteristic of the power may be inferred from the unknown input of the trained graph neural network obtained as a result.Conventionally, even in prediction calculations requiring a lot of time, it is possible to predict output in real time without passing through a circuit simulator by using the inference by the graph neural network. For example, by performing inference roughly using the graph neural network and then interpolating the prediction by calculation of a circuit simulator, the number of times of usage of the circuit simulator that require prediction calculation time and calculation cost can be reduced. In addition, a result calculated with the circuit simulator or an actually measured result may be used again as teacher data.Modification 3In Modification 3, it is described that the wiring may have a current direction, the component name list may have a voltage of a specific frequency or a frequency characteristic of a voltage, and the combination list may have a current of a specific frequency or a frequency characteristic of a current.In the direction of current, the netlist of the electrical circuit shown in FIG. 6 yields the following combination list.(1); (IN,A)(2); (A,B)(3); (B,C),(C,D),(D,B)(4); (D, OUT)G-A; (GND,A)G-B; (GND,B)G-C; (GND,C)For example, when writing to (IN,A) in consideration of the writing order (IN,A), this may be defined as the direction of the current from the IN terminal to the A terminal.When applying the component name list and the wiring name list to the graph theory, the component name list is a node and the wiring name list is an edge. If the direction of the current is not taken into account, the graph network becomes a non-directional graph.In contrast, the graph network can be considered as a directed graph by defining the write order. Note that in the case of a circuit including an alternating current, the current direction cannot be correctly defined by the circuit diagram alone.In the case of a directional graph, it is possible to detect the current direction from a time difference of arrival by bringing the circuit into an operating state by circuit simulation or actual measurement, superimposing pulsed signals not affecting this operation, and simultaneously observing a plurality of points of the wiring to be measured with a voltage probe or a current probe. However, in the circuit simulation, detection is difficult because no time difference occurs on the wiring.In this case, the processing unit 12 virtually arranges a small inductance of about a residual inductance (about 1 nH / mm) of the wiring on the wiring, and can estimate the direction of the current from the voltage at both ends of the inductance or the time difference of the current changes.In addition, signals can run bidirectionally during communication. In such a case, if not only (A, B) but also (B, A) are included in the combination list, it is possible to perform the processing as if the signals are bidirectionally running.In graph theory, a combination list may be defined as an adjacence matrix.To form the adjacence matrix, a square matrix having the same number of rows and columns as the maximum value of the elements of the combination list is prepared, the rows and columns of the square matrix are designed to correspond to the combination list, for example, 1 is input to the corresponding part, and all non-corresponding components are set to 0, whereby an adjacence matrix can be prepared.For example, when (5,3) is included in the combination list, an adjacence matrix can be created by setting 5 rows and 3 columns to 1. If the current flow in the electrical circuit is not taken into account, this adjacence matrix is a symmetric matrix, and if (5,3) is in the combination list, 1 is input in 5 rows and 3 columns and 3 rows and 5 columns.On the other hand, when the current direction is taken into account in the circuit, only one of five rows and three columns and three rows and five columns is set to 1, and the other is set to 0. As a result, a symmetric matrix is obtained when the current direction is not taken into account, while an asymmetric matrix is obtained when the current direction is taken into account.Both in the case where the current direction is not taken into account and in the case where the current direction is taken into account, the adjacence matrix is an upper triangular matrix or a lower triangular matrix.Particularly, in the second embodiment described later, since there is no self-loop, the adjacence matrix is an upper triangular matrix in which the diagonal components are 0 or a lower triangular matrix in which the diagonal components are 0.However, even if only one signal is present in a circuit that performs both reception and transmission through a single wiring, such as a bidirectional signal, that is, an antenna or a communication signal, in the circuit, the upper triangular matrix or the lower triangular matrix is not formed, but an asymmetrical matrix is formed.In addition, in the component name list, a voltage having a certain frequency or a frequency characteristic of a voltage in the electric circuit may be set similarly to a component constant or the like.When the frequency characteristic is set in the component name list, it is necessary to convert the frequency characteristic into a discrete value and input a signal as an amplitude at a discrete frequency.For example, if it is desired to input frequency characteristics of 1 MHz to 10 MHz, 10 elements attached to each component need only be set in increments of 1 MHz.In this case, the matrix is set as a matrix having the same number of rows as the number of components and the number of columns for each frequency increment (10 columns in increments of 1 MHz from 1 MHz to 10 MHz).However, it is necessary to set the frequency band or the increments to the same conditions for all the schedules used for processing and all the components in the schedules.It should be noted that although 1 MHz increments from 1 MHz to 10 MHz are illustrated, if the increments are common to all components, the frequency increments may be any increment, such as a logarithm, and need not be uniform.Moreover, the order of the frequencies may be different, and the component name list may be configured as a single matrix by combining it such that the identification number and the frequency characteristic defined by the component type, the model number of the component, or the like are different columns.In addition, a current having a specific frequency or a frequency characteristic of a current can be specified to the combination list. Also in this case, it can be viewed similarly to the frequency characteristic of the voltage.The combination list may be input as a matrix in which the vertical axis includes rows corresponding to the number of combinations in the combination list and the horizontal axis includes columns corresponding to the number of frequency increments (10 columns in 1-MHz increments from 1 MHz to 10 MHz) if the frequency bands and frequencies are the same for all circuit plans and all wirings.However, the combination list is relevant to the combination itself, and it is undesirable to add stream information to the combination list in the same manner as the component name list. Therefore, it is desirable that these frequency characteristics are defined as a single matrix and added to the combination list as attribute information (edge attribute in graph theory) of wiring.Since the combination list includes lines corresponding to the number of combinations, the combination list can also be used for a directed graph, and even in a case where the frequency characteristics of the outgoing stream are different from the frequency characteristics of the incoming stream, they can be processed as different.Moreover, in the combination list, information other than the current or the frequency characteristic of the current, for example, the length of the wiring line or the thickness of the wiring line, may also be input to the single matrix as information of different columns.As described above, the information processing apparatus 1 according to the first embodiment includes the acquisition unit 11 to acquire a netlist of an electric circuit, and the processing unit 12 to extract a component name list and a wiring name list from the netlist, and to generate the component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, the wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, and the combination list including an extracted component name obtained by extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list, and outputting the updated component name list and the combination list.In this way, the information processing apparatus 1 can provide list information in which information deterioration caused by conversion of an electric circuit to a graph network can be suppressed.An information processing device 1 according to the first embodiment includes an acquisition unit 11 for acquiring a netlist of an electric circuit, and a processing unit 12 for extracting a component name list and a wiring name list from the netlist, and a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, and a combination list including an extracted component name obtained by extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list and a wiring name corresponding to the extracted component name, creating the updated component name list and outputting the combination list.In this way, the information processing apparatus 1 can provide list information in which information deterioration caused by conversion of an electric circuit to a graph network can be suppressed. In addition, since the information processing device 1 can suppress an increase in the number of component combinations, it is possible to reduce an increase in the calculation amount and the calculation time required for the processing of the graph neural network using the list information including the combination list.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 outputs the updated component name list and the combination list in which the component names are replaced with unique identification numbers for the respective characteristics of the components. Thus, the information processing device 1 can reduce the amount of information by expressing the list information with a numerical value, and can prevent information deterioration occurring in the conversion of the list information to the graph network. This is because, when the definition obtained by converting the feature of the component into a numerical value is used in reverse, the feature of the component can be determined from the numerical value, that is, the feature of the component and the numerical value are bijective.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 defines a unique identification number for each component type. Thus, the information processing device 1 can reduce the amount of information by expressing the list information with a numerical value, and can prevent information deterioration occurring in the conversion of the list information to the graph network. This is because, when the definition obtained by converting the component type into a numerical value is reversely applied, the component type can be determined from the numerical value, that is, the component type and the numerical value are bijective.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 defines a unique identification number for each model number of the components. Thus, the information processing device 1 can reduce the amount of information by expressing the list information with a numerical value, and can prevent information deterioration occurring in the conversion of the list information to the graph network. This is because, when the definition obtained by converting the model number of the component into a numerical value is used in reverse, the model number of the component can be determined from the numerical value, that is, the component type and the numerical value are bijective.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 replaces a component name in the component name list with a row or a column of a feature amount matrix obtained by one-hot expression of a feature of the component. Thus, the information processing device 1 can calculate the component name in the component name list and the feature of the component in a matrix. This is because, when the definition obtained by converting the feature of the component into the one-hot vector representation is used in reverse, the feature of the component can be determined from the one-hot vector representation.In the information processing device 1 according to the first embodiment, in a case where the electric circuit includes two or more semiconductors, the processing unit 12 changes the element corresponding to the semiconductor in the feature amount matrix to a different value for each semiconductor. Thus, the information processing apparatus 1 can prevent information deterioration occurring in the conversion of the list information to the graph network. This is because the semiconductor can be determined from the element corresponding to the semiconductor by inversely using the definition obtained by converting the semiconductor into the element corresponding to each semiconductor.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 replaces an element corresponding to a passive circuit in the feature amount matrix with a function value calculated by replacing a circuit constant of a component in a function including logarithmization. Thus, the information processing device 1 can reduce the amount of information by expressing the list information with a numerical value, and can prevent information deterioration occurring in the conversion of the list information to the graph network. This is because the circuit constant is a real number larger than 0 and has a bijective relationship with the function including logarithmization, so that the numerical value of the original circuit constant can be calculated from the numerical value after the function is executed from the function including logarithmization.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 may perform both or one of normalization and standardization of the function value. Thus, the information processing device 1 can reduce the amount of information by expressing the list information with a numerical value, and can prevent information deterioration occurring in the conversion of the list information to the graph network. This is because, in the normalization or standardization, the value before normalization or standardization and the value after normalization or standardization are bijective, and thus can be bidirectionally converted.In the information processing apparatus 1 according to the first embodiment, in a case where there are three or more combinations of component names corresponding to a single wiring name in the combination list, the processing unit 12 divides each of the combinations into two combinations. Thus, the information processing device 1 can easily create the adjacence matrix of the graph network from the combination list.In the information processing device 1 according to the first embodiment, in a case where the combination list has three or more component names, the processing unit 12 divides the combination list into lists having two component names.Thus, the information processing apparatus 1 can prevent information deterioration occurring in the conversion of the list information to the graph network.In the information processing apparatus 1 according to the first embodiment, the acquisition unit 11 acquires each of the netlists from two or more electric circuits. The processing unit 12 extracts a component name list from each of the netlists, combines the extracted component name list into a component name list, and removes duplicate component names from the combined component name list. Thus, the information processing apparatus 1 can suppress an increase in the information amount of the component name list.In the information processing device 1 according to the first embodiment, the component name list is a node in a graph network, the wiring name list is an edge in the graph network, and the combination list is an adjacence matrix in the graph network. Thus, the information processing device 1 can use the list information as a graph network.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 refers to a database including a semiconductor as a disturbance source and a terminal number of the semiconductor, performs a search process of continuously searching adjacent components from the electric circuit having a terminal corresponding to the terminal number as a starting point, on condition that the same component is not passed twice or more, extracts a current loop representing the semiconductor, and ends the search process. In this way, the information processing device 1 can search for a semiconductor, a capacitor, a coil, a ground, and a semiconductor loop path.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 determines whether or not there is a component indicating a noise filter in the current loop. In this way, the information processing device 1 can extract a noise filter provided in a current loop which is a path through which a current flows.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 extracts a feature of a semiconductor to be searched and a feature of a current loop indicating the semiconductor from one or more electric circuits including one or more semiconductors, and searches for a semiconductor similar to the semiconductor to be searched using the extracted feature of the semiconductor and the feature of the current loop. In this way, the information processing apparatus 1 can search for similar semiconductors.In the information processing device 1 according to the first embodiment, the processing unit 12 extracts the combination list according to a direction in which a current flows, and generates an adjacence matrix of an asymmetric matrix from the extracted combination list. In this way, the information processing apparatus 1 can also suppress the occurrence of information degradation in a circuit in which the current flow direction is known.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 sets an amplitude of the current between the interconnected components to a real number and sets an amplitude of the current between non-interconnected wirings in the admittance matrix to 0. In this way, the information processing apparatus 1 can also suppress the occurrence of information degradation in a circuit in which the current flow direction is known.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 sets a combination of a node and an edge as input data of a graph neural network. Thus, the information processing device 1 can train a graph neural network using the graph network.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 trains the graph neural network to classify the electric circuit using a data set obtained by combining the graph network and the circuit classification data assigned to each of the plurality of electric circuits as training data, and inputs the graph network not used for the training to the graph neural network to classify the electric circuit. In this way, the information processing device 1 can classify the electric circuits.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 simultaneously trains a generative network and an identification network in a generative adventrial network using a data set obtained by combining the graph network and correct response data of a characteristic of each of a plurality of the electric circuits as training data, and inputs data indicating a characteristic similar to the correct response data to the generative network to generate the graph network that is new.In this way, the information processing apparatus 1 can automatically design an electric circuit corresponding to a new graph network.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 trains the graph neural network to predict a voltage or a frequency characteristic of a voltage to be applied to a node using a data set obtained by combining the graph network and correct response data, which is a matrix having a feature amount obtained by applying a voltage or a frequency characteristic of a voltage to each of the nodes in the graph network as an element, as training data, and predicts the voltage or the frequency characteristic of the voltage in a part or all of the nodes in the graph network that is not used for the training using the graph neural network. In this way, the information processing device 1 can predict the output voltage of the unknown circuit or the frequency characteristic of the output voltage without executing the circuit simulation.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 trains the graph neural network to predict a component type using a dataset obtained by combining the graph network and data including a component type corresponding to each of the nodes in the graph network as training data, and predicts a component type that is a part of or all of the nodes in the graph network that is not used for the training using the graph neural network. In this way, the information processing apparatus 1 can predict the component type.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 trains the graph neural network to predict a stream or a frequency characteristic of a stream at the edge using a data set obtained by combining the graph network and correct response data, which is a matrix having a feature amount indicating the stream or the frequency characteristic of the stream at each edge of the graph network as an element, as training data, and predicts the stream or the frequency characteristic of the stream at a part or all of the edges of the graph network that is not used for the training using the graph neural network.In this way, the information processing device 1 can predict the output voltage or the frequency characteristic of the output voltage of the unknown circuit without executing the circuit simulation.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 trains the graph neural network to predict the performance or a frequency characteristic of the performance in at least one node or an edge using a data set obtained by combining the graph network and correct response data, which is a matrix having a feature amount indicating the performance or the frequency characteristic of the performance in at least a part or all of the nodes or edges included in the graph network as an element, as training data, and predicts the performance or the frequency characteristic of the performance in at least a part or all of the nodes or edges included in the graph network not used for the training using the graph neural network. In this way, the information processing apparatus 1 can predict the output power or the frequency characteristic of the output power of the unknown circuit without executing the circuit simulation.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 trains the graph neural network to predict the presence or absence of an edge between nodes in the graph network using the graph network as training data, and predicts the presence or absence of an edge between nodes in the graph network that is not used for the training using the graph neural network.In this way, the information processing apparatus 1 can predict the presence or absence of an edge between nodes in a graph network that is not used for the training.In the information processing apparatus 1 according to the first embodiment, the processing unit 12 trains a graph neural network to cluster a finite number of electric circuits depending on characteristics thereof using the graph network as training data, and classifies the electric circuits into similar electric circuit groups by clustering graph networks not used for the training using the graph neural network. In this way, the information processing apparatus 1 can classify similar electric circuit groups.An information processing method according to the first embodiment includes executing, by an information processing apparatus 1, acquisition of a netlist of an electric circuit, extraction of a component name list and a wiring name list from the netlist, creation of a component name list updated by adding component names indicating a ground terminal, an input terminal and an output terminal, creation of a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring and an output wiring, extraction of a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list, and creation of a combination list including an extracted component name, outputting the updated component name list and the combination list. In this way, it is possible to provide list information in which information degradation caused by conversion of an electric circuit to a graph network can be suppressed.An information processing method according to the first embodiment includes executing, by an information processing apparatus 1, acquisition of a netlist of an electric circuit, extraction of a component name list and a wiring name list from the netlist, creation of a component name list updated by adding component names indicating a ground terminal, an input terminal and an output terminal, creation of a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring and an output wiring, extraction of a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list, and creation of a combination list, including an extracted component name and a wiring name corresponding to the extracted component name, and outputting the updated component name list and the combination list. In this way, it is possible to provide list information in which information degradation caused by conversion of an electric circuit to a graph network can be suppressed. Further, since an increase in the number of component combinations can be suppressed, an increase in the calculation amount and the calculation time required for the processing of the graph neural network can be reduced using the list information including the combination list.Second EmbodimentFIG. 16 is a block diagram illustrating a configuration example of an information processing apparatus 1A according to a second embodiment. In FIG. 16, an information processing apparatus 1 acquires a netlist of an electric circuit and provides list information in which information deterioration occurs when the electric circuit is converted to a graph network using the acquired netlist can be suppressed. The graph network of the electric circuit is information representing the electric circuit having a node representing a component and an edge representing a wiring line. The graph network also includes information indicating a feature amount of the node and a feature amount of the edge.As illustrated in FIG. 16, the information processing apparatus 1A includes an acquisition unit 11 and a processing unit 12A.The acquisition unit 11 executes a first process of acquiring a netlist of the electric circuit. For example, the information processing apparatus 1 is connected to a computer equipped with a circuit design CAD, and the acquisition unit 11 acquires a netlist created using the circuit design CAD from the computer.Moreover, the acquisition unit 11 may acquire a circuit diagram model of an electric circuit that operates in a circuit simulator and convert the circuit diagram indicated by the circuit diagram model into a netlist.That is, the acquisition of the netlist by the acquisition unit 11 includes the acquisition of the netlist by conversion of the shift schedule.The processing unit 12A adds a component name indicating a two-terminal component to the updated component name list by regarding a component connected to three or more wirings as the number of the two-terminal components equal to the number of the wirings by using a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, and a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring from the updated component name list, removes a component name indicating a component before being viewed as the two-terminal component, connecting the three or more wirings to one terminal of the two-terminal component, connecting other terminals of the two-terminal component through a new wiring, adding a wiring name indicating the new wiring to the updated wiring name list, extracting a component name corresponding to a wiring name in the updated wiring name list from the updated component name list, constructing the combination list including the extracted component name, and outputting the updated component name list and the combination list. Moreover, the processing unit 12A may output an updated component name list and combination list in which the component names are replaced with identification numbers.The information processing device 1A is, for example, a computer connected to an information network.The computer may be a server or client that may be connected to a cloud or the like via an information network, or a self-contained computer that is not connected to the information network. Moreover, it may be a computer used in a closed network environment at a factory, referred to as edge computing.In addition, the information processing device 1A may be a smartphone, a tablet terminal, a PC, or a microcomputer.FIG. 17 is a flowchart illustrating an information processing method according to the second embodiment, and shows a sequence of operations performed by the information processing apparatus 1A. The acquisition unit 11 acquires the netlist (step ST 1D). The processing unit 12A extracts a component name list from the netlist (step ST 2D- 1), and extracts a wiring name list from the netlist (step ST 2D- 2).For example, the processing unit 12A stores all the component names included in the netlist in the component name list, and stores all the wiring names included in the netlist in the wiring name list.Note that either the processing of step ST 2D- 1 or the processing of step ST 2D- 2 may be executed first, or may be executed simultaneously.The processing unit 12A adds the ground wiring, the input wiring, and the output wiring included in the netlist to the component name list as a ground terminal, an input terminal, and an output terminal (step ST 3D- 1). The processing unit 12A removes the ground wiring, the input wiring, and the output wiring from the wiring name list (step ST 3D- 2). Thus, information indicating the ground terminal, the input terminal, and the output terminal remains in the component name list as component information, so that it is possible to suppress information deterioration when the electric circuit is converted to the graph network using the list information including the component name list. Note that either the processing of step ST 3D- 1 or the processing of step ST 3D- 2 may be executed first, or may be executed simultaneously.Subsequently, the processing unit 12 determines whether there is a component connected to three or more wirings using the component name list and the wiring name list (step ST 4D). When there is no component connected to three or more wirings (step ST 4D; NO), the processing proceeds to step ST 5D. In FIG. 17, the processing of step ST 5D, step ST 6D, step ST 7D, step ST 12D, step ST 13D, and step ST 14D is similar to that of step ST 4, step STS, step ST 6, step ST 7, step ST 8, and step ST 9 in FIG. 5, and thus the description thereof is omitted.If there are components connected to three or more wirings (step ST 4D; YES), the processing unit 12A regards the components connected to three or more wirings as a number of components having two terminals equal to the number of wirings (step ST 8D). Subsequently, the processing unit 12A gives a new component name for the two-terminal component (step ST 9D). Then, the processing unit 12A connects three or more wirings to a two-terminal component, and connects the other terminals of the two-terminal component to each other by adding a new wiring (step ST 10D). The processing unit 12A adds the wiring name assigned to the new wiring to the wiring name list (step ST 11D).In this manner, the processing unit 12A connects the component decomposed from one component to two terminals, and gives a new wiring name to the wiring used for each connection. Since the number of the other terminals of each of the two-terminal components is equal to the number of the three or more wirings, the respective terminals and wirings are connected. By performing the conversion in this manner, it is possible to prevent self-loop or multiple pages, and it is possible to prevent information deterioration at the time of converting the electric circuit to the graphene sheet and converting the graphene sheet to the electric circuit.A self-loop occurs, for example, when wiring is performed from one terminal of a semiconductor to another terminal of the same semiconductor without passing through a circuit component, but such wiring may be necessary to define the operation of the semiconductor and occurs in such a case. In the first embodiment, information deterioration occurs because such a condition is discarded, but by being divided into two-terminal components as in the second embodiment, conversion to a graph network can be performed while simultaneously carrying such information.Moreover, multiple pages are generated when a bus is wired from one semiconductor to another semiconductor in a case where a plurality of input terminals are provided to secure a current capacity by a power supply of the like.In the first embodiment, even in this case, information deterioration occurs because such a condition is discarded, but by dividing such information into two-terminal components as in the second embodiment, conversion into a graph network can be performed while simultaneously carrying such information.Similarly to the first embodiment, a component name that each wiring name carries is extracted from the wiring name list updated in step ST 11D, and a combination list of component names is extracted.Similarly to the first embodiment, in a case where a single wiring name carries three or more component names, one wiring is decomposed into a combination of two components.In addition, an identification number is assigned to each component name based on the updated component name list, and the identification number is replaced with an identification number corresponding to each component name in the combination list based on the identification number.Further, the component name list is replaced with an identification number, the component name list replaced with the identification number, and the combination list replaced with the identification number are output, and the processing is completed.FIG. 18 is a circuit diagram illustrating an example (4) of the electric circuit. FIG. 19 is a circuit diagram illustrating an example (5) of the electric circuit. In FIG. 18, in a component A, three wirings are connected (1) between an input terminal "IN" and the component A, (2) between a component B and the component A, and between GND and the component A. The component A is decomposed into three components having two ports, each of which is denoted by A1, A2, A3, for example. In order to connect one terminal of the decomposed components to one terminal of the other decomposed components, A1 and A2, A2 and A3, and A3 and A1 are connected to each other. These are designated, for example, as A1-A2, A1-A3 and A2-A3, respectively. The name G-A3 is also assigned between A3 and GND. Similarly, the component B is decomposed, and the decomposed components and the wiring between the components are named, so that the electric circuit has the structure shown in FIG. 18.The same applies to FIG. 19, and since the components that carry three or more wirings in FIG. 18 are the component A and the component E, each of the components is decomposed, and a name is given to the wiring between the decomposed components. Note that, although the circuit diagram has been set as a processing target for convenience of explanation, a netlist may be similarly processed.The netlist explained in the first embodiment will be explained below. When the component A in the # wiring is searched in the netlist, it can be seen that the component A is routed from the wiring of (1), (2), and GND.Thus, it can be determined that three wirings are connected to the component A, and the component A can be decomposed into a component having two terminals. #Component #Verdrahtung (1); IN,A (2); A,B (3); B,C,D (4); D,OUT GND; A,B,CAs shown in FIG. 18, by dividing the component into the two-terminal component, the component name list becomes "A1, A2, A3, B1, B2, B3, C, D, GND, IN, OUT", and the wiring name list becomes "(1), (2), (3), (4), A1-A2, A2-A3, A1-A3, B1-B2, B2-B3, B1-B3, G-A3, G-B3, G-C".Similarly to the first embodiment, the processing unit 12A adds "IN", "OUT", and "GND" to the component name list, and removes "IN", "OUT", and "GND" from the wiring name list.Similarly, when the components are decomposed into two-terminal components, as shown in FIG. 19, the component name list is "A1, A2, A3, C, D, E1, E2, E3, F, GND, IN, OUT", and the wiring name list is "(1A), (2A), (3A), (4A), (5A), A1-A2, A2-A3, A1-A3, E1-E2, E2-E3, E1-E3, G-A3, G-E3, G-C".For the three-terminal or more components, the combination list of the electric circuits shown in FIG. 18 corresponding to the combination list prepared from the updated wiring name list and the combination list of the two-terminal components is as follows. (1) to (4) G-C, G-A3, and G-B3 are created from a netlist, and A1-A2, A1-A3, A1-A3, B1-B2, B2-B3, and B1-B3 are combination lists created from an updated wiring name list.(1); IN,A1(2); A2, B1(3); B2, C, D(4); D, OUTA1-A2; A1, A2A2-A3; A2, A3A1-A3; A1, A3B1-B2; B1, B2B2-B3; B2,B3B1-B3; B1, B3G-A3; GND,A3G-B3; GND,B3G-C; GND,CSimilarly, the following combination list may also be extracted for the circuit diagram shown in FIG. 19.(1A); IN,A1(2A); A2, D(3A); D,C,E1(4A); E2, F(5A); F, OUTA1-A2; A1, A2A2-A3; A2, A3A1-A3; A1, A3E1-E2; E1, E2E2-E3; E2, E3E1-E3; E1, E3G-A3; GND,A3G-E3; GND,E3G-C; GND,CAfter the circuit components having three or more terminals are decomposed as described above, the structure is similar to the first embodiment.The component name list related to the electric circuit shown in FIG. 18 is "A 1, A 2, A 3, B 1, B 2, B 3, C, D, GND, IN, OUT" as described above, and the component name list related to the electric circuit shown in FIG. 19 is "A 1, A 2, A 3, C, D, E 1, E 2, E 3, F, GND, IN, OUT". When these two are combined and the overlap is removed, "A1, A2, A3, B1, B2, B3, C, D, E1, E2, E3, F, GND, IN, OUT" is obtained. When each component name is assigned a different identification number, the combined list looks like, for example.A1→1A2→2A3→3B1→4B2→5B3→6C→7D→8E1->9E2→10E3→11F→12GND→13IN→14OUT→15When the identification numbers are used, the component name list related to the circuit shown in FIG. 18 is "1, 2, 3, 4, 5, 6, 7, 8, 13, 14, 15", and the component name list related to the circuit shown in FIG. 19 is "1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 15".Moreover, also in the combination list, a combination list relating to the circuit shown in FIG. 18 is as follows by dividing a combination having three or more component names into two and replacing each component name with an identification number.(1); (14,1)(2); (2,4)(3); (5,7),(7,8),(8,5)(4); (8,15)A1-A2; (1.2)A2-A3; (2,3)A1-A3; (1,3)B1-B2; (4.5)B2-B3; (5,6)B1-B3; (4,6)G-A3; (13.3)G-B3; (13.3)G-C; (13.7)In addition, the combination list regarding the circuits shown in FIG. 19 is as follows.(1A); (15.1)(2A); (2.8)(3A); (8.7)(8,9),(7.9)(4A); (10,12)(5A); (12,15)A1-A2; (1.2)A2-A3; (2,3)A1-A3; (1,3)E1-E2; (9.10)E2-E3; (10,11)E1-E3; (9.11)G-A3; (13.3)G-E3; (13,11)G-C; (13.7)As an output result of the processing unit 12A, the component name list related to the circuit shown in FIG. 18 is "1, 2, 3, 4, 5, 6, 7, 8, 13, 14, 15", and the combination list is "(14, 1) (2, 4) (5, 7) (7, 8) (8, 5) (8, 15) (1, 2) (2, 3) (1, 3) (4, 5) (5, 6) (4, 6) (13, 3) (13, 3) (13, 7)". Moreover, the component name list related to the circuit shown in FIG. 19 is "1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 15", and the combination list is "(15, 1) (2, 8) (8, 7) (8, 9), (7, 9) (10, 12) (12, 15) (1, 2) (2, 3) (1, 3) (9, 10) (10, 11) (9, 11) (13, 3) (13, 11) (13, 7)".In a component of a circuit, particularly a semiconductor, an operation can be controlled by short-circuiting one terminal of the semiconductor and another terminal of the same semiconductor through wiring. The electric circuit having this structure has a self-loop in which the wiring comes out of itself and returns to itself.However, it is possible to create a combination list relating to the electric circuit with the self-loop from the netlist, but it is not possible to convert the combination list with the self-loop to the original netlist. This is because information deterioration occurs in converting the netlist to the combination list. On the other hand, it is possible to eliminate the wiring which becomes the self-loop by performing the division into the components of three or more elements as described above. Thus, the information processing apparatus 1A according to the second embodiment can create a combination list related to an electric circuit having no self-loop using a netlist related to an electric circuit having self-loop. Consequently, the combination list can be converted into the netlist without causing information degradation.In an electric circuit to which a power supply having a large current is connected, for example, wirings connected to the same power supply may be connected to a plurality of terminals of a semiconductor to distribute the current.Further, there is an electric circuit including a semiconductor in which a power supply for pull-up or a signal for control is connected to a plurality of terminals.Since these connection relationships are multiple pages, in a case where the multiple pages are included in the combination list, no information about the individual pages remains, and the combination list cannot be returned to the netlist, similarly to the self-loop. Therefore, it is considered that information deterioration has occurred.On the other hand, in the information processing apparatus 1A according to the second embodiment, even an electric circuit having multiple pages can return the combination list to the original netlist. Thus, it is possible to convert the netlist into the combination list and inversely convert the combination list into the netlist without causing any deterioration in information.FIG. 20 is a schematic diagram illustrating an example (1) of an electric circuit and a graph network according to the second embodiment. The electric circuit shown in FIG. 20 includes a switching power supply U 1, and when a voltage is applied between the input terminal and the ground GND, another voltage is output between the output terminal and the ground GND. The result of extracting the component list and the combination list from the netlist with respect to the electric circuit is referred to as a graph. In the electric circuit illustrated in FIG. 20, the graph cannot be converted into a circuit diagram. In particular, since the information of the wiring lines gray-shown in the upper part of FIG. 20 is absent, it is considered that information deterioration occurred in the conversion of the graph.FIG. 21 is a schematic diagram illustrating an example (2) of an electric circuit and a graph network according to the second embodiment. As illustrated in the first embodiment, the graph shown in FIG. 21 is configured by providing the input terminal, the output terminal, and the ground terminal in the component name list. It is to be noted that the circuit diagram has a similar structure as in FIG. 20.However, it is to be noted that the line between "IN" and "U 1" in the lower graph of FIG. 21 is a multi-side, and also in the line from "U 1" to "OUT", there is a line passing through L 1 and a line not passing through L 1, and the circuit diagram and the graph are not the same. In many cases where the graph is used, some information degradation is allowed, and therefore the method of the first embodiment is more effective than the conventional method. However, the shift schedule is not completely reversibly converted from the graph.FIG. 22 is a schematic diagram illustrating an example (3) of an electric circuit and a graph network according to the second embodiment. When the processing unit 12A decomposes a component having three or more terminals in the electric circuit into components having two terminals, the electric circuit has a structure in which the components having two terminals are connected to each wiring, as illustrated in FIG. 22. That is, the two-terminal components in the electric circuit are all connected to each other, so that the graph and the circuit diagram can be reversibly converted.The disassembly of the components as described above has an advantage that the graph and the circuit diagram can be converted reversibly, but it is necessary to take into account the wiring connecting the disassembled components. That is, since the necessary information or the calculation amount increases with the number of wirings connecting the decomposed components, it is not necessarily excellent compared to the first embodiment. Therefore, it is desirable to select and use the information processing method according to the first embodiment or the information processing method according to the second embodiment depending on the inference accuracy required for the graph neural network or the allowable calculation amount.Also in the second embodiment, the processing unit 12A can remove a divided node and a wiring connected to the node unless a self loop or multiple pages are generated. For example, in a case where it can be determined that there is no information about the multiple pages or the self loop itself, the node and the wiring connected to the node can be removed. By removing in this manner, not only the processing can be expedited, but also the inference accuracy of the graph neural network can be improved because unnecessary information is not involved.FIG. 23 is a graph illustrating an example of a calculation result of inference accuracy by the information processing apparatus 1A according to the second embodiment, and shows a result in a case where components of three or more ports are decomposed.For comparison with the result shown in FIG. 15 in which the inference accuracy is the highest, only the identification number of the component is assigned to the node, and only the connection information between the identification numbers is input to the edge. Similar to Fig. 15, the correct response data is a classification problem of classifying nine circuits by type.The training including the circuit constants was performed with the same graph neural network as the graph neural network with which the result shown in FIG. 15 was obtained, and the inference of the classification was performed with the graph neural network after the training. The inference accuracy is thus 95.32% and is thus 3.58% below the result shown in FIG. 15. This is because training is performed by including the relationship between the two-port components obtained by the division, and the number of training data is expected to be small to determine these unknowns. As described above, the information processing method of the second embodiment is a method suitable for the case where a high lossless transformation is required between the netlist and the graph, but the information processing method of the first embodiment may be superior in some cases.On the other hand, the weighting of the calculated edge cannot be trained when correct information is obtained in advance by circuit simulation or the like, and the update may be stopped in training the graph neural network. In this case, it is possible to improve the inference accuracy of the graph neural network even when the processing of decomposing the three- or more-terminal component into a two-terminal component is performed.In this way, it is desirable to use the information processing method according to the first embodiment and the information processing method according to the second embodiment depending on the data or the purpose of use that can be prepared.In the above example, the correct response data is used as a circuit type, but the frequency characteristic of the output waveform or the like obtained by the circuit simulator may be used as training data. In this case, it is possible to generate as many teacher data as is necessary for training with the aid of the circuit simulator.If the correct response data is changed by predicting a signal waveform of a specific wiring in the circuit, predicting the area of the eye pattern of the signal waveform, predicting the heat generation of a specific part of the circuit, predicting the cost of components necessary for the construction of the circuit, or predicting the frequency characteristic of electromagnetic interference arriving at the output terminal without being limited to the output waveform, it is possible to freely train the graph neural network according to the purpose of use.Moreover, by creating and using attribute information data of an edge in combination with the circuit simulation, similar calculations as described above can also be performed in a directed graph including the directivity of the current.It is also possible to assign a frequency characteristic of a voltage to a node or to assign a frequency characteristic of a current to an edge. However, as described in Modification 3, when the frequency data is input to the column of the attribute information of the node or the edge of the graph neural network by one frequency, a large matrix is obtained, and a large calculation time and a large amount of calculation are required for the training. In such a case, although a high-performance computer having a large working memory can be prepared for training, for example, by training information obtained by converting frequency characteristics into a vector size by graph embedding, even if the input data includes a scaled-up matrix having frequency characteristics in a large circuit, a computational amount thereof can be reduced, and it is possible to train a graph neural network without using a high-performance computer.In addition, in an electric circuit having a plurality of components connected in parallel to a single wiring, the number of combinations of components increases even in the information processing method according to the second embodiment explained above. That is, when the electric circuit has a plurality of components connected in parallel to a single wiring, the combination of the components corresponding to each other in the combination list increases approximately in proportion to the square of the number of components connected in parallel to the wiring. For this reason, the amount of calculation required for the current loop search increases exponentially, and the search time also increases.Accordingly, the information processing apparatus 1A can create a combination list including wiring names and component names in order to suppress an increase in the number of combinations of component names for a scaled-up circuit in which a plurality of components are connected in parallel to a single wiring. Similar to the first embodiment, for example, the processing unit 12A creates a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, and creates a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring. Then, as described above, the processing unit 12A adds a component name indicating a two-terminal component to the updated component name list by regarding components connected to three or more wirings as two-terminal components having the same number as the number of wirings, and removes a component name indicating a component before being viewed as a two-terminal component from the updated component name list. Moreover, the processing unit 12A defines a connection relationship in which three or more wirings are connected to a single terminal of the two-terminal component and the other terminal of the two-terminal component is connected by a new wiring, and adds a wiring name indicating the new wiring to the updated wiring name list. Thereafter, the processing unit 12A extracts a component name corresponding to a wiring name in the updated wiring name list from the updated component name list, creates a combination list including the extracted component name and the corresponding wiring name, and outputs the updated component name list and the combination list. That is, the combination list includes the component name corresponding to the wiring name in the updated wiring name list and the corresponding wiring name. The graph network converted from the list information including the combination list has characteristics that the component name and the wiring name are represented by nodes, and as shown in FIG. 10, a node adjacent to a node having an arbitrary component name is a node of a wiring name. Thus, the number of combinations can be set to a number proportional to the first power of the number of components.As described above, in the information processing apparatus 1A according to the second embodiment, the processing unit 12A adds a component name indicating a two-terminal component to the updated component name list by regarding a component connected to three or more wirings as the number of the two-terminal components equal to the number of the wirings, by using a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, and a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring removes a component name indicating a component before being viewed as the two-terminal component, from the updated component name list, connects the three or more wirings to one terminal of the two-terminal component, connects other terminals of the two-terminal component through a new wiring, adds a wiring name indicating the new wiring to the updated wiring name list, extracts a component name corresponding to a wiring name in the updated wiring name list from the updated component name list, creates the combination list including the extracted component name, and outputs the updated component name list and the combination list.In this way, the information processing apparatus 1A can provide list information in which information deterioration caused by conversion of an electric circuit to a graph network can be suppressed. By defining the two-terminal component, it is also possible to prevent self-loop or multiple pages, and it is possible to suppress information deterioration that occurs when the electric circuit is converted into a graphene net and the graphene net is converted into an electric circuit.In the information processing apparatus 1A according to the second embodiment, the processing unit 12A creates a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, and a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, adds, to the updated component name list, a component name indicating a two-terminal component by regarding a component connected to three or more wirings as a two-terminal component whose number is equal to the number of wirings, and removes a component name indicating a component before being viewed as the two-terminal component from the updated component name list. A connection relationship in which three or more wirings are connected to one terminal of a two-terminal component and another terminal of the two-terminal component is connected through a new wiring is defined, a wiring name indicating a new wiring is added to an updated wiring name list, a component name corresponding to a wiring name in the updated wiring name list is extracted from the updated component name list, a combination list including the extracted component name and the corresponding wiring name is created, and the updated component name list and the combination list are output. In this way, the information processing apparatus 1A can provide list information in which information deterioration caused by conversion of an electric circuit to a graph network can be suppressed. In addition, since the information processing device 1A can suppress an increase in the number of component combinations, the amount of calculation and the calculation time required for the processing of the graph neural network using the list information including the combination list can be reduced.In the information processing apparatus 1A according to the second embodiment, the processing unit 12A outputs the updated component name list and the combination list in which the component names are replaced with unique identification numbers for the respective component feature. Thus, the information processing device 1A can reduce the amount of information by expressing the list information with a numerical value, and can prevent information deterioration that occurs in the conversion of the list information to the graph network.An information processing method according to the second embodiment includes executing, by the information processing apparatus 1A, adding, to the updated component name list, component names indicating a two-terminal component by regarding a component connected to three or more wirings as a number of two-terminal components equal to a number of wirings, removing a component name indicating a component before being viewed as the two-terminal component from the updated component name list, connecting each of the three or more wirings to a single terminal of the two-terminal component, connecting other terminals of the two-terminal component through a new wiring, and adding a wiring name indicating the new wiring to the updated wiring name list, extracting a component name corresponding to a wiring name in the updated wiring name list from the updated component name list, and creating a combination list including the extracted component name and outputting the updated component name list and the combination list. In this way, by defining the two-dimensional component, it is possible to prevent self-loop or multiple pages, and it is possible to prevent information deterioration at the time of converting the electric circuit to the graphene sheet and converting the graphene sheet to the electric circuit.In the information processing apparatus 1A according to the second embodiment, the processing unit 12A removes a node from the two-terminal component as long as no self-loop or multiple pages are generated in the wiring connecting the two-terminal components. Thus, the information processing device 1A can provide list information in which information deterioration at the time of creating the graph information of an electric circuit can be suppressed.An information processing method according to the second embodiment includes executing, by the information processing apparatus 1A, creating a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal and a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, adding, to the updated component name list, component names indicating a two-terminal component by regarding a component connected to three or more wirings as a number of two-terminal components equal to a number of wirings, removing a component name indicating a component before being viewed as the two-terminal component, from the updated component name list, connecting each of the three or more wirings to a single terminal of the two-terminal component, connecting other terminals of the two-terminal component through a new wiring, and adding a wiring name indicating the new wiring to the updated wiring name list, extracting a component name corresponding to a wiring name in the updated wiring name list from component names in the updated component name list, creating a combination list including the extracted component name, and outputting the updated component name list and the combination list.In this way, it is possible to provide list information in which information degradation caused by conversion of an electric circuit to a graph network can be suppressed.In addition, by defining the two-terminal component, it is also possible to prevent self-loop or multiple pages, and it is possible to suppress information deterioration that occurs when the electric circuit is converted into a graph network and the graph network is converted into an electric circuit.The information processing method according to the second embodiment includes executing, by the information processing apparatus 1A, extracting a component name corresponding to a wiring name in the updated wiring name list from component names in the updated component name list, creating a combination list including the extracted component name and the corresponding wiring name list, and outputting the updated component name list and the combination list. In this way, it is possible to provide list information in which information degradation caused by conversion of an electric circuit to a graph network can be suppressed. Further, since an increase in the number of component combinations can be suppressed, an increase in the calculation amount and the calculation time required for the processing of the graph neural network can be reduced using the list information including the combination list.Note that combinations of the individual embodiments, modifications of any components of the individual embodiments, or omissions of any components in the individual embodiments are possible.INDUSTRIAL APPLICABILITYAn information processing apparatus according to the present disclosure may be used, for example, to design a circuit using a circuit design CAD and a circuit board design CAD.LIST OF REFERENCE CHARACTERS1, 1A: information processing apparatus, 11: acquisition unit, 12, 12A: processing unit, 100: input interface, 101: output interface, 102: processing circuit, 103: processor; 104: random access memoryReferences included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedJP 2007-128383 A

[0003]

Claims

An information processing apparatus comprising: an acquisition unit to acquire a netlist of an electric circuit; and a processing unit to extract a component name list and a wiring name list from the netlist, and create a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, and a combination list including an extracted component name obtained by extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list, and output the updated component name list and the combination list.The information processing apparatus according to claim 1, wherein the processing unit adds, to the updated component name list, component names indicating a two-terminal component by regarding a component connected to three or more wirings as an equal number of two-terminal components as a number of wirings, removes, from the updated component name list, a component name indicating a component before being viewed as a two-terminal component, each of the three or more wirings connects to a terminal of the two-terminal component, connects other terminals of the two-terminal component through a new wiring, adds, to the updated wiring name list, a wiring name indicating the new wiring, a component name corresponding to a wiring name in the updated wiring name list, extracted from the updated component name list, and the combination list including the extracted component name is created, and outputs the updated component name list and the combination list.An information processing apparatus comprising: an acquisition unit to acquire a netlist of an electric circuit; A processing unit to extract a component name list and a wiring name list from the netlist and create a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal, a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring, and a combination list including an extracted component name obtained by extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list and a wiring name corresponding to the extracted wiring name, and output the updated component name list and the combination list.The information processing apparatus according to claim 3, wherein the processing unit adds, to the updated component name list, component names indicating a two-terminal component by regarding a component connected to three or more wirings as an equal number of two-terminal components as a number of wirings, removes, from the updated component name list, a component name indicating a component before being viewed as a two-terminal component, each of the three or more wirings connects to a terminal of the two-terminal component, connects other terminals of the two-terminal component through a new wiring, adds, to the updated wiring name list, a wiring name indicating the new wiring, a component name corresponding to a wiring name in the updated wiring name list, from the updated component name list, the combination list including the extracted component name and the wiring name corresponding to the extracted component name is created, and the updated component name list and the combination list are output.The information processing apparatus according to any one of claims 1 to 4, wherein the processing unit outputs the updated component name list and the combination list in which a component name is replaced with a unique identification number common to each of features of components.The information processing apparatus according to claim 5, wherein the processing unit defines the unique identification number common to each of types of components.The information processing apparatus according to claim 5, wherein the processing unit defines the unique identification number common to each of model numbers of components.The information processing apparatus according to claim 5, wherein the processing unit replaces a component name in the updated component name list with a row or a column of a feature amount matrix obtained by one-hot expression of a feature of the component.The information processing apparatus according to claim 8, wherein in a case where the electric circuit includes two or more semiconductor elements, the processing unit changes elements corresponding to the semiconductor elements in the feature amount matrix to different values, respectively.The information processing apparatus according to claim 8, wherein the processing unit replaces an element corresponding to a passive circuit in the feature amount matrix with a function value calculated by substituting a circuit constant of a component into a function including logarithmization.The information processing apparatus according to claim 10, wherein the processing unit performs both or one of normalization and standardization to the function value.The information processing apparatus according to claim 5, wherein in a case where there are three or more combinations of component names corresponding to a single wiring name in the combination list, the processing unit divides each of the combinations into two combinations of component names.The information processing apparatus according to any one of claims 1 to 5, wherein the acquisition unit acquires each of the netlists from two or more electric circuits, and the processing unit extracts a component name list from the respective netlist, combines the extracted component name list into a single component name list, and removes duplicate component names of the component names from the combined one single component name list.The information processing apparatus according to claim 2, wherein the processing unit removes a node from the two-terminal component unless a self-loop or multiple pages are generated in the wiring connecting the two-terminal component.The information processing apparatus according to any one of claims 1 to 5, wherein the component name list is a node in a graph network, the wiring name list is an edge in the graph network, and the combination list is an adjacence matrix in the graph network.The information processing apparatus according to claim 15, wherein the processing unit refers to a database including a semiconductor element as a disturbance source and a terminal number of the semiconductor element, performs a search process of continuously searching for adjacent components from the electric circuit having a terminal corresponding to the terminal number as a starting point under a condition that a same component among the components as the node is not passed twice or more, extracts a current loop representing the semiconductor element, and ends the search process.The information processing apparatus according to claim 16, wherein the processing unit determines whether or not a noise filter is present in the current loop.The information processing apparatus according to claim 16, wherein the processing unit extracts a feature of the semiconductor element as a search target and a feature of the current loop indicating the semiconductor element from one or a plurality of the electric circuits including one or more of the semiconductor elements, and searches for the semiconductor element similar to the semiconductor element as the search target using the extracted feature of the semiconductor element and the feature of the current loop.The information processing apparatus according to claim 16, wherein the processing unit extracts the combination list according to a direction in which a current flows, and generates an adjacence matrix of an asymmetric matrix from the extracted combination list.The information processing apparatus according to claim 19, wherein the processing unit sets an amplitude of the current to a real number between the interconnected components, and sets an amplitude of the current to 0 between non-interconnected wirings in the adjacence matrix.The information processing apparatus according to claim 15, wherein the processing unit sets a combination of a node and an edge as input data of a graph neural network.The information processing apparatus according to claim 21, wherein the processing unit trains the graph neural network to classify the electric circuit using a dataset obtained by combining the graph network and circuit classification data assigned to each of a plurality of the electric circuits as training data, and classifies the electric circuit into the graph neural network by inputting the graph network not used for the training.The information processing apparatus according to claim 21, wherein the processing unit simultaneously trains a generative network and an identification network in a generative adventrial network using a dataset obtained by combining the graph network and correct response data of a characteristic of each of a plurality of the electric circuits as training data, and generates the graph network that is new by inputting data indicating a characteristic similar to the correct response data into the generative network.The information processing apparatus according to claim 21, wherein the processing unit trains the graph neural network to predict a voltage or a frequency characteristic of a voltage to be applied to a node using a data set obtained by combining the graph network and correct response data that is a matrix having a feature amount obtained by applying a voltage or a frequency characteristic of a voltage to each of nodes in the graph network as an element as training data, and predicts the voltage or the frequency characteristic of the voltage in a part of or in all of nodes in the graph network that is not used for the training using the graph neural network.The information processing apparatus according to claim 21, wherein the processing unit trains the graph neural network to predict a component type using a dataset obtained by combining the graph network and data including a component type corresponding to each of nodes in the graph network as training data, and predicts a component type that is a part of or all of nodes in the graph network that is not used for the training using the graph neural network.The information processing apparatus according to claim 21, wherein the processing unit trains the graph neural network to predict a stream or a frequency characteristic of a stream at the edge using a data set obtained by combining the graph network and correct response data that is a matrix having a feature amount indicating the stream or the frequency characteristic of the stream at each of edges of the graph network as an element as training data, and predicts the stream or the frequency characteristic of the stream at a part or all of edges of the graph network that is not used for the training using the graph neural network.The information processing apparatus according to claim 21, wherein the processing unit trains the graph neural network to predict a power or a frequency characteristic of power in at least one of a node or an edge using a dataset obtained by combining the graph network and correct response data that is a matrix having a feature amount that trains the power or the frequency characteristic of the power in at least a part or all of nodes included in the graph network as an element as training data, and predicts the power or the frequency characteristic of the power in at least one of a part or all of nodes or edges included in the graph network not used for the training using the graph neural network.The information processing apparatus according to claim 21, wherein the processing unit trains the graph neural network to predict presence or absence of an edge between nodes in the graph network using the graph network as training data, and predicts presence or absence of an edge between nodes in the graph network that is not used for the training using the graph neural network.The information processing apparatus according to claim 21, wherein the processing unit trains the graph neural network to cluster the electric circuit into a finite number depending on characteristics of the electric circuit using the graph network as training data, and classifies the electric circuit into a similar electric circuit group by clustering the graph network not used for the training using the graph neural network.An information processing method comprising executing, by an information processing apparatus: acquiring a netlist of an electric circuit; extracting a component name list and a wiring name list from the netlist; creating a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal; creating a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring; extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list, and creating a combination list including the extracted component name; and outputting the updated component name list and the combination list.The information processing method according to claim 30, wherein the method comprises executing, by the information processing apparatus: adding, to the updated component name list, component names indicating a two-terminal component by regarding a component connected to three or more wirings as an equal number of two-terminal components as a number of wirings; removing a component name indicating a component before being viewed as a two-terminal component from the updated component name list; connecting each of the three or more wirings to a single terminal of the two-terminal component, connecting other terminals of the two-terminal component through a new wiring, and adding a wiring name indicating the new wiring to the updated wiring name list; extracting a component name corresponding to a wiring name in the updated wiring name list from the updated component name list, and creating the combination list including the extracted component name; and outputting the updated component name list and the combination list.An information processing method comprising executing, by an information processing apparatus: acquiring a netlist of an electric circuit; extracting a component name list and a wiring name list from the netlist; creating a component name list updated by adding component names indicating a ground terminal, an input terminal, and an output terminal; creating a wiring name list updated by removing wiring names indicating a ground wiring, an input wiring, and an output wiring; extracting a component name corresponding to a wiring name in the updated wiring name list from the component names in the updated component name list, and creating a combination list including the extracted component name and a wiring name corresponding to the extracted component name; outputting the updated component name list and the combination list.The information processing method according to claim 32, wherein the method comprises executing, by the information processing apparatus: adding, to the updated component name list, component names indicating a two-terminal component by regarding a component connected to three or more wirings as an equal number of two-terminal components as a number of wirings; removing a component name indicating a component before being viewed as a two-terminal component from the updated component name list; connecting each of the three or more wirings to a single terminal of the two-terminal component; connecting other terminals of the two-terminal component through a new wiring; and adding a wiring name indicating the new wiring to the updated wiring name list, extracting a component name corresponding to a wiring name in the updated wiring name list from component names in the updated component name list, and creating a combination list including the extracted component name and a wiring name corresponding to the extracted component name, and outputting the updated component name list and the combination list.The information processing method according to any one of claims 30 to 33, wherein the method comprises executing, by the information processing apparatus: outputting the updated component name list and the combination list in which a component name is replaced with a unique identification number common to each of features of components.

Images