Semiconductor device, method for controlling a semiconductor device, and method for manufacturing a semiconductor device

Abstract

A semiconductor device according to the present invention comprises: a drift layer having a first pillar region of a first conductivity type and a second pillar region of a second conductivity type arranged alternately; a base region of the second conductivity type arranged in the drift layer on a first main surface side; a gate insulating layer arranged in contact with the base region; a gate electrode arranged through the gate insulating layer; a carrier storage region of the first conductivity type arranged between the base region and the second pillar region;and an emitter region of the first conductivity type arranged in a surface layer of the base region on the first main surface side, wherein a lower end of the second pillar region, which is an end region on the second main surface side, is located closer to the second main surface side than a lower end of the first pillar region, which is an end region on the second main surface side, and wp3 > wp2 and wp1 > wp2, where wp1 denotes the width of an upper end of the second pillar region, which is an end region on the first main surface side, wp2 denotes the width of the second pillar region at the same position as a lower end of the first pillar region, and wp3 denotes the width of the lower end of the second pillar region.;

Description

BACKGROUND OF THE INVENTIONField of the InventionThe present invention relates to a semiconductor device, a method for controlling a semiconductor device, and a method for manufacturing a semiconductor device.Description of the Prior ArtA superjunction structure in which n-type pillar regions and p-type pillar regions are alternately arranged in plan view is a structure mainly used for a drift layer of a power metal oxide semiconductor field effect transistor (MOSFET). By narrowing the pitch dimensions of the n-type pillar regions and the p-type pillar regions, the density of the n-type pillar regions can be increased (the resistance of the n-type pillar regions can be decreased). The power MOSFET using a superjunction structure can achieve lower turn-on voltages than those of the conventional power MOSFETs (power MOSFETs without using the superjunction structure) at the same breakdown voltage.Superjunction IGBTs (Insulated Gate Bipolar Transistors) obtained by applying a superjunction structure to IGBTs exhibit an improved injection enhanced (IGBT) effect by utilizing holes injected from p-type collector layers on the back surfaces than conventional IGBTs (IGBTs without using a superjunction structure), so that the conductivity modulation is improved. This awakens expectation directed to further reduction of the turn-on voltage.A technology has been disclosed in which the movement of holes injected from a p-type collector layer on the back surface is restricted by disposing an n-type carrier storage region between an n-type drift region and a p-type base region in a conventional IGBT so as to achieve a decrease in turn-on voltage (see, for example, Patent Document 1).It is also known to enable improvement of the conflict-of-goal relationship between the collector-emitter turn-on voltage Vce (sat) and the turn-off losses Eoff in a super junction IGBT more than those in conventional IGBTs (see, for example, Patent Document 2).Also known is a superjunction structure in which n-type pillar regions and p-type pillar regions are vertically formed in the depth direction (for example, see Non-Patent Document 1).Prior Art DocumentPatent DocumentsPatent Document 1: Japanese Patent JP 3 288 218 B2Patent Document 2: Japanese Unexamined Patent Application Publication JP 2009-525 610 ANon-Patent DocumentNon-Patent Document 1: T. Tamaki et al., "Vertical Charge Imbalance Effect on 600 V-class Trench-Filling Superjunction Power MOSFETs", Proceedings of the 23rd International Symposium on Power Semiconductor Devices & IC's, May 23-26, 2011, pp. 308-311SummaryProblem to be Solved by the InventionHowever, Patent Documents 1 and 2 and Non-Patent Document 1 do not disclose a superjunction structure that can make a decrease in on-voltage compatible with the robustness of the breakdown voltage. For example, in Patent Document 2, p-type pillar regions are electrically connected to a p-type base region, and holes injected from the back surface in the on state are ejected to an emitter terminal through the p-type pillar regions and the p-type base region.Consequently, a decrease in the turn-on voltage requires an increase in the density of the n-type pillar regions by narrowing the pitch amounts in arranging the n-type pillar regions and the p-type pillar regions.Narrowing the distance dimensions is limited by the manufacturing technology, however. In addition, increasing the density of the n-type pillar regions creates a conductive state that causes electrons to disproportionately flow through the n-type pillar regions and causes holes to disproportionately flow through the p-type pillar regions. Consequently, there is a limitation in reducing the turn-on voltage.Since a structure in which the n-type pillar regions and the p-type pillar regions are vertically formed in the depth direction exhibits high sensitivity of the element breakdown voltage with respect to the density of the pillar regions as in Non-Patent Document 1, this causes a disadvantage in that the robustness of the breakdown voltage against manufacturing variations is significantly deteriorated.The present invention has been made to solve such problems, and an object thereof is to provide a semiconductor device having a super junction structure that can make the reduction of the on-state voltage compatible with the robustness of the breakdown voltage, a method of controlling a semiconductor device, and a method of manufacturing a semiconductor device.Ways of Solving the ProblemIn order to solve the problems, a semiconductor device according to the present invention has a first main surface and a second main surface facing the first main surface, and includes: a drift layer including a first pillar region of a first conductivity type and a second pillar region of a second conductivity type, the first pillar region and the second pillar region being alternately arranged in a direction parallel to the first main surface and the second main surface; a base region of the second conductivity type, the base region being selectively arranged in the drift layer on the first main surface side; a gate insulating layer arranged in contact with the base region; a gate electrode disposed to face the base region through the gate insulating film; a carrier storage region of the first conductivity type, the carrier storage region being disposed between the base region and the second pillar region; an emitter region of the first conductivity type, the emitter region being selectively disposed in a surface layer of the base region on the first main surface side, wherein a lower end of the second pillar region, which is an end region on the second main surface side, is located closer to the second main surface side than a lower end of the first pillar region, which is an end region on the second main surface side, and wp3>wp2 and wp1>wp2, wherein wp1 denotes the width of an upper end of the second pillar region, which is an end region on the first main surface side, wp2 denotes the width of the second pillar region at the same position as a lower end of the first pillar region, and wp3 denotes the width of the lower end of the second pillar region.Effects of the InventionThe present invention can make a decrease in turn-on voltage compatible with the robustness of the breakdown voltage.The objects, features, aspects and advantages of this invention will become more apparent from the following detailed description and the accompanying drawings.Brief Description of the DrawingsFIG. 1 is a cross-sectional view showing an exemplary structure of a semiconductor device according to Embodiment 1. FIG. 2 illustrates a relation between the ratio of the amount of impurities in a p-type pillar region to the amount of impurities in an n-type pillar region and the breakdown voltage of a semiconductor device. FIG. 3 illustrates a relation between the ratio of the amount of impurities in a p-type pillar region to the amount of impurities in an n-type pillar region and the breakdown voltage of a semiconductor device. FIG. 4 illustrates a relation between the ratio of the amount of impurities in a p-type pillar region to the amount of impurities in an n-type pillar region and the breakdown voltage of a semiconductor device. FIG. 5 illustrates a relation between the ratio of the amount of impurities in a p-type pillar region to the amount of impurities in an n-type pillar region and the breakdown voltage of a semiconductor device. FIG. 6 is a graph showing exemplary electric field strengths in the direction from the first main surface to the second main surface of the semiconductor device. FIG. 7 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 8 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 9 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 10 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 11 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 12 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 13 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 14 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 15 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 16 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 17 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 1. FIG. 18 is a cross-sectional view showing an exemplary structure of a semiconductor device according to a modification of Embodiment 1. FIG. 19 is a cross-sectional view showing an exemplary structure of a semiconductor device according to Embodiment 2. FIG. 20 is a cross-sectional view showing an exemplary structure of a semiconductor device according to a modification 1 of Embodiment 2. FIG. 21 is a cross-sectional view showing an exemplary structure of a semiconductor device according to a modification 2 of Embodiment 2. FIG. 22 is a cross-sectional view showing an exemplary structure of a semiconductor device according to Embodiment 3. FIG. 23 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 3. FIG. 24 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 3. FIG. 25 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 3. FIG. 26 is a cross-sectional view showing an exemplary process for manufacturing the semiconductor device according to Embodiment 3. FIG. 27 is a cross-sectional view showing an exemplary structure of a semiconductor device according to a modification of Embodiment 3. FIG. 28 is a plan view showing an exemplary upper layout of a semiconductor device according to Embodiment 4. FIG. 29 is a cross-sectional view taken along A 1-A 2 in FIG. 28. FIG. 30 is a graph showing an exemplary timing chart of the first gate voltage and the second gate voltage for driving the semiconductor device according to Embodiment 4. FIG. 31 is a graph showing an example delay time dependence of the second gate voltage on the surge voltage and the turn-off losses in the semiconductor device according to Embodiment 4. FIG. 32 is a cross-sectional view showing an exemplary structure of a semiconductor device according to a modification of Embodiment 4.DESCRIPTION OF PREFERRED EMBODIMENTSEmbodiments of the present invention will be described with reference to the drawings. In the embodiments below, the first conductivity type is the n-type and the second conductivity type is the p-type. Like reference numerals are assigned to like areas in the drawings. A termination structure in the surrounding area of a device (a semiconductor device) is not shown, but a cross-sectional structure of a unit cell. A semiconductor substrate to be used in the device may be the one suitably manufactured using the substrate manufacturing technology necessary for manufacturing the device without depending on a method for manufacturing the substrate, such as a wafer manufactured by a magnetic field applied Czochralski method (MCZ), a wafer manufactured by a floating zone method (FZ), or an epitaxial substrate manufactured by a Czochralski method (CZ).The device may be a vertical metal oxide semiconductor field effect transistor (MOSFET) using an n-type drain layer instead of a p-type collector layer on the back surface, or an n-type collector layer may be partially patterned together with the p-type collector layer. Alternatively, the device may be a reverse conducting IGBT having both a MOSFET region and a diode region on the front surface, and in which a p-type collector region is disposed on the back surface of a semiconductor substrate immediately below the MOSFET region and an n-type cathode region is disposed on the back surface of the semiconductor substrate immediately below the diode region.Embodiment 1Structure of Semiconductor Device according to Embodiment 1FIG. 1 is a cross-sectional view showing an exemplary structure of a semiconductor device according to Embodiment 1. the semiconductor device in FIG. 1 is a planar gate type super junction IGBT element manufactured using a silicon-based semiconductor substrate. Although a semiconductor device whose emitter-to-collector breakdown voltage is about 1200 V is specifically described below as an example, the following description is also applicable to super junction IGBT elements having other breakdown voltage values, or to semiconductor devices having other super junction structures.The semiconductor device in FIG. 1 has a first main surface and a second main surface facing the first main surface. The first main surface is a surface on the upper side of the paper plane in FIG. 1, and corresponds to the front surface of the semiconductor device. The second main surface is a surface on the lower side of the paper plane in FIG. 1, and corresponds to the back surface of the semiconductor device.A drift layer 10 includes n-type pillar regions 107 (first first conductivity type pillar regions) and p-type pillar regions 108 (second conductivity type pillar regions) alternately arranged in a direction parallel to the first main surface and the second main surface. P-type base regions 105 are selectively disposed in the drift layer 10 on the first main surface side. N-type emitter regions 103 and p-type body contact regions 104 are selectively disposed in a surface layer of the p-type base regions 105 on the first main surface side. An n-type carrier storage region (CS region) 106 is disposed between the p-type base regions 105 and the p-type pillar regions 108.A gate insulating film 101 is disposed in contact with the p-type base regions 105. A gate electrode 102 is disposed to face the p-type base regions 105 through the gate insulating film 101. A lower end of the p-type second pillar portion 108, which is an end portion on the second main surface side, is located closer to the second main surface side than a lower end of the n-type first pillar portion 107, which is an end portion on the second main surface side. Assuming that wp 1 denotes the width of the upper end of the p-type pillar region 108, which is an end region on the first main surface side, wp 2 denotes the width of the p-type pillar region 108 at the same position (the same depth position) as the lower end of the n-type pillar region 107, and wp 3 denotes the width of the lower end of the p-type pillar region 108, then wp 3>wp 2 and wp 1>wp 2 hold.An n-type bottom layer 109 is disposed on the second main surface side with respect to the drift layer 10. An n-type buffer layer 110 is disposed on the second main surface side with respect to the n-type bottom layer 109. A p-type collector layer 111 is disposed on the second main surface side with respect to the n-type buffer layer 110. A collector electrode 112 is disposed on the second main surface side with respect to the p-type collector layer 111.A plurality of gate electrodes 102 arranged in stripes are arranged above the n-type pillar regions 107. Arranging the gate electrodes 102 in stripes in the depth direction from the paper plane (vertical direction to the paper plane) in FIG. 1, similarly to the p-type pillar regions 108, forms a MOSFET having a planar gate structure.Although FIG. 1 exemplarily shows a structure in which a single gate electrode 102 is disposed above a single n-type pillar region 107, and the pitch dimensions of the n-type pillar region 107 and the gate electrode 102 in the width direction are identical, the widths of the n-type pillar region 107 and the gate electrode 102 in the width direction may be different.Effects of Semiconductor Device According to Embodiment 1Next, the effects of the semiconductor device according to Embodiment 1 will be described.FIGS. 2 to 5 show the relation between the ratio of the amount of impurities in a p-type column region to the amount of impurities in an n-type column region and the breakdown voltage of a semiconductor device. In FIG. 5, the horizontal axis denotes the ratio (Qp / Qn) of the amount (Qp) of impurities in the p-type column region to the amount (Qn) of impurities in the n-type column region, and the vertical axis denotes the breakdown voltage of the semiconductor device. Structures A to C in FIGS. 2 to 4 are super junction structures. The structures A and B are superjunction structures of semiconductor devices according to Comparative Examples, and the structure C is a superjunction structure of the semiconductor device according to Embodiment 1. FIG. 5 illustrates a simulation result regarding the influence of the ratio of the impurities in each of the structures A to C in FIGS. 2 to 4 on the breakdown voltage.FIG. 6 is a graph showing example electric field strengths in the direction (depth direction) from the first main surface to the second main surface of the semiconductor device. The structures A to C in FIG. 6 correspond to the structures A to C in FIGS. 2 to 4.The operations of the semiconductor devices according to the comparative examples will be described. As shown in FIGS. 2 and 3, each of the semiconductor devices according to the comparative examples is a semiconductor device including a drift layer including an n-type pillar region and a p-type pillar region, so that a super junction structure (the structure A or B) is formed.Depletion layers extend from a p-n junction interface between the p-type column region and the n-type column region to the p-type column region and the n-type column region by applying a voltage between a collector electrode as a positive electrode and an emitter electrode as a negative electrode. Here, setting the pitch or impurity concentrations of the p-type column region and the n-type column region so that the depletion layers extending from adjacent column regions may penetrate each other may ensure the breakdown voltage.The breakdown voltage of a semiconductor device depends on the ratio of impurity amounts in a drift layer. When the amount (Qn) of impurities in the n-type column region is equal to the amount (Qp) of impurities in the p-type column region, i.e., Qn= Q, the extension of the depletion layers corresponding to a voltage is maximized, and the breakdown voltage becomes the greatest. In contrast, if one of the amounts of impurities is larger due to variations in the manufacturing processes, i.e., Qn> Q or Qn< Q, the depletion layers do not expand sufficiently and the breakdown voltage decreases.In addition, the sensitivity of the ratio of impurity amounts in a drift layer to a breakdown voltage of a semiconductor device changes in accordance with the shape of a pillar region. For example, when the upper end width and the lower end width (the width of the bottom) of a p-type pillar region are the same and the p-type pillar region is formed in the vertical direction, the sensitivity of the influence of changes in the ratio of impurity amounts in the pillar region on the breakdown voltage is increased.When Qn= Q where the breakdown voltage becomes the greatest, the space charge density in the drift layer becomes nearly zero, the electric field intensity distribution in the depth direction becomes flat, and the breakdown voltage is maximized. Here, the state in which the amount (Qn) of impurities in the n-type column region is equal to the amount (Qp) of impurities in the p-type column region and the balance of the charge amount is achieved is referred to as a charge balance state.In contrast, the state having charge imbalance, in which one of the amount (Qn) of impurities in the n-type column region or the amount (Qp) of impurities in the p-type column region is larger, is referred to as a charge imbalance state. When Qn> Q, the voltage applied to the drift layer at a positive space charge density is maintained. When Qn< Q, the voltage applied to the drift layer at a negative space charge density is maintained. Here, the electric field intensity distribution in the drift layer has a slope corresponding to the redundancy charge amount ΔQ (ΔQ= Q-Qn) in the direction from the first main surface to the second main surface. Consequently, the breakdown voltage in the charge imbalance state is lower than the breakdown voltage in the charge imbalance state.For example, as disclosed in Non-Patent Document 1, a decrease in breakdown voltage can be suppressed by utilizing the redundancy charge amount in the drift layer by forming a p-type pillar region whose lower end width is smaller than its upper end width and which has a shape tapering in the forward direction from the first main surface to the second main surface. This method enables the electric field distribution to have its electric field peak at a depth in the vicinity of almost the center of the charge equilibrium state drift layer (Qn= Q) by not making the redundancy charge amount in the drift layer uniform but reducing the redundancy charge amount in the drift layer in the direction from the first main surface to the second main surface to have a non-uniform redundancy charge amount.Here, when Qn> Q, the position of the electric field peak is shifted to a shallow region (toward the first main surface), whereas when Qn< Q, the position of the electric field peak is shifted to a deep region (toward the second main surface). Consequently, the shape of the electric field intensity distribution does not vary significantly from that in the charge equilibrium state even in the charge imbalance state (no significant variation as in a p-type column region having a vertical shape). As a result, the sensitivity of the ratio of impurity amounts in the drift layer to the breakdown voltage can be reduced.The advantages of reducing the ratio of the impurity amounts in the drift layer to the breakdown voltage of the semiconductor device and improving the breakdown voltage of the semiconductor device as described above are applicable to super junction MOSFET elements. In each of the superjunction MOSFET elements, a carrier storage region serving as a current spreading layer may reduce the JFET resistance occurring between p-type base regions. Since the resistance component cannot be reduced in a bottom layer even in the superjunction MOSFET element, it is difficult to sufficiently reduce the on-resistance. Consequently, forming an n-type buffer region and a p-type collector region on a second main surface side enables bipolar operations, and then forming a carrier storage region can further reduce on-resistance.By making the gate electrode conductive by applying a positive voltage higher than or equal to a threshold voltage of a MOS to the gate electrode, an inversion layer is formed in an area of a p-type base region immediately below the gate electrode. Then, electrons are injected from an emitter electrode to a drift layer through an n-type emitter region and the inversion layer. The electrons injected into the drift layer are shifted toward the second main surface by the electric field, and move toward the collector electrode through the n-type buffer layer and the p-type collector layer.The electrons moved from the first main surface reduce the potential of the n-type buffer layer. Consequently, the intrinsic potential of a p-n junction decreases on the second main surface side, and holes are injected from the p-type collector layer. Here, when the concentration of holes injected from the p-type collector layer is higher than that of an n-type bottom layer and the drift layer, conductivity modulation occurs, so that on-resistance can be reduced.However, as illustrated in FIG. 5, the breakdown voltage value of the semiconductor device using the p-type pillar region having the forward-direction tapered shape (the structure B in FIG. 3 ) is lower than that of the semiconductor device using the p-type pillar region having the vertical shape (the structure A in FIG. 2 ) even in the charge equilibrium state (Qn= Q). This is because the semiconductor device using the p-type pillar region having the vertical shape has a nearly flat electric field intensity distribution in the depth direction, whereas the semiconductor device using the p-type pillar region having the forwardly tapered shape has a vertex in the drift layer in the electric field intensity distribution in the depth direction, and the electric field intensity of each of an upper region and the vicinity of a bottom of the p-type pillar region decreases as shown in FIG. 6.When the upper end of the p-type pillar region is connected to the p-type base region, the holes injected from the p-type collector layer to the n-type buffer layer and the n-type bottom layer in the conductive state are ejected to an emitter electrode when they are through the p-type pillar region and the p-type base region. This weakens the effect of conductivity modulation in the drift layer on the first main surface side and increases the turn-on voltage.Consequently, increasing the upper end width (wp 1) of the p-type pillar region 108 more than the width (wp 2) of the p-type pillar region 108 at the same depth position as the lower end of the n-type pillar region 107 (wp 1>wp 2) in the semiconductor device according to Embodiment 1 (the structure C in FIG. 4 ) causes the sensitivity of the ratio of impurity amounts in the drift layer 10 with respect to the breakdown voltage to be lowered.Further, disposing the n-type bottom layer 109 under the drift layer 10, disposing the lower end of the p-type pillar region 108 closer to second main surface side than the n-type pillar region 107, and increasing the maximum width (wp 3) of the bottom of the p-type pillar region 108 in the n-type bottom layer 109 more than wp 2 (wp 3>wp 2) may increase the electric field strength near the bottom of the p-type pillar region 108 and improve the breakdown voltage. Further, forming the n-type carrier storage region 106 between the upper ends of the p-type pillar regions 108 and the p-type base regions 105 causes holes to be stored (or the IE effect) using the n-type carrier storage region 106 as a potential barrier of the holes injected from the p-type collector layer 111. Consequently, the on-resistance can be reduced.As shown in FIG. 1, the n-type carrier storage region 106 is separated immediately below the center of the gate electrode 102 (at a position corresponding to the center of the gate electrode 102) in the semiconductor device using the planar gate structure. Separating the n-type carrier storage region 106 immediately below the center of the gate electrode 102 may increase an electric field increase at a junction interface between the p-type base regions 105 and the n-type carrier storage region 106 and achieve a desired breakdown voltage.Even if the n-type carrier storage region 106 is separated immediately below the center of the gate electrode 102, the n-type carrier storage region 106 is formed at a position lower than those of the p-type base regions 105 so as to surround the p-type base regions 105, and the planar extents of the n-type carrier storage region 106 (width of the n-type carrier storage region 106 in the direction parallel to the first main surface and the second main surface) are made larger than the planar extents of the p-type base regions 105 (width of the p-type base regions 105 in the direction parallel to the first main surface and the second main surface). Consequently, the breakdown voltage during non-conduction can be maintained without impairing the function of storing carriers during conduction.Forming the n-type carrier storage region 106 and the p-type base regions 105 by ion implantation and diffusion treatment and increasing the impurity concentration of the n-type carrier storage region 106 more than those of the p-type pillar regions 108 separate the p-type base regions 105 from the p-type pillar regions 108 by the n-type carrier storage region 106. As shown in FIG. 1, the p-type pillar regions 108, which are separated from the p-type base regions 105 by the n-type carrier storage region 106, assume a floating state (an electrically floating state).This allows the n-type carrier storage region 106 sandwiched between the p-type pillar regions 108 and the p-type base regions 105 to function as a charge storage layer. However, the p-type pillar regions 108 and the p-type base regions 105 need not always be separated outside an active region, which is an essential part of a device, for example. For example, connecting the p-type pillar regions 108 to the p-type base regions 105 in a region other than the essential region of the device may emit unnecessary carriers generated during operation of the device through contacts of an emitter electrode 100, and improve long-term reliability and robustness of the device.Method of Manufacturing Semiconductor Device according to Embodiment 1Next, wafer processes in the method for manufacturing the semiconductor device according to Embodiment 1 will be described. First, processes necessary for forming the first main surface side will be described with reference to FIGS. 7 to 15, and only processes necessary for mainly manufacturing the essential portion of the device in FIG. 1 will be described here. The thicknesses of an n-type lower epitaxial layer 409 (the n-type bottom layer 109) and an n-type upper epitaxial layer 407 (the drift layer 10), which will be described later, are exemplarily described as thicknesses of super junction IGBT elements belonging to a class having approximately 1200 V breakdown voltage. For example, the following may be appropriately added:A process not directly relevant to the present invention, such as a cleaning treatment process before a gate oxide film, a sintering treatment process on, for example, an intermediate layer and a metal wire, or a passivation film forming process, processes necessary to fabricate a device termination structure, and an assembling process in which a device is cut into dice and the devices cut into dice are assembled into modules, may be appropriately added.First, as shown in FIG. 7, the n-type lower epitaxial layer 409 doped with phosphorus on the order of, for example, about 10 13 cm -3 is formed to a thickness of about 30 to 50 μm on, for example, an n-type silicon single crystal substrate 400 doped with antimony. Then, the upper n-type epitaxial layer 407 doped with phosphorus on the order of, for example, about 10 15 cm -3 is formed to a thickness of about 50 μm to 70 μm on the lower n-type epitaxial layer 409. Thus, a semiconductor wafer in which the n-type lower epitaxial layer 409 and the n-type upper epitaxial layer 407 are formed on the n-type silicon single crystal substrate 400 is prepared.Although an n-type substrate is exemplified as a silicon single crystal substrate, the silicon single crystal substrate may be a p-type substrate instead of the n-type substrate because the n-type silicon single crystal substrate 400 is finally ground and removed as described later. Although the impurity concentration of the semiconductor wafer is not limited, the impurity concentration of the lower n-type epitaxial layer 409 is preferably lower than that of the upper n-type epitaxial layer 407, so that a desired breakdown voltage is obtained. The surface of the upper n-type epitaxial layer 407 of the semiconductor wafer is the first main surface, and an area opposite to the first main surface is the second main surface.Next, a hard mask layer 410 for forming trench grooves of, for example, plasma tetraethyl orthosilicate (P-TEOS) is patterned on the first main surface as shown in FIG. 8. Then, by dry etching the upper n-type epitaxial layer 407 so as to reach the lower n-type epitaxial layer 409 using the hard mask layer for forming the trench grooves 401 for p-type pillar regions as a mask, the trench grooves 401 for p-type pillar regions (trench grooves for second pillar regions) are formed. Mesa regions sandwiched between the trench grooves 401 for p-type pillar regions become the n-type pillar regions 107. In addition, the lower n-type epitaxial layer 409 corresponds to the n-type bottom layer 109.Although the bottom of the p-type pillar region trench grooves 401 preferably reaches the n-type lower epitaxial layer 409, as long as impurities at the bottom of the p-type pillar regions 108 reach the inside of the n-type bottom layer 109 by a thermal diffusion process described later, the bottom of the p-type pillar region trench grooves 401 does not always need to reach the n-type lower epitaxial layer 409 at this time. Further, boron may be ion implanted into the bottom of the trench grooves 401 for p-type pillar regions. Then, the unnecessary hard mask layer 410 is removed.As shown in FIG. 9, the trench grooves 401 for p-type pillar regions are subjected to embedded epitaxial growth using a material doped with, for example, boron, so that an epitaxial layer is embedded in the trench grooves 401 for p-type pillar regions. Here, an epitaxial growth growth region 411 is also formed on the n-type pillar regions 107, so that the trench grooves 401 for p-type pillar regions are completely embedded.Next, as shown in FIG. 10, the growth region 411 except for the trench grooves 401 for p-type pillar regions is removed, for example, by a planarization process using chemical mechanical polishing (CMP), and the first main surface of the semiconductor wafer is planarized. Although a method of forming a superjunction structure using a trench filling epitaxial embedding method is exemplarily described herein as shown in FIG. 10, the superjunction structure may be formed by a multi-epitaxial manufacturing method.Next, as shown in FIG. 11, a gate oxide film is formed on almost the whole of the first main surface of the semiconductor wafer by thermal oxidation, and a polysilicon film (corresponding to the gate electrode 102) is formed on the gate oxide film using, for example, chemical vapor deposition (CVD) at low pressure. Then, dry etching of the polysilicon layer and the gate oxide layer using a resist layer as a mask is performed by lithography to pattern the gate electrodes 102 and the gate insulating film 101.For example, although an Si oxide layer of about 100 nm is exemplarily described herein as the gate insulating layer 101 and the polysilicon layer is exemplarily described as a material of the gate electrodes 102, amorphous silicon or a metal such as molybdenum may also be used as a material of the gate electrodes 102. Then, the unnecessary resist layer is removed.Next, as shown in FIG. 12, ion implantation of phosphorus at a dose of about 10 14 cm -2 constitutes the n-type carrier storage region 106.Next, as shown in FIG. 13, a thermal diffusion process at, for example, 1100° C. for about 140 minutes diffuses the n-type carrier storage region 106 immediately below the gate electrodes 102. At the same time, diffusing boron at the bottom of the p-type pillar regions 108 into the n-type bottom layer 109 increases the width of the bottom of each of the p-type pillar regions 108.Next, as shown in FIG. 14, ion implantation of boron at a dosage of, for example, about 3×10 14 cm -2 forms the p-type base regions 105. Then, a thermal diffusion process at, for example, 1100° C. for about 30 minutes diffuses the p-type base regions 105. Here, of course, the n-type carrier storage region 106 and the bottom of the p-type column regions 108 are further diffused on the n-type bottom layer 109.Next, for example, antimony or arsenic at a dosage of about 4×10 15 cm -2 forms the n-type emitter regions 103 by lithography using a resist layer for an n-type emitter region as a mask. Then, the unnecessary resist film for the n-type emitter region is removed. Then, for example, boron at a dosage of about 4×10 15 cm -2 using a resist layer for a p-type body contact region as a mask, forms the p-type body contact regions 104 by lithography. Then, the n-type emitter regions 103 and the p-type body contact regions 104 are heat-treated at, for example, about 1000° C. by lamp radiation heating or using a diffusion furnace, so that the n-type emitter regions 103 and the p-type body contact regions 104 are activated.Next, a phosphosilicate glass (PSG) film is deposited on almost the whole of the first main surface of the semiconductor wafer by CVD. Here, a boron-phosphosilicate glass (BPSG) layer or spin-on-glass (SOG) layer may be overlaid thereon and planarized.Next, as shown in FIG. 15, a resist layer for opening emitter contact holes is formed to open emitter contact holes by dry etching using a resist layer for opening emitter contact holes as a mask. Then, the unnecessary resist layer is removed. Then, depositing an aluminum-based metal layer by sputtering through a barrier metal layer of, for example, TiW forms the emitter electrode 100.Next, processes necessary for forming the second main surface side in the wafer processes in the method for manufacturing the semiconductor device according to Embodiment 1 will be described with reference to FIGS. 16 and 17.As shown in FIG. 16, the n-type silicon single crystal substrate 400 on the second main surface of the semiconductor wafer is completely removed, and the n-type silicon single crystal substrate 400 is abraded so that the n-type bottom layer 109 is exposed in a surface layer of the second main surface. When the abrasive debris remains on the abraded second major surface, an abrasive debris layer may be removed by a chemical etching treatment. Further, when the second main surface is abraded, it is preferable to protect an element pattern formed on sides of the first main surface by, for example, applying a resist or adhering a protective adhesive tape to the first main surface.Next, as shown in FIG. 17, ion implantation of phosphorus at a dosage of, for example, about 5×10 12 cm -2 on the second main surface of the semiconductor wafer forms the n-type buffer layer 110. Then, ion implantation at a dosage of, for example, about 1×10 13 cm -2 forms the p-type collector layer 111 at a position shallower than the n-type buffer layer 110 (a position on the second main surface side). Then, the n-type buffer layer 110 and the p-type collector layer 111 are activated by, for example, a laser heat treatment device.Modification of Embodiment 1FIG. 18 is a cross-sectional view schematically showing a structure of a semiconductor device according to a modification of Embodiment 1. In FIG. 18, the same reference numerals are assigned to the portions identical to those in FIG. 1, and the description is omitted. The semiconductor device according to this modification is different from the semiconductor device according to Embodiment 1 in that an n-type JFET region 121 having a higher impurity concentration than the n-type pillar regions 107 is formed again between the n-type carrier storage regions 106 which extend in the vertical direction with respect to the paper plane in FIG. 18 and are arranged in stripes.In the semiconductor device according to this modification, the n-type JFET region 121 can reduce the width of the depletion layer expanding from the p-type base regions 105 during conduction achieved by injecting electrons from the inversion layer formed in a surface of the adjacent p-type base regions 105 to an upper region of the n-type pillar regions 107.A structure for separating the n-type carrier storage regions 106 arranged in stripes using the n-type pillar regions 107, as in a conventional semiconductor device, has a problem in that a decrease in cell pitch causes the depletion layer extending from the p-type base regions 105 to narrow the current paths between the adjacent n-type carrier storage regions 106 and increase the on-resistance of the semiconductor device. Forming the n-type JFET region 121 according to this modification can solve such a problem and reduce on-resistance.Embodiment 2FIG. 19 is a cross-sectional view schematically showing a structure of a semiconductor device according to Embodiment 2; in FIG. 19, the same reference numerals are assigned to the regions identical to those in FIG. 1, and the description thereof is omitted. The semiconductor device according to Embodiment 2 is different from the semiconductor device according to Embodiment 1 in that p-type pillar bottom regions 122 lower than the lower end of the n-type pillar regions 107 (at positions on the second main surface side) include impurities having a concentration higher than those of the p-type pillar regions 108 closer to the first main surface side than the p-type pillar bottom regions 122.As shown in FIG. 19, the p-type pillar bottom regions 122 are located at positions lower than the lower end of the n-type pillar regions 107, and are located below the p-type pillar regions 108. Further, the p-type pillar bottom regions 122 have a higher impurity concentration than the p-type pillar regions 108. Forming the p-type pillar bottom regions 122 can more improve the electric field of the n-type bottom layer 109.Accordingly, for example, if the thickness of the drift layer 10 necessary to achieve a desired breakdown voltage cannot be sufficiently secured, forming the p-type pillar bottom regions 122 located at positions lower than the lower end of the n-type pillar regions 107 with a higher impurity concentration than the p-type pillar regions 108 located higher than the p-type pillar bottom regions 122 may increase the stress shared by the n-type pillar layer 109. Consequently, the breakdown voltage can be improved.Modifications 1 and 2 of Embodiment 2FIG. 20 is a cross-sectional view schematically showing a structure of a semiconductor device according to Modification 1 of Embodiment 2. FIG. 21 is a cross-sectional view schematically showing a structure of a semiconductor device according to Modification 2 of Embodiment 2. In FIGS. 20 and 21, the same reference numerals are assigned to the regions identical to those in FIG. 19, and the description thereof is omitted.The semiconductor device according to Modification 1 in FIG. 20 is different from the semiconductor device according to Embodiment 2 in that the p-type pillar bottom regions 122 and 123 include a plurality of regions having different widths and different impurity concentrations in the depth direction. The p-type pillar bottom regions 122 in the semiconductor device according to Modification 1 in FIG. 20 are formed only as extensions of the p-type pillar regions 108. This point is different from the semiconductor device according to Embodiment 2.Further, the semiconductor device according to Modification 2 in FIG. 21 is different from the semiconductor device according to Embodiment 2 in that an n-type JFET region 124 having a higher impurity concentration than the n-type pillar regions 107 is disposed between the adjacent p-type pillar bottom regions 122. The n-type JFET region 124 is in contact with the lower end of the n-type pillar regions 107. The semiconductor device according to Modification 2 is identical to that according to Embodiment 2 or Modification 1, wherein the p-type pillar bottom regions 122 are different in impurity concentration from the p-type pillar regions 108.In the semiconductor device according to Embodiment 2 in FIG. 19, the single p-type pillar bottom region 122 having a higher impurity concentration than the p-type pillar regions 108 located at a position shallower than the lower end of the n-type pillar regions 107 is formed. The semiconductor device according to Modification 1 in FIG. 20 includes the plurality of p-type pillar bottom regions 123 arranged in the depth direction, so that the electric field distribution can be more accurately controlled.Further, increasing the impurity concentration of the p-type pillar bottom regions 122 to improve the breakdown voltage expands the depletion layers between the adjacent p-type pillar bottom regions 122, and increases the turn-on voltage. To address this problem, the n-type JFET region 124, which has a higher impurity concentration than the n-type pillar regions 107, is disposed between the p-type pillar bottom regions 122 in the semiconductor device according to Modification 2 in FIG. 21. This can make the improvement of the breakdown voltage compatible with the reduction of the on-resistance.Embodiment 3Structure of Semiconductor Device according to Embodiment 3FIG. 22 is a cross-sectional view showing a structure of a semiconductor device according to Embodiment 3. The semiconductor device according to Embodiment 3 is a trench gate type super junction IGBT element manufactured using a silicon-based semiconductor substrate. Although a semiconductor device whose emitter-to-collector breakdown voltage is about 1200 V is specifically described below as an example, the following description is applicable to superjunction IGBT elements having other breakdown voltage values or to semiconductor devices having other superjunction structures.The semiconductor device according to Embodiment 3 is different from the semiconductor device according to Embodiment 1 in that the semiconductor device according to Embodiment 1 is a planar gate type MOS semiconductor device, whereas the semiconductor device according to Embodiment 3 is a trench gate type MOS semiconductor device.As shown in FIG. 22, the n-type carrier storage region 106 separates the upper end of the p-type pillar regions 108 from the p-type base regions 105 selectively formed above the p-type pillar regions 108 on the first main surface side. Trench grooves 201 are selectively disposed above the n-type pillar regions 107 such that the trench grooves 201 penetrate the p-type base regions 105 from the n-type emitter regions 103 with a lower resistance formed in a surface layer of the p-type base regions 105, and reach a part of the n-type carrier storage region 106. In each of the trench grooves 201, the gate electrode 102 is disposed through the gate insulating film 101.The depth position of the bottom (lower end) of the trench groove 201 is shallower than the depth position of the upper end of the p-type pillar regions 108. This can prevent a decrease in breakdown voltage caused by an increase in electric field between the upper portion of the p-type pillar portions 108 and the trench grooves 201.Method of Manufacturing Semiconductor Device according to Embodiment 3Next, wafer processes in the method for manufacturing the semiconductor device according to Embodiment 3 will be described with reference to FIGS. 23 to 26. Although only processes necessary to mainly manufacture the essential portion of the device in FIG. 22 are described here, the description of the processes up to manufacturing the super junction IGBT elements on the first main surface side will be omitted because the processes are the same as the method of manufacturing the super junction IGBT element with planar gate as shown in FIGS. 7 to 10. Since the processes on the second main surface side are substantially identical to those in FIG. 16 or the subsequent drawings, only the differences will be described here.After a superjunction structure is formed on the n-type silicon single crystal substrate 400 on the first main surface side, ion implantation of phosphorus is performed at a dose of, for example, about 10 14 cm -2 so that the n-type carrier storage region 106 is formed as shown in FIG. 23.Next, as shown in FIG. 24, ion implantation of boron at a dose of, for example, about 3×10 14 cm -2 constitutes the p-type base region 105.Next, as shown in FIG. 25, a thermal diffusion process at, for example, 1100° C. for about 140 minutes diffuses the n-type carrier storage region 106 and the p-type base region 105. At the same time, diffusing boron at the bottom of the p-type pillar regions 108 into the n-type bottom layer 109 increases the width of the bottom of each of the p-type pillar regions 108.Next, a trench gate MOSFET in which the gate electrode 102 is embedded in each of the trench grooves 201 (gate trench grooves) through the gate insulating film 101 is formed as shown in FIG. 26.Although the trench gate structure is formed after the p-type base region 105 is formed in FIGS. 25 and 26, the p-type base region 105 may also be formed after the trench gate structure is formed first.Modification of Embodiment 3FIG. 27 is a cross-sectional view schematically showing a structure of a semiconductor device according to a modification of Embodiment 3. The same reference numerals are assigned to the portions identical to those in FIG. 22, and the description thereof will be omitted. The semiconductor device according to this modification is different from the semiconductor device according to Embodiment 3 in that only the gate electrode 102 is formed in each of the trench grooves 201 in the semiconductor device according to Embodiment 3, whereas in this modification, the n-type emitter region 103 on the first main surface side is not formed in the p-type base regions 105 that is in contact with the sidewalls of some of the trench grooves 201.Here, dummy gate electrodes 202 are formed through the gate insulating film 101 in the trench grooves 201 in contact with the p-type base regions 105 on the first main surface side whose n-type emitter region 103 is not formed. The dummy gate electrodes 202 embedded in the trench grooves 201 of trench dummy gates may be connected to the gate electrodes 102 or the emitter electrode 100.Since the n-type emitter region 103 on the first main surface side is not formed in the p-type base regions 105 which are in contact with the sidewalls of the trench grooves 201 of the trench dummy gates, and electrons are not injected through the sidewalls of the trench grooves 201 of the trench dummy gates, the trench dummy gates are referred to as such, so that it is possible to distinguish from the original gates (trench gates). In this modification, disposing these trench dummy gates above the p-type pillar regions 108, for example, may improve the hole memory effect and reduce the turn-on voltage.As shown in FIG. 22, narrowing the interval between the trench grooves 201 to decrease on-resistance in a semiconductor device composed of trench gates results in increase of saturation current because channel density is increased. When a load such as a motor is short-circuited, a larger saturation current leads to a risk that a larger current is conducted and elements are destroyed. Thus, the structure using the trench dummy gates is an effective means when only narrowing the trench pitch dimensions is desired without increasing the channel density.It is preferable that the trench grooves 201 of the trench dummy gates are disposed above the p-type pillar regions 108 and the trench grooves 201 of the trench gates are disposed above the n-type pillar regions 107, which allows electrons to be efficiently injected from the n-type emitter regions 103 into the n-type carrier storage regions 106 and the n-type pillar regions 107 below the n-type carrier storage region 106 by the inversion layer formed in the p-type base regions 105 in the vicinity of the sidewalls of the trench grooves 201 of the trench gates.High electrical charges occurring in switching operations create a dynamic avalanche effect, and hot charge carriers created by the avalanche effect may be trapped by a MOS interface of the trench dummy gates above the p-type pillar regions 108. When the p-type pillar regions 108 are floating, storing the charges trapped at the bottom of the trench grooves 201 above the p-type pillar regions 108 for long-term operation gradually causes the charge balance to be canceled near the top of the p-type pillar regions 108, and this deteriorates the long-term reliability. Consequently, a structure for connecting the p-type pillar regions 108 to the p-type base regions 105, for example, in a termination structure region outside an active region or in a gate wiring region, and separating the p-type pillar regions 108 from the p-type base regions 105 in the active region can make a reduction in on-resistance compatible with ensuring long-term reliability.Embodiment 4FIG. 28 is a plan view schematically showing an upper layout of a semiconductor device according to Embodiment 4. As shown in FIG. 28, first gate electrodes 203 and second gate electrodes 204 are alternately arranged in the active region. The plurality of first gate electrodes 203 disposed in the active area are bonded near the center of the upper layout (connected to a first gate line 304), and are electrically connected to a first gate electrode terminal 302. Further, the plurality of second gate electrodes 204 disposed in the active region are bonded in the vicinity of the active region (connected to a second gate line 305), and are electrically connected to a second gate electrode terminal 303.As described later, disposing the first gate electrodes 203 above the n-type pillar regions 107 and disposing the second gate electrodes 204 above the p-type pillar regions 108 may individually drive the gates and effect fine-tuned control suitable for reducing the switching losses, for example.FIG. 29 is a cross-sectional view schematically showing a structure of a part A 1-A 2 of the semiconductor device according to Embodiment 4 in FIG. 28. The semiconductor device according to Embodiment 4 is a trench gate type super junction IGBT element manufactured using a silicon-based semiconductor substrate. The semiconductor device according to Embodiment 4 is different from the semiconductor devices according to Embodiments 1 to 3 in that there are two types of gates to which different voltages can be applied.As shown in FIG. 29, the n-type carrier storage region 106 separates the upper end of the p-type pillar regions 108 from the p-type base regions 105 selectively formed above the p-type pillar regions 108 on the first main surface side. The trench grooves 201 are selectively disposed above the n-type pillar regions 107 such that the trench grooves 201 penetrate the p-type base regions 105 from the n-type emitter regions 103 with a lower resistance formed in a surface layer of the p-type base regions 105, and reach a part of the n-type carrier storage region 106. In the trench grooves 201, the first gate electrodes 203 are arranged to face the n-type pillar regions 107 through the gate insulating film 101.Further, the trench grooves 201 are selectively disposed above the p-type pillar regions 108 such that the trench grooves 201 penetrate the p-type base regions 105 from the n-type low resistance emitter regions 103 formed in a surface layer of the p-type base regions 105, and reach a part of the n-type carrier storage region 106. In the trench grooves 201, the second gate electrodes 204 are disposed to face the p-type pillar regions 108 through the gate insulating film 101.As shown in FIG. 28, the first gate electrodes 203 are arranged to share the active area of the semiconductor device, and the second gate electrodes 204 are formed from the outermost periphery to the inner periphery in the active area. The first gate electrodes 203 span the first gate line 304, and the second gate electrodes 204 span the second gate line 305. The first gate line 304 and the second gate line 305 are routed and arranged on the upper surface of the semiconductor device.The first gate line 304 is electrically connected to the first gate electrode terminal 302, and the second gate line 305 is electrically connected to the second gate electrode terminal 303. Although the first gate line 304 and the second gate line 305 may be formed of polysilicon or amorphous silicon, they are preferably formed of a metal wiring material such as aluminum, so that the delay of a gate signal is further reduced.Although FIG. 28 shows a layout in which the first gate electrodes 203 span the first gate line 304 in the active region and thus share the active region of the semiconductor device and the second gate electrodes 204 span the second gate line 305 circumferentially across the semiconductor device, the first gate electrodes 203 may also span the first gate line 304 circumferentially across the semiconductor device and the second gate electrodes 204 may span the second gate line 305 in the active region. Of course, the same advantages can be obtained not only with the layout of the gate lines for dividing the active region but also with a layout in which the first gate electrodes 203 and the second gate electrodes 204 are alternately connected from right and left or up and down in the active region toward the active region.FIG. 30 is a graph exemplarily showing a timing chart of the first gate voltage and the second gate voltage for driving the semiconductor device according to Embodiment 4. The first gate voltage is applied to the first gate electrode terminal 302, whereas the second gate voltage is applied to the second gate electrode terminal 303.Operation of Semiconductor Device according to Embodiment 4The operation of the semiconductor device according to Embodiment 4 will be described.The semiconductor device according to Embodiment 4 includes the drift layer 10 including the n-type pillar regions 107 and the p-type pillar regions 108, so that a super junction structure is formed.While the emitter electrode 100 is grounded and the power supply voltage is applied to the collector electrode 112, when the first gate voltage is lower than or equal to a gate threshold voltage of the MOSFET formed in the first main surface, a reverse bias voltage is applied between the p-type base regions 105 and the drift layer 10, and the collector electrode 112 and the emitter electrode 100 are in a turn-off state where it is interrupted.Next, simultaneously applying voltages exceeding the gate threshold voltage of the MOSFET formed in the first main surface to the first gate electrodes 203 and the second gate electrodes 204 as the first gate voltage and the second gate voltage, respectively, performs forming an n-type inversion layer in parts of the p-type base regions 105 that are in contact with the first gate electrodes 203 and the second gate electrodes 204 through the gate insulating film 101. Then, conducting the electric current from the collector electrode 112 to the emitter electrode 100 through this inversion layer allows the semiconductor device to assume the on state which is turned on from an off state.In order to set the current flowing through the semiconductor device in this on state back to the off state, a zero bias voltage or a negative bias voltage is applied to the second gate electrodes 204 as a second gate voltage, and a zero bias voltage or a negative bias voltage is applied to the first gate electrodes 203 as a first gate voltage after the time Δt has elapsed since the initial application, as shown in FIG. 30.Once the n-type inversion layer formed at the MOS interface of the p-type base regions 105 in contact with the first gate electrodes 203 and the second gate electrodes 204 through the gate insulating film 101 disappears, the supply of electrons from the n-type emitter regions 103 to the drift layer 10 is stopped. The stored carriers in the drift layer 10 and the n-type bottom layer 109 are attenuated, and depletion layers between the p-type pillar regions 108 and the n-type pillar regions 107 in the drift layer 10 are pierced, so that the voltage between the collector electrode 112 and the emitter electrode 100 is increased and the semiconductor device is brought into an off state.Here, Δt is suitably set between 0.1 microseconds and 10 microseconds.Effects and Advantages of Semiconductor Device According to Embodiment 4The effects and advantages of the semiconductor device according to Embodiment 4 will be described.In a process of turning off the semiconductor device, first, a turn-off signal is output to the second gate electrodes 204 formed above the p-type pillar regions 108 as the second gate voltage. Then, the n-type inversion layer formed at the MOS interface of the p-type base regions 105 in contact with the second gate electrodes 204 disappears, and the supply of electrons from the n-type emitter regions 103 adjacent to the second gate electrodes 204 through the gate insulating film 101 is interrupted. Here, a p-type inversion layer is formed in a part of the n-type carrier storage region 106 in contact with the second gate electrodes 204 through the gate insulating film 101.Thereby, a PNP bipolar transistor is formed using the p-type column regions 108 as the p-type emitter, the n-type carrier storage region 106 as the n-type base, and the p-type inversion layer as the p-type collector. The formation of such a PNP bipolar transistor ejects the holes from the upper portion of the p-type column regions 108 to the p-type base regions 105, through the n-type carrier storage region 106 and the p-type inversion layer. Thereby, the carriers stored in the drift layer 10 are ejected so that a depletion layer extends between p-n junctions of the p-type pillar regions 108 and the n-type pillar regions 107 in the drift layer 10 and up to a region of the n-type bottom layer. At this time, the super junction region is not fully depleted.After the delay time Δt in which the turn-off signal is output to the second gate electrodes 204 as the second gate voltage, a zero bias voltage or a negative bias voltage is applied to the first gate electrodes 203 as the first gate voltage. Since the n-type inversion layer formed at the MOS interface of the p-type base regions 105 in contact with the first gate electrodes 203 through the gate insulating film 101 also disappears, the supply of electrons from the n-type emitter regions 103 is completely stopped. Since the turn-off signal is first output to the second gate electrodes 204 as a second gate voltage, the time required for completely depletion the drift layer 10 becomes shorter as Δt increases.This has been confirmed in a simulation, as well as that the turn-off losses Eoff decrease and are saturated at a certain point as Δt increases, as shown in FIG. 31. While carriers are also stored in the n-type bottom layer 109, a depletion layer penetrates into the n-type bottom layer 109 at the time when only one kind of the first gate electrodes 203 or the second gate electrodes 204 are turned off, and the collector-to-emitter voltage takes a peak value. Consequently, the surge voltage Vcep hardly affects the value Δt. Consequently, Δt>0 can reduce the turn-off losses Eoff without increasing the surge voltage Vcep at the turn-off time.Modification of Embodiment 4FIG. 32 is a cross-sectional view schematically showing a structure of a semiconductor device according to a modification of Embodiment 4. The same reference numerals are assigned to the portions identical to those in FIG. 29 etc., and the description thereof is omitted. The semiconductor device according to this modification is different from the semiconductor device according to Embodiment 4 in that the semiconductor device according to this modification has a planar gate structure.In the semiconductor device according to this modification, when the turn-off signal is output to the second gate electrodes 204 as the second gate voltage earlier by the time Δt than that when the turn-off signal is output to the first gate electrodes 203 as the first gate voltage, the n-type inversion layer formed at the MOS interface of the p-type base regions 105 in contact with the second gate electrodes 204 disappears, and the supply of electrons from the n-type emitter regions 103 adjacent to the second gate electrodes 204 through the gate insulating layer 101 is interrupted.Here, a p-type inversion layer is formed in a part of the n-type carrier storage region 106 in contact with the second gate electrodes 204 through the gate insulating film 101. Since the p-type inversion layer is connected to both the p-type base regions 105 and the p-type pillar regions 108, the stored charge carriers in the drift layer 10 are ejected to the emitter electrode 100 connected to the p-type base regions 105 through the p-type pillar regions 108 and the p-type inversion layer. Consequently, when the turn-off signal is output to the first gate electrodes 203 as the first gate voltage, the time for completely depletion the drift layer 10 is shortened. Consequently, turn-off losses can be reduced without increasing surge voltage.The embodiments can be freely combined with each other, as well as appropriately modified or omitted, within the scope of the present invention.While the present invention has been described in detail, the foregoing description is illustrative in all aspects and does not limit the present invention. Accordingly, numerous modifications may be devised which are not described by way of example.List of reference characters10 Drift layer 100 Emitter electrode 101 Gate insulating layer 102 Gate electrode 103 N-type emitter region 104 P-type body contact region 105 P-type base region 106 N-type carrier storage region 107 N-type pillar region 108 P-type pillar region 109 N-type bottom layer 110 N-type buffer layer 111 P-type collector layer 112 Collector electrode 121 JFET region 122 P-type pillar bottom region 123 P-type pillar bottom region 124 JFET region 201 Trench groove 202 Dummy gate electrode 203 First gate electrode 204 Second gate electrode 302 First gate electrode terminal 303 Second Gate electrode terminal 304 First gate line 305 Second gate line 400 N-type silicon single crystal substrate 401 Trench groove for p-type pillar regions 407 Upper n-type epitaxial layer 409 Lower n-type epitaxial layer 410 Hard mask layer 411 Growth region.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedJP 3 288 218 B2

[0006] JP 2009-525 610 A

[0006] Cited Non-Patent LiteratureT. Tamaki et al., "Vertical Charge Imbalance Effect on 600 V-class Trench-Filling Superjunction Power MOSFETs", Proceedings of the 23rd International Symposium on Power Semiconductor Devices & ICs, May 23-26, 2011, pp. 308-311

[0007]

Claims

A semiconductor device having a first main surface and a second main surface facing the first main surface, the semiconductor device comprising: a drift layer including a first pillar region of a first conductivity type and a second pillar region of a second conductivity type, the first pillar region and the second pillar region being alternately arranged in a direction parallel to the first main surface and the second main surface; a second conductivity type base region, the base region being selectively arranged in the drift layer on the first main surface side; a gate insulating layer arranged in contact with the base region; a gate electrode arranged to face the base region through the gate insulating layer; a first conductivity type carrier storage region, the carrier storage region being arranged between the base region and the second pillar region; and an emitter region of the first conductivity type, the emitter region being selectively disposed in a surface layer of the base region on the first main surface side, a lower end of the second pillar region, which is an end region on the second main surface side, being located closer to the second main surface side than a lower end of the first pillar region, which is an end region on the second main surface side, and wp3>wp2and wp1>wp2, wherein wp1 denotes the width of an upper end of the second pillar region, which is an end region on the first main surface side, wp2 denotes the width of the second pillar region at the same position as a lower end of the first pillar region, and wp3 denotes the width of the lower end of the second pillar region.The semiconductor device according to claim 1, further comprising: a first conductivity type bottom layer, the bottom layer being disposed on the second main surface side with respect to the drift layer; a first conductivity type buffer layer, the buffer layer being disposed on the second main surface side with respect to the bottom layer; and a second conductivity type collector layer, the collector layer being disposed on the second main surface side with respect to the buffer layer.The semiconductor device according to claim 1 or 2, wherein the carrier storage region is separated at a position corresponding to the center of the gate electrode in the direction parallel to the first main surface and the second main surface.The semiconductor device according to claim 3, wherein the carrier storage region has a width larger than the base region in the direction parallel to the first main surface and the second main surface.The semiconductor device according to any one of claims 1 to 4, wherein in the second pillar region, the impurity concentration included in a region from the same position as the lower end of the first pillar region to the lower end of the second pillar region is higher than the impurity concentration included in a region from the upper end of the second pillar region to the same position as the lower end of the first pillar region.The semiconductor device according to claim 5, further comprising: a first conductivity type JFET region, the JFET region being disposed on the second main surface side with respect to the first pillar region and in contact with the lower end of the first pillar region, the JFET region having a higher impurity concentration than the first pillar region.The semiconductor device according to any one of claims 1, 2, 5 or 6, wherein the gate electrode penetrates the base region and reaches the carrier storage region.The semiconductor device according to any one of claims 1 to 7, wherein the second pillar region is connected to the base region.The semiconductor device according to any one of claims 1 to 7, wherein the second pillar region is partially separated from the base region.The semiconductor device according to any one of claims 7 to 9, wherein the gate electrode includes a first gate electrode and a second gate electrode, the first gate electrode is disposed to face the first pillar region through the gate insulating film, and the second gate electrode is disposed to face the second pillar region through the gate insulating film.A method for controlling a semiconductor device, the method comprising: outputting a turn-off signal to the second gate electrode before outputting a turn-off signal to the first gate electrode, when a turn-on state in which electric current is supplied to the semiconductor device according to claim 10 is switched to a turn-off state in which electric current is not supplied.A method of manufacturing a semiconductor device, the method comprising the steps of: (a) preparing a semiconductor wafer in which a lower epitaxial layer of a first conductivity type is formed on a semiconductor substrate and an upper epitaxial layer of the first conductivity type is formed on a surface layer of the lower epitaxial layer; (b) forming a trench groove for the second pillar region, which penetrates the upper epitaxial layer and reaches the lower epitaxial layer, and forming the upper epitaxial layer, which excludes the trench groove for the second pillar region, as a first pillar region; (c) subjecting the trench groove for the second pillar region to embedded epitaxial growth using a material doped with impurities of a second conductivity type to form a second pillar region; (d) planarizing a first main surface to expose the first pillar region and the second pillar region in the first main surface, the first main surface being a surface of the semiconductor wafer on the upper epitaxial layer side; (e) forming a gate insulating film covering the first pillar region and extending from the first pillar region to a part of the second pillar region, and forming a gate electrode on the gate insulating film; (f) implanting ions from a first main surface side so that a first conductivity type carrier storage region is formed in a surface layer of the second pillar region; (g) performing a thermal diffusion process for diffusing the carrier storage region to immediately below the gate electrode and diffusing an end region of the second pillar region on a second main surface side to immediately below the first pillar region, the second main surface facing the first main surface; (h) implanting ions from the first main surface side to form a second conductivity type base region in a surface layer of the carrier storage region, wherein wp3>wp2and wp1>wp2appeared, wherein wp1denotes the width of an upper end of the second pillar region, which is an end region on the first main surface side, wp2denotes the width of the second pillar region at the same position as a lower end of the first pillar region, and wp3 denotes the width of the lower end of the second pillar region.A method for manufacturing a semiconductor device, the method comprising: (a) preparing a semiconductor wafer in which a lower epitaxial layer of a first conductivity type is formed on a semiconductor substrate and an upper epitaxial layer of the first conductivity type is formed on a surface layer of the lower epitaxial layer; (b) forming a trench groove for the second column region penetrating the upper epitaxial layer and reaching the lower epitaxial layer, and forming the upper epitaxial layer excluding the trench groove for the second column region as a first column region; (c) subjecting the trench groove for the second column region to embedded epitaxial growth using a material doped with impurities of a second conductivity type so as to form a second column region; (d) planarizing a first main surface so as to expose the first pillar region and the second pillar region in the first main surface, the first main surface being a surface of the semiconductor wafer on the upper epitaxial layer side; (e) implanting ions from a first main surface side so as to form a first conductivity type carrier storage region in a surface layer of the first pillar region and the second pillar region; (f) implanting ions from the first main surface side so as to form a second conductivity type base region in a surface layer of the carrier storage region; (g) performing a thermal diffusion process for diffusing the carrier storage region and the base region and diffusing an end region of the second pillar region on a second main surface side immediately below the first pillar region, the second main surface facing the first main surface; (h) forming a gate trench groove penetrating the base region and reaching the carrier storage region, forming a gate insulating film on an inner wall of the gate trench groove, and forming a gate electrode so that the gate trench groove is embedded, wherein wp3>wp2and wp1>wp2, wherein wp1denotes the width of an upper end of the second pillar region, which is an end region on the first main surface side, wp2denotes the width of the second pillar region at the same position as a lower end of the first pillar region, and wp3 denotes the width of the lower end of the second pillar region.The method according to claim 12 or 13, further comprising the steps of: (i) completely removing the semiconductor substrate from the second main surface side so as to expose the lower epitaxial layer; (j) implanting ions from the second main surface side to form a first conductivity type buffer layer in a surface layer of the lower epitaxial layer; (k) implanting ions from the second main surface side to form a second conductivity type collector layer in a surface layer of the buffer layer; and (1) activating the buffer layer and the collector layer.The method according to any one of claims 12 to 14, wherein the semiconductor substrate is a substrate doped with impurities of the first Czochralski method (MCZ) or floating zone method (FZ) employed.

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