Semiconductor device and method for its manufacture

Abstract

A semiconductor device comprising: an outer trench (22) formed in an active region (50), a gate insulating layer (10) and a gate electrode layer (11) formed in the gate trench (22), a gate line electrode (15) formed on the interlayer insulating layer (13) covering the gate electrode layer (11), and an outer trench (6) formed in a drift layer (2) in a terminal region (60). Formed in the outer trench (6) are a potential fixing layer (8) covering a corner region at the upper end (6a) of the outer trench (6), and an insulating layer (9) formed on the potential fixing layer (8).The gate insulating layer (10) and the gate electrode layer (11) extend to the inside of the outer trench (6), and the gate electrode layer (11) is connected to the gate line electrode (15) through a contact hole formed in the intermediate insulating layer (13) in the outer trench (6).

Description

Technical FieldThe present invention relates to a trench gate type semiconductor device and its manufacturing method, and more particularly to the structure of a gate electrode on the outer periphery side of the semiconductor device.Prior ArtA semiconductor device having a trench gate structure, such as an insulated gate bipolar transistor (IGBT) or an insulated gate metal oxide semiconductor field effect transistor (MOSFET), is used for electric power control of a vehicle-mounted device or an industrial device, for example.On the semiconductor device having the trench gate structure, there is disposed "a front gate region" in which a trench in which a gate electrode is embedded (hereinafter referred to as a "gate trench") extends from an active region in which a main current flows to a terminal region on the outside of the active region. Although the drain voltage is low when the semiconductor device is in the on state, a voltage is applied to the gate electrode; thus, the electric field occurring in a gate insulating film becomes large, and tends to concentrate particularly in a corner portion at the upper end of the gate trench.Patent Document 1 described below discloses a technique of forming a gate insulating film in contact with a thick field insulating film formed by local oxidation of silicon (LOCOS) in a gate trench in a front gate region so that the electric field concentration in a corner region at the upper end of the gate trench is reduced.Patent Document 2 described below discloses a technique of disposing a field plate electrode together with a gate electrode in a gate trench in a front gate region and setting the potential of the field plate electrode to the gate potential or the source potential.PRIOR ART DOCUMENTSPatent DocumentsPatent Document 1: Japanese Patent Application Laid-Open JP 2001-102 572 APatent Document 2: Japanese Patent Application Laid-Open JP 2011-199 109 ASummaryProblem to be Solved by the InventionEven when the withstand voltage of the gate insulating film of the front gate region is improved by the field insulating film as in Patent Document 1, in a case where the corner portion at the upper end of the gate trench has a canopy part that is, for example, of a rectangular shape, the field insulating film having a small thickness is locally formed; thus, the effect that the withstand voltage of the gate insulating film is improved is not sufficiently obtained.In a case where the potential of the field plate electrode is the gate potential in the front gate region as disclosed in Patent Document 2, when the thickness of the gate insulating film is not sufficiently large, there is a possibility that breakdown of the gate insulating film occurs in the corner region at the upper end of the gate trench. Again, in a case where the potential of the field plate electrode is the source potential, there is a possibility that a gate-source leakage current may occur through the insulating layer between the gate electrode and the field plate electrode. There is also a possibility that the gate insulating film having a small thickness is locally formed on the field plate electrode depending on the shape of the field plate electrode, and such a configuration causes breakdown of the gate insulating film.The present invention is intended to solve the above problems, and an object thereof is to provide a semiconductor device capable of preventing breakdown of a gate insulating film in a corner portion at the upper end of a gate trench of a front gate region.Ways of Solving the ProblemA semiconductor device according to the present invention includes: a drift layer of a first conductivity type; a well region of a second conductivity type formed on a surface region of the drift layer; an impurity region of the first conductivity type formed on a surface region of the well region; a gate trench passing through the impurity region and the well region in an active region and reaching the drift layer; a gate insulating film formed to have contact with an inner surface of the gate trench; a gate electrode film formed on the gate insulating film; an intermediate insulating film covering the gate electrode film; a gate line electrode formed on the intermediate insulating layer and connected to the gate electrode layer; an outer trench formed in the drift layer in a terminal region on an outer side of the active region; a potential fixing layer formed in the outer trench and covering a corner region at an upper end of the outer trench; and an insulating layer formed on the potential fixing layer, wherein the gate insulating layer and the gate electrode layer extend to the inner side of the outer trench of the terminal region, and the gate electrode layer is connected to the gate line electrode through a contact hole formed in the intermediate insulating layer in the outer trench.Effects of the InventionAccording to the present invention, since the corner portion at the upper end of the outer trench is covered by the potential fixing layer and the insulating layer, the gate electrode and the gate insulating layer leading to the outer trench are formed on the insulating layer and are separated from the corner portion at the upper end of the outer trench. Consequently, the breakdown of the gate insulating film is prevented by concentration of the electric field caused by the shape of the corner portion at the upper end of the outer trench.These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying diagrams.Brief Description of the DrawingsFIG. 1 is a schematic plan view showing a schematic configuration of a semiconductor device according to Embodiment 1. FIG. 2 is a schematic view showing a schematic configuration of a boundary region between an active region 50 and a terminal region 60 in the semiconductor device according to Embodiment 1. FIG. 3 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line A 1-A 2 in FIG. 2 according to Embodiment 1. FIG. 4 is a schematic cross-sectional view showing a schematic configuration of the semiconductor device taken along line B 1-B 2 in FIG. 2 according to Embodiment 1. FIG. 5 is a schematic cross-sectional view showing a schematic configuration of the semiconductor device taken along line C 1-C 2 in FIG. 2 according to Embodiment 1. FIG. 6 is a schematic cross-sectional view showing a schematic configuration of the semiconductor device taken along line D 1-D 2 in FIG. 2 according to Embodiment 1. FIG. 7 is a partial cross-sectional view showing a method of manufacturing the semiconductor device taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 8 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 9 is a partial cross-sectional view showing a method of manufacturing the semiconductor device taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 10 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 11 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 12 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 13 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line D 1-D 2 in FIG. 2, according to Embodiment 1. FIG. 14 is a partial cross-sectional view showing a method of manufacturing the semiconductor device taken along line D 1-D 2 in FIG. 2, according to Embodiment 1. FIG. 15 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line D 1-D 2 in FIG. 2, according to Embodiment 1. FIG. 16 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line D 1-D 2 in FIG. 2, according to Embodiment 1. FIG. 17 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line D 1-D 2 in FIG. 2, according to Embodiment 1. FIG. 18 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line D 1-D 2 in FIG. 2, according to Embodiment 1. FIG. 19 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line D 1-D 2 in FIG. 2, according to Embodiment 1. FIG. 20 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line D 1-D 2 in FIG. 2, according to Embodiment 1. FIG. 21 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line D 1-D 2 in FIG. 2, according to Embodiment 1. FIG. 22 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line B 1-B 2 in FIG. 2 according to an embodiment 2. FIG. 23 is a schematic cross-sectional view showing a schematic configuration of the semiconductor device taken along line C 1-C 2 in FIG. 2 according to Embodiment 1. FIG. 24 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 25 is a partial cross-sectional view showing a method of manufacturing the semiconductor device taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 26 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 27 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 28 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 29 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 30 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line B 1-B 2 in FIG. 2, according to Embodiment 1. FIG. 31 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line C 1-C 2 in FIG. 2, according to Embodiment 2. FIG. 32 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line C 1-C 2 in FIG. 2, according to Embodiment 2. FIG. 33 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line C 1-C 2 in FIG. 2, according to Embodiment 2. FIG. 34 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line C 1-C 2 in FIG. 2, according to Embodiment 2. FIG. 35 is a partial cross-sectional view showing a method of manufacturing the semiconductor device taken along line C 1-C 2 in FIG. 2, according to Embodiment 2. FIG. 36 is a partial cross-sectional view showing a method of manufacturing the semiconductor device, taken along line C 1-C 2 in FIG. 2, according to Embodiment 2. FIG. 37 is a partial cross-sectional view showing a method of manufacturing the semiconductor device taken along line C 1-C 2 in FIG. 2, according to Embodiment 2. FIG. 38 is a schematic plan view showing a schematic configuration of a semiconductor device according to Embodiment 3. FIG. 39 is a schematic view showing a schematic configuration of a semiconductor device according to Embodiment 3. FIG. 40 is a schematic cross-sectional view showing a schematic configuration of the semiconductor device taken along line D 1-D 2 in FIG. 39 according to Embodiment 3. FIG. 41 is a schematic view showing a schematic configuration of a semiconductor device according to Embodiment 4. FIG. 42 is a schematic cross-sectional view showing a schematic configuration of the semiconductor device taken along line D 1-D 2 in FIG. 41 according to Embodiment 4. FIG. 43 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D 1-D 2 in FIG. 2 according to an embodiment 5. FIG. 44 is a schematic cross-sectional view showing a schematic configuration of the semiconductor device taken along line D 1-D 2 in FIG. 39 according to Embodiment 5. FIG. 45 is a schematic cross-sectional view showing a schematic configuration of the semiconductor device taken along line D 1-D 2 in FIG. 41 according to Embodiment 5. FIG. 46 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line B 1-B 2 in FIG. 2, FIG. 39, or FIG. 41 according to an embodiment 6. FIG. 47 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D 1-D 2 in FIG. 2 according to an embodiment 6. FIG. 48 is a schematic cross-sectional view showing a schematic configuration of the semiconductor device taken along line D 1-D 2 in FIG. 39 according to Embodiment 6. FIG. 49 is a schematic cross-sectional view showing a schematic configuration of the semiconductor device taken along line D 1-D 2 in FIG. 41 according to Embodiment 6.DESCRIPTION OF EMBODIMENTSEmbodiments of a technique according to the present invention will be described below with reference to the diagrams. The diagrams are schematically illustrated; thus, the size and mutual relation of the positions of the images respectively illustrated in different diagrams are not necessarily accurately illustrated, but they can be appropriately changed. Like reference numerals are assigned to similar constituent elements, and the same applies to their names and functions. Thus, detailed description thereof may be omitted in some cases.In the description, terms each indicating a specific position and direction, such as "upper side", "lower side", "lateral side", "bottom", "front side" or "rear side", are used; these terms are used for convenience and ease of understanding of the embodiments, and do not refer to a position and a direction in actual use.The "one" constituent element described in the embodiments may be "one or more" constituent elements as long as it is consistent with the embodiments. Further, the constituent elements are conceptual units. Thus, a constituent element may have multiple structures, and a constituent element may correspond to a part of a structure.In the following embodiments, the first conductivity type of an n-type semiconductor and the second conductivity type thereof is the p-type, but it is also conceivable in reverse that the first conductivity type is the p-type and the second conductivity type is the n-type. Although a MOSFET is described as an example of the semiconductor device, the semiconductor device may also be an IGBT. In the following description, the material of the semiconductor substrate and the drift layer is silicon carbide (SiC) as a wide bandgap semiconductor having a larger bandgap than silicon, but it may also be, for example, silicon, another wide bandgap semiconductor such as gallium nitride or diamond, or a combination thereof.In the following description, "impurity concentration" indicates the peak value of the impurity concentration in each region.Embodiment 1FIG. 1 is a schematic plan view showing a schematic configuration of a semiconductor device according to Embodiment 1. FIG. 2 is a schematic view showing a schematic configuration of a boundary region between an active region 50 and a terminal region 60 in the semiconductor device according to Embodiment 1, and illustrates a part of a region 40 surrounded by a broken line in FIG. 1. The illustration of, for example, an intermediate insulating layer 13, a front surface electrode 14, and a front surface ohmic electrode 19 is omitted to simplify the description in FIG. 2.Further, FIGS. 3 to 6 are schematic diagrams each showing a cross-sectional configuration of the semiconductor device according to Embodiment 1. FIG. 3 is a cross-sectional view taken along line A 1-A 2 in FIG. 2, FIG. 4 is a cross-sectional view taken along line B 1-B 2 in FIG. 2, FIG. 5 is a cross-sectional view taken along line C 1-C 2 in FIG. 2, FIG. 6 is a cross-sectional view taken along line D 1-D 2 in FIG. 2.The active region 50 is a region in which a current flows by forming a channel in the semiconductor device in an on state, and the terminal region 60 is a region in the vicinity of the active region 50. the terminal region 60 is disposed so as to surround the active region 50 at an outer periphery region of a chip of the semiconductor device, and in the terminal region 60, a p-type terminal electric field relaxation region 18 such as a field limiting ring (FLR) and an n-type channel stop region 31 that suppresses the formation of a depletion layer to an end part of the chip are formed.A gate trench 22 is disposed at a drift layer 2 of the active region 50, and an outer trench 6 corresponding to a gate trench of a front gate region is disposed at the drift layer 2 of the terminal region 60. As shown in FIG. 2, the gate trench 22 is formed in a stripe shape in plan view. A cell is formed in each of the plurality of regions divided by the gate trench 22 in the active region 50. Although FIG. 2 illustrates the example of the plurality of square cells arranged in a strip shape, the shape of the cell may also be a circular shape or a polygonal shape such as a hexagonal shape, and the cell may also be arranged in a checkerboard pattern or a zigzag pattern.For example, as shown in FIGS. 3 to 6, the drift layer 2, a well region 3, an impurity region 4, and a contact region 5 are disposed on a front side of the semiconductor substrate 1 constituting the semiconductor device. At the active region 50, the gate trench 22, a trench bottom electric field relaxation region 16, a gate insulating film 10, and a gate electrode layer 11 are disposed. at the terminal region 60, the outer trench 6, the trench bottom electric field relaxation region 16, a high-concentration trench bottom well region 17, a terminal electric field relaxation region 18, a backing insulating film 7, a potential fixing film 8, an insulating film 9, the gate insulating film 10, the gate electrode layer 11, a field insulating film 12, and a gate line electrode 15 are disposed.The gate electrode layer 11 formed in the outer trench 6 in the terminal region 60 extends to surround the gate trench 22 in plan view. The front surface ohmic electrode 19, the intermediate insulating layer 13, and the front surface electrode 14 are collectively disposed on a front surface of the semiconductor substrate 1 at both the active region 50 and the terminal region 60. A back surface ohmic electrode 20 and a back surface electrode 21 are arranged on both the active region 50 and the terminal region 60 in common on a back surface of the semiconductor substrate 1.The drift layer 2 is disposed on the semiconductor substrate 1 formed of n-type silicon carbide, and is formed of n-type silicon carbide. It is sufficient that the n-type impurities of the drift layer 2 are nitrogen or phosphorus, and the impurity concentration of the drift layer 2 is about equal to or greater than 1×10 14 cm -3 and equal to or less than 1×10 18 cm -3. It is sufficient that the thickness of the drift layer 2 is about equal to or greater than 5 μm and equal to or less than 300 μm.The well region 3 is a p-type region disposed on a surface region of the drift layer 2, and is formed of silicon carbide. It is sufficient that the p-type impurities of the well region 3 are aluminum, boron, or gallium, and the impurity concentration of the well region 3 is about equal to or greater than 1×10 15 cm -3 and equal to or less than 1×10 20 cm -3. Here, the impurity concentration of the well region 3 may or may not be constant in the depth direction. It is sufficient that the thickness of the well region 3 is about equal to or greater than 0.3 μm and equal to or less than 3 μm.The impurity region 4 is an n-type region disposed on a surface region of the well region 3, and is formed of silicon carbide. It is sufficient that the n-type impurities of the impurity region 4 are nitrogen or phosphorus, and the impurity concentration of the impurity region 4 is about equal to or greater than 1×10 17 cm -3 and equal to or less than 1×10 22 cm -3. It is sufficient that the thickness of the impurity region 4 is equal to or less than that of the well region 3.The contact region 5 is a p-type region disposed on the surface region of the well region 3 and having a higher impurity concentration than the well region 3, and is formed of silicon carbide. It is sufficient that the p-type impurities of the contact region 5 are aluminum, boron, or gallium, and the impurity concentration of the well region 5 is about equal to or greater than 1×10 18 cm -3 and equal to or less than 1×10 22 cm -3. It is sufficient that the thickness of the contact region 5 is equal to or smaller than that of the well region 3.A contact hole 25 (hereinafter referred to as "source contact hole 25") reaching the impurity region 4 and the contact region 5 is formed in the intermediate insulating film 13, and the front surface ohmic electrode 19 connected to the impurity region 4 and the contact region 5 is formed in the bottom of the source contact hole 25. The impurity region 4 and the contact region 5 are electrically connected to the front surface electrode 14 as a main electrode through the front surface ohmic electrode 19 in the source contact hole 25.Here, the contact region 5 is connected to the impurity region 4 by the front surface ohmic electrode 19. When the contact region 5 is formed, a path connected to the front surface ohmic electrode 19 from the well region 3 via the contact region 5 is formed, and electrical connection from the well region 3 to the front surface ohmic electrode 19 is preferably achieved. The contact portion 5 may also be omitted.The gate trench 22 passes through the well region 3 from the surface of the impurity region 4 and reaches the drift layer 2, and as shown in FIG. 2, the gate trench 22 is disposed on the active region 50 in a stripe shape (i.e., in a shape of a plurality of lines parallel to each other). When the gate trench 22 is arranged in the stripe shape, in a case where the semiconductor device is a trench gate type silicon carbide MOSFET, a plane such as the (1-100) plane having high channel mobility may be used as the channel, and characteristics of the semiconductor device may be improved. The gate trench 22 extends in the direction of the terminal region 60 In the following description, the direction in which the gate trench 22 extends is referred to as the "extending direction" of the gate trench 22.It is sufficient that the width of the gate trench 22 is about equal to or greater than 0.5 μm and equal to or less than 10 μm. When the gate trench 22 has a tapered shape in the cross-sectional view, the width of the gate trench 22 denotes the width of the widest part of the tapered shape. It is sufficient that the depth of the gate trench 22 is about equal to or greater than 0.5 μm and equal to or less than 6 μm.The trench bottom surface electric field relaxation region 16 is a p-type region disposed on the lower side of a bottom surface of the gate trench 22, and is formed of silicon carbide. The trench bottom surface electric field relaxation region 16 has a conductivity type opposite to that of the drift layer 2, and has a function of relaxing the electric field on the gate insulating film 10 formed on the bottom surface of the gate trench 22 in the semiconductor device in an operation state. Breakdown of the gate insulating film 10 is thereby prevented.It is sufficient that the depth of the electric field relaxation region 16 for the trench bottom surface is about equal to or greater than 1 μm and equal to or less than 3.0 μm toward the lower side from the bottom surface of the gate trench 22. The trench bottom surface electric field relaxation region 16 may be in contact with the bottom surface of the gate trench 22. It is sufficient that the p-type impurities of the trench bottom surface electric field relaxation region 16 are aluminum, boron, or gallium, and the impurity concentration of the trench bottom surface electric field relaxation region 16 is about equal to or greater than 1×10 15 cm -3 and equal to or less than 1×10 19 cm -3.The outer trench 6 is a wide trench formed to have substantially the same depth as the gate trench 22 in the terminal region 60. The trench bottom surface electric field relaxation region 16 is also disposed on the lower side of the outer trench 6.The trench bottom surface high concentration well region 17 has a conductivity type opposite to that of the drift layer 2, and is disposed in the trench bottom surface electric field relaxation region 16 on the lower side of the outer trench 6. The trench bottom surface high concentration well region 17 is a p-type region having a higher concentration than the trench bottom surface electric field relaxation region 16, and is formed of silicon carbide.A contact hole 26 (hereinafter referred to as "outer peripheral region well region contact hole 26") reaching the trench bottom surface high concentration well region 17 is formed in the intermediate insulating layer 13, and the front surface ohmic electrode 19 connected to the trench bottom surface high concentration well region 17 is formed in a bottom of the trench bottom surface contact hole 26 at the outer peripheral region. The trench bottom surface electric field relaxation region 16 is electrically connected to the front surface electrode 14 through the trench bottom surface high concentration well region 17 and the front surface ohmic electrode 19 in the well region contact hole 26 at the outer surrounding region.The trench bottom surface high concentration well region 17 has an effect of reducing contact resistance between the trench bottom surface electric field relaxation region 16 and the front surface ohmic electrode 19, and an effect of reducing surface resistance on a surface of the trench bottom surface electric field relaxation region 16. It is sufficient that the depth of the high-concentration well region 17 for the trench bottom surface is approximately equal to or greater than 0.1 μm and equal to or less than 2.0 μm toward the lower side from the bottom surface of the outer trench 6.The trench bottom surface high concentration well region 17 may be in contact with the bottom surface of the outer trench 6. It is sufficient that the p-type impurities of the trench-bottom-surface high-concentration well region 17 are aluminum, boron, or gallium, and the impurity concentration of the trench-bottom-surface high-concentration well region 17 is about equal to or greater than 1×10 18 cm -3 and equal to or less than 1×10 22 cm -3.The terminal electric field relaxation region 18 is a p-type electric field relaxation region continuously or intermittently formed so as to surround the active region 50, and is, for example, a field limiting ring (FLR). The terminal electric field relaxation region 18 is formed by ion-implanting aluminum, boron, or gallium, for example, from the surface of the drift layer 2 to a depth of about 0.2 μm to 3 μm so that the depth of the drift layer 2 is not exceeded. It is sufficient that the concentration of the p-type impurity of the terminal electric field relaxation region 18 is higher than the impurity concentration of the drift layer 2, and is equal to or greater than 1×10 15 cm -3 and equal to or less than 1×10 19 cm -3.The field insulating film 12 is formed to be in contact with the surface of the drift layer 2 from the inside of the outer trench 6 to an end part of the chip. The field insulating layer 12 may be formed of an insulating material such as silicon dioxide. The thickness of the field insulating film 12 may be, for example, equal to or greater than 0.1 μm and equal to or less than 5.0 μm.The underlapping insulating film 7 is formed so as to cover the inner part of the outer trench 6 and an upper end corner portion 6 a(hereinafter referred to as "outer trench upper end corner portion 6 a"), and is in contact with the well region 3, the drift layer 2, the trench bottom surface electric field relaxation region 16, and the trench bottom surface high concentration well region 17. A part of the backing insulating film 7 is also formed on the field insulating film 12. The backing insulating layer 7 is formed of an insulating material such as silicon dioxide. The thickness of the backing insulating film 7 is, for example, about equal to or greater than 10 nm and equal to or less than 1000 nm.The potential fixing layer 8 is a layer having conductivity such as polysilicon, is formed on the spacer insulating layer 7, and covers the inner part of the outer trench 6 and the corner portion 6 aat the upper end of the outer trench via the spacer insulating layer 7. In the present embodiment, the potential fixing layer 8 is a first polysilicon layer made of polysilicon.A contact hole 27 (hereinafter referred to as "potential fixing layer connection contact hole 27") reaching the potential fixing layer 8 on the field insulating layer 12 is formed in the intermediate insulating layer 13, and the potential fixing layer 8 is connected to the front surface electrode 14 through the potential fixing layer connection contact hole 27. Since the potential on the front surface electrode 14 is the source potential, the potential of the potential fixing layer 8 is also the source potential. The potential fixing layer 8 has a thickness greater than the gate insulating film 10, and preferably has a thickness more than three times as large as the gate insulating film 10.The insulating layer 9 is formed so as to cover the potential fixing layer 8. The insulating layer 9 suppresses the flow of the gate leakage current between the potential fixing layer 8 and the gate electrode layer 11. The thickness of the insulating layer 9 is, for example, about equal to or greater than 10 nm and equal to or less than 1000 nm, and preferably has a thickness equal to or greater than the gate insulating layer 10.The gate insulating film 10 is formed to have contact with the inner surface of the gate trench 22, a part of the surface of the drift layer 2, the insulating film 9, and the field insulating film 12, and is formed of silicon dioxide. The thickness of the gate insulating film 10 may be, for example, about equal to or greater than 10 nm and equal to or less than 200 nm.The gate electrode layer 11 is formed on the gate insulating film 10 in the gate trench 22 and on the gate insulating film 10 formed on the insulating film 9 in the outer trench 6. In this way, the gate insulating film 10 and the gate electrode layer 11 extend from the inside of the gate trench 22 to the inside of the outer trench 6.In the present embodiment, the gate electrode layer 11 is a second polysilicon layer made of polysilicon. The gate electrode layer 11 formed in the terminal region 60 has, for example, a thickness larger than the gate insulating film 10. a contact hole 28 (hereinafter referred to as "gate contact hole 28") reaching the gate electrode layer 11 is formed in the intermediate insulating film 13, and the gate electrode layer 11 is connected to the gate line electrode 15 connected to a gate electrode terminal 29 via the gate contact hole 28.The front surface electrode 14, the gate line electrode 15, and the gate electrode terminal 29 are formed on the intermediate insulating film 13, and are formed of, for example, a metal material such as aluminum. The front surface electrode 14, the gate line electrode 15, and the gate electrode terminal 29 are arranged to be separated from each other.The back surface ohmic electrode 20 is formed on the back surface of the semiconductor substrate 1, and is formed of a reaction product of a metal layer of nickel as a main component and the semiconductor substrate 1, such as nickel silicide. The back surface electrode 21 is formed to contact the back surface ohmic electrode 20, and is formed of, for example, titanium, nickel, silver, gold, or aluminum.The semiconductor device according to Embodiment 1 is formed of the above-described components.A method of manufacturing the semiconductor device according to Embodiment 1 will be described next with reference to FIGS. 7 to 21. FIGS. 7 to 21 are explanatory diagrams of each stage of manufacture of the semiconductor device. Here, FIGS. 7 to 12 correspond to the cross section taken along the line B 1-B 2 in FIG. 2, and FIGS. 13 to 21 correspond to the cross section taken along the line D 1-D 2 in FIG. 2.First, the n-type silicon carbide semiconductor substrate 1 having a 4H polytype is prepared, and the n-type drift layer 2 is epitaxially formed thereon by a vapor chemical deposition (CVD) method. At this time, the impurity concentration of the n-type drift layer 2 is within a range of 1×10 14 cm -3 to 1×10 18 cm -3, and the thickness of the drift layer 2 is 5 μm to 300 μm.Subsequently, aluminum, boron, or gallium are ion-implanted using a resist mask formed on the drift layer 2 by photolithography processing, so that the p-type well region 3 is formed on the surface region of the drift layer 2. The well region 3 may be formed by epitaxial growth.Subsequently, nitrogen or phosphorus is ion-implanted using a resist mask formed on the well region 3 by photolithography processing, so that the n-type impurity region 4 is formed on the surface region of the well region 3.Subsequently, a silicon dioxide layer having a thickness of about 1 μm to 2 μm is formed on the well region 3 and the impurity region 4, and an etching mask in which formation regions where the gate trench 22 and the outer trench 6 are formed are opened is formed by reactive ion etching (RIE). Then, when the gate trench 22 and the outer trench 6 are formed by RIE, the states in FIGS. 7 and 13 are reached.After a resist mask covering a part of the outer trench 6 is formed by photolithography processing while the etching mask remains, aluminum, boron, or gallium are ion-implanted from the surface side of the drift layer 2, and thus the trench bottom surface electric field relaxation region 16 is formed on the lower side of the gate trench 22 and the outer trench 6.After the above-described etching mask and resist mask are removed and a resist mask is formed by photolithography processing, aluminum, boron, or gallium are ion-implanted from the surface side of the drift layer 2, so that the terminal electric field relaxation region 18 is formed in the terminal region 60.After a resist mask is formed by photolithography processing, aluminum, boron, or gallium are ion-implanted, and thus the p-type contact region 5 is formed on the surface region of the well region 3, and the trench bottom surface high concentration well region 17 is formed on the surface region of the trench bottom surface electric field relaxation region 16. A heating temperature of the semiconductor substrate 1 in this ion implantation is preferably equal to or higher than 150° C. When the heating temperature is equal to or higher than 150° C., the electric resistance of the contact region 5 can be decreased, and resistance losses in the operating state of the semiconductor device can be decreased.Subsequently, anneal processing is performed after the etch mask is removed so as to activate the impurities that have been ion-implanted. The annealing processing is carried out in an inactive gas atmosphere of, for example, argon, or in vacuum, at a temperature of about 1500°C to 1900°C for about 30 seconds to 1 hour. Here, a carbon layer may be formed on the semiconductor substrate 1 before the annealing processing to prevent deterioration of silicon carbide due to high temperature heating, i.e., surface roughening. Consequently, the states in FIGS. 8 and 14 are achieved.Next, an insulating film of silicon dioxide serving as the field insulating film 12 is formed by, for example, a CVD method, and a resist mask is formed on this insulating film by photolithography processing. Then, an opening is formed in the insulating layer by etching so that the field insulating layer 12 is formed, and the resist mask is removed. Consequently, the state in Fig. 15 is achieved.Next, the inner part of the outer trench 6 and the corner portion at the upper end are covered by, for example, a thermal oxidation method or a CVD method, and the underlapping insulating film 7 is formed to have contact with the well region 3, the drift layer 2, the trench bottom surface electric field relaxation region 16, and the trench bottom surface high concentration well region 17. A part of the backing insulating film 7 is also formed on the field insulating film 12.Subsequently, a conductive material of, for example, polysilicon serving as the potential fixing layer 8 is formed on the underlapping insulating film 7 by, for example, a CVD method, and a resist mask is formed on the polysilicon by photolithography processing. Then, the polysilicon is etched, thereby forming the potential fixing layer 8 in the terminal portion 60. A part of the potential fixing layer 8 is also formed on the field insulating layer 12. At this time, the polysilicon in the active region 50 is completely removed by etching until the underlapping insulating film 7 is exposed by an etch-back process. Then, resist mask is removed. Consequently, the state in Fig. 16 is achieved.Next, a layer of, for example, silicon dioxide serving as the insulating layer 9 is formed so as to cover the potential fixing layer 8 by, for example, a CVD method. When the potential fixing layer 8 is formed of polysilicon as a material, this layer may be formed of, for example, silicon dioxide by thermally oxidizing the surface of the potential fixing layer 8. Then, a resist mask is formed by photolithography processing, and the insulating layer 9 is formed by etching. The underlapping insulating film 7 and the insulating film 9 in the gate trench 22 in the active region 50 are completely removed by etching, thus exposing the drift layer 2. Consequently, the state in Fig. 17 is achieved.Next, the gate insulating film 10 is formed on the surface of the drift layer 2, the inner surface of the gate trench 22, and the insulating film 9, and the field insulating film 12 in the terminal region 60, for example, by a thermal oxidation method or a CVD method. Consequently, the states of Figs. 9 and 18 are achieved.Then, a conductive material of, for example, polysilicon serving as the gate electrode layer 11 is formed by, for example, a CVD method, and a resist mask is formed on the polysilicon by photolithography processing. Then, polysilicon is etched to form the gate electrode layer 11, and the resist mask is removed. At this time, polysilicon is formed in the active region 50 by an etch-back process so that the upper end of the gate electrode layer 11 is at a location equal to or lower than the surface position of the drift layer 2 in the gate trench 22. Consequently, the states of Figs. 10 and 19 are achieved.Next, the intermediate insulating layer 13 is formed by, for example, a decompression CVD method, and a resist mask is formed on the intermediate insulating layer 13 by photolithography processing. Subsequently, the intermediate insulating film 13 is etched to form the source contact hole 25 reaching the impurity region 4 and the contact region 5 and the well region contact hole 26 at the outer surrounding region reaching the trench bottom surface high concentration well region 17.Then, a metal layer formed of, for example, Ni as a main component is formed on the impurity region 4 and the contact region 5 exposed to the source contact hole 25 and the trench bottom surface high concentration well region 17 exposed to the well region contact hole 26 at the outer surrounding region, and anneal processing is performed, thus forming the front surface ohmic electrode 19. Then, the metal layer on the intermediate insulating layer 13 is removed by etching, and the resist mask is removed.Further, a metal layer formed of, for example, Ni as a main component is formed on the back surface of the semiconductor substrate 1, and annealing processing is performed so that the back surface ohmic electrode 20 is formed. Here, it is sufficient that the heating temperature in each annealing processing is about equal to or higher than 600° C. and equal to or lower than 1100° C.Then, a resist mask is formed on the intermediate insulating layer 13 by photolithography processing, and the intermediate insulating layer 13 is etched, so that the connection contact hole 27 for the potential fixing layer reaching the potential fixing layer 8 and the gate contact hole 28 reaching the gate electrode layer 11 are formed, and the resist mask is removed. Consequently, the states in FIGS. 11 and 20 are achieved.Then, a metal layer made of, for example, aluminum is formed on the intermediate insulating layer 13 and the front surface ohmic electrode 19 and the inner sides of the connection contact hole 27 for the potential fixing layer and the gate contact hole 28, for example, by a sputtering method or an evaporation method, and a resist mask is formed on the metal layer by photolithography processing. Subsequently, pattern formation is performed on the metal layer by etching so that the front surface electrode 14, the gate line electrode 15, and the gate electrode terminal 29 are formed, and then the resist mask is removed. Consequently, the states in FIGS. 12 and 21 are achieved.Finally, the back surface electrode 21 is formed on the back surface ohmic electrode 20 by, for example, a sputtering method or evaporation method, and the structure of the semiconductor device shown in FIGS. 4 and 6 is complete.The channel stop region 31 suppressing the extension of a depletion layer to an end part of the semiconductor device may be provided at the terminal region 60 as shown in FIG. 1. The channel stop region 31 is an n-type region disposed on a side closer to the outer periphery than the outer trench 6, and is formed of silicon carbide. It is sufficient that the n-type impurities of the channel stop region 31 are nitrogen or phosphorus, and the impurity concentration of the channel stop region 31 is about equal to or greater than 1×10 17 cm -3 and equal to or less than 1×10 22 cm -3. The thickness of the channel stop region 31 may be the same as that of the impurity region 4, or may be different therefrom.It is sufficient that the channel stop region 31 is formed by ion implantation. The channel stop region 31 may be formed simultaneously with the impurity region 4 using the resist mask for forming the impurity region 4, or may be formed before or after the formation of the impurity region 4. For example, when the channel stop region 31 is formed simultaneously with the impurity region 4, it is sufficient that the channel stop region 31 and the impurity region 4 are formed after the gate trench 22 and the outer trench 6 are formed.The order of performing the process of forming the well region 3 and the process of forming the impurity region 4 may be reversed. As the method for forming the well region 3 and the impurity region 4, after n-type impurities are ion-implanted into the surface region of the well region 3, a resist mask is formed thereon by photolithography processing, and p-type impurities are ion-implanted into a position different from the impurity region 4, thus forming the well region 3.In the above-described manufacturing method, the thickness of the etching mask and the RIE process are adjusted so that the etching mask remains after the gate trench 22 and the outer trench 6 are formed, and the trench bottom surface electric field relaxation region 16 is formed by ion implantation using the etching mask that has remained and the resist mask that has been formed by photolithography processing. However, it is also conceivable that the etching mask does not remain but is removed, and the trench bottom surface electric field relaxation region 16 is formed by ion implantation using only the resist mask formed by photolithography processing.The trench bottom surface electric field relaxation region 16 located on the lower side of the outer trench 6 may be formed simultaneously with the trench bottom surface electric field relaxation region 16 located on the lower side of the gate trench 22, or may be formed before or after the formation of the trench bottom surface electric field relaxation region 16 located on the lower side of the gate trench 22. In addition, it is conceivable that p-type impurities are ion-implanted in an oblique direction with respect to the gate trench 22, a p-type semiconductor layer is formed in the drift layer 2 that is in contact with a side surface of the gate trench 22, and the trench bottom surface electric field relaxation region 16 and the well region 3 are electrically connected to each other via the semiconductor layer.When the trench bottom surface electric field relaxation region 16 and the well region 3 are electrically connected to each other, the trench bottom surface electric field relaxation region 16 is connected to the front surface electrode 14 and grounded via the well region 3, compared to the state where the trench bottom surface electric field relaxation region 16 is in a floating state; thus, the frequency characteristics of the semiconductor device are improved.Although the example that the semiconductor device is the MOSFET is described in the present embodiment, when the semiconductor device is an IGBT, it is sufficient that the conductivity type of the semiconductor substrate 1 is the p-type, and the semiconductor substrate 1 may be ground to reduce the thickness thereof.Next, the operation of the semiconductor device according to the present embodiment will be described.When a gate voltage is equal to or greater than a threshold value between gate electrode terminal 29 and front surface electrode 14, a channel is formed in well region 3 facing gate electrode layer 11, and electrons flow from impurity region 4 to drift layer 2. when a voltage is applied between front surface electrode 14 and back surface electrode 21 and an electric field occurs, electrons reach back surface electrode 21 through drift layer 2 and semiconductor substrate 1.Here, when the gate insulating film 10 is formed to have contact with a surface and an inner side of each of the gate trench 22 and the outer trench 6, an electric field occurs in the gate insulating film 10 near a corner portion at the upper end 22 a(hereinafter, referred to as a "corner portion 22 aat the upper end of the gate trench") of the outer trench 6 and the corner portion 6 aat the upper end of the outer trench.However, in the active region 50, the gate electrode layer 11 is formed at a lower position than the corner portion 22 aat the upper end of the gate trench. Consequently, the concentration of the electric field caused by the shape of the corner portion 22 aat the upper end of the gate trench is suppressed, and breakdown of the gate insulating film 10 is prevented.Meanwhile, in the terminal region 60, the gate insulating film 10 is formed on the insulating film 9, and is separated from the corner region 6 aat the upper end of the outer trench. Consequently, the breakdown of the gate insulating film 10 is prevented by concentration of the electric field caused by the shape of the corner portion 6a at the upper end of the outer trench. Although the corner portion 6a at the upper end of the outer trench is covered by the underlying insulating film 7, the well portion 3 and the potential fixing film 8 have source potential, and also the potential fixing film 8 is insulated from the gate electrode film 11 by the insulating film 9 and the gate insulating film 10. Consequently, the underlapping insulating film 7 of the corner portion 6a at the upper end of the outer trench is not damaged by the gate voltage.Here, when the thickness of the potential fixing layer 8 is sufficiently large, since the potential fixing layer 8 covers the corner portion at the upper end and the inner part of the outer trench 6 via the underlying insulating layer 7, the curvature of the upper part of the potential fixing layer 8 can be increased by the difference in level of the outer trench 6. When the curvature of the upper part of the potential fixing layer 8 is increased, a decrease in the thickness of the insulating layer 9 and the gate insulating layer 10 formed on the potential fixing layer 8 can be prevented, and the effect of preventing the breakdown of the insulating layer 9 and the gate insulating layer 10 caused by the concentration of the electric field is further increased.When the thickness of the insulating layer 9 is small, insulation between the potential fixing layer 8 and the gate electrode layer 11 is insufficient, and there is a possibility that the gate-source leakage current increases as in the case where the potential of the field plate electrode is the source potential in Patent Document 2, and a portion between the potential fixing layer 8 and the gate electrode layer 11 is damaged by the electric field and short-circuited. In order to prevent such a state, the thickness of the insulating layer 9 is preferably larger than that of the gate insulating layer 10.According to such a configuration, the region between the potential fixing layer 8 and the gate electrode layer 11 can be insulated with a thickness twice or more as large as the gate insulating film 10, the insulation characteristics between the source and the gate in the terminal region 60 can be increased more than the active region 50, the gate-source leakage current in the terminal region 60 is suppressed, and also the effect of preventing the breakdown of the insulating film 9 and the gate insulating film 10 is improved.Meanwhile, when a voltage lower than a threshold is applied between gate electrode terminal 29 and front surface electrode 14, a channel is not formed in well region 3 facing gate trench 11, a current flowing from back surface electrode 21 toward front surface electrode 14 does not occur, and the semiconductor device enters an off state. In the semiconductor device in the off state, a voltage higher than that in the on state is applied between the front surface electrode 14 and the back surface electrode 21, and a depletion layer extends from the well region 3 to the drift layer 2.At this time, the depletion layer also extends from the trench bottom surface electric field relaxation region 16 to the drift layer 2. Accordingly, the electric field generated by the high voltage applied between front surface electrode 14 and back surface electrode 21 suppresses the breakdown of gate insulating film 10 in the bottom surface or a corner part of the bottom surface of each of gate trench 22 and outer trench 6.When the state of the semiconductor device is switched from the off state to the on state, the voltage applied between the front surface electrode 14 and the back surface electrode 21 decreases, and the depletion layer extending to the drift layer 2 shrinks. The semiconductor device is operated to alternately repeat the on-state and the off-state described above.With the semiconductor device according to Embodiment 1, breakdown of the gate insulating film 10 can be prevented in the corner region 22 aat the upper end of the gate trench and in the corner region 6 aat the upper end of the outer trench.Embodiment 2FIGS. 22 and 23 are diagrams each showing the configuration of a semiconductor device according to Embodiment 2. FIG. 22 is a cross-sectional view taken along line B 1-B 2 in FIG. 2, and FIG. 23 is a cross-sectional view taken along line C 1-C 2 in FIG. 2. in the present embodiment, the cross-sectional configurations taken along line A 1-A 2 and line D 1-D 2 in FIG. 2 are similar to those according to Embodiment 1.In Embodiment 2, the underlying insulating film 7 and the potential fixing film 8 are disposed below the gate insulating film 10 and the gate electrode film 11 in the gate trench 22 in the active region 50. The pad insulating film 7 is formed to contact the inner surface of the gate trench 22, and the potential fixing film 8 is formed on the pad insulating film 7 in the gate trench 22. The gate insulating film 10 is formed to have contact with the inner surface of the gate trench 22 and the upper surface of the potential fixing layer 8, and the gate electrode layer 11 is formed on the gate insulating film 10.In the present embodiment, the potential of the potential fixing layer 8 formed in the gate trench has the floating potential. The under-pad insulating film 7 is formed to have a thickness larger than the gate insulating film 10, so that the influence of the electric field occurring in the bottom surface of the gate trench 22 by the drain voltage is reduced.In FIG. 22, the electric field relaxation region 16 for the trench bottom surface is formed on the lower side of the gate trench 22, but may be omitted. When the trench bottom surface electric field relaxation region 16 is not formed, the electric field occurring in the bottom surface of the gate trench 22 by the drain voltage in the semiconductor device in the off state is divided by the depletion layer formed between the well region 3 and the drift layer 2, the underlying insulating layer 7, and the potential fixing layer 8. When the concentration of phosphorus in polysilicon of the potential fixing layer 8 is decreased, depletion of the polysilicon is increased, and the electric field relaxation effect can be increased.When the trench bottom surface electric field relaxation region 16 is not formed, the current narrowing in the on-state semiconductor device caused by the depletion layer extending from the well region 3 to the drift layer 2 and the depletion layer extending from the trench bottom surface electric field relaxation region 16 to the drift layer 2 is released. Consequently, an effect of improving the turn-on characteristics is also obtained.A method of manufacturing the semiconductor device according to Embodiment 2 will be described next with reference to FIGS. 24 to 37. FIGS. 24 to 37 are explanatory diagrams of the respective manufacturing stage of the semiconductor device. Here, FIGS. 24 to 30 correspond to the cross section taken along the line B 1-B 2 in FIG. 2, and FIGS. 31 to 37 correspond to the cross section taken along the line C 1-C 2 in FIG. 2.First, similarly to Embodiment 1, the semiconductor substrate 1 made of n-type silicon carbide with 4H polytype is prepared, and the n-type drift layer 2 is epitaxially grown thereon by chemical vapor deposition (CVD), so that the well region 3, the impurity region 4, the gate trench 22, and the trench bottom surface electric field relaxation region 16 are formed. Consequently, the states in FIGS. 24 and 31 are achieved.Next, an insulating film of silicon dioxide serving as the field insulating film 12 is formed by, for example, a CVD method, and a resist mask is formed on this insulating film by photolithography processing. Then, an opening is formed in the insulating layer by etching so that the field insulating layer 12 is formed, and the resist mask is removed.Then, the backing insulating film 7 is formed by, for example, a thermal oxidation method or a CVD method. Consequently, the states in Figs. 25 and 32 are achieved.Subsequently, a conductive material of polysilicon, for example, serving as the potential fixing layer 8 is formed on the underlapping insulating film 7 by, for example, a CVD method, and it is etched so that a desired thickness remains in the gate trench 22 by an etch-back process. Subsequently, a resist mask is formed by photolithography processing, the potential fixing layer 8 in the active region 50 and the potential fixing layer 8 in the terminal region 60 are separated by etching so that the potential fixing layer 8 in the active region 50 has floating potential, and the resist mask is removed. Consequently, the states of Figs. 26 and 33 are achieved.Next, the insulating layer 9 is formed of silicon dioxide so as to cover the potential fixing layer 8, for example, by a CVD method. When the potential fixing layer 8 is formed of polysilicon as a material, the insulating layer 9 can be formed by thermally oxidizing the potential fixing layer 8. Consequently, the states in Figs. 27 and 34 are achieved.Then, a resist mask is formed by photolithography processing, and etching is performed until the upper side of a sidewall of the potential fixing layer 8 and the upper end part thereof are exposed in the gate trench 22. Subsequently, the gate insulating film 10 is formed on the surface of the drift layer 2, the inner surface of the gate trench 22, and the insulating film 9 by, for example, a thermal oxidation method or a CVD method. Consequently, the states in FIGS. 28 and 35 are achieved.Then, a conductive material of, for example, polysilicon serving as the gate electrode layer 11 is formed by, for example, a CVD method, and a resist mask is formed on the polysilicon by photolithography processing. Then, polysilicon is etched to form the gate electrode layer 11, and the resist mask is removed. At this time, polysilicon is formed in the active region 50 by an etch-back process so that the upper end of the gate electrode layer 11 is at a location equal to or lower than the surface position of the drift layer 2 in the gate trench 22. Consequently, the states in Figs. 29 and 36 are achieved.Next, the intermediate insulating layer 13 is formed by, for example, a decompression CVD method, and a resist mask is formed on the intermediate insulating layer 13 by photolithography processing. Subsequently, the intermediate insulating film 13 is etched to form the source contact hole 25 reaching the impurity region 4 and the contact region 5 and the well region contact hole 26 at the outer surrounding region reaching the trench bottom surface high concentration well region 17.Then, a metal layer formed of, for example, Ni as a main component is formed on the impurity region 4 and the contact region 5 exposed to the source contact hole 25 and the trench bottom surface high concentration well region 17 exposed to the well region contact hole 26 at the outer surrounding region, and annealing processing is performed, thus forming the front surface ohmic electrode 19. Then, the metal layer on the intermediate insulating layer 13 is removed by etching, and the resist mask is removed.Further, a metal layer formed of, for example, Ni as a main component is formed on the back surface of the semiconductor substrate 1, and annealing processing is performed so that the back surface ohmic electrode 20 is formed. Here, it is sufficient that the heating temperature in each annealing processing is about equal to or higher than 600° C. and equal to or lower than 1100° C. Consequently, the states in Figs. 30 and 37 are achieved.Then, a metal layer made of, for example, aluminum is formed on the intermediate insulating layer 13 and the front surface ohmic electrode 19 and the inner sides of the connection contact hole 27 for the potential fixing layer and the gate contact hole 28, for example, by a sputtering method or an evaporation method, and a resist mask is formed on the metal layer by photolithography processing. Subsequently, pattern formation is performed on the metal layer by etching so that the front surface electrode 14, the gate line electrode 15, and the gate electrode terminal 29 are formed, and then the resist mask is removed.Finally, the back surface electrode 21 is formed on the back surface ohmic electrode 20 by, for example, a sputtering method or evaporation method, and the structure of the semiconductor device shown in FIGS. 22 and 23 is complete.Although the example in which the potential fixing layer 8 in the active region 50 and the potential fixing layer 8 in the terminal region 60 are separated by etching so that the potential fixing layer 8 in the active region 50 has floating potential is described in Embodiment 2, in a case where the potential fixing layer 8 in the terminal region 60 is not connected to an external electrode but has the floating potential, as described in Embodiment 4, the potential fixing layer 8 in the active region 50 and the potential fixing layer 8 in the terminal region 60 may be connected to each other.An effect similar to that in Embodiment 1 can also be obtained with the semiconductor device according to Embodiment 2. The thickness of the underlying insulating film 7 formed on the bottom surface of the gate trench 22 is larger than that of the gate insulating film 10, and the gate electrode film 11 is not located on the bottom surface of the gate trench 22, thus reducing the influence of the electric field occurring in the insulating film (e.g., silicon dioxide) on the bottom surface of the gate trench 22 by the drain voltage or the gate voltage in the semiconductor device in the off state, compared to the case where only the gate insulating film 10 is formed on the bottom surface of the gate trench 22.Embodiment 3FIGS. 38 to 40 are diagrams each showing a configuration of a semiconductor device according to Embodiment 3. FIG. 38 is a schematic view showing a schematic configuration of the semiconductor device according to Embodiment 3, and FIG. 39 illustrates a configuration of a region 41 surrounded by a broken line in FIG. 38. FIG. 40 is a cross-sectional view taken along line D 1-D 2 in FIG. 39 The illustration of, for example, the intermediate insulating layer 13, the front surface electrode 14, and the front surface ohmic electrode 19 is omitted to facilitate the description of FIG. 39.The semiconductor device according to Embodiment 3 has a ground electrode terminal 30 to which ground potential of 0 V is supplied, and a ground wiring electrode 23 connected thereto. In Embodiments 1 and 2, the example is described that the potential fixing layer 8 is connected to the front surface electrode 14 and the potential of the potential fixing layer 8 is the source potential. In Embodiment 3, the potential fixing layer 8 is connected to the ground wiring electrode 23, and the potential of the potential fixing layer 8 is set at ground potential. The other configurations are similar to those in Embodiment 1.Also in a case where the potential fixing layer 8 has the ground potential, the gate insulating film 10 is formed to be separated from the corner portion 6 aat the upper end of the outer trench in the terminal portion 60. Consequently, the concentration of the electric field caused by the shape of the corner portion 6a at the upper end of the outer trench is suppressed, and breakdown of the gate insulating film 10 is prevented. Although the corner portion 6a at the upper end of the outer trench is covered by the underlying insulating film 7, the well portion 3 has source potential and the potential fixing film 8 has ground potential, and also the potential fixing film 8 is insulated from the gate electrode film 11 by the insulating film 9 and the gate insulating film 10. Consequently, the underlapping insulating film 7 of the corner portion 6a at the upper end of the outer trench is not damaged by the gate voltage.Embodiment 4FIGS. 41 and 42 are diagrams each showing a configuration of a semiconductor device according to Embodiment 4. FIG. 41 is a schematic view showing a schematic configuration of the semiconductor device according to Embodiment 4, and illustrates a configuration of the region 40 surrounded by the broken line in FIG. 1. FIG. 42 is a cross-sectional view taken along line D 1-D 2 in FIG. 41 The illustration of, for example, the intermediate insulating layer 13, the front surface electrode 14, and the front surface ohmic electrode 19 is omitted to facilitate the description in FIG. 41.In Embodiment 4, the potential fixing layer connection contact hole 27 is not formed in the intermediate insulating layer 13, and the potential fixing layer 8 is not connected to any other electrode. That is, the potential of the potential fixing layer 8 is set to the floating potential. The other configurations are similar to those in Embodiments 1 to 3.Also in a case where the potential fixing layer 8 has the floating potential, the gate insulating film 10 is formed to be separated from the corner portion 6 aat the upper end of the outer trench in the terminal portion 60. Consequently, the concentration of the electric field caused by the shape of the corner portion 6a at the upper end of the outer trench is suppressed, and breakdown of the gate insulating film 10 is prevented. Although the corner portion 6a at the upper end of the outer trench is covered by the underlying insulating film 7, the well portion 3 has source potential and the potential fixing film 8 has ground potential, and also the potential fixing film 8 is insulated from the gate electrode film 11 by the insulating film 9 and the gate insulating film 10. Consequently, the underlapping insulating film 7 of the corner portion 6a at the upper end of the outer trench is not damaged by the gate voltage.Embodiment 5FIGS. 43 to 45 are diagrams each showing a configuration of a semiconductor device according to Embodiment 5. FIG. 43 is a cross-sectional view taken along the line D 1-D 2 in FIG. 2, FIG. 44 is a cross-sectional view taken along the line D 1-D 2 in FIG. 39, and FIG. 45 is a cross-sectional view taken along the line D 1-D 2 in FIG. 41.In Embodiments 1 to 4, the example is described that the well region 3 and the trench bottom surface electric field relaxation region 16 are separated from each other in the terminal region 60.In Embodiment 5, the well region 3 and the trench bottom surface electric field relaxation region 16 are connected to each other by a p-type outer trench side surface connection layer 24 formed on a side surface of the outer trench 6. The other configurations are similar to those in Embodiments 1 to 4. FIG. 43 corresponds to the configuration in FIG. 6 with the surface connection layer 24 present on the outer trench side, FIG. 44 corresponds to the configuration in FIG. 40 with the surface connection layer 24 present on the outer trench side, and FIG. 45 corresponds to the configuration in FIG. 42 with the surface connection layer 24 present on the outer trench side.It is sufficient that the surface connection layer 24 on the outer trench side is formed by ion implantation after forming the trench bottom surface electric field relaxation region 16, the p-type impurities are aluminum, boron, or gallium, and the impurity concentration is, for example, about equal to or greater than 1×10 17 cm -3 and equal to or less than 1×10 22 cm -3.When the well region 3 and the trench bottom surface electric field relaxation region 16 are connected in the side surface of the outer trench 6, the path of the displacement current occurring at the turn-off operation and flowing to the front surface electrode 14 is enlarged. Consequently, an increase in the potential of the underlapping insulating film 7 at the corner portion 6 aat the upper end of the outer trench caused by the displacement current is suppressed, and breakdown of the underlapping insulating film 7 is prevented.Embodiment 6FIGS. 46 to 49 are diagrams each showing a configuration of a semiconductor device according to Embodiment 6. FIG. 46 is a cross-sectional view taken along the line B 1-B 2 in FIG. 2, FIG. 39 or FIG. 41, FIG. 47 is a cross-sectional view taken along the line D 1-D 2 in FIG. 2, FIG. 48 is a cross-sectional view taken along the line D 1-D 2 in FIG. 39, and FIG. 49 is a cross-sectional view taken along the line D 1-D 2 in FIG. 41.In Embodiment 6, the under bump insulating film 7 is not formed, but the potential fixing layer 8 is in contact with the inner surface of the outer trench 6 and the corner portion 6 aat the upper end of the outer trench. The other configurations are similar to those in Embodiments 1 to 5. FIG. 47 corresponds to the configuration in FIG. 43 with the backing insulating layer 7 omitted, FIG. 48 corresponds to the configuration in FIG. 44 with the backing insulating layer 7 omitted, and FIG. 49 corresponds to the configuration in FIG. 45 with the backing insulating layer 7 omitted.Also in a case where the underlapping insulating film 7 is omitted, the gate insulating film 10 is formed to be separated from the corner portion 6 aat the upper end of the outer trench in the terminal portion 60. Consequently, the concentration of the electric field caused by the shape of the corner portion 6a at the upper end of the outer trench is suppressed, and breakdown of the gate insulating film 10 is prevented.In a manner similar to Embodiments 1 to 5, the potential of the potential fixing layer 8 is set to any one of the source potential, the ground potential, and the floating potential. Even if the potential of the potential fixing layer 8 is the source potential or the ground potential, a current hardly flows from the back surface electrode 21 to the potential fixing layer 8 by the influence of the pn junction between the drift layer 2 and the well region 3, the surface connection layer 24 on the outer trench side, the electric field relaxation region 16 for the trench bottom surface, and the high concentration well region 17 for the trench bottom surface, and there is little influence on the loss.The respective embodiments may be freely combined, or each embodiment may be appropriately varied or features may be omitted.The foregoing description is in all aspects illustrative and not restrictive, and it is therefore to be understood that numerous modification examples not described by way of example may be devised.List of reference characters1 Semiconductor substrate 2 Drift layer 3 Well region 4 Impurity region 5 Contact region 6 Outer trench 6 a Eckbereich region at the upper end of the outer trench 7 Underlying insulating layer 8 Potential fixing layer 9 Insulating layer 10 Gate insulating layer 11 Gate electrode layer 12 Field insulating layer 13 Intermediate insulating layer 14 Front surface electrode, 15 gate line electrode 16 trench bottom surface electric field relaxation region 17 trench bottom surface high concentration well region 18 terminal electric field relaxation region 19 front surface ohmic electrode 20 back surface ohmic electrode 21 back surface electrode 22 gate trench 22 aa gate trench upper end corner region 23 ground wiring electrode 24 trench outer side surface connection layer 25 source contact hole 26 outer surrounding region well region contact hole 27 potential fixing layer connection contact hole 28 gate contact hole 29 gate electrode terminal 30 ground electrode terminal 31 channel stop region 50 active region 60 terminal region.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedJP 2001-102 572 A

[0005] JP 2011-199 109 A

[0005]

Claims

A semiconductor device comprising: a drift layer of a first conductivity type; a well region of a second conductivity type formed on a surface region of the drift layer; a first conductivity type impurity region formed on a surface region of the well region; a gate trench passing through the impurity region and the well region in an active region and reaching the drift layer; a gate insulating layer formed to contact an inner surface of the gate trench; a gate electrode layer formed on the gate insulating layer; an intermediate insulating layer covering the gate electrode layer; a gate line electrode formed on the intermediate insulating layer and connected to the gate electrode layer; an outer trench formed in the drift layer in a terminal region on an outer side of the active region; a potential fixing layer formed in the outer trench and covering a corner region at an upper end of the outer trench; and an insulating layer formed on the potential fixing layer, wherein the gate insulating layer and the gate electrode layer extend to the inner side of the outer trench of the terminal region, and the gate electrode layer is connected to the gate line electrode through a contact hole formed in the intermediate insulating layer in the outer trench.The semiconductor device according to claim 1, wherein the potential fixing layer has a thickness greater than the thickness of the gate insulating layer.The semiconductor device according to claim 1 or 2, further comprising: a backing insulating layer formed below the potential fixing layer.The semiconductor device according to claim 3, wherein the thickness of the underlapping insulating layer is equal to or greater than the thickness of the gate insulating layer.The semiconductor device according to any one of claims 1 to 4, wherein a part of the potential fixing layer is formed on a bottom part of the gate trench, and the gate insulating film and the gate electrode layer are formed in the gate trench on the gate trench, and the potential fixing layer is formed on the bottom part of the gate trench to have floating potential.The semiconductor device according to any one of claims 1 to 5, further comprising: a trench bottom surface electric field relaxation region of the second conductivity type formed on the lower side of the outer trench; and a trench outer side surface connection layer of the second conductivity type formed on a side surface of the outer trench and connecting the well region and the trench bottom surface electric field relaxation region.The semiconductor device according to any one of claims 1 to 6, further comprising: a front surface electrode formed on the intermediate insulating layer and connected to the well region, wherein the potential fixing layer is connected to the front surface electrode through a contact hole formed in the intermediate insulating layer.The semiconductor device according to any one of claims 1 to 6, further comprising: a ground wiring electrode formed on the intermediate insulating layer, wherein the potential fixing layer is connected to the ground wiring electrode through a contact hole formed in the intermediate insulating layer.The semiconductor device according to any one of claims 1 to 6, wherein the potential fixing layer is formed to have floating potential.The semiconductor device according to any one of claims 1 to 9, wherein the gate electrode layer in the terminal region surrounds the gate trench in plan view.The semiconductor device according to any one of claims 1 to 10, wherein the thickness of the potential fixing layer is three times or more as large as the thickness of the gate insulating layer.The semiconductor device according to any one of claims 1 to 11, wherein the thickness of the insulating layer is equal to or greater than the thickness of the gate insulating layer.The semiconductor device according to any one of claims 1 to 12, wherein the upper end of the gate electrode layer of the gate trench is located at a position lower than the upper end of the gate trench.A method of manufacturing a semiconductor device, comprising: a step of forming a drift layer of a first conductivity type; a step of forming a well region of a second conductivity type on a surface region of the drift layer; a step of forming an impurity region of the first conductivity type on a surface region of the well region; a step of forming a gate trench that passes through the impurity region and the well region in an active region and reaches the drift layer; a step of forming an outer trench in the drift layer in a terminal region on the outside of the active region; a step of forming a potential fixing layer in the outer trench so as to cover a corner region at the upper end of the outer trench; a step of forming an insulating layer on the potential fixing layer; a step of forming a gate insulating film in the gate trench and the outer trench; a step of forming a gate electrode layer on the gate insulating film in the gate trench and the outer trench; a step of forming an intermediate insulating film covering the gate electrode layer; a step of forming a contact hole reaching the gate electrode layer in the intermediate insulating film in the outer trench; and a step of forming a gate line electrode connected to the gate electrode layer through the contact hole on the intermediate insulating film.The method for manufacturing the semiconductor device according to claim 14, wherein the potential fixing layer is formed to have a thickness greater than the thickness of the gate insulating layer.The method for manufacturing the semiconductor device according to claim 14 or claim 15, further comprising: a step of forming a spacer insulating layer disposed below the potential fixing layer before forming the potential fixing layer.The method for manufacturing the semiconductor device according to any one of claims 14 to 16, wherein a part of the potential fixing layer is formed in the gate trench in the step of forming the potential fixing layer.

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