Semiconductor device

Abstract

Semiconductor device (100), comprising: an insulating substrate (1); a first conductive layer (2) which is bonded to the insulating substrate (1); a second conductor layer (3) which is bonded to the first conductor layer (2) and has an overhang part (3a) which is a side end part that projects in a lateral direction from a side end part of the first conductor layer (2); a sealing element (10) having a sub-area embedded in a space (4) between the overhanging part (3a) and the insulating substrate (1); and a semiconductor element (5) covered with the sealing element (10), wherein a recessed step section (2b) is provided in a cross-sectional view in an outer circumferential part of the first conductor layer (2).

Description

Technical field

[0001] The present disclosure relates to a semiconductor device. Background State of the art

[0002] A semiconductor device has been proposed in which a slight undercut shape is provided on a side surface of a circuit structure, which is a single conductor layer, by etching or stamping (for example, patent document 1). According to such a configuration, it is possible to prevent the detachment of a sealing element due to a temperature change or the like by means of an adhesion effect caused by the undercut shape.

[0003] EP 1 039 539 B1 discloses a method for manufacturing a ceramic printed circuit board for mounting high-density electrical components and a corresponding ceramic printed circuit board.

[0004] DE 10 2019 135 373 A1 discloses a semiconductor device comprising a substrate consisting of an insulator, a first conductor film, a semiconductor chip, and an external terminal block that is connected to the substrate at a position separated from the first conductor film via a bonding layer. State of the art document / Patent document

[0005] Patent document 1: Japanese patent no. JP 6 210 818 B2 Summary Problem to be solved by the invention

[0006] In the prior art configuration, where the undercut shape is formed on the side surface of the individual conductor layer by etching or stamping, the undercut shape depends on the thickness of the conductor layer. This presents a problem: the undercut shape is not stable, and the desired effect of preventing the sealing element from detaching cannot be achieved.

[0007] Thus, the present disclosure has been developed in view of the aforementioned problem, and one of its objectives is to provide a technique suitable for more reliably preventing the detachment of a sealing element. Means to solve the problem

[0008] This problem is solved by the features of the independent claims. The dependent claims contain advantageous embodiments of the invention.

[0009] A semiconductor device according to the present disclosure comprises an insulating substrate, a first conductor layer bonded to the insulating substrate, a second conductor layer bonded to the first conductor layer and having an overhang part which is a side end part projecting in a lateral direction from a side end part of the first conductor layer, a sealing element having a partial area embedded in a space between the overhang part and the insulating substrate, and a semiconductor element covered with the sealing element, wherein a recessed step part is provided in a cross-sectional view in an outer circumferential part of the first conductor layer or the second conductor layer. Effects of the invention

[0010] According to the present disclosure, a second conductor layer has an overhanging portion, which is a side-end portion projecting laterally from a side-end portion of the first conductor layer, and a sealing element has a portion embedded in a space between the overhanging portion and the insulating substrate. According to such a configuration, it is possible to more reliably prevent the sealing element from detaching.

[0011] The functions, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. Brief description of the drawings [ Fig. Figure 1] is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [ Fig. 2] is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. [ Fig. Figure 3] is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment. [ Fig. 4] is a cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment. [ Fig. Figure 5] is a cross-sectional view showing a configuration of a semiconductor device according to a fifth embodiment. [ Fig. Figure 6] is a cross-sectional view showing a configuration of a semiconductor device according to a sixth embodiment. [ Fig. Figure 7] is a cross-sectional view showing a configuration of a semiconductor device according to a seventh embodiment. [ Fig. Figure 8] is a top view showing a configuration of the semiconductor device according to the seventh embodiment. [ Fig. Figure 9] is a cross-sectional view showing a configuration of a semiconductor device according to an eighth embodiment. [ Fig. Figure 10] is a cross-sectional view showing a configuration of a semiconductor device according to a ninth embodiment. [ Fig. Figure 11] is a top view showing a configuration of the semiconductor device according to the ninth embodiment. [ Fig.

[12] is a cross-sectional view showing a configuration of a semiconductor device according to a tenth embodiment. Description of the embodiments

[0012] The following descriptions illustrate embodiments with reference to the accompanying drawings. Features described in the following embodiments are examples, and not all features are necessarily essential. Furthermore, similar components in a number of embodiments are identified by the same or similar reference numerals, and mainly different components are described. Additionally, certain positions and directions in the following description, such as "top," "bottom," "left," "right," "front," or "back," need not necessarily correspond to actual positions and directions in practice. <Erste Ausführungsform>

[0013] Fig. Figure 1 is a cross-sectional view showing a configuration of a semiconductor device 100 according to the first embodiment. The semiconductor device 100 comprises a ceramic insulating substrate 1, a first conductor layer 2, a second conductor layer 3, a semiconductor element 5, a solder 6, a wire 7, a third conductor layer 8, a base part 9, and a sealing element 10.

[0014] The ceramic insulating substrate 1 is an insulating substrate consisting, for example, of aluminum nitride (AlN) or silicon nitride (SiN). The first conductor layer 2 is bonded to the ceramic insulating substrate 1, that is, to a front surface of the ceramic insulating substrate 1, and the third conductor layer 8 is bonded to the underside of the ceramic insulating substrate 1, that is, to a rear surface of the ceramic insulating substrate 1.

[0015] The first conductor layer 2 and the third conductor layer 8 each have multiple circuit structures. After the first conductor layer 2 is bonded to the ceramic insulating substrate 1, a circuit structure can be formed on the first conductor layer 2 by etching or similar processes, or after the circuit structure on the first conductor layer 2 has been formed by punching or similar processes, the first conductor layer 2 can be bonded to the ceramic insulating substrate 1. The circuit structure of the third conductor layer 8 is formed in a similar manner to the circuit structure of the first conductor layer 2.

[0016] The second conductor layer 3 is bonded to the first conductor layer 2, that is, to a front surface of the first conductor layer 2. The second conductor layer 3 has an overhang 3a, which is a side end part that extends in a lateral direction (a direction corresponding to a left-right direction). Fig. 1 corresponds) with respect to a side end portion of the first conductor layer 2. The overhang portion 3a projects laterally from the side end portion of the first conductor layer 2 by, for example, approximately 50 µm. An undercut shape is formed by the side portion of the first conductor layer 2 and the overhang portion 3a of the second conductor layer 3. It should be noted that the second conductor layer 3 can be suitably structured to maintain a wiring ratio through the circuit structure of the first conductor layer 2.

[0017] For example, the material of the first conductor layer 2 and the second conductor layer 3 is aluminum or copper, including an alloy. For instance, if the material of the first conductor layer 2 is aluminum and the material of the second conductor layer 3 is copper, an improvement in the heat dissipation of the semiconductor device 100 can be expected, or an improvement in the reliability of the semiconductor device 100 can be expected due to an improvement in strength. The material of the third conductor layer 8 can be the same as the material of the first conductor layer 2. To bond the first conductor layer 2 and the second conductor layer 3, methods such as brazing, soldering, welding, liquid or solid diffusion bonding, or similar processes can be used.

[0018] The semiconductor element 5 is electrically connected to the second conductor layer 3. In the example of Fig. In step 1, the semiconductor element 5 is bonded to a front surface of the second conductor layer 3 by the solder 6. The semiconductor element 5 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a reverse-conducting IGBT (RC-IGBT), a Schottky blocking diode (SBD), or a PN junction diode (PND). The material of the semiconductor element 5 can be ordinary silicon (Si) or a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. In the case where the material of the semiconductor element 5 is a wide-bandgap semiconductor, stable operation at high temperature and high voltage, as well as high switching speed, can be achieved.

[0019] The semiconductor element 5 is electrically connected to another circuit structure (not shown) or the like via wire 7. The material of wire 7 is, for example, aluminum. The semiconductor element 5 can also be electrically connected to another circuit structure or the like via a busbar (not shown) instead of wire 7. Although not shown, another circuit structure can be electrically connected to an external terminal, for example, by soldering or welding.

[0020] The base part 9 is bonded beneath the third conductor layer 8. The base part 9 is made of, for example, aluminum, copper, or similar materials and is a cooling component, such as a finned tube or a base plate.

[0021] The sealing element 10 covers the semiconductor element 5. In the example of Fig. The sealing element 10 also covers the first conductor layer 2, the second conductor layer 3, and so on. The sealing element 10 is made of a resin, such as an epoxy or a gel, and is formed by injection molding. It should be noted that the sealing element 10 also fills a portion of the space beneath the overhanging part 3a. In other words, the sealing element 10 has a portion that is embedded in a space 4 between the overhanging part 3a and the ceramic insulating substrate 1. <Zusammenfassung der ersten Ausführungsform>

[0022] In general, the temperature of the semiconductor device changes depending on the excitation operation and the external environment. If, due to this temperature change, the sealing element 10 detaches from the ceramic insulating substrate 1, the first conductor layer 2, the second conductor layer 3, the semiconductor element 5, and the like, there is a possibility that the reliability of the semiconductor device will deteriorate.

[0023] In contrast, according to the semiconductor device 100 of the first embodiment, the second conductor layer 3 has the overhang portion 3a, which is a side end portion projecting laterally from the side end portion of the first conductor layer 2, and the sealing element 10 has a partial area that is embedded in the space 4 between the overhang portion 3a and the ceramic insulating substrate 1. According to such a configuration, it is possible to prevent the sealing element 10 from detaching in a vertical direction due to an adhesive effect by the overhang portion 3a.

[0024] Furthermore, by designing the second conductor layer 3 to be slightly larger laterally than the first conductor layer 2, the length of the overhang of the overhanging portion 3a can be stabilized. This stabilizes the undercut shape, regardless of the thickness of the first conductor layer 2 or similar factors, thus more reliably preventing the sealing element from detaching. Additionally, in configurations with multiple groups of the first conductor layer 2 and the second conductor layer 3, insulation between the groups can be ensured simply by maintaining a gap between the second conductor layers 3, making it easy to secure the insulation.

[0025] It should be noted that, although in the preceding description the length of the overhang of the overhang part 3a from the side end part of the first conductor layer 2 is described as being about 50 µm, the length may be 50 µm or more if the size in the lateral direction of the semiconductor device 100 may be somewhat large. <Zweite Ausführungsform>

[0026] Fig. Figure 2 is a cross-sectional view showing a configuration of the semiconductor device 100 according to a second embodiment. The configuration of Fig. 2 is similar to the configuration in which a fourth conductor layer 11 is added to the configuration of Fig. The fourth conductor layer 11 is added. The fourth conductor layer 11 is bonded to the third conductor layer 8 in a similar way to how the second conductor layer 3 is bonded to the first conductor layer 2. Furthermore, the strength of the fourth conductor layer 11 differs from the strength of the third conductor layer 8.

[0027] In general, a bulge occurs in the ceramic insulation substrate 1, to which circuit structures such as the first conductor layer 2 and the third conductor layer 8 are bonded, due to a difference in strength between the first conductor layer 2 and the third conductor layer 8. In particular, in a case where the material of the first conductor layer 2 is pure aluminum and the material of the second conductor layer 3 is a copper alloy, for example, a relatively large bulge occurs in the ceramic insulation substrate 1.

[0028] In contrast, according to the semiconductor device 100 of the second embodiment, the fourth conductor layer 11, which has a different strength than the third conductor layer 8, is bonded beneath the third conductor layer 8. According to this configuration, the strength of the third conductor layer 8 and the fourth conductor layer 11 can improve the balance between the upper and lower strength of the ceramic insulating substrate 1, thus preventing warping of the ceramic insulating substrate 1. This is expected to improve the reliability and simplify the assembly of the semiconductor device 100. <Dritte Ausführungsform>

[0029] Fig. Figure 3 is a cross-sectional view showing a configuration of the semiconductor device 100 according to a third embodiment. It should be noted that a representation of the sealing element 10 is shown in Figure 3. Fig. 3 and subsequent drawings are omitted.

[0030] The configuration of Fig. 3 is similar to the configuration in which a recess 3b is located in the second conductor layer 3 in the configuration of Fig. 1. The recess 3b of the second conductor layer 3 is slightly larger than an upper section, which is part of the first conductor layer 2, and is adapted to the upper section of the first conductor layer 2. In this state, the second conductor layer 3 is bonded to the first conductor layer 2. The recess 3b is formed, for example, by punching or machining in the second conductor layer 3.

[0031] According to the semiconductor device 100 of the third embodiment, as described above, the recess 3b, which is adapted to a portion of the first conductor layer 2, is provided in the second conductor layer 3. In such a configuration, during the bonding process between the first conductor layer 2 and the second conductor layer 3, the first conductor layer 2 and the second conductor layer 3 are easily positioned, and misalignment between them can be reduced, thus stabilizing the length of the overhang portion 3a. Furthermore, in the configuration where multiple groups of the first conductor layer 2 and the second conductor layer 3 are provided, the spacing between the second conductor layers 3, that is, the spacing between the respective groups, can be stabilized, thus stabilizing the insulation. It is also possible to prevent a decrease in the strength of the first conductor layer 2.

[0032] The shape of the recess 3b in a top view can be a polygon, such as a rectangle or a hexagon, or it can be a circle. In a case where the shape of the recess 3b in a top view is a polygon, it is possible to prevent rotation of one of the first conductor layer 2 and the second conductor layer 3 with respect to the other. <Vierte Ausführungsform>

[0033] Fig. Figure 4 is a cross-sectional view showing a configuration of the semiconductor device 100 according to a fourth embodiment. The configuration of Fig. 4 is similar to the configuration in which the configuration of Fig. 1. A projection 3c is provided in the second conductor layer 3, and a recess 2a is provided in the first conductor layer 2. The projection 3c is located in the central part of a lower section of the second conductor layer 3. The recess 2a of the first conductor layer 2 is slightly larger than the projection 3c, which is part of the second conductor layer 3, and is adapted to the projection 3c of the second conductor layer 3. In this state, the second conductor layer 3 is bonded to the first conductor layer 2. The recess 2a is formed, for example, by punching or machining in the first conductor layer 2. The recess 2a can be formed before or after the first conductor layer 2 is bonded to the ceramic insulating substrate 1. The projection 3c is formed, for example, by punching or machining on the second conductor layer 3.

[0034] According to the semiconductor device 100 of the fourth embodiment, as described above, the recess 2a, which is adapted to the part of the second conductor layer 3, is provided in the first conductor layer 2. According to such a configuration, the same effects as those of the third embodiment can be obtained.

[0035] It should be noted that the shape of the recess 2a in a top view can be a polygon, such as a rectangle or a hexagon, or it can be a circle. In a case where the shape of the recess 2a in a top view is a polygon, it is possible to prevent rotation of one of the first conductor layer 2 and the second conductor layer 3 relative to the other. <Fünfte Ausführungsform>

[0036] Fig. Figure 5 is a cross-sectional view showing a configuration of the semiconductor device 100 according to a fifth embodiment. The configuration of Fig. 5 is similar to the configuration in which a recessed and relatively thin step portion 2b is located in an outer circumferential part of the first conductor layer 2 in the cross-sectional view in the configuration of Fig. 1 is provided. In the example of Fig. In section 5, the step section 2b is provided in the outer circumferential part of an upper surface of the first conductor layer 2 on the side of the second conductor layer 3. The step section 2b is formed, for example, by stamping or machining in the first conductor layer 2. The step section 2b can be formed before or after the first conductor layer 2 is bonded to the ceramic insulating substrate 1. The depth of the step section 2b can be, for example, half the thickness of the first conductor layer 2 or less by halving it. The width of the step section 2b is, for example, 50 µm or more and 5 mm or less.

[0037] The thickness of the first conductor layer 2 can be, for example, approximately 0.1 mm to 2 mm, or it can be less than 0.1 mm. However, if the thickness of the first conductor layer 2 is less than 0.1 mm, the space 4 between the overhanging part 3a and the ceramic insulating substrate 1 becomes small, so the sealing element 10 is less likely to fill the space 4.

[0038] In contrast, according to the semiconductor device 100 of the fifth embodiment, the recessed step portion 2b is provided in the outer circumferential part of the first conductor layer 2. With this configuration, a sufficient size of space 4 between the overhang portion 3a and the ceramic insulating substrate 1 can be ensured, making it easy to fill space 4 with the sealing element 10. Furthermore, even if the length of the overhang portion 3a cannot be increased to reduce the size of the semiconductor device 100, a holding effect can be achieved by filling the space between the second conductor layer 3 and the step portion 2b with the sealing element 10. It is therefore possible to achieve both a reduction in size and an improvement in the reliability of the semiconductor device 100. <Sechste Ausführungsform>

[0039] Fig. Figure 6 is a cross-sectional view showing a configuration of the semiconductor device 100 according to a sixth embodiment. The configuration of Fig. 6 is similar to the configuration in which a recessed and relatively thin step section 3d is located in an outer circumferential part of the second conductor layer 3 in the cross-sectional view in the configuration of Fig. 1 is provided. In the example of Fig. In embodiment 6, the stepped portion 3d is provided in the outer circumferential part of a lower surface of the second conductor layer 3 on the side of the first conductor layer 2. The stepped portion 3d is formed, for example, by stamping or machining in the second conductor layer 3. The shape, depth, and dimensions of the stepped portion 3d are, for example, similar to the shape, depth, and dimensions of the stepped portion 2b according to the fifth embodiment.

[0040] According to the semiconductor device 100 of the sixth embodiment, as described above, the recessed step portion 3d is provided in the outer circumferential part of the surface of the second conductor layer 3 on the side of the first conductor layer 2. According to such a configuration, effects similar to those of the fifth embodiment can be obtained.

[0041] It should be noted that the fifth and sixth embodiments can be combined. In other words, the stage part 2b can be provided in the first conductor layer 2 and the stage part 3d can be provided in the second conductor layer 3. <Siebte Ausführungsform>

[0042] Fig. Figure 7 is a cross-sectional view showing a configuration of the semiconductor device 100 according to a seventh embodiment, and Fig. Figure 8 is a top view showing the configuration of the semiconductor device 100. It should be noted that in Fig. 8 a different protrusion 3e than the protrusion 3e is located behind the second conductor layer 3, and is thus represented by a dashed line, which is a hidden line.

[0043] The configurations of Fig. 7 and Fig. 8 are similar to the configuration in which the overhang 3e, which projects towards the ceramic insulating substrate 1, is provided in the overhang part 3a, and a cutout part 3f in an outer circumferential part of the overhang part 3a in a top view in the configuration of Fig. 1 is planned.

[0044] For example, the overhang 3e is formed by providing a cut at both ends of a portion of each side part of the second conductor layer 3 by machining, laser cutting or punching, and bending the part downwards, for example by pressing. As in Fig. As shown in Figure 8, the cutout section 3f is formed in a sub-area of ​​the second conductor layer 3, which is used for the projection 3e. It should be noted that the formation of the projection 3e and the cutout section 3f is not limited to this.

[0045] The width of the cutout 3f in one direction along each side of the second conductor layer 3 is, for example, 1 mm to 10 mm, and the depth of the cutout 3f is, for example, 0.2 mm to 2 mm. The angle at which the other projection 3e protrudes from the second conductor layer 3 is, for example, 45° to 135°, and the height of the projection 3e is less than the thickness of the first conductor layer 2.

[0046] According to the semiconductor device 100 of the seventh embodiment, as described above, the overhang 3e, which projects towards the ceramic insulating substrate 1, is provided in the overhang portion 3a. According to such a configuration, at the time of bonding the first conductor layer 2 and the second conductor layer 3, the first conductor layer 2 and the second conductor layer 3 are easily positioned, and misalignment between them can be reduced, so that the length of the overhang portion 3a can be stabilized.

[0047] Furthermore, in the seventh embodiment, the cutout part 3f is provided in the outer circumferential part of the overhang part 3a in a top view. According to such a configuration, detachment of the sealing element 10 in the lateral direction can be prevented by a holding effect obtained by filling the cutout part 3f with the sealing element 10. <Achte Ausführungsform>

[0048] Fig. Figure 9 is a cross-sectional view showing a configuration of the semiconductor device 100 according to an eighth embodiment. The configuration of Fig. 9 is similar to the configuration in which the second conductor layer 3 has a plurality of sublayers 3g, 3h and 3i which are in a thickness direction (direction that corresponds to the vertical direction in Fig. 9 corresponds) to the second conductor layer 3 in the configuration of Fig. 1 are stacked. A side end portion of a sublayer away from the first conductor layer 2 from the plurality of sublayers 3g to 3i protrudes laterally from a side end portion of a sublayer near the first conductor layer 2 from the plurality of sublayers 3g to 3i. The materials or thicknesses of the plurality of sublayers 3g to 3i need not be the same and can be changed as required. The number of the plurality of sublayers contained in the second conductor layer 3 is not limited to three.

[0049] According to the semiconductor device 100 of the eighth embodiment, as described above, the first conductor layer 2 has a plurality of sublayers 3g to 3i, and the side end portion of the sublayer furthest from the first conductor layer 2 projects laterally from the side end portion of the sublayer closest to the first conductor layer 2. According to such a configuration, a path to the space 4 between the overhang portion 3a and the ceramic insulating substrate 1 can be widened, making it easy to fill the space 4 with the sealing element 10 during manufacturing. Furthermore, for example, in a case where the size of the semiconductor element 5 varies and a bonding area has some clearance, the size of the space 4 can be increased while ensuring spacing and insulation between the circuit structures.Furthermore, for example, if the material of one of the sublayers 3g to 3i is aluminum and the material of one of the other sublayers is copper, warping of the semiconductor device 100 can be prevented. <Neunte Ausführungsform>

[0050] Fig. Figure 10 is a cross-sectional view showing a configuration of the semiconductor device 100 according to a ninth embodiment, and Fig. Figure 11 is a top view showing the configuration of semiconductor device 100. The configurations of Fig. 10 and Fig. 11 are similar to the configuration in which a through hole 3j in the overhang part 3a is located along the thickness direction of the second conductor layer 3 in the configuration of Fig. 1 is provided. The diameter of the through-hole 3j is, for example, 80% or more of the thickness of the second conductor layer 3 and is formed by machining or punching.

[0051] According to the semiconductor device 100 of the ninth embodiment, as described above, the through-hole 3j is provided in the overhanging part 3a along the thickness direction of the second conductor layer 3. According to this configuration, lateral detachment of the sealing element 10 can be prevented by a retention effect achieved by filling the through-hole 3j with the sealing element 10. Furthermore, during manufacturing, the sealing element 10 easily flows through the through-hole 3j into the space 4 under the overhanging part 3a, thus simplifying the process of filling the space 4 with the sealing element 10. <Zehnte Ausführungsform>

[0052] Fig. Figure 12 is a cross-sectional view showing a configuration of the semiconductor device 100 according to a tenth embodiment. The configuration of Fig. 12 is similar to the configuration in which a corner part 3k of the overhang part 3a forms an acute angle in the cross-sectional view in the configuration of Fig. 1. In the example of Fig. 12. The corner part 3k, formed by a top surface and a side surface of the overhang part 3a, has an acute angle. The corner part 3k is formed, for example, by machining or stamping, and an angle of an interior angle of the corner part 3k is, for example, 45° or less.

[0053] In a case where detachment of the sealing element 10 cannot be prevented, a break is generally generated in the sealing element 10, and there is a possibility that the lifetime and reliability of the semiconductor device 100 will deteriorate, depending on where the break is generated.

[0054] In contrast, according to the semiconductor device 100 of the tenth embodiment, the corner part 3k of the overhang part 3a has an acute angle in the cross-sectional view. According to such a configuration, even if a fracture occurs, the acute corner part 3k can intentionally guide the fracture in a direction where the impact on the semiconductor device 100 is minimal. For example, the direction in which the impact on the semiconductor device 100 is minimal is away from the semiconductor element 5. As a result, the fracture propagation direction can be controlled, thus preventing a deterioration in the lifetime and reliability of the semiconductor device 100.

[0055] It should be noted that the embodiments and modifications can be freely combined, and the embodiments and modifications can be suitably modified or omitted.

[0056] The foregoing description is descriptive in all aspects and not limiting. It is understood that numerous modifications can be assumed that are not shown. Explanation of reference symbols 1 Ceramic insulation substrate 2 first conductor layer 2a Advanced 2b Step section 3 second conductor layer 3a Overhang section 3b Advanced 3c, 3e Overhang 3D step section 3f section 3g, 3h, 3i partial shift 3j through hole 3k corner piece 4 rooms 5 Semiconductor element 8 third conductor layer 10 sealing element 11 fourth layer of conductors 100 semiconductor devices

Claims

[1] Semiconductor device (100), comprising: an insulating substrate (1); a first conductive layer (2) which is bonded to the insulating substrate (1); a second conductor layer (3) which is bonded to the first conductor layer (2) and has an overhang part (3a) which is a side end part that projects in a lateral direction from a side end part of the first conductor layer (2); a sealing element (10) having a sub-area embedded in a space (4) between the overhanging part (3a) and the insulating substrate (1); and a semiconductor element (5) covered with the sealing element (10), wherein a recessed step section (2b) is provided in a cross-sectional view in an outer circumferential part of the first conductor layer (2). [2] Semiconductor device (100) according to claim 1, wherein a recess (3b) which is to be adapted to a part of the first conductor layer (2) is provided in the second conductor layer (3). [3] Semiconductor device (100), comprising: an insulating substrate (1); a first conductive layer (2) which is bonded to the insulating substrate (1); a second conductor layer (3) which is bonded to the first conductor layer (2) and has an overhang part (3a) which is a side end part that projects in a lateral direction from a side end part of the first conductor layer (2); a sealing element (10) having a sub-area embedded in a space (4) between the overhanging part (3a) and the insulating substrate (1); and a semiconductor element (5) covered with the sealing element (10), wherein a recessed step part (3d) is provided in a cross-sectional view in an outer circumferential part of the second conductor layer (3) [4] Semiconductor device (100) according to claim 3, wherein a recess (2a) which is to be adapted to a part of the second conductor layer (3) is provided in the first conductor layer (2). [5] Semiconductor device (100) according to any one of claims 1 to 4, further comprising: a third conductive layer (8) bonded beneath the insulating substrate (1); and a fourth conductor layer (11) which is bonded below the third conductor layer (8) and has a strength that differs from the strength of the third conductor layer (8). [6] Semiconductor device (100) according to any one of claims 1 to 5, wherein an overhang (3e) projecting towards the insulating substrate (1) is provided in the overhang part (3a). [7] Semiconductor device (100) according to one of claims 1 to 6, wherein a cutout (3f) in a top view is provided in an outer circumferential part of the overhang part (3a). [8] Semiconductor device (100) according to any one of claims 1 to 7, wherein the second conductor layer (3) has a plurality of sublayers (3g, 3h, 3i) stacked in a thickness direction of the second conductor layer (3), and a side end part of a sublayer away from the first conductor layer (2) from the plurality of sublayers in the lateral direction of a side end part of a sublayer near the first conductor layer (2) from the plurality of sublayers. [9] Semiconductor device (100) according to any one of claims 1 to 8, wherein a through hole (3j) is provided in the overhang part (3a) along a thickness direction of the second conductor layer (3). [10] Semiconductor device (100) according to any one of claims 1 to 9, wherein a corner part (3k) of the overhang part (3a) has an acute angle in a cross-sectional view. [11] Semiconductor device (100) according to any one of claims 1 to 10, wherein a material of the semiconductor element (5) is a wide bandgap semiconductor.

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