semiconductor device

Abstract

An object of the present disclosure is to provide a technique capable of more reliably preventing peeling of a sealing member. A semiconductor device includes an insulating substrate, a first conductor layer bonded to the insulating substrate, a second conductor layer, a sealing member, and a semiconductor element. The second conductive layer is bonded to the first conductor layer and has an overhang portion, which is a side end portion protruding in a lateral direction from a side end portion of the first conductor layer. The sealing member has a portion embedded in a space between the overhang portion and the insulating substrate. The semiconductor element is covered with the sealing member.

Description

Technical FieldThe present disclosure relates to a semiconductor device.Background ArtA semiconductor device in which a slight undercut shape is provided on a side surface of a circuit pattern, which is a single conductor layer, by etching or punching has been proposed (for example, Patent Document 1). According to such a configuration, it is possible to prevent peeling of a sealing member due to a temperature change or the like by an adhesive effect by the undercut shape.Prior Art DocumentPatent DocumentPatent Document 1: Japanese Patent No. 6210818SummaryProblem to be Solved by the InventionIn the configuration of the related art in which the undercut shape is provided on the side surface of the single conductor layer by etching or punching, the undercut shape depends on a thickness of the conductor layer. Thus, there is a problem that the undercut shape is not stable and an effect of preventing detachment of the sealing member cannot be obtained.Thus, the present disclosure has been developed in view of the above problem, and an object thereof is to provide a technique capable of more reliably preventing detachment of a sealing member.Means for Solving the ProblemA semiconductor device according to the present disclosure includes an insulating substrate, a first conductor layer bonded to the insulating substrate, a second conductor layer bonded to the first conductor layer and having an overhang part which is a side end part protruding in a lateral direction from a side end part of the first conductor layer, a sealing member having a partial region embedded in a space between the overhang part and the insulating substrate, and a semiconductor element covered with the sealing member.Effects of the InventionAccording to the present disclosure, a second conductor layer has an overhang part which is a side end part that protrudes in a lateral direction from a side end part of the first conductor layer, and a sealing member has a partial region embedded in a space between the overhang part and the insulating substrate. According to such a configuration, it is possible to more reliably prevent peeling of the sealing member.Objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.Brief Description of the Drawings[FIG. 1 ] is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment.[FIG. 2 ] is a cross-sectional view illustrating a configuration of a semiconductor device according to a second embodiment.[FIG. 3 ] is a cross-sectional view illustrating a configuration of a semiconductor device according to a third embodiment.[FIG. 4 ] is a cross-sectional view illustrating a configuration of a semiconductor device according to a fourth embodiment.[FIG. 5 ] is a cross-sectional view illustrating a configuration of a semiconductor device according to a fifth embodiment.[FIG. 6 ] is a cross-sectional view illustrating a configuration of a semiconductor device according to a sixth embodiment.[FIG. 7 ] is a cross-sectional view illustrating a configuration of a semiconductor device according to a seventh embodiment.[FIG. 8 ] is a plan view illustrating a configuration of the semiconductor device according to the seventh embodiment.[FIG. 9 ] is a cross-sectional view illustrating a configuration of a semiconductor device according to an eighth embodiment.[FIG. 10 ] is a cross-sectional view illustrating a configuration of a semiconductor device according to a ninth embodiment.[FIG. 11 ] is a plan view illustrating a configuration of the semiconductor device according to the ninth embodiment.[FIG. 12 ] is a cross-sectional view illustrating a configuration of a semiconductor device according to a tenth embodiment.DESCRIPTION OF THE EMBODIMENTSHereinafter, embodiments will be described with reference to the accompanying drawings. Features described in the following embodiments are examples, and all features are not necessarily essential. Further, in the following description, similar components are denoted by the same or similar reference numerals in a plurality of embodiments, and different components are mainly described. Further, in the following description, certain positions and directions such as "upper", "lower", "left", "right", "front", or "rear" need not necessarily coincide with actual positions and directions in practice.< Embodiment>FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device 100 according to the first embodiment. The semiconductor device 100 includes a ceramic insulating substrate 1, a first conductor layer 2, a second conductor layer 3, a semiconductor element 5, a solder 6, a wire 7, a third conductor layer 8, a base part 9, and a sealing member 10.The ceramic insulating substrate 1 is an insulating substrate made of, for example, aluminum nitride (AlN) or silicon nitride (SiN). The first conductor layer 2 is bonded to the ceramic insulating substrate 1, that is, a front surface of the ceramic insulating substrate 1, and the third conductor layer 8 is bonded below the ceramic insulating substrate 1, that is, a back surface of the ceramic insulating substrate 1.The first conductor layer 2 and the third conductor layer 8 have a plurality of circuit structures. After the first conductor layer 2 is bonded to the ceramic insulating substrate 1, a circuit pattern may be formed on the first conductor layer 2 by etching or the like, or after the circuit pattern is formed on the first conductor layer 2 by punching or the like, the first conductor layer 2 may be bonded to the ceramic insulating substrate 1. The circuit pattern of the third conductor layer 8 is formed in a similar manner to the circuit pattern of the first conductor layer 2.The second conductor layer 3 is bonded to the first conductor layer 2, that is, a front surface of the first conductor layer 2. The second conductor layer 3 has an overhang part 3 awhich is a side end part that protrudes in a lateral direction (a direction corresponding to a left-right direction in FIG. 1 ) with respect to a side end part of the first conductor layer 2. The overhang part 3 aprotrudes in a lateral direction from the side end part of the first conductor layer 2 by about 50 μm, for example. An undercut shape is formed by the side part of the first conductor layer 2 and the overhang part 3 aof the second conductor layer 3. Note that the second conductor layer 3 may be appropriately patterned to maintain a wiring ratio by the circuit structure of the first conductor layer 2.A material of the first conductor layer 2 and the second conductor layer 3 is, for example, aluminum or copper including an alloy. For example, in a case where the material of the first conductor layer 2 is aluminum and the material of the second conductor layer 3 is copper, improvement of heat dissipation of the semiconductor device 100 can be expected, or improvement of reliability of the semiconductor device 100 by improvement of strength can be expected. A material of the third conductor layer 8 may be the same as the material of the first conductor layer 2. in order to bond the first conductor layer 2 and the second conductor layer 3, for example, brazing, soldering, welding, liquid or solid diffusion bonding, or the like may be used.The semiconductor element 5 is electrically connected to the second conductor layer 3. In the example of FIG. 1, the semiconductor element 5 is bonded to a front surface of the second conductor layer 3 by the solder 6. The semiconductor element 5 is, for example, a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a reverse conducting IGBT (RC-IGBT), a Schottky barrier diode (SBD), or a PN junction diode (PND). A material of the semiconductor element 5 may be ordinary silicon (Si) or a wide band gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. In a case where the material of the semiconductor element 5 is a wide band gap semiconductor, stable operation at high temperature and high voltage and high switching speed can be achieved.The semiconductor element 5 is electrically connected to another circuit pattern (not illustrated) or the like by the wire 7. The material of the wire 7 is, for example, aluminum. The semiconductor element 5 may be electrically connected to another circuit structure or the like by a bus bar (not illustrated) instead of the wire 7. Although not illustrated, another circuit structure may be electrically connected to an external terminal by, for example, soldering or welding.The base part 9 is bonded under the third conductor layer 8. The base part 9 is made of, for example, aluminum, copper, or the like, and is a cooling member such as a pin blade or a base plate.The sealing member 10 covers the semiconductor element 5. in the example of FIG. 1, the sealing member 10 also covers the first conductor layer 2, the second conductor layer 3, and the like. A material of the sealing member 10 is, for example, a resin such as an epoxy or a gel, and the sealing member 10 is formed by transfer molding. Note that the sealing member 10 also fills a portion under the overhang portion 3 a. In other words, the sealing member 10 has a portion embedded in a space 4 between the overhang part 3 aand the ceramic insulation substrate 1.< Of First Embodiment>Generally, a temperature of the semiconductor device changes depending on an excitation operation and an external environment. When the sealing member 10 is peeled from the ceramic insulating substrate 1, the first conductor layer 2, the second conductor layer 3, the semiconductor element 5, and the like due to this temperature change, there is a possibility that reliability of the semiconductor device deteriorates.In contrast, according to the semiconductor device 100 of the first embodiment, the second conductor layer 3 includes the overhang part 3 awhich is a side end part protruding in the lateral direction from the side end part of the first conductor layer 2, and the sealing member 10 includes a partial region embedded in the space 4 between the overhang part 3 aand the ceramic insulation substrate 1. According to such a configuration, it is possible to prevent detachment of the sealing member 10 in a vertical direction by an adhesive effect by the overhang part 3 a.In addition, by configuring a size of the second conductor layer 3 in the lateral direction to be slightly larger than a size of the first conductor layer 2 in the lateral direction, a length of a protrusion of the overhang part 3 acan be stabilized. Thus, the undercut shape can be stabilized regardless of the thickness of the first conductor layer 2 or the like, so that the effect of preventing the sealing member from being peeled off can be obtained more reliably. In addition, in the configuration in which a plurality of groups of the first conductor layer 2 and the second conductor layer 3 are provided, it is possible to secure insulation between the groups only by securing a distance between the second conductor layers 3, so that it is easy to secure insulation.Note that although in the above description, the length of the protrusion of the overhang part 3 afrom the side end part of the first conductor layer 2 is described as about 50 μm, the length may be 50 μm or more if the size in the lateral direction of the semiconductor device 100 may be slightly large.< Embodiment>FIG. 2 is a cross-sectional view illustrating a configuration of the semiconductor device 100 according to a second embodiment. The configuration of FIG. 2 is similar to the configuration in which a fourth conductor layer 11 is added to the configuration of FIG. 1. The fourth conductor layer 11 is bonded under the third conductor layer 8 in a similar manner as the second conductor layer 3 is bonded to the first conductor layer 2. Further, the strength of the fourth conductor layer 11 is different from the strength of the third conductor layer 8.Generally, in the ceramic insulating substrate 1 to which circuit patterns such as the first conductor layer 2 and the third conductor layer 8 are bonded, warpage occurs in the ceramic insulating substrate 1 due to a difference in strength between the first conductor layer 2 and the third conductor layer 8. Specifically, in a case where the material of the first conductor layer 2 is pure aluminum and the material of the second conductor layer 3 is a copper alloy, for example, a relatively large bulge occurs in the ceramic insulation substrate 1.In contrast, according to the semiconductor device 100 of the second embodiment, the fourth conductor layer 11 having a different strength from the third conductor layer 8 is bonded under the third conductor layer 8. According to such a configuration, the strength of the third conductor layer 8 and the fourth conductor layer 11 can improve a balance of upper and lower strengths of the ceramic insulating substrate 1, so that warping of the ceramic insulating substrate 1 can be prevented. By this means, improvement of reliability and ease of assembling of the semiconductor device 100 can be expected.< Embodiment>FIG. 3 is a cross-sectional view illustrating a configuration of the semiconductor device 100 according to a third embodiment. Note that illustration of the sealing member 10 is omitted in FIG. 3 and subsequent drawings.The configuration of FIG. 3 is similar to the configuration in which a recess 3 bis provided in the second conductor layer 3 in the configuration of FIG. 1. The recess 3 bof the second conductor layer 3 is slightly larger than an upper portion, which is a part of the first conductor layer 2, and is fitted to the upper portion of the first conductor layer 2. In this state, the second conductor layer 3 is bonded to the first conductor layer 2. The recess 3 bis formed in the second conductor layer 3 by, for example, punching or machining.According to the semiconductor device 100 according to the third embodiment, as described above, the recess 3 b, which is fitted to a part of the first conductor layer 2, is provided in the second conductor layer 3. According to such a configuration, at the time of bonding the first conductor layer 2 and the second conductor layer 3, the first conductor layer 2 and the second conductor layer 3 are easily positioned, and misalignment therebetween can be reduced, so that a length of protrusion of the overhang part 3 acan be stabilized. In addition, in the configuration in which a plurality of groups of the first conductor layer 2 and the second conductor layer 3 are provided, a distance between the second conductor layers 3, that is, a distance between the respective groups can be stabilized, so that insulation can be stabilized. In addition, it is possible to prevent a decrease in strength of the first conductor layer 2.A shape of the recess 3 bin a plan view may be a polygon such as a rectangle or a hexagon, or may be a circle. In a case where the shape of the recess 3 bin a plan view is a polygon, it is possible to prevent rotation of one of the first conductor layer 2 and the second conductor layer 3 with respect to the other.< Embodiment>FIG. 4 is a cross-sectional view illustrating a configuration of the semiconductor device 100 according to a fourth embodiment. The configuration of FIG. 4 is similar to the configuration in which, in the configuration of FIG. 1, a protrusion 3 cis provided in the second conductor layer 3 and a recess 2 ais provided in the first conductor layer 2. The protrusion 3 cis provided in a center part of a lower portion of the second conductor layer 3. The recess 2 aof the first conductor layer 2 is slightly larger than the protrusion 3 c, which is a part of the second conductor layer 3, and is fitted to the protrusion 3 cof the second conductor layer 3. In this state, the second conductor layer 3 is bonded to the first conductor layer 2. The recess 2 ais formed in the first conductor layer 2 by, for example, punching or machining. The recess 2 amay be formed before or after the first conductor layer 2 is bonded to the ceramic insulation substrate 1. The protrusion 3 cis formed on the second conductor layer 3 by, for example, punching or machining.According to the semiconductor device 100 according to the fourth embodiment, as described above, the recess 2 athat is matched with the part of the second conductor layer 3 is provided in the first conductor layer 2. According to such a configuration, the same effects as those of the third embodiment can be obtained.Note that a shape of the recess 2 ain a plan view may be a polygon such as a rectangle or a hexagon, or may be a circle. In a case where the shape of the recess 2 ain a plan view is a polygon, it is possible to prevent rotation of one of the first conductor layer 2 and the second conductor layer 3 with respect to the other.< Embodiment>FIG. 5 is a cross-sectional view illustrating a configuration of the semiconductor device 100 according to a fifth embodiment. The configuration of FIG. 5 is similar to the configuration in which a recessed and relatively thin step part 2 bis provided in an outer peripheral part of the first conductor layer 2 in the cross-sectional view in the configuration of FIG. 1. In the example of FIG. 5, the step part 2 bis provided in the outer peripheral part of an upper surface of the first conductor layer 2 on the second conductor layer 3 side. The step part 2 bis formed in the first conductor layer 2 by, for example, punching or machining. The step part 2 bmay be formed before or after the first conductor layer 2 is bonded to the ceramic insulation substrate 1. A depth of the step part 2 bmay be, for example, one half of the thickness of the first conductor layer 2 or less by bisecting. A width of the step part 2 bis, for example, 50 μm or more and 5 mm or less.The thickness of the first conductor layer 2 may be, for example, about 0.1 mm to 2 mm, or may be less than 0.1 mm. However, when the thickness of the first conductor layer 2 is less than 0.1 mm, the space 4 between the overhang part 3 aand the ceramic insulating substrate 1 becomes small, so that the sealing member 10 is less likely to fill the space 4.In contrast, according to the semiconductor device 100 of the fifth embodiment, the recessed step part 2 bis provided in the outer peripheral part of the first conductor layer 2. According to such a configuration, a size of the space 4 between the overhang part 3 aand the ceramic insulating substrate 1 can be secured, so that it becomes easy to fill the space 4 with the sealing member 10. In addition, even in a case where the length of the protrusion of the overhang part 3 acan no longer be made to make the semiconductor device 100 smaller, a holding effect can be obtained by filling the space between the second conductor layer 3 and the step part 2 bwith the sealing member 10. It is therefore possible to achieve both reduction in size and improvement in reliability of the semiconductor device 100.< Embodiment>FIG. 6 is a cross-sectional view illustrating a configuration of the semiconductor device 100 according to a sixth embodiment. The configuration of FIG. 6 is similar to the configuration in which a recessed and relatively thin step part 3 dis provided in an outer peripheral part of the second conductor layer 3 in the cross-sectional view in the configuration of FIG. 1. In the example of FIG. 6, the step part 3 dis provided in the outer peripheral part of a lower surface of the second conductor layer 3 on the first conductor layer 2 side. The step part 3 dis formed in the second conductor layer 3 by, for example, punching or machining. The configuration, depth, and dimension of the step part 3 dare similar to the configuration, depth, and dimension of the step part 2 bin accordance with the fifth embodiment, for example.According to the semiconductor device 100 according to the sixth embodiment, as described above, the recessed step part 3 dis provided in the outer peripheral part of the surface of the second conductor layer 3 on the first conductor layer 2 side. According to such a configuration, effects similar to those of the fifth embodiment can be obtained.Note that the fifth embodiment and the sixth embodiment may be combined. In other words, the step part 2 bmay be provided in the first conductor layer 2 and the step part 3 dmay be provided in the second conductor layer 3.< Embodiment>FIG. 7 is a cross-sectional view illustrating a configuration of the semiconductor device 100 according to a seventh embodiment, and FIG. 8 is a plan view illustrating the configuration of the semiconductor device 100. Note that, in FIG. 8, a protrusion 3 edifferent from the protrusion 3 eis located behind the second conductor layer 3, and thus is represented by a broken line which is a hidden line.The configurations of FIGS. 7 and 8 are similar to the configuration in which the protrusion 3 eprotruding toward the ceramic insulating substrate 1 is provided in the overhang part 3 a, and a cutout part 3 fis provided in an outer peripheral part of the overhang part 3 ain a plan view in the configuration of FIG. 1.For example, the protrusion 3 eis formed by providing a cut at both ends of a part of each side part of the second conductor layer 3 by machining, laser cutting or punching, and bending the part downward by, for example, pressing. As shown in FIG. 8, the cut-out part 3 fis formed in a portion of the second conductor layer 3 used for the protrusion 3 e. Note that the formation of the protrusion 3 eand the cut-out part 3 fis not limited to this.A width of the cutout part 3 fin a direction along each side of the second conductor layer 3 is, for example, 1 mm to 10 mm, and a depth of the cutout part 3 fis, for example, 0.2 mm to 2 mm. An angle by which the protrusion 3 e other than the protrusion 3 eprotrudes from the second conductor layer 3 is, for example, 45° to 135°, and a height of the protrusion 3 eis less than the thickness of the first conductor layer 2.According to the semiconductor device 100 according to the seventh embodiment, as described above, the protrusion 3 eprotruding toward the ceramic insulating substrate 1 is provided in the overhang part 3 a. According to such a configuration, at the time of bonding the first conductor layer 2 and the second conductor layer 3, the first conductor layer 2 and the second conductor layer 3 are easily positioned, and misalignment therebetween can be reduced, so that a length of the protrusion of the overhang part 3 acan be stabilized.Further, in the seventh embodiment, the cut-out part 3 fis provided in the outer peripheral part of the overhang part 3 ain a plan view. According to such a configuration, peeling of the sealing member 10 in the lateral direction can be prevented by a holding effect obtained by filling the cutout part 3 fwith the sealing member 10.< Embodiment>FIG. 9 is a cross-sectional view illustrating a configuration of the semiconductor device 100 according to an eighth embodiment. The configuration of FIG. 9 is similar to the configuration in which the second conductor layer 3 includes a plurality of sub-layers 3 g, 3 h, and 3 istacked in a thickness direction (direction corresponding to the vertical direction in FIG. 9 ) of the second conductor layer 3 in the configuration of FIG. 1. A side end part of a sublayer remote from the first conductor layer 2 of the plurality of sublayers 3 gto 3 iprotrudes in the lateral direction from a side end part of a sublayer close to the first conductor layer 2 of the plurality of sublayers 3 gto 3 i. Materials or thicknesses of the plurality of sub-layers 3 gto 3 ineed not be the same and may be changed as necessary. The number of the plurality of sub-layers included in the second conductor layer 3 is not limited to three.According to the semiconductor device 100 according to the eighth embodiment, as described above, the first conductor layer 2 includes the plurality of sub-layers 3 gto 3 i, and the side end part of the sub-layer away from the first conductor layer 2 protrudes in the lateral direction from the side end part of the sub-layer near the first conductor layer 2. According to such a configuration, a path to the space 4 between the overhang part 3 aand the ceramic insulating substrate 1 can be widened, so that it is easy to fill the space 4 with the sealing member 10 at the time of manufacturing. In addition, for example, in a case where the size of the semiconductor element 5 varies and a bonding surface has a margin, a size of the space 4 can be increased while a distance and insulation between the circuit patterns can be secured. In addition, for example, when the material of one of the sub-layers 3 gto 3 iis aluminum and the material of one of the remaining sub-layers is copper, warpage of the semiconductor device 100 can be prevented.< Embodiment>FIG. 10 is a cross-sectional view illustrating a configuration of the semiconductor device 100 according to a ninth embodiment, and FIG. 11 is a plan view illustrating the configuration of the semiconductor device 100. The configurations of FIGS. 10 and 11 are similar to the configuration in which a through hole 3 jis provided in the overhang part 3 aalong the thickness direction of the second conductor layer 3 in the configuration of FIG. 1. A diameter of the through hole 3 jis, for example, 80% or more of the thickness of the second conductor layer 3 and is formed by machining or punching.According to the semiconductor device 100 according to the ninth embodiment, as described above, the through hole 3 jis provided in the overhang part 3 aalong the thickness direction of the second conductor layer 3. According to such a configuration, peeling of the sealing member 10 in the lateral direction can be prevented by a holding effect obtained by filling the through hole 3 jwith the sealing member 10. In addition, at the time of manufacturing, the sealing member 10 easily flows through the through hole 3 jinto the space 4 under the overhang part 3 a, so that it becomes easy to fill the space 4 with the sealing member 10.< Embodiment>FIG. 12 is a cross-sectional view illustrating a configuration of the semiconductor device 100 according to a tenth embodiment. The configuration of FIG. 12 is similar to the configuration in which a corner part 3 kof the overhang part 3 ain the cross-sectional view has an acute angle in the configuration of FIG. 1. In the example of FIG. 12, the corner part 3 kformed by an upper surface and a side surface of the overhang part 3 ahas an acute angle. The corner part 3 kis formed by machining or punching, for example, and an angle of an inner angle of the corner part 3 kis 45° or less, for example.In general, in a case where peeling of the sealing member 10 cannot be prevented, a crack is generated in the sealing member 10, and there is a possibility that the durability and reliability of the semiconductor device 100 deteriorate depending on a location where the crack is generated.In contrast, according to the semiconductor device 100 of the tenth embodiment, the corner part 3 kof the overhang part 3 ahas an acute angle in the cross-sectional view. According to such a configuration, even when a fracture is generated, the sharp corner part 3 kcan intentionally guide the fracture in a direction in which an influence on the semiconductor device 100 is small. The direction in which the influence on the semiconductor device 100 is small is, for example, a direction away from the semiconductor element 5. as a result, a fracture propagating direction can be controlled, so that it is possible to prevent deterioration of the durability and reliability of the semiconductor device 100.Note that the embodiments and modifications can be freely combined, and the embodiments and modifications can be appropriately modified or omitted.The foregoing description is illustrative in all aspects and is not restrictive. It is understood that numerous modifications may be adopted which are not shown.Explanation of Reference Numerals1 Ceramic insulation substrate 2 First conductor layer 2 a Vertiefung 2 bStep part 3 Second conductor layer 3 a Part 3 b Vertiefung 3 c, 3 e 3 dStep part 3 f Ausschnitt part 3 g, 3 h, 3 i Teil 3 jThrough hole 3 k Eck part 4 Space 5 Semiconductor element 8 Third conductor layer 10 Sealing member 11 Fourth conductor layer 100 Semiconductor deviceReferences included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedJP 6210818

[0003]

Claims

A semiconductor device, comprising: an insulating substrate; a first conductor layer bonded to the insulating substrate; a second conductor layer bonded to the first conductor layer and having an overhang part which is a side end part that protrudes in a lateral direction from a side end part of the first conductor layer; a sealing member having a partial region embedded in a space between the overhang part and the insulating substrate; and a semiconductor element covered with the sealing member.The semiconductor device according to claim 1, further comprising: a third conductor layer bonded under the insulating substrate; and a fourth conductor layer bonded under the third conductor layer and having a strength different from the strength of the third conductor layer.The semiconductor device according to claim 1 or 2, wherein a recess to be fitted to a part of the first conductor layer is provided in the second conductor layer.The semiconductor device according to any one of claims 1 to 3, wherein a recess to be fitted to a part of the second conductor layer is provided in the first conductor layer.The semiconductor device according to any one of claims 1 to 4, wherein a recessed step part is provided in an outer peripheral part of the first conductor layer in a cross-sectional view.The semiconductor device according to any one of claims 1 to 5, wherein a recessed step part is provided in an outer peripheral part of the second conductor layer in a cross-sectional view.The semiconductor device according to any one of claims 1 to 6, wherein a protrusion protruding toward the insulating substrate is provided in the protrusion part.The semiconductor device according to any one of claims 1 to 7, wherein a cutout is provided in an outer peripheral part of the overhang part in a plan view.The semiconductor device according to any one of claims 1 to 8, wherein the second conductor layer includes a plurality of sub-layers stacked in a thickness direction of the second conductor layer, and a side end part of a sub-layer remote from the first conductor layer out of the plurality of sub-layers protrudes in the lateral direction from a side end part of a sub-layer close to the first conductor layer out of the plurality of sub-layers.The semiconductor device according to any one of claims 1 to 9, wherein a through hole is provided in the overhang part along a thickness direction of the second conductor layer.The semiconductor device according to any one of claims 1 to 10, wherein a corner part of the overhang part has an acute angle in a cross-sectional view.The semiconductor device according to any one of claims 1 to 11, wherein a material of the semiconductor element is a wide band gap semiconductor.

Images