semiconductor device

Abstract

The goal is to provide a technology that can improve layout flexibility in a semiconductor device including semiconductor elements, detect the temperature of a semiconductor element while taking heat distribution in the semiconductor device into account, and maximize an effective area of the semiconductor elements. A semiconductor device includes: a base plate; semiconductor elements; and wiring elements arranged adjacent to the respective semiconductor elements on the base plate. A diode detecting a temperature of an adjacent one of the semiconductor elements is arranged in each of the wiring elements. The wire pad of each of the wiring elements is arranged to oppose the wire pad of the adjacent semiconductor element. The diode of each of the wiring elements is arranged closer to the adjacent semiconductor element.The wire pad of each of the semiconductor elements is connected by a wire to the wire pad of the wiring element adjacent to the semiconductor element.

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present disclosure relates to a semiconductor device. Description of the background technology

[0002] Semiconductor devices mounted on power converters such as inverters employ a structure in which a plurality of semiconductor elements are connected in parallel and the semiconductor elements are driven to pass a large current. For example, in a semiconductor device including a plurality of semiconductor elements, Patent Document 1 discloses a structure including a wiring element separate from the semiconductor elements as a means for maximizing the effective area of the semiconductor elements. DOCUMENT ACCORDING TO THE PRIOR ART PATENT DOCUMENT

[0003] Patent document 1: WO2020 / 110170 SUMMARY PROBLEM TO BE SOLVED BY THE INVENTION

[0004] In the technology described in Patent Document 1, arranging the wiring element in the center of a base plate and arranging the plurality of semiconductor elements to surround the wiring element unifies the wire length from each of the semiconductor elements to the wiring element. This imposes restrictions on the arrangement of the semiconductor elements and the wiring element, as well as on the routing of external electrodes. Thus, the problem of limited layout flexibility has arisen.

[0005] Furthermore, monitoring overheating and overcurrent conditions in the semiconductor device requires each of the semiconductor elements to have a temperature sensing element that senses the temperature of the semiconductor element. Thus, maximizing the effective area of all the semiconductor elements has been difficult. If one of the semiconductor elements has a temperature sensing element, only the temperature of the semiconductor element that includes the temperature sensing element can be sensed. Thus, a semiconductor element that senses the temperature cannot be selected taking into account the heat distribution in the semiconductor device.

[0006] The present disclosure aims to provide a technology that can improve layout flexibility in a semiconductor device including a plurality of semiconductor elements, detect the temperature of a semiconductor element in consideration of a heat distribution in the semiconductor device, and maximize an effective area of the semiconductor elements. MEANS TO SOLVE THE PROBLEM

[0007] A semiconductor device according to the present disclosure comprises: a base plate; a plurality of semiconductor elements mounted on the base plate, each of the semiconductor elements having a wire pad;and a plurality of wiring elements arranged adjacent to the respective semiconductor elements on the base plate, each of the wiring elements having a wire pad, wherein a temperature sensor that detects a temperature of an adjacent one of the semiconductor elements is arranged in each of the wiring elements, the wire pad of each of the wiring elements is arranged to face the wire pad of the adjacent one of the semiconductor elements, the temperature sensor of each of the wiring elements is arranged closer to the adjacent one of the semiconductor elements, and the wire pad of each of the semiconductor elements is connected via a wire to the wire pad of a corresponding one of the wiring elements that is adjacent to the semiconductor element. EFFECTS OF THE INVENTION

[0008] The plurality of wiring elements are arranged adjacent to the respective semiconductor elements, and the wire pad of each of the wiring elements is arranged to face the wire pad of the adjacent semiconductor element according to the present disclosure. Thus, the semiconductor element and the wiring element can be wired with a given wire length or less without interference. This improves the flexibility in the layout of the semiconductor device more than conventional ones, without requiring the semiconductor elements to be arranged to surround the wiring element.

[0009] Moreover, since a temperature sensor for each of the semiconductor elements is arranged in a corresponding one of the wiring elements, the semiconductor element that detects the temperature can be selected in consideration of a heat distribution in the semiconductor device.

[0010] The temperature sensor of each of the wiring elements is positioned closer to the adjacent semiconductor element. This allows the temperature sensor to exhibit better thermal bondability with the semiconductor element and to achieve better temperature detection accuracy. Since a temperature sensor is eliminated for the semiconductor elements, the effective area of the semiconductor elements can be maximized.

[0011] The object, features, aspects and advantages of this disclosure will become more apparent from the following detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [ Fig. 1] is a plan view of a semiconductor device according to Embodiment 1. [ Fig. 2] is a cross-sectional view of the semiconductor device according to Embodiment 1. [ Fig. 3] is a plan view of a wiring element included in the semiconductor device according to Embodiment 1. [ Fig. 4] is a cross-sectional view of a line AA in Fig. 3. [ Fig. 5] is a cross-sectional view of a line BB in Fig. 3. [ Fig. 6] is an equivalent circuit diagram of the semiconductor device according to Embodiment 1. [ Fig. 7] is a plan view of a semiconductor device according to Embodiment 2. [ Fig. 8] is a plan view of a wiring element included in the semiconductor device according to Embodiment 2. [ Fig. 9] is an equivalent circuit diagram of the semiconductor device according to Embodiment 2. [ Fig. 10] is a plan view of a semiconductor device according to Embodiment 3. [ Fig. 11] is a plan view of a wiring element included in the semiconductor device according to Embodiment 3. [ Fig. 12] is a cross-sectional view of a line CC in Fig. 11. [ Fig. 13] is an equivalent circuit diagram of a semiconductor device and a control board when the control board has a high-voltage diode. [ Fig. 14] is an equivalent circuit diagram of the semiconductor device according to Embodiment 3 and a control board when the semiconductor device has high-voltage diodes. [ Fig. 15] is a plan view of a wiring element included in a semiconductor device according to Embodiment 4. [ Fig. 16] is an equivalent circuit diagram of a wiring element included in the semiconductor device according to Embodiment 4. [ Fig. 17] is a plan view of a semiconductor device according to Embodiment 5. [ Fig. 18] is a cross-sectional view of the semiconductor device according to Embodiment 5. [ Fig. 19] is a plan view of a semiconductor device according to Embodiment 6. DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] [Overall Structure of a Semiconductor Device]

[0012] An embodiment 1 will be described below with reference to the drawings. Fig. 1 is a plan view of a semiconductor device 100 according to Embodiment 1. Fig. 2 is a cross-sectional view of the semiconductor device 100 according to Embodiment 1. Fig. 3 is a plan view of a wiring member 10 included in the semiconductor device 100 according to Embodiment 1. Fig. 4 is a cross-sectional view of a line AA in Fig. 3. Fig. 5 is a cross-sectional view of a line BB in Fig. 3. Fig. 6 is an equivalent circuit diagram of the semiconductor device 100 according to Embodiment 1. In Fig. 2, an extension direction of an external electrode 20 and a control terminal 22 was changed to facilitate observation of the connectivity relationship of components.

[0013] As in Fig. 1 and Fig. 2, the semiconductor device 100 includes a base plate 1, a plurality of (e.g., three) semiconductor elements 2, a plurality of (e.g., three) wiring elements 10, the external electrode 20, and four control terminals 22.

[0014] The base plate 1 is made of a metal such as Cu and Al as its main material. Furthermore, the base plate 1 is rectangular in plan view and functions as a drain terminal. The base plate 1 may be referred to as drain terminal 1 hereinafter.

[0015] The plurality of semiconductor elements 2 are mounted on the base plate 1 by bonding their rear surfaces via a conductive bonding material 5 such as solder, Ag paste material, or Cu paste material. Each of the semiconductor elements 2 is a metal-oxide-semiconductor field-effect transistor (MOSFET). The surface electrode of each of the semiconductor elements 2 is divided into two regions: a region in which a main electrode terminal 3 for passing a main current is disposed, and a region in which wire pads 4 for transmitting a drive voltage signal, a temperature signal, and an overcurrent signal of the semiconductor element 2 are disposed. The region in which the wire pads 4 are disposed is in Fig. 1 right (closer to the wiring element 10), and the area in which the main connection electrode 3 is arranged is in Fig. 1 left.

[0016] The main terminal electrode 3 is bonded to the external electrode 20 via the conductive bonding material 5, and each of the wire pads 4 is connected to a wire pad 12 of the adjacent wiring element 10. Each of the semiconductor elements 2 may be a semiconductor element such as an insulated gate bipolar transistor (IGBT) or a reverse conducting IGBT, except for a MOSFET.

[0017] A plurality of wiring elements 10 are arranged adjacent to the respective semiconductor elements 2 on the base plate 1. The plurality of wiring elements 10 are arranged on the base plate 1 by bonding their rear surfaces via the conductive bonding material 5. In each of the wiring elements 10, a resistor 14 that suppresses oscillation of an adjacent one of the plurality of semiconductor elements 2 and a diode 13 that functions as a temperature sensor that measures or detects the temperature of the adjacent semiconductor element 2 are arranged. The diode 13 of each of the wiring elements 10 is arranged closer to the adjacent semiconductor element 2.

[0018] The external electrode 20 is made of Cu and is arranged on the main terminal electrodes 3 of the plurality of semiconductor elements 2 to connect the plurality of semiconductor elements 2. The main terminal electrode 3 functions as a source terminal, and the external electrode 20 arranged on the main terminal electrodes 3 also functions as a source terminal. The external electrode 20 may be referred to as the source terminal 20.

[0019] As in Fig. 1 and Fig. 6, the plurality of semiconductor elements 2 are connected in parallel, and the plurality of wiring elements 10 are connected to the plurality of semiconductor elements 2 while being adjacent to the plurality of semiconductor elements 2.

[0020] The four control terminals 22 are terminals for inputting and outputting signals when controlling the semiconductor elements 2. The four control terminals 22 are a current detection terminal 22a, a Kelvin source terminal 22b, a gate terminal 22c, and a temperature detection anode terminal 22d. The control terminals 22 are connected to the semiconductor elements 2 via the wiring elements 10. In Embodiment 1, a current detection scheme is used as a short-circuit detection scheme for detecting a short-circuit state of the semiconductor elements 2. [Structure of a wiring element]

[0021] Next, a structure of each of the wiring elements 10 will be described. As shown in Fig. 3, Fig. 4 and Fig. As illustrated in Figure 5, each of the wiring elements 10 comprises a Si substrate 11 as the base material. A back electrode 15 made of Al, Ti, Ni, or Au is formed on the rear surface of the Si substrate 11. The rear surface of each of the wiring elements 10 is bonded to the base plate 1 via the conductive bonding material 5, similar to the semiconductor elements 2.

[0022] A thermal oxide film 16 is formed on the front surface of the Si substrate 11. Passive elements such as the resistor 14 made of polycrystalline silicon (poly-Si) 18 and the diode 13 made of polycrystalline silicon (p-type) 18a and polycrystalline silicon (n-type) 18b are formed on the thermal oxide film 16. An interlayer insulating film 17 is formed on the thermal oxide film 16 and the polycrystalline silicon 18, the polycrystalline silicon 18a, and the polycrystalline silicon 18b to insulate the resistor 14 from signal terminals of the diode 13 on the front surface side of the Si substrate 11. In addition, the wire pads 12, each functioning as a surface electrode made of Al, are formed on the interlayer insulating film 17.

[0023] A contact portion 17a for electrically connecting the resistor 14 and the diode 13 to the wire pad 12, which functions as a surface electrode, is arranged as part of the interlayer insulating film 17. As shown in Fig. 1, each of the wire pads 4 of the semiconductor elements 2 is connected to the control terminal 22 via the wiring element 10. The wiring element 10 has the function of forwarding wires. As shown in Fig. 1, Fig. 4 and Fig. As illustrated in FIG. 5, the wire pad 12 for connecting the wire pad 4 of the semiconductor element 2 to the control terminal 22 via a wire 21 is arranged on the front surface of the wiring element 10. The wire pad 12 of each of the wiring elements 10 is arranged to oppose the wire pad 4 of the adjacent semiconductor element 2, and the wire pads 12 are arranged in different portions. The wire pad 4 of each of the semiconductor elements 2 is connected to the wire pad 12 of the wiring element 10 adjacent to the semiconductor element 2 via the wire 21.

[0024] A sealant (not illustrated) made of, for example, an epoxy resin seals the interior of the semiconductor device 100 to provide electrical insulation. [Advantages]

[0025] Next, advantages of the semiconductor device 100 according to Embodiment 1 will be described in comparison with the technology described in Patent Document 1 (WO2020 / 110170).

[0026] According to the technology described in Patent Document 1, arranging the wiring element in the center of the base plate and arranging the semiconductor elements to surround the wiring element standardizes the wire length from each semiconductor element to the wiring element. This imposes restrictions on the arrangement of the semiconductor elements and the wiring element, as well as on the routing of the external electrodes. Thus, the problem of limited layout flexibility arose.

[0027] In contrast, the semiconductor device 100 according to Embodiment 1 includes the base plate 1, the plurality of semiconductor elements 2 each having the wire pads 4, and the plurality of wiring elements 10 arranged adjacent to the respective semiconductor elements 2 on the base plate 1 and each having the wire pads 12. In each of the wiring elements 10, a diode 13 is arranged as a temperature sensor that detects the temperature of an adjacent one of the plurality of semiconductor elements 2. The wire pad 12 of each of the wiring elements 10 is arranged to face the wire pad 2 of the adjacent semiconductor element 2. The diode 13 of each of the wiring elements 10, which functions as a temperature sensor, is arranged closer to the adjacent semiconductor element 2. The wire pad 4 of each of the semiconductor elements 2 is connected to the wire pad 12 of the wiring element 10 adjacent to the semiconductor element 2 via the wire 21.

[0028] Since the plurality of wiring elements 10 are arranged adjacent to the respective semiconductor elements 2, and the wire pad 12 of each of the wiring elements 10 is arranged to face the wire pad 4 of the adjacent semiconductor element 2, the semiconductor element 2 and the wiring element 10 can be wired with a given wire length or less without any interference. This improves the layout flexibility of the semiconductor device 100 more than conventional ones, without requiring the semiconductor elements 2 to be arranged to surround the wiring element 10.

[0029] Moreover, since the diode 13 is arranged in each of the wiring elements 10 as a temperature sensor for a corresponding one of the semiconductor elements 2, the semiconductor element 2 that detects the temperature can be selected in consideration of a heat distribution in the semiconductor device 100.

[0030] The diode 13, which functions as a temperature sensor for each of the wiring elements 10, is arranged closer to the adjacent semiconductor element 2. The diode 13 thus exhibits better thermal connectivity with the semiconductor element 2 and has better accuracy in detecting the temperature of the semiconductor element 2. Since a temperature sensor can be omitted for the semiconductor elements 2, the effective area of the semiconductor elements 2 can be maximized.

[0031] When the plurality of semiconductor elements 2 are driven in parallel, variations in the characteristics of the semiconductor elements 2 and stray inductance of the main terminals and the wires 21 in the semiconductor device 100 cause transient surge voltage and current deviation. This may lead to malfunction and breakage in the semiconductor elements 2. To suppress gate oscillations of the semiconductor elements 2 caused by a surge voltage at the time of shutdown, a compensating resistor designed to suppress the oscillations is typically arranged on a gate line of the semiconductor element 2.Further, since the resistor 14 that suppresses an oscillation operation of the adjacent semiconductor element 2 is arranged in each of the wiring elements 10 in Embodiment 1, a malfunction and breakage in the semiconductor device 100 can be suppressed at a low cost without having to arrange a balancing resistor in the semiconductor elements 2. [Embodiment 2]

[0032] Next, a semiconductor device 100A according to Embodiment 2 will be described. Fig. 7 is a plan view of the semiconductor device 100A according to Embodiment 2. Fig. 8 is a plan view of a wiring element 10A included in the semiconductor device 100A according to Embodiment 2. Fig. 9 is an equivalent circuit diagram of the semiconductor device 100A according to Embodiment 2. In Embodiment 2, the same reference numerals are assigned to the same constituent elements described in Embodiment 1, and their description is omitted.

[0033] As in Fig. 7, Fig. 8 and Fig. As illustrated in Figure 9, the short-circuit detection scheme for detecting a short-circuit state of the semiconductor elements 2 in Embodiment 2 has been changed from the current detection scheme to a desaturation voltage detection scheme. Thus, instead of the current detection terminal 22a (see Fig. 1) a desaturation voltage detection output terminal 22e for externally extracting a desaturation voltage (a drain voltage) from each of the semiconductor elements 2 is arranged as the control terminal 22. The desaturation voltage detection output terminal 22e is connected to the drain terminal 1. Changing the short-circuit detection scheme from the current detection scheme to the desaturation voltage detection scheme makes a current detection element 4a formed in each of the semiconductor elements 2 and a current detection path formed in each of the wiring elements 10 as shown in Fig. 1 are superfluous. The current detection path here is a partial area formed in the wiring element 10 in a path from the current detection element 4a via the wire 21 and the wire pad 12 in Fig. 1 to current detection terminal 22a.

[0034] As described above, the semiconductor device 100A according to Embodiment 2 further includes the control terminals 22 for inputting and outputting signals when controlling each of the semiconductor elements 2, and the control terminals 22 include the output terminal 22e for detecting a desaturation voltage to externally extract a drain voltage of each of the semiconductor elements 2.

[0035] Since the current detection element 4a of each of the semiconductor elements 2 and the current detection path of each of the wiring elements 10 can be omitted, the cost of the semiconductor device 100A can be reduced without impairing a function of protecting the semiconductor elements 2. [Embodiment 3]

[0036] Next, a semiconductor device according to Embodiment 3 will be described. Fig. 10 is a plan view of a semiconductor device 100B according to Embodiment 3. Fig. 11 is a plan view of a wiring element 10B included in the semiconductor device 100B according to Embodiment 3. Fig. 12 is a cross-sectional view of a line CC in Fig. 11. In Embodiment 3, the same reference numerals are assigned to the same constituent elements described in Embodiments 1 and 2, and their description is omitted.

[0037] As in Fig. 10, Fig. 11 and Fig. 12, a high-voltage diode 19 is arranged in each of the wiring elements 10B in Embodiment 3, which isolates the output terminal 22e for detecting a desaturation voltage to externally extract a drain voltage of the adjacent semiconductor element 2. In the Si substrate 11, an N - -Layer 29, an N + -Layer 30, a P - -Layer 31 and a P + -Layer 32 is formed.

[0038] Next, the advantages of disposing the high-voltage diode 19 in each of the wiring elements 10B will be described in comparison with disposing the high-voltage diode 19 in a control board for controlling a semiconductor device. Fig. 13 is an equivalent circuit diagram of the semiconductor device and the control board when the control board includes the high-voltage diode 19. Fig. 14 is an equivalent circuit diagram of the semiconductor device 100B according to Embodiment 3 and a control board when the semiconductor device 100B includes the high-voltage diodes 19.

[0039] As in Fig. 13, the control board includes the high-voltage diode 19 as well as a control IC 33, a resistor 34 and a capacitor 35, and the high-voltage line must be installed in a portion of the control board connected to the desaturation voltage detection output terminal 22e.

[0040] In contrast, if the high voltage diode 19 is as in Fig. 14 illustrates that the output terminal 22e for detecting a desaturation voltage in the semiconductor device 100B is electrically isolated in each of the wiring elements 10B. Since the control board is not required to have a high-voltage line, it is expected that the control board will be downsized and that layout flexibility will be improved.

[0041] Assuming that I CHG a charging current, R DESAT a value of the resistor 34, V F a forward voltage of the high-voltage diode 19 and V DS a desaturation voltage of the semiconductor element 2, which is a MOSFET, an overcurrent decision threshold V DESAT the control IC 33 expressed by V DESAT = I CHG × R DESAT + V F + V DS .

[0042] The desaturation voltage V DS of the MOSFET has positive temperature characteristics, where the absolute value increases with increasing temperature. Thus, the overcurrent decision threshold V DESAT The higher the ambient temperature, the higher the overcurrent threshold V. The control IC 33 monitors the overcurrent decision threshold V DESAT and goes into overcurrent protection mode when the overcurrent decision threshold V DSAT higher than or equal to a given level. However, the monitoring range of the control IC 33 has a limitation. An excessive increase in the overcurrent decision threshold V DESAT at high temperatures affects an operating temperature range of the overcurrent protection circuit.

[0043] In addition, the arrangement of the high-voltage diode 19 near the semiconductor element 2 in each of the wiring elements 10B as shown in Fig. 14 illustrates the temperature of the high voltage diodes 19 more strongly than that in Fig. 13. The forward voltage V F The high-voltage diode 19 has negative temperature characteristics, where the forward voltage decreases the more the temperature increases, and operates in a direction that cancels out the temperature characteristics of the MOSFET's desaturation voltage. This improves the accuracy of detecting the overcurrent decision threshold V DSAT . [Embodiment 4]

[0044] Next, a semiconductor device according to Embodiment 4 will be described. Fig. 15 is a plan view of a wiring element 10C included in the semiconductor device according to Embodiment 4. Fig. 16 is an equivalent circuit diagram of the wiring element 10C included in the semiconductor device according to Embodiment 4. In Embodiment 4, the same reference numerals are assigned to the same constituent elements described in Embodiments 1 to 3, and their descriptions are omitted.

[0045] In Embodiment 4, protective diodes 24 are added to Embodiment 1. Specifically, the protective diodes 24 that protect the adjacent semiconductor element 2 from electrostatic destruction are as shown in Fig. 15 and Fig. 16 illustrates the arrangement in each of the wiring elements 10C. Specifically, the protection diodes 24 are arranged between a gate terminal G and a Kelvin source terminal KS and between a current detection terminal CS and the Kelvin source terminal KS in each of the wiring elements 10C. The gate terminal G, the Kelvin source terminal KS, the current detection terminal CS and a temperature detection anode terminal A in Fig. 15 and Fig. 16 are connected via wires 21 to the gate terminal 22c, the Kelvin source terminal 22b, the current detection terminal 22a and the temperature detection anode terminal 22d, respectively. Fig. 1 connected.

[0046] Since this can suppress the electrostatic destruction of the semiconductor elements 2, the reliability and mountability of the semiconductor device are improved. [Embodiment 5]

[0047] Next, a semiconductor device 100D according to Embodiment 5 will be described. Fig. 17 is a plan view of the semiconductor device 100D according to Embodiment 5. Fig. 18 is a cross-sectional view of the semiconductor device 100D according to Embodiment 5. In Embodiment 5, the same reference numerals are assigned to the same constituent elements described in Embodiments 1 to 4, and their description is omitted.

[0048] As in Fig. 17 and Fig. As illustrated in FIG. 18, the plurality of wiring elements 10 are arranged in partial areas corresponding to the respective semiconductor elements 2 on the external electrode 20, so that in Embodiment 5, each of the wiring elements 10 is adjacent to and above a corresponding one of the semiconductor elements 2 via the external electrode 20. The plurality of wiring elements 10 are arranged on the external electrode 20 by bonding their rear surfaces via the conductive bonding material 5.

[0049] In each of the wiring elements 10, the resistor 14 that suppresses oscillation of a corresponding one of the semiconductor elements 2 adjacent to and below the wiring element 10 via the external electrode 20, and the diode 13 that functions as a temperature sensor that detects the temperature of the semiconductor element 2 adjacent to and below the wiring element 10 via the external electrode 20 are arranged. The wire pad 12 of each of the wiring elements 10 is arranged so as to be opposite to the wire pad 4 of the semiconductor element 2 adjacent to and below the wiring element 10 via the external electrode 20, and the wire pads 12 are arranged in other portions. The diode 13 of each of the wiring elements 10 is arranged closer to the semiconductor element 2 adjacent to and below the wiring element 10 via the external electrode 20.The wire pad 4 of each of the semiconductor elements 2 is connected via the wire 21 to the wire pad 12 of a corresponding one of the wiring elements 10, which is adjacent to and above the semiconductor element 2.

[0050] As described above, the semiconductor device 100D according to Embodiment 5 can improve layout flexibility, detect the temperature of the semiconductor element 2 while considering heat distribution in the semiconductor device 100D, and maximize the effective area of the semiconductor elements 2, similarly to Embodiment 1. Moreover, malfunction and breakage in the semiconductor device 100D can be suppressed at low cost without having to dispose a compensation resistor in the semiconductor elements 2.

[0051] Since the plurality of wiring elements 10 are arranged in the portions corresponding to the respective semiconductor elements 2 on the external electrode 20 such that each of the wiring elements 10 is adjacent to and above one of the semiconductor elements 2 via the external electrode 20, the area of the base plate 1 can be reduced more than that according to Embodiment 1. This can downsize the semiconductor device 100D. [Embodiment 6]

[0052] Next, the semiconductor device 100E according to Embodiment 6 will be described. Fig. 19 is a plan view of the semiconductor device 100E according to Embodiment 6. In Embodiment 6, the same reference numerals are assigned to the same constituent elements described in Embodiments 1 to 5, and their description is omitted.

[0053] In Embodiment 5, the plurality of wiring elements 10 are arranged on the upper surface of the external electrode 20 in regions in which the main terminal electrode 3 is arranged in the semiconductor element 2, respectively.

[0054] In contrast, in Embodiment 6, the main terminal electrode 3, which is the surface electrode of each of the semiconductor elements 2, is as shown in Fig. 19 illustrates the two regions 3a and 3b. Each of the wiring elements 10 is arranged on one region 3a, and the external electrode 20 is arranged on the other regions 3b.

[0055] Specifically, each of the wiring elements 10 is bonded to one region 3a in the semiconductor element 2 via a conductive bonding material (not shown) so that the wiring element 10 is adjacent to and above the semiconductor element 2. Furthermore, the external electrode 20 is bonded to the other regions 3b in the semiconductor elements 2 via a conductive bonding material (not shown).

[0056] In each of the wiring elements 10, the resistor 14 that suppresses oscillation of a corresponding one of the semiconductor elements 2 adjacent to and below the wiring element 10 and the diode 13 that functions as a temperature sensor that detects the temperature of the semiconductor element 2 adjacent to and below the wiring element 10 are arranged. The wire pad 12 of each of the wiring elements 10 is arranged to oppose the wire pad 4 of the semiconductor element 2 adjacent to and below the wiring element 10, and the wire pads 12 are arranged in other portions. The diode 13 of each of the wiring elements 10 is arranged closer to the semiconductor element 2 adjacent to and below the wiring element 10.The wire pad 4 of each of the semiconductor elements 2 is connected via the wire 21 to the wire pad 12 of the wiring element 10, which is adjacent to and above the semiconductor element 2.

[0057] As described above, the semiconductor device 100E according to Embodiment 6 can improve layout flexibility, detect the temperature of the semiconductor element 2 while considering heat distribution in the semiconductor device 100E, and maximize the effective area of the semiconductor elements 2, similarly to Embodiment 1. Moreover, malfunction and breakage in the semiconductor device 100E can be suppressed at low cost without having to dispose a compensation resistor in the semiconductor elements 2.

[0058] Furthermore, the main terminal electrode 3 of each of the semiconductor elements 2 is divided into two regions 3a and 3b, each of the wiring elements 10 is arranged on one region 3a, and the external electrode 20 is arranged on the other regions 3b. This improves the thermal connection between the wiring elements 10 and the semiconductor elements 2 and improves the accuracy in detecting the temperature of the semiconductor element 2 more than that in Embodiment 5. [Modifications of Embodiments 1 to 6]

[0059] Although Embodiments 1 to 6 describe that the number of semiconductor elements 2 and the number of wiring elements 10, 10A, 10B or 10C are both three, the numbers are not limited to these, but should be two or more and be equal numbers.

[0060] Although in Embodiments 1 to 6, as many wiring elements 10, 10A, 10B or 10C are arranged as semiconductor elements 2, the wiring elements 10, 10A, 10B or 10C need not be as many as the semiconductor elements 2, but two or more of the wiring elements 10, 10A, 10B or 10C may form the one Si substrate 11.

[0061] A capacitor including a silicon oxide film or an interlayer insulating film may be formed in each of the wiring elements 10, 10A, 10B, or 10C in Embodiments 1 to 6. Forming a low-pass filter for the resistor 14 in each of the wiring elements 10, 10A, 10B, or 10C improves the switching noise tolerance of the semiconductor element 2.

[0062] Furthermore, a resistance value of the resistor 14 arranged in each of the wiring elements 10, 10A, 10B, or 10C can be adjusted by laser trimming in Embodiments 1 to 6. This can suppress fluctuations in the balancing resistors connected between the semiconductor elements 2. When the balancing resistors are arranged at gates to prevent gate oscillations at the time of turning off parallel operations, a large difference in the value between the balancing resistors connected to the semiconductor elements 2 increases the risk of oscillation but reduces fluctuations in the resistance value. This can reduce the risk of oscillation and suppress malfunctions of the semiconductor elements 2.

[0063] The protection diodes 24 according to Embodiment 4 can be used in Embodiments 2 and 3. The desaturation voltage detection output terminal 22e according to Embodiment 2, the high-voltage diodes 19 according to Embodiment 3, and the protection diodes 24 according to Embodiment 4 can be used in Embodiments 5 and 6.

[0064] Although the present disclosure has been described in detail, the foregoing description is illustrative in all aspects and does not limit the present disclosure. Thus, numerous modifications may be conceived that have not been exemplified.

[0065] Embodiments may be freely combined and appropriately modified or omitted. EXPLANATION OF REFERENCE SYMBOLS

[0066] 1 Base plate, 2 Semiconductor element, 3 Main terminal electrode, 3a, 3b Area, 4 Wire pad, 10, 10A, 10B, 10C Wiring element, 12 Wire pad, 13 Diode, 14 Resistor, 19 High voltage diode, 20 External electrode, 21 Wire, 22 Control terminal, 22e Output terminal for detecting a desaturation voltage, 24 Protection diode QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] WO 2020 / 110170 [0003, 0025]

Claims

[1] A semiconductor device comprising: a base plate; a plurality of semiconductor elements mounted on the base plate, each of the semiconductor elements having a wire pad; and a plurality of wiring elements arranged adjacent to the respective semiconductor elements on the base plate, each of the wiring elements having a wire pad, wherein a temperature sensor which detects a temperature of an adjacent one of the semiconductor elements is arranged in each of the wiring elements, the wire pad of each of the wiring elements is arranged so that it faces the wire pad of the adjacent one of the semiconductor elements, the temperature sensor of each of the wiring elements is arranged closer to the adjacent one of the semiconductor elements and the wire pad of each of the semiconductor elements is connected via a wire to the wire pad of a corresponding one of the wiring elements adjacent to the semiconductor element. [2] The semiconductor device according to claim 1, wherein a resistor that suppresses an oscillation operation of the adjacent one of the semiconductor elements is further disposed in each of the wiring elements. [3] A semiconductor device according to claim 1 or 2, further comprising: at least one control terminal for supplying and outputting a signal when controlling each of the semiconductor elements, wherein the at least one control terminal has a terminal for externally extracting a drain voltage from each of the semiconductor elements. [4] A semiconductor device according to claim 3, wherein a high-voltage diode isolating the terminal for externally extracting the drain voltage of the adjacent one of the semiconductor elements is arranged in each of the wiring elements. [5] A semiconductor device according to any one of claims 1 to 4, wherein a protection diode that protects the adjacent one of the semiconductor elements from electrostatic destruction is arranged in each of the wiring elements. [6] A semiconductor device comprising: a base plate; a plurality of semiconductor elements mounted on the base plate, each of the semiconductor elements having a wire pad; an external electrode disposed on the semiconductor elements and connecting the semiconductor elements; and a plurality of wiring elements arranged in partial areas corresponding to the respective semiconductor elements on the external electrode such that each of the wiring elements is adjacent to and above a corresponding one of the semiconductor elements via the external electrode, each of the wiring elements having a wire pad, wherein in each of the wiring elements, a temperature sensor is arranged which detects a temperature of the corresponding one of the semiconductor elements which is adjacent to and below the wiring element via the external electrode, the wire pad of each of the wiring elements is arranged so as to be opposite to the wire pad of the corresponding one of the semiconductor elements, which is adjacent to and below the wiring element via the external electrode, the temperature sensor of each of the wiring elements is arranged closer to the corresponding one of the semiconductor elements which is adjacent to and below the wiring element via the external electrode, and the wire pad of each of the semiconductor elements is connected via a wire to the wire pad of the wiring element adjacent to and above the semiconductor element. [7] A semiconductor device according to claim 6, wherein further disposed in each of the wiring elements is a resistor which suppresses an oscillation operation of the corresponding one of the semiconductor elements adjacent to and below the wiring element via the external electrode. [8] A semiconductor device comprising: a base plate; a plurality of semiconductor elements mounted on the base plate, each of the semiconductor elements having a wire pad and a surface electrode divided into two regions; an external electrode disposed on the semiconductor elements and connecting the semiconductor elements; and a plurality of wiring elements each arranged in one of the two regions of the corresponding one of the semiconductor elements such that the wiring element is adjacent to and above the semiconductor element, each of the wiring elements having a wire pad, wherein the external electrode is connected to the other of the two regions of each of the semiconductor elements, in each of the wiring elements, a temperature sensor is arranged which detects a temperature of the corresponding one of the semiconductor elements which is adjacent to and below the wiring element, the wire pad of each of the wiring elements is arranged so as to be opposite to the wire pad of the corresponding one of the semiconductor elements which is adjacent to and below the wiring element, the temperature sensor of each of the wiring elements is arranged closer to the corresponding one of the semiconductor elements that is adjacent to and below the wiring element, and the wire pad of each of the semiconductor elements is connected via a wire to the wire pad of the wiring element adjacent to and above the semiconductor element. [9] A semiconductor device according to claim 8, wherein each of the wiring elements further includes a resistor which suppresses an oscillation operation of the corresponding one of the semiconductor elements adjacent to and below the wiring element. [10] A semiconductor device according to any one of claims 1 to 9, wherein a capacitor including a silicon oxide film or an interlayer insulating film is formed in each of the wiring elements. [11] A semiconductor device according to any one of claims 2, 7 and 9, wherein a resistance value of the resistor arranged in each of the wiring elements is adjustable by laser trimming.

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