Printed circuit board, light-emitting substrate, backlight module and display device

Abstract

A printed circuit board includes a substrate, a first conductive layer, a first insulating layer, and a second conductive layer. The first conductive layer is disposed on one side of the substrate. The first conductive layer includes a plurality of signal lines and a plurality of first conductive portions. The first insulating layer is provided with first through-holes extending through the first insulating layer. The second conductive layer includes a plurality of second conductive portions. A second conductive portion passes through a first through-hole to be in electrical contact with a first conductive portion. The second conductive portion includes contact pads, and a contact pad is a part of the second conductive portion exposed through the first through-hole in the first insulating layer.The first conductive layer and the second conductive layer each comprise at least one main conductive layer, and the main conductive layer is capable of forming a first intermetallic compound with solder. At least one of the first conductive layer and the second conductive layer further comprises a stop layer disposed between two adjacent main conductive layers and capable of forming a second intermetallic compound with the solder. The reaction rate between the stop layer and the solder is lower than the reaction rate between the main conductive layer and the solder.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technologies, and more particularly to a circuit board, a light-emitting substrate, a backlight module, and a display device. BACKGROUND

[0002] With the development of light-emitting diode technology, backlight sources using submillimeter (i.e., mini-LEDs) and even micrometer-scale (i.e., micro-LEDs) light-emitting diodes (LEDs) have become widely used. Therefore, not only can the image contrast of a product such as a liquid crystal display (LCD) that uses the backlight reach the level of an organic light-emitting diode (OLED), but the product can also retain the technical advantages of a liquid crystal display. This can improve the display effect of the image and provide users with a good visual experience. SUMMARY

[0003] One aspect is the provision of a printed circuit board. The printed circuit board comprises a substrate, a first conductive layer, a first insulating layer, and a second conductive layer.

[0004] The first conductive layer is arranged on one side of the substrate. The first conductive layer comprises a plurality of signal lines and a plurality of first conductive portions. The first insulating layer is arranged on a side of the first conductive layer facing away from the substrate. The first insulating layer is provided with first through-holes extending through the first insulating layer. The second conductive layer is arranged on a side of the first insulating layer facing away from the substrate. The second conductive layer comprises a plurality of second conductive portions. A second conductive portion passes through a first through-hole to be in electrical contact with a first conductive portion, the second conductive portion comprises contact pads, and a contact pad is a portion of the second conductive portion exposed through the first through-hole in the first insulating layer.

[0005] The first conductive layer and the second conductive layer each comprise at least one main conductive layer, and the main conductive layer is capable of forming a first intermetallic compound with the solder. At least one of the first conductive layer and the second conductive layer further comprises a stop layer, and the stop layer is disposed between two adjacent main conductive layers and is capable of forming a second intermetallic compound with the solder. The reaction rate between the stop layer and the solder is lower than the reaction rate between the main conductive layer and the solder.

[0006] In some embodiments, the material of the stop layer comprises one of nickel, a copper alloy having a copper atomic content of more than 40%, and a nickel alloy having a nickel atomic content of more than 40%.

[0007] In some embodiments, a thickness of the stop layer is in a range of 100 Å to 5000 Å inclusive.

[0008] In some embodiments, the circuit board further comprises an antioxidant layer. The antioxidant layer is disposed on a side of the second conductive layer facing away from the substrate, and the antioxidant layer is capable of forming a third intermetallic compound with the solder.

[0009] In some embodiments, the antioxidant layer encloses both conductive traces and the second conductive portion in the second conductive layer.

[0010] In some embodiments, the material of the antioxidant layer comprises nickel or a nickel alloy having a nickel atom content of more than 40%.

[0011] In some embodiments, a thickness of the antioxidant layer is in a range of 100 Å to 40,000 Å inclusive.

[0012] In some embodiments, the first conductive layer further comprises an adhesive layer, and the adhesive layer is disposed between a main conductive layer of the first conductive layer and the substrate, and the adhesive layer is incapable of reacting with the solder.

[0013] In some embodiments, the adhesive layer material comprises one of titanium, molybdenum, a molybdenum-niobium alloy, a molybdenum-titanium alloy, a molybdenum-tungsten alloy, a molybdenum-tantalum alloy, and a molybdenum-niobium-titanium alloy.

[0014] In some embodiments, the thickness of the adhesive layer is in a range of 100 Å to 2000 Å inclusive.

[0015] In some embodiments, an area of ​​an orthographic projection of the first conductive portion on the substrate is larger than an area of ​​an orthographic projection of the solder pad on the substrate, and the orthographic projection of the solder pad on the substrate is within the range of the orthographic projection of the first conductive portion on the substrate.

[0016] In some embodiments, the first conductive layer comprises a single main conductive layer and a single stop layer, the second conductive layer comprises another single main conductive layer and another single stop layer, and two stop layers are located between the single main conductive layer of the first conductive layer and the another single main conductive layer of the second conductive layer. Alternatively, the first conductive layer comprises a single main conductive layer, the second conductive layer comprises another single main conductive layer and a single stop layer, and the single stop layer is located between the single main conductive layer of the first conductive layer and the another single main conductive layer of the second conductive layer.Alternatively, the first conductive layer comprises a single main conductive layer and a single stop layer, the second conductive layer comprises another single main conductive layer, and the another single stop layer is located between the single main conductive layer of the first conductive layer and the another single main conductive layer of the second conductive layer.

[0017] In some embodiments, the plurality of second conductive portions are divided into a plurality of groups of component conductive portions and a plurality of groups of chip conductive portions. One group of component conductive portions is configured to be connected to a light-emitting device, and one group of chip conductive portions is configured to be connected to a microchip. The circuit board includes a plurality of drive units arranged in an array, and each drive unit includes a plurality of groups of component conductive portions. The circuit board further includes interconnect lines. The plurality of groups of component conductive portions in a drive unit are electrically connected by interconnect lines, and the interconnect lines are located in at least one of the first conductive layer and the second conductive layer.

[0018] In some embodiments, the plurality of second conductive portions are divided into a plurality of component conductive portion groups and a plurality of chip conductive portion groups. The signal lines include a first signal line and a second signal line. The first signal line is electrically connected to a component conductive portion group, and the second signal line is electrically connected to a chip conductive portion group. The first insulating layer is further provided with second through-holes extending through the first insulating layer. The circuit board further includes a plurality of component transmission lines and a plurality of chip transmission lines.

[0019] The plurality of component transmission lines are located in the second conductive layer. One end of a component transmission line is in electrical contact with the first signal line through a second through-hole, and another end thereof is in electrical contact with a second conductive portion of the group of component conductive portions. The plurality of chip transmission lines are located in the second conductive layer. One end of a chip transmission line is in electrical contact with the second signal line through another second through-hole, and another end thereof is in electrical contact with a second conductive portion of the group of chip conductive portions.

[0020] In some embodiments, the circuit board further comprises a first passivation layer and a second passivation layer. The first passivation layer is disposed between the first conductive layer and the first insulating layer and exposes at least a portion of the first conductive portion. The second passivation layer is disposed between the first insulating layer and the second conductive layer and exposes at least a portion of the first conductive portion. A plurality of solder pads electrically connected to a same electronic component are exposed through a same first via, such that the first insulating layer is not present in a region between the plurality of solder pads electrically connected to the same electronic component.

[0021] In some embodiments, the circuit board further comprises a third passivation layer and a second insulating layer. The third passivation layer is arranged on a side of the second conductive layer facing away from the substrate and exposes at least the solder pad. The second insulating layer is arranged on a side of the third passivation layer facing away from the substrate and exposes at least the contact area. The third passivation layer and / or the second insulating layer further expose a region between a plurality of solder pads electrically connected to the same electronic component, such that the third passivation layer and / or the second insulating layer are not present in the region between the plurality of solder pads electrically connected to the same electronic component.

[0022] Another aspect is the provision of a light-emitting substrate. The light-emitting substrate comprises a circuit board and an electronic component. The circuit board is the circuit board described in one of the above embodiments. The pins of an electronic component are electrically connected to the solder pads on the circuit board by the solder.

[0023] In some embodiments, the circuit board comprises an anti-oxidation layer, and the anti-oxidation layer comprises both the conductive traces and the second conductive portions in the second conductive layer. The light-emitting substrate further comprises a reflective layer. The reflective layer is disposed on a side of the anti-oxidation layer facing away from the substrate and is in contact with the anti-oxidation layer. The reflective layer is provided with a plurality of openings, and the pins of the electronic component are electrically connected to the solder and the solder pads through an opening.

[0024] Another aspect is the provision of a backlight module. The backlight module comprises the light-emitting substrate as described in any of the above embodiments and a plurality of optical films. The light-emitting substrate includes a light-exit surface and a non-light-exit surface that are opposite to each other. The plurality of optical films are arranged on the light-exit surface of the light-emitting substrate.

[0025] Another aspect is the provision of a display device. The display device comprises the backlight module described above and a display panel. The display panel is arranged on a side of the plurality of optical films in the backlight module facing away from the light-emitting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly describe technical solutions in the present disclosure, the accompanying drawings used in some embodiments of the present disclosure are briefly introduced below. Of course, the accompanying drawings described below are merely accompanying drawings of some embodiments of the present disclosure, and a person skilled in the art can create other drawings according to these drawings. Furthermore, the accompanying drawings described below may be regarded as schematic representations, but do not impose limitations on the actual size of a product, an actual process of a method, and an actual timing of a signal included in the embodiments of the present disclosure. Fig. 1 is a structural diagram of a display device according to some embodiments; Fig. 2 is a cross-sectional view of a display device according to some embodiments; Fig. 3 is a circuit diagram of a light-emitting substrate according to some embodiments; Fig. 4A is a plan view of a light-emitting substrate in Fig. 3; Fig. 4B is a structural diagram of a Fig. circuit board shown in Figure 4A; Fig. 4C is a structural diagram of another in Fig. circuit board shown in Figure 4A; Fig. 4D is a structural diagram of another in Fig. circuit board shown in Figure 4A; Fig. 5 is an enlarged partial view of an area A in Fig. 4B; Fig. 6A is a sectional view taken along a section line XX' in Fig. 4B; Fig. 6B is another sectional view taken along a section line YY' in Fig. 4B; Fig. 7A is a sectional view taken along a section line AA' in Fig. 5; Fig. 7B is another sectional view taken along a section line AA' in Fig. 5; Fig. 8A is a sectional view taken along a section line BB' in Fig. 5; Fig. 8B is another sectional view taken along a section line BB' in Fig. 5; Fig. 9A is another sectional view taken along a section line BB' in Fig. 5; Fig. 9B is another sectional view taken along a section line BB' in Fig. 5; Fig. 10A is another sectional view taken along a section line BB' in Fig. 5; Fig. 10B is another sectional view taken along a section line BB' in Fig. 5; and Fig. 11 is a cross-sectional view of a circuit board covered with a reflective layer according to some embodiments. DETAILED DESCRIPTION

[0027] Technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings. Of course, the described embodiments are only some, but not all, embodiments of the present disclosure. All other embodiments that a person skilled in the art obtains based on the embodiments of the present disclosure fall within the scope of the present disclosure.

[0028] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" and other forms thereof, such as the third-person singular "comprises" and the present participle form "comprising," are understood to be broad and inclusive, that is, "including, but not limited to." In describing the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are intended to indicate that certain features, structures, materials, or properties related to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s).Furthermore, the specific features, structures, materials, or properties described herein may be included in one or more embodiments or examples in any suitable manner.

[0029] Hereinafter, terms such as "first" and "second" are used for descriptive purposes only and are not intended to indicate the relative importance or imply the number of the specified technical features. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the term "a plurality of" or "the plurality of" means two or more, unless otherwise specified.

[0030] In the description of some embodiments, the terms "coupled" and "connected," and their derivatives, may be used. The term "connected" should be understood in a broad sense. The term "connected" may, for example, represent a fixed connection, a detachable connection, or a connection as an integral body; the term "connected" may be directly "connected" or indirectly "connected" through an intermediate medium. The term "coupled" may, for example, mean that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content presented herein.

[0031] The phrase "at least one of A, B, and C" has the same meaning as the phrase "at least one of A, B, or C," and both include the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0032] The phrase “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0033] As used herein, the term "if" may be understood as "when" or "in a case where" or "in response to the determination that" or "in response to the determination," depending on the context. Similarly, the phrase "if it is determined that" or "when [a specified condition or event] is detected" may be understood as "in a case where it is determined that" or "in response to the determination that" or "in a case where [the specified condition or event] is detected" or "in response to the detection of [the specified condition or event]," depending on the context.

[0034] The use of the term “applicable to” or “configured for” means an open and inclusive formulation that does not exclude devices that are applicable or configured to perform additional tasks or steps.

[0035] Furthermore, the use of the term “based on” is intended to be open and inclusive, since a process, step, calculation, or other action that is “based on” one or more of the specified conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those specified.

[0036] As used herein, the term "approximate," "substantially," or "approximately" includes a stated value and an average value within an acceptable range of deviation from a specified value. The acceptable range of deviation is determined by a person skilled in the art, taking into account the measurement in question and the errors inherent in measuring a particular quantity (i.e., the limitations of the measurement system).

[0037] The term "parallel," "perpendicular," or "equal" as used herein includes a specified condition and a condition similar to the specified condition. A region of the similar condition lies within an acceptable deviation range. The acceptable deviation range is determined by a person skilled in the art, taking into account the measurement in question and the errors associated with measuring a particular quantity (i.e., the limitations of the measurement system).For example, the term “parallel” includes absolute parallelism and near-parallelism, and an acceptable range of deviation from near-parallelism may be a deviation within 5°; the term “perpendicular” includes absolute perpendicularity and near-perpendicularity, and an acceptable range of deviation from near-perpendicularity may also be a deviation within 5°; and the term “equal” includes absolute equality and near-equality, and an acceptable range of deviation from near-equality may be a difference between two equals that is less than or equal to 5% of either equal.

[0038] When a layer or element is referred to as being on another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be one or more intermediate layers between the layer or element and the other layer or substrate.

[0039] Example embodiments are described herein with reference to sectional views and / or plan views as idealized example drawings. In the accompanying drawings, the layer thicknesses and the sizes of the regions are shown enlarged for clarity. Deviations in the shapes from the accompanying drawings, e.g., due to manufacturing technologies and / or tolerances, may be considered. Therefore, the example embodiments should not be understood as being limited to the shapes of the regions shown here, but as also including manufacturing-related shape deviations. For example, an etched region shown in a rectangular shape generally has a curved shape.Therefore, the regions illustrated in the accompanying drawings are schematic and their shapes are not intended to show the actual shapes of the regions in a device and are not intended to limit the scope of the exemplary embodiments.

[0040] A compound consisting of a metal and a metal, or of a metal and a metalloid (such as H, B, N, S, P, C, Si), is referred to herein as an intermetallic compound (IMC). The elements in the intermetallic compound are linked by one or more metallic bonds to obtain metallic properties. The intermetallic compound is the product of an interfacial reaction.

[0041] As in Fig. 1, some embodiments of the present disclosure provide a display device 1000. The display device 1000 may be any device that displays moving images (e.g., a video) or still images (e.g., a still image), independent of text or images.

[0042] The display device 1000 may be, for example, any product or component having a display function, such as a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigation device, a wearable device, an augmented reality (AR) device, and a virtual reality (VR) device.

[0043] In some embodiments, the display device 1000 may be a liquid crystal display (LCD).

[0044] As in Fig. 2, the display device 1000 may include a display panel 100, a backlight module 200, and a glass cover 300.

[0045] The display panel 100 includes a light-emitting surface and a non-light-emitting surface. The light-emitting surface refers to a surface (an upper surface of the display panel 100 in Fig. 2) the display panel 100 for displaying an image, and the non-light-emitting surface refers to another surface (a lower surface of the display panel 100 in Fig. 2) opposite the light exit surface.

[0046] The backlight module 200 is arranged on the light-facing surface of the display panel 100, and the backlight module 200 serves to provide a light source for the display panel 100.

[0047] The glass cover 300 is arranged on the light-emitting surface of the display panel 100 and serves to protect the display panel 100. The material used for the glass cover 300 can be selected from, for example, rigid materials such as glass, quartz, plastic, or flexible materials such as polymer resin.

[0048] In some examples, with continued reference to Fig. 2, the backlight module 200 may include a light-emitting substrate 210 and a plurality of optical films 220.

[0049] The light-emitting substrate 210 has a light-emitting surface and a non-light-emitting surface that are opposite to each other. The light-emitting surface refers to a surface (a top surface of the light-emitting substrate 210 in Fig. 2) of the light-emitting substrate 210 for providing a light source, and the non-light-emitting surface refers to another surface (a lower surface of the light-emitting substrate 210 in Fig. 2) opposite the light-emitting surface.

[0050] The plurality of optical films 220 are arranged on the light-emitting surface of the light-emitting substrate 210.

[0051] The light-emitting substrate 210 can directly emit white light, and the white light is incident on the display panel 100 after undergoing light uniformization treatment by the plurality of optical films 220. Alternatively, the light-emitting substrate 210 can emit light of a different color (e.g., blue light), and then the light is incident on the display panel 100 after undergoing color conversion and light uniformization treatment by the plurality of optical films 220.

[0052] As in Fig. 2, the plurality of optical films 220 includes, for example, a diffusion plate 221, a quantum dot film 222, a diffusion film 223, and a composite film 224, which are arranged sequentially in a direction away from the light-emitting substrate 210.

[0053] The diffusion plate 221 can diffuse the light emitted from the light-emitting substrate 210 and support the quantum dot film 222, the diffusion film 223, and the composite film 224. The quantum dot film 222 can convert the light into white light when the light of a specific color emitted from the light-emitting substrate 210 is excited, thereby improving the utilization rate of the light energy of the light-emitting substrate 210. The diffusion film 223 can evenly distribute the light passing through the diffusion film 223. The composite film 224 can improve the luminous efficiency of the backlight module 200 and the display brightness of the display device 1000.

[0054] It should be noted that the composite film 224 may include a brightness enhancement film (BEF) and a reflective polarization enhancement film (Dual Brightness Enhancement Film (DBEF) and utilizes the principles of total internal reflection, refraction, and polarization to increase the light flux within a certain angular range, thereby improving the brightness of the display device 1000.

[0055] For example, the light-emitting substrate 210 emits blue light in a direction away from the light-emitting substrate 210. The quantum dot sheet 222 may include a red quantum dot material, a green quantum dot material, and a transparent material. When the blue light emitted by the light-emitting substrate 210 passes through the red quantum dot material, the blue light is converted into red light. When the blue light passes through the green quantum dot material, the blue light is converted into green light. The blue light can directly pass through the transparent material. Then, the blue light, red light, and green light are mixed and superimposed in a specific ratio to appear as white light.The diffusion plate 221 and the diffusion film 223 can uniform the white light to improve the light shadow generated by the light-emitting substrate 210 and thereby improve the display image quality of the display device 1000.

[0056] In some embodiments (see Fig. 2) The light-emitting substrate 210 comprises a circuit board 10, electronic components 20 and a reflective layer 30.

[0057] As in Fig. As shown in Figure 2, the circuit board 10 includes a functional area 10A and a peripheral area 10B. The functional area 10A is configured to provide the electronic components 20, and the peripheral area 10B is configured to be connectable to another circuit board.

[0058] As in Fig. As shown in Figure 2, the reflective layer 30 is arranged on the circuit board 10. Furthermore, a boundary of the reflective layer 30 may, for example, coincide with a boundary of the functional area 10A of the circuit board 10. That is, the edge area 10B of the circuit board 10 may not be provided with the reflective layer 30.

[0059] As in Fig. As shown in Figure 2, the reflective layer 30 is provided with a plurality of openings 301. The pins of the electronic component 20 can be electrically connected to solder joints and solder pads in the circuit board 10 through the opening 301, so that the electronic component 20 is mounted on the circuit board 10.

[0060] The reflectance of the reflective layer 30 is greater than or equal to 90%. The material of the reflective layer 30 may comprise, for example, white ink and / or silicone-based white glue. The material of the reflective layer 30 may comprise, for example, resin (e.g., epoxy resin or polytetrafluoroethylene resin), titanium dioxide (TiO2), and an organic solvent (e.g., dipropylene glycol methyl ether).

[0061] As in Fig. 2, the electronic components 20 may include light-emitting devices 21 and / or microchips 22.

[0062] As in Fig. As shown in Figure 2, the light-emitting device 21 may include a micro-LED and a mini-LED. The size (e.g., the length) of the micro-LED is less than 50 micrometers, e.g., in a range from 10 micrometers to 50 micrometers. The size (e.g., the length) of the mini-LED is in a range from 50 micrometers to 150 micrometers, e.g., in a range from 80 micrometers to 120 micrometers.

[0063] As in Fig. As shown in Figure 2, the microchip 22 may include a sensor chip and a control chip. The sensor chip may be, for example, a light-sensitive sensor chip or a thermosensitive sensor chip. The control chip serves to provide a control signal for the light-emitting device 21. The embodiments of the present disclosure are explained below using an example of the microchip 22 with the control chip.

[0064] In the current art, repairing the light-emitting substrate involves removing potentially faulty electronic components. Removing the electronic components from the circuit board is likely to damage the surface structures of the solder pads, making it impossible to re-solder the solder pads to the electronic components. As a result, the product may have poor maintainability and low yield.

[0065] As in Fig. 6A, the circuit board 10 provided by some embodiments of the present disclosure includes a substrate 11, a first conductive layer 12, a first insulating layer 172, and a second conductive layer 13.

[0066] In some examples, the ratio between the thickness of the first conductive layer 12 and the thickness of the second conductive layer 13 in a direction perpendicular to a plane in which the substrate 11 is located is in a range of 1:5 to 5:1. For example, the thickness of the first conductive layer 12 is equal to the thickness of the second conductive layer 13; alternatively, the thickness of the first conductive layer 12 is 0.2 times, 0.5 times, 0.7 times, 1.1 times, 1.2 times, 1.5 times, 2 times, 2.5 times, 3 times, 4.5 times, or 5 times the thickness of the second conductive layer 13, which is not limited within the scope of the present disclosure.

[0067] In some examples, substrate 11 may be a flexible substrate. The flexible substrate may be, for example, a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (also referred to as polyethylene naphthalate-2-formate, PEN), or a polyimide (PI) substrate.

[0068] In some examples, the substrate 11 may be a rigid substrate. The rigid substrate may be, for example, a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0069] As in Fig. 6A, the first conductive layer 12 is disposed on one side of the substrate 11, the first insulating layer 172 is disposed on a side of the first conductive layer 12 facing away from the substrate 11, and the second conductive layer 13 is disposed on a side of the first insulating layer 172 facing away from the substrate 11.

[0070] As in Fig. 5 and Fig. 6A, the first insulating layer 172 is provided with first through holes H1 extending through the first insulating layer 172.

[0071] It should be noted that the material of the first insulating layer 172 comprises a resin, e.g., an epoxy resin. The thickness of the first insulating layer 172 ranges from 2 µm to 10 µm. For example, the thickness of the first insulating layer 172 is 2 µm, 3 µm, 4 µm, 5 µm, 7 µm, 8 µm, and 10 µm.

[0072] With reference to the Fig. 3, Fig. 4A and Fig. 5, the first conductive layer 12 includes a plurality of signal lines 120 and a plurality of first conductive portions 151, and the second conductive layer 13 includes a plurality of second conductive portions 152. The second conductive portion 152 is in electrical contact with the first conductive portion 151 through the first through-hole H1. The second conductive portion 152 includes a contact pad P, and the contact pad P is a part of the second conductive portion 152 exposed through the first through-hole H1 in the first insulating layer 172. The above-mentioned electronic component 20 is soldered to the solder pad P with solder to fix it to the circuit board 10. The solder may include, for example, tin.

[0073] It should be noted that an area of ​​an orthographic projection of the first conductive portion 151 on the substrate 11 may be the same as an area of ​​an orthographic projection of the solder pad P on the substrate 11, or may be different from the area of ​​the orthographic projection of the solder pad P on the substrate 11. For example, the area of ​​the orthographic projection of the first conductive portion 151 on the substrate 11 is larger than the area of ​​the orthographic projection of the solder pad P on the substrate 11, and the orthographic projection of the solder pad P on the substrate 11 is located within the orthographic projection of the first conductive portion 151 on the substrate 11, which is advantageous for flattening an upper surface of the solder pad P.

[0074] It should be understood that the first conductive layer 12 may be formed by a variety of deposition and photolithography processes, and the second conductive layer 13 may be formed by a variety of deposition and photolithography processes. That is, the first conductive layer 12 and the second conductive layer 13 may each be a laminated structure formed by stacking a plurality of layers of conductive materials.

[0075] For example, the first conductive layer 12 and the second conductive layer 13 each comprise at least one main conductive layer 141, and the main conductive layer 141 and the solder may form a first intermetallic compound (see Fig. 6A). For ease of distinction, a conductive main layer 141 in the first conductive layer 12 is hereinafter referred to as a first conductive main layer 121, and a conductive main layer 141 in the second conductive layer 13 is referred to as a second conductive main layer 131.

[0076] As in Fig. As shown in Figure 6A, the thickness of the first main conductive layer 121 ranges from 0.6 µm to 4 µm. For example, the thickness of the first main conductive layer 121 is 0.6 µm, 0.9 µm, 1.8 µm, 2.7 µm, 3.6 µm, and 4 µm.

[0077] As in Fig. As shown in Figure 6A, the thickness of the second main conductive layer 131 may range from 3000 Å to 1.8 µm. For example, the thickness of the second main conductive layer 131 is 3000 Å, 6000 Å, 9000 Å, 1.2 µm, 1.5 µm, and 1.8 µm.

[0078] It should be noted that the material of the conductive main layer 141 is metal. The material of the conductive main layer 141 is, for example, copper or silver.

[0079] Furthermore, at least one of the first conductive layer 12 and the second conductive layer 13 comprises a stop layer 142. The stop layer 142 is arranged between two adjacent conductive main layers 141. In this case, in a region where any solder pad P is located, there are at least two conductive main layers 141 and one stop layer 142 between two adjacent conductive main layers 141. For ease of differentiation, a stop layer 142 in the first conductive layer 12 is referred to below as a first stop layer 122, and a stop layer 142 in the second conductive layer 13 is referred to as a second stop layer 132.

[0080] As in Fig. 5 and Fig. For example, as shown in Figure 9A, the first conductive layer 12 includes a first main conductive layer 121 and a first stop layer 122, and the second conductive layer 13 includes a second main conductive layer 131. The first stop layer 122 is located between the first main conductive layer 121 and the second main conductive layer 131.

[0081] In this case, the first conductive portion 151 includes the first conductive main layer 121 and the first stop layer 122, and the second conductive portion 152 includes the second conductive main layer 131. That is, in the area where the solder pad P is located, there are two conductive main layers 141 and a stop layer 142 between the two conductive main layers 141.

[0082] Another example, as in Fig. 5 and Fig. As shown in Figure 9B, the first conductive layer 12 includes a first conductive main layer 121, and the second conductive layer 13 includes a second conductive main layer 131 and a second stop layer 132. The second stop layer 132 is located between the first conductive main layer 121 and the second conductive main layer 131.

[0083] In this case, the first conductive portion 151 comprises the first conductive main layer 121, and the second conductive portion 152 comprises the second conductive main layer 131 and the second stop layer 132. That is, in the area where the solder pad P is located, there are two conductive main layers 141 and a stop layer 142 between the two conductive main layers 141.

[0084] Another example: As in the Fig. 5 and Fig. As shown in Figure 8A, the first conductive layer 12 includes a first main conductive layer 121 and a first stop layer 122, and the second conductive layer 13 includes a second main conductive layer 131 and a second stop layer 132. Both the first stop layer 122 and the second stop layer 132 are located between the first main conductive layer 121 and the second main conductive layer 131.

[0085] In this case, the first conductive portion 151 includes the first conductive main layer 121 and the first stop layer 122, and the second conductive portion 152 includes the second conductive main layer 131 and the second stop layer 132. That is, in the area where the solder pad P is located, there are two conductive main layers 141 and two stop layers 142 between the two conductive main layers 141.

[0086] Note that, in addition to the above-mentioned embodiments, the first conductive layer 12 and the second conductive layer 13 may also include a plurality of main conductive layers 141 and a plurality of stopper layers 142, which can be specifically configured depending on the actual situation. The embodiments of the present disclosure are not listed individually here.

[0087] The stop layer 142 and the solder may form a second intermetallic compound, and the reaction rate between the stop layer 142 and the solder is lower than the reaction rate between the main conductive layer 141 and the solder.

[0088] In this case, the material of the stop layer 142 consists of a simple metal substance or an alloy. The simple metal substance may comprise nickel. The alloy may comprise a copper alloy with a copper atomic content of more than 40% or a nickel alloy with a nickel atomic content of more than 40%. The copper alloy may comprise, for example, a binary or ternary copper alloy, such as a nickel-copper alloy, a nickel-copper-aluminum alloy, a copper-magnesium-aluminum alloy, or a copper-titanium alloy. The nickel alloy may comprise, for example, a binary or ternary nickel alloy, such as a nickel-aluminum alloy, a nickel-molybdenum alloy, a nickel-tungsten alloy, a nickel-titanium alloy, or a nickel-copper alloy.

[0089] Furthermore, in a case where the material of the stop layer 142 comprises a nickel alloy having a nickel atom content of more than 40%, the content of nickel atoms in the stop layer 142 may gradually decrease from the stop layer 142 toward the substrate 11, so that the reaction rate between a part of the stop layer 142 near the substrate 11 and the solder is lower than the reaction rate between a part of the stop layer 142 away from the substrate 11 and the solder.

[0090] It should be noted that the thickness of the stop layer 142 can range from 100 Å to 5000 Å. For example, the thickness of the stop layer 142 can be 100 Å, 500 Å, 1000 Å, 2000 Å, 3000 Å, 4000 Å, or 5000 Å.

[0091] In this case, when soldering the electronic component 20 and the solder pads P with solder, the solder is first heated to melt, and then the metal atoms therein form first intermetallic compounds with the metal atoms in the main conductive layer 141 while diffusing, and form fourth intermetallic compounds with the metal atoms in the pins of the electronic component 20, thereby realizing soldering. By adjusting the thickness of the main conductive layer 141, the pins of the electronic component 20 and the solder pads P can be reliably connected.

[0092] It goes without saying that as the solder continues to diffuse, the metal atoms in the solder may form further intermetallic compounds with metal atoms in the stop layer 142. Since the reaction rate between the stop layer 142 and the solder is relatively slow, the stop layer 142 can slow the diffusion rate of the solder, and thus the diffusion position of the solder at the stop layer 142 can be stopped relatively easily.

[0093] In this way, during maintenance, when the electronic component 20 is removed, the pins of the electronic component 20 will remove at most the main conductive layer 141 and the stop layer 142 that react with it, and there will be at least one main conductive layer 141 that has not reacted with the solder on one side of the stop layer 142 of the reaction near the substrate 11. That is, after the electronic component 20 is removed, a region where the solder pad P of the electronic component 20 has been removed can be re-soldered, thereby improving the maintenance rate of the light-emitting substrate 210.

[0094] It should be noted that in the first conductive portion 151 and the second conductive portion 152, each main conductive layer 141 can be soldered once. That is, the sum of the number of main conductive layer(s) 141 included in the first conductive portion 151 and the number of main conductive layer(s) 141 included in the second conductive portion 152 is equal to the total number of electronic components 20 that can be repeatedly soldered. That is, the number of main conductive layers 141 included in the above-mentioned first conductive layer 12 and second conductive layer 13 can be determined, for example, according to the number of required repairs.

[0095] In some embodiments, as in Fig. 5 and Fig. 7A, the circuit board 10 further includes an antioxidant layer 143. The antioxidant layer 143 is disposed on a side of the second conductive layer 13 facing away from the substrate 11 to prevent oxidation of the exposed upper surfaces of the two conductive traces and the second conductive portions 152 in the second conductive layer 13. Furthermore, the antioxidant layer 143 and the solder may form a third intermetallic compound, allowing the solder to diffuse into the main conductive layer 141 for soldering.

[0096] In some examples, such as the Fig. 6A, Fig. 7A and Fig. As shown in Figure 8A, the antioxidant layer 143 is located on the surfaces of both the conductive lines and the second conductive portions 152 in the second conductive layer 13, away from the substrate 11. That is, the antioxidant layer 143 covers the conductive lines in the second conductive layer 13 and the exposed upper surface of the second conductive portion 152. In this way, the antioxidant layer 143 and the second conductive layer 13 can be formed in a single etching process using the same mask, thereby simplifying the process flow.

[0097] It is noted that for the conductive paths in the second conductive layer 13, reference can be made to the following description and that the embodiments of the present disclosure do not include details here.

[0098] In some other examples, such as Fig. 6B, Fig. 7B and Fig. 8B, the anti-oxidation layer 143 covers the conductive traces and the second conductive portions 152 in the second conductive layer 13. That is, the anti-oxidation layer 143 covers the exposed top and side surfaces of the conductive traces and solder pads P in the second conductive layer 13. In this case, the anti-oxidation layer 143 covers the exposed top and side surfaces of the conductive traces and solder pads P and completely encloses the exposed surfaces of the conductive traces and solder pads P.

[0099] For this reason, it is not necessary to provide other insulating anti-oxidation layers, such as a passivation layer and resin, on the printed circuit board 10. That is, with reference to the Fig. 2, Fig. 5 and Fig. 6B that in a case where the printed circuit board 10 includes the anti-oxidation layer 143 and the anti-oxidation layer 143 includes the conductive traces and the second conductive portions 152 located in the second conductive layer 13, as in Fig. 11, the above reflective layer 30 may be arranged, for example, on a side of the antioxidant layer 143 which is remote from the substrate 11 and in contact with the antioxidant layer 143.

[0100] With such a provision, the process flow can be simplified and the cost of mass production can be reduced. Furthermore, an adverse effect on the reaction between the solder and the solder pad P due to a reduction in the surface roughness of the solder pad P caused by the etching process during the formation of the passivation layer and resin can be avoided, and the inability to achieve effective soldering due to warpage of the solder pad P caused by the stress of the passivation layer and resin can be avoided.

[0101] The material of the antioxidant layer 143 may be the same as or different from that of the stop layer 142. If the material of the antioxidant layer 143 is the same as that of the stop layer 142, the second intermetallic compound is the same as the third intermetallic compound.

[0102] The material of the anti-oxidation layer 143 comprises, for example, nickel or a nickel alloy with a nickel atomic content of more than 40%. The material of the anti-oxidation layer 143 comprises, for example, a binary or ternary nickel alloy, such as a nickel-aluminum alloy, a nickel-molybdenum alloy, a nickel-tungsten alloy, a nickel-titanium alloy, or a nickel-copper alloy.

[0103] It should be noted that the thickness of the antioxidant layer 143 ranges from 100 Å to 40,000 Å. The thickness of the antioxidant layer 143 may be, for example, 100 Å, 500 Å, 5,000 Å, 8,000 Å, 10,000 Å, 20,000 Å, 30,000 Å, or 40,000 Å.

[0104] In some embodiments, as in Fig. 6A, the first conductive layer 12 further includes an adhesive layer 144, and the adhesive layer 144 is disposed between the main conductive layer 141 of the first conductive layer 12 and the substrate 11 to improve the adhesion between the main conductive layer 141 and the substrate 11.

[0105] The adhesive layer 144 cannot react with the solder, preventing the solder from diffusing onto the substrate 11 and damaging the substrate 11. A material of the adhesive layer 144 is, for example, a simple metal substance or a metal alloy. The simple metal substance includes, for example, titanium or molybdenum. The metal alloy includes, for example, a molybdenum-niobium alloy, a molybdenum-titanium alloy, a molybdenum-tungsten alloy, a molybdenum-tantalum alloy, or a molybdenum-niobium-titanium alloy.

[0106] It should be noted that the thickness of the adhesive layer 144 ranges from 100 Å to 2000 Å. For example, the thickness of the adhesive layer 144 is 100 Å, 300 Å, 500 Å, 1000 Å, 1200 Å, 1500 Å, and 2000 Å.

[0107] In some embodiments relating to Fig. 3 and Fig. 4A, the electronic components 20 include light-emitting devices 21 and microchips 22. The light-emitting substrate 210 includes a plurality of drive units 110 arranged in an array, and each drive unit 110 includes a plurality of light-emitting devices 21 connected in series and / or parallel.

[0108] As in Fig. As shown in Figure 4A, each drive unit 110 includes, for example, four light-emitting devices 21 connected in series. Of course, each drive unit 110 may include four, five, seven, or eight light-emitting devices 21, and the connection method of the plurality of light-emitting devices 21 in the drive unit 110 is not limited to a series connection but may also be a parallel connection. The embodiments of the present disclosure are not limited to this.

[0109] As in the Fig. 4A, Fig. 4B and Fig. As shown in Figure 5, the plurality of second conductive portions 152 may be provided with a plurality of groups of component conductive portions 1520. The group of component conductive portions 1520 is configured to connect the light-emitting devices 21, that is, at least a portion of a surface of the group of component conductive portions 1520 remote from the substrate 11 is exposed to form a contact area P to achieve a reliable electrical connection between the pins of the light-emitting device 21 and the solder.

[0110] As in the Fig. 4B and Fig. 5, the group of conductive portions for device 1520 includes a conductive anode portion 1521 and a conductive cathode portion 1522.

[0111] On this basis and with reference to the Fig. 4A, Fig. 4B, Fig. 5 and Fig. 6B, the circuit board 10 further comprises connecting lines 161. The plurality of light-emitting devices 21 in the same drive unit 110 are electrically connected by the connecting lines 161, that is, the groups of conductive portions for component 1520 in the same drive unit 110 are electrically connected by the connecting lines 161.

[0112] As in the Fig. 4B, Fig. 4C, Fig. 4D and Fig. 5, for example, one end of a connecting line 161 is electrically connected to a cathodic conductive portion 1522 of a group of conductive portions for component 1520, and the other end thereof is electrically connected to an anodic conductive portion 1521 of another group of conductive portions for component 1520.

[0113] The above-mentioned connecting lines 161 are located in the first conductive layer 12 and / or the second conductive layer 13.

[0114] As in Fig. 4C, the connecting line 161 is located, for example, in the first conductive layer 12. In another example, as shown in Fig. 4B, the connecting line 161 is located in the second conductive layer 13. In another example shown in Fig. 4D, the connection line 161 includes a first connection pattern and a second connection pattern that overlap, the first connection pattern being arranged in the first conductive layer 12 and the second connection pattern being arranged in the second conductive layer 13.

[0115] It should be noted that an area of ​​the first interconnection pattern may be the same as or different from an area of ​​the second interconnection pattern. For example, the area of ​​the first interconnection pattern is larger than the area of ​​the second interconnection pattern, and an orthographic projection of the second interconnection pattern on the substrate 11 is located within an orthographic projection of the first interconnection pattern on the substrate 11, which may facilitate the flatness of the upper surface of the interconnection line 161.

[0116] The aforementioned microchip 22 may, for example, be a drive chip that drives the plurality of light-emitting devices 21 to emit light. A single microchip 22 may drive only the plurality of light-emitting devices 21 in a corresponding drive unit 110 to emit light, or a single microchip 22 may separately drive a plurality of light-emitting devices 21 in a plurality of drive units 110 to emit light.

[0117] For example, all four drive units 110 are electrically connected to a microchip 22, and the microchip 22 is electrically connected to a plurality of light-emitting devices 21 in the four drive units 110 to drive the plurality of light-emitting devices 21 in the four drive units 110 to emit light.

[0118] As in the Fig. 4A and Fig. 4B, the plurality of second conductive portions 152 further includes a plurality of groups of conductive portions for chips 1530. The group of conductive portions for chips 1530 is configured to connect the microchip 22. That is, at least a portion of a surface of the group of conductive portions for chips 1530 that is remote from the substrate 11 is exposed to form a solder pad P to achieve a reliable electrical connection between the pins of the microchip 22 and the solder.

[0119] As in the Fig. 3, Fig. 4A and Fig. 4B, the group of conductive sections for chips 1530 includes a data conductive section DataP, a clock conductive section CLKP, an address conductive section Di_in, a relay conductive section Di_out, a chip power conductive section VCCP, and a ground conductive section GNDP and output conductive sections OutP.

[0120] The number of data conductive sections DataP can be one, the number of clock conductive sections CLKP can be one, the number of address conductive sections Di_in can be one, the number of relay conductive sections Di_out can be one, the number of chip power conductive sections VCCP can be one, the number of ground conductive sections GNDP can be one, and the number of output conductive sections OutP can be an even number, for example, the number of output conductive sections OutP can be four.

[0121] On this basis, as in the Fig. 3, Fig. 4A and Fig. 4B, the plurality of signal lines 120 may also include, for example, first signal lines 1210 and second signal lines 1220. The first signal line 1210 is electrically connected to the group of conductive portions for device 1520, and the second signal line 1220 is electrically connected to the group of conductive portions for chips 1530.

[0122] On this basis, the first insulating layer 172 is provided with second through-holes H2 extending through the first insulating layer 172 (see Fig. 4A and Fig. 6A). The above circuit board 10 further includes a plurality of component transmission lines 133 and a plurality of chip transmission lines 130. The plurality of component transmission lines 133 are located in the second conductive layer 13, and the plurality of chip transmission lines 130 are located in the second conductive layer 13.

[0123] With reference to the Fig. 3, Fig. 4B, Fig. 5 and Fig. 6A, one end of a component transmission line 133 is in electrical contact with a first signal line 1210 through a second through-hole H2, and the other end thereof is in electrical contact with a second conductive portion 152 of a group of conductive portions for components 1520. One end of a chip transmission line 130 is in electrical contact with a second signal line 1220 via a second through-hole H2, and the other end thereof is in electrical contact with a second conductive portion 152 of a group of conductive portions for chips 1530. Therefore, a reduction in the occupied area of ​​the circuit line and the prevention of short circuits at the intersections of the circuit line can be avoided.

[0124] For example, the first signal lines 1210, as shown in Fig. 3, the device power supply signal lines 123 and the second signal lines 1220 include the common voltage lines 124, the data signal lines 125, the clock signal lines 126, the feedback signal lines 127, the address signal lines 128, and the chip power supply signal lines 129.

[0125] As in the Fig. 3, Fig. 4A and Fig. 5, the device power supply signal line 123 is electrically connected to an anode line portion 1521 of a first light-emitting device 21 in the drive unit 110 through a device transmission line 133. The common voltage line 124 is electrically connected to a ground conductive portion GNDP through a chip transmission line 130. The data signal line 125 is electrically connected to a data conductive portion DataP through a chip transmission line 130. The clock signal line 126 is electrically connected to a clock conductive portion CLKP through a chip transmission line 130. The feedback signal line 127 is electrically connected to a relay conductive portion Di_out through a chip transmission line 130. The address signal line 128 is electrically connected to an address conductive portion Di_in through a chip transmission line 130.The chip power supply signal line 129 is electrically connected to a conductive chip power section VCCP by a chip transmission line 130.

[0126] In some embodiments relating to Fig. 4A, Fig. 4B and Fig. 6A, the circuit board 10 further comprises interconnection transmission lines 134. The plurality of interconnection transmission lines 134 are located in the second conductive layer 13. One end of an interconnection transmission line 134 is in electrical contact with a second conductive portion 152 through a second through-hole H2 (see Fig. 5) a group of conductive portions for component 1520, and the other end thereof is in electrical contact with a second conductive portion 152 through a second through-hole H2 (see Fig. 5) a group of conductive sections for chips 1530.

[0127] In some embodiments, as in Fig. 10A, the circuit board 10 further includes a first passivation layer 171 and a second passivation layer 173.

[0128] Here, the materials of the first passivation layer 171 and the second passivation layer 173 may include at least one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For example, the materials of the first passivation layer 171 and the second passivation layer 173 each include silicon nitride (SiN). The thicknesses of the first passivation layer 171 and the second passivation layer 173 are each in a range of 1000 Å to 4000 Å inclusive. For example, the thicknesses of the first passivation layer 171 and the second passivation layer 173 are each in a range of 1000 Å, 1500 Å, 2000 Å, 2500 Å, 3000 Å, 3500 Å, and 4000 Å.

[0129] As in Fig. As shown in Figure 10A, the first passivation layer 171 is disposed between the first conductive layer 12 and the first insulating layer 172. The second passivation layer 173 is disposed between the first insulating layer 172 and the second conductive layer 13.

[0130] On this basis, as in Fig. 10A, a plurality of solder pads P electrically connected to the same electronic component 20 are exposed through the same first through-hole H1, so that the first insulating layer 172 is not present in a region between the plurality of solder pads P electrically connected to the same electronic component 20.

[0131] In this case, the number of film layers between the plurality of solder pads P electrically connected to the same electronic component 20 is reduced, thereby reducing a height difference of the soldering surfaces of the plurality of solder pads P electrically connected to the same electronic component 20 and improving the flatness of the electronic component 20 after fixation (e.g., improving the flatness of a surface of the light-emitting device 21 on a light-output side so that the outgoing light can be relatively uniform).

[0132] In some embodiments, as in Fig. 10A, the circuit board 10 further includes a third passivation layer 174 and a second insulating layer 175.

[0133] Here, the material of the third passivation layer 174 may comprise at least one of the inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For example, the material of the third passivation layer 174 comprises silicon nitride (SiN). The thickness of the third passivation layer 174 ranges from 1000 Å to 6000 Å inclusive. For example, the thickness of the third passivation layer 174 may be 1000 Å, 2000 Å, 3000 Å, 4000 Å, 5000 Å, or 6000 Å.

[0134] Furthermore, the material of the second insulating layer 175 is made of resin, e.g., epoxy resin. The thickness of the second insulating layer 175 ranges from 2 µm to 10 µm inclusive. For example, the thickness of the second insulating layer 175 is 2 µm, 3 µm, 4 µm, 5 µm, 7 µm, 8 µm, and 10 µm.

[0135] As in Fig. As shown in Figure 10A, the third passivation layer 174 is arranged on a side of the second conductive layer 13 facing away from the substrate 11 and exposes at least the contact area. The second insulating layer 175 is arranged on a side of the third passivation layer 174 facing away from the substrate 11 and exposes at least the contact area P.

[0136] On this basis, the third passivation layer 174 and / or the second insulating layer 175 further exposes a region between the plurality of solder pads P electrically connected to the same electronic component 20, so that the third passivation layer 174 and / or the second insulating layer 175 are not present in the region between the plurality of solder pads P electrically connected to the same electronic component 20.

[0137] As in Fig. 10B, for example, the second insulating layer 175 further exposes the area between the plurality of solder pads P electrically connected to the same electronic component 20, so that no second insulating layer 175 is present in the area between the plurality of solder pads P electrically connected to the same electronic component 20.

[0138] In some embodiments, as in Fig. 11, the circuit board 10 further comprises a marking layer 18 and a fourth passivation layer 19.

[0139] One material of the marking layer 18 is metal. For example, the material of the marking layer 18 comprises at least one of the elements molybdenum, titanium, copper, and niobium. The thickness of the marking layer 18 is in a range from 300 Å to 1000 Å inclusive. For example, the thickness of the marking layer 18 is 300 Å, 400 Å, 500 Å, 600 Å, 800 Å, or 1000 Å.

[0140] Furthermore, a material of the fourth passivation layer 19 may comprise at least one of the inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For example, the material of the fourth passivation layer 19 comprises silicon nitride (SiN). The thickness of the fourth passivation layer 19 is in a range from 1000 Å to 3000 Å inclusive. For example, the thickness of the fourth passivation layer 19 is 1000 Å, 1500 Å, 2000 Å, 2500 Å, or 3000 Å.

[0141] As in Fig. As shown in Figure 11, the marking layer 18 is disposed between the substrate 11 and the first conductive layer 12, and the fourth passivation layer 19 is disposed between the marking layer 18 and the first conductive layer 12. The marking layer 18 includes at least one alignment mark 181 to facilitate alignment by capturing an image of the alignment mark 181 during the process.

[0142] The above descriptions merely illustrate specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto. Modifications or substitutions that anyone skilled in the art can conceive within the technical scope of the present disclosure are included within the scope of the present disclosure. Therefore, the scope of the present disclosure is subject to the scope of the claims.

Claims

[1] Printed circuit board, comprising: a substrate; a first conductive layer disposed on one side of the substrate; wherein the first conductive layer comprises a plurality of signal lines and a plurality of first conductive portions; a first insulating layer disposed on a side of the first conductive layer facing away from the substrate; wherein the first insulating layer is provided with first through holes extending through the first insulating layer; and a second conductive layer disposed on a side of the first insulating layer facing away from the substrate; wherein the second conductive layer comprises a plurality of second conductive portions; wherein a second conductive portion passes through a first through-hole to be in electrical contact with a first conductive portion; wherein the second conductive portion comprises solder pads, and a solder pad is a portion of the second conductive portion exposed through the first through-hole in the first insulating layer; wherein the first conductive layer and the second conductive layer each comprise at least one main conductive layer, and the main conductive layer is capable of forming a first intermetallic compound with the solder; at least one of the first conductive layer and the second conductive layer further comprises a stop layer, and the stop layer is arranged between two adjacent main conductive layers and is capable of forming a second intermetallic compound with the solder; and a reaction rate between the stop layer and the solder is lower than a reaction rate between the main conductive layer and the solder. [2] The printed circuit board according to claim 1, wherein a material of the stop layer comprises one of nickel, a copper alloy having a copper atomic content of more than 40%, and a nickel alloy having a nickel atomic content of more than 40%. [3] The printed circuit board according to claim 1 or 2, wherein a thickness of the stop layer is in a range of 100 Å to 5000 Å inclusive. [4] The printed circuit board according to any one of claims 1 to 3, further comprising an antioxidant layer, wherein the antioxidant layer is disposed on a side of the second conductive layer facing away from the substrate, and the antioxidant layer is capable of forming a third intermetallic compound with the solder. [5] The printed circuit board according to claim 4, wherein the antioxidant layer encloses both conductive traces and the second conductive portions in the second conductive layer. [6] The printed circuit board according to claim 4 or 5, wherein a material of the antioxidant layer comprises nickel or a nickel alloy having a nickel atomic content of more than 40%. [7] The printed circuit board according to any one of claims 4 to 6, wherein a thickness of the antioxidant layer is in a range of 100 Å to 40,000 Å inclusive. [8] The printed circuit board according to any one of claims 1 to 7, wherein the first conductive layer further comprises an adhesive layer, and the adhesive layer is disposed between a conductive main layer of the first conductive layer and the substrate, and the adhesive layer cannot react with the solder. [9] The printed circuit board according to claim 8, wherein a material of the adhesive layer comprises one of titanium, molybdenum, a molybdenum-niobium alloy, a molybdenum-titanium alloy, a molybdenum-tungsten alloy, a molybdenum-tantalum alloy, and a molybdenum-niobium-titanium alloy. [10] The printed circuit board according to claim 8 or 9, wherein a thickness of the adhesive layer is in a range of 100 Å to 2000 Å inclusive. [11] The printed circuit board according to any one of claims 1 to 10, wherein an area of ​​an orthographic projection of the first conductive portion on the substrate is larger than an area of ​​an orthographic projection of the solder pad on the substrate, and the orthographic projection of the solder pad on the substrate is within the range of the orthographic projection of the first conductive portion on the substrate. [12] A printed circuit board according to any one of claims 1 to 11, wherein the first conductive layer comprises a single conductive main layer and a single stop layer, the second conductive layer comprises a further single conductive main layer and a further single stop layer, and two stop layers are arranged between the single conductive main layer of the first conductive layer and the further single conductive main layer of the second conductive layer; or the first conductive layer comprises a single conductive main layer, the second conductive layer comprises a further single conductive main layer and a single stop layer, and the single stop layer is arranged between the single conductive main layer of the first conductive layer and the further single conductive main layer of the second conductive layer; or the first conductive layer comprises a single conductive main layer and a single stop layer, the second conductive layer comprises a further single conductive main layer, and the single stop layer is arranged between the single conductive main layer of the first conductive layer and the further single conductive main layer of the second conductive layer. [13] The circuit board according to any one of claims 1 to 12, wherein the plurality of second conductive portions are divided into a plurality of groups of conductive portions for components and a plurality of groups of conductive portions for chips; one group of conductive portions for components is configured to be connected to a light-emitting component, and one group of conductive portions for chips is configured to be connected to a microchip; the circuit board comprises a plurality of drive units arranged in an array, and each drive unit comprises a plurality of groups of conductive portions for components; the circuit board further comprises: Connecting lines, wherein the plurality of groups of conductive portions for components in a same drive unit are electrically connected by connecting lines, and the connecting lines are arranged in the first conductive layer and / or the second conductive layer. [14] The printed circuit board according to any one of claims 1 to 13, wherein the plurality of second conductive portions are divided into a plurality of groups of conductive portions for components and a plurality of groups of conductive portions for chips; the signal lines comprise a first signal line and a second signal line; the first signal line is electrically connected to a group of conductive portions for components, and the second signal line is electrically connected to a group of conductive portions for chips; and the first insulating layer is further provided with second through-holes extending through the first insulating layer; the circuit board further comprises: a plurality of component transmission lines located in the second conductive layer, one end of a component transmission line being in electrical contact with the first signal line through a second through-hole, and another end thereof being in electrical contact with a second conductive portion of the group of conductive portions for components; and a plurality of chip transmission lines located in the second conductive layer, one end of a chip transmission line being in electrical contact with the second signal line through another second through-hole, and another end thereof being in electrical contact with a second conductive portion of the group of conductive portions for chips. [15] The printed circuit board according to any one of claims 1 to 14, further comprising: a first passivation layer disposed between the first conductive layer and the first insulating layer and exposing at least a portion of the first conductive portion; and a second passivation layer disposed between the first insulating layer and the second conductive layer and exposing at least a portion of the first conductive portion; wherein a plurality of solder pads electrically connected to a same electronic component are exposed through a same first through-hole, so that the first insulating layer is not present in a region between the plurality of solder pads electrically connected to the same electronic component. [16] Printed circuit board according to one of claims 1 to 15, further comprising: a third passivation layer disposed on a side of the second conductive layer facing away from the substrate and exposing at least the solder pad; and a second insulating layer arranged on a side of the third passivation layer facing away from the substrate and exposing at least the solder pad; wherein the third passivation layer and / or the second insulating layer further expose a region between a plurality of solder pads electrically connected to a same electronic component, such that the third passivation layer and / or the second insulating layer are not present in the region between the plurality of solder pads electrically connected to the same electronic component. [17] A light-emitting substrate comprising: a printed circuit board, wherein the printed circuit board is the printed circuit board according to any one of claims 1 to 16; and electronic components, where pins of an electronic component are electrically connected to solder pads in the circuit board by the solder. [18] The light-emitting substrate according to claim 17, wherein the circuit board comprises an antioxidant layer, and the antioxidant layer encloses both conductive traces and the second conductive portions in the second conductive layer; and the light-emitting substrate further comprises a reflective layer; the reflective layer is disposed on a side of the antioxidant layer facing away from the substrate and is in contact with the antioxidant layer; the reflective layer is provided with a plurality of openings therein, and the pins of the electronic component are electrically connected to the solder and the solder pads through an opening. [19] Backlight module comprising: the light-emitting substrate according to claim 17 or 18, wherein the light-emitting substrate has a light-exit surface and a non-light-exit surface that are opposite to each other; and a plurality of optical films arranged on the light-exit surface of the light-emitting substrate. [20] Display device comprising: the backlight module according to claim 19; and a display panel disposed on a side of the plurality of optical films in the backlight module remote from the light-emitting substrate.

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