OPERATING METHOD, SEMICONDUCTOR MODULE AND MANUFACTURING METHOD

Abstract

In one embodiment, the operating method is intended for the operation of a semiconductor module (10) and comprises: - Providing the semiconductor module (10), wherein the semiconductor module (10) comprises a plurality of power semiconductor components (1), wherein the power semiconductor components (1), seen in plan view, are arranged next to one another and the power semiconductor components (1) are connected to one another by a bus line (5), - controlling a current through the power semiconductor components (1) via a first voltage (Vg,bus) provided by the bus line (5), - Providing control signals (Ucont) for the power semiconductor components (1) via the bus line (5), which are modulated as a second voltage onto the first modulated voltage (Vg,bus).

Description

[0001] An operating method for a semiconductor module is provided. Furthermore, a semiconductor module is also provided. Furthermore, a method for manufacturing such a semiconductor module is also provided.

[0002] Document US 2015 / 0333737 A1 relates to a control circuit for a gate driver circuit.

[0003] Document US 2013 / 0200927 A1 discloses a transistor with overtemperature protection.

[0004] One problem to be solved is to provide a robust semiconductor module with improved thermal behavior and a corresponding operating method.

[0005] This object is achieved, inter alia, by an operating method, a semiconductor module, and a manufacturing method as defined in the independent patent claims. Exemplary further developments are the subject of the dependent claims.

[0006] For example, the semiconductor module described and operated accordingly herein includes multiple semiconductor components interconnected by a bus line. Logic units on a power semiconductor chip in each of the semiconductor components, in combination with the bus line, can ensure, for example, consistent temperatures of the power semiconductor chips throughout the semiconductor module. This is achieved, for example, by modulating temperature information onto a gate voltage supplied to individual power semiconductor chips of the semiconductor module.

[0007] Paralleling power semiconductor chips is limited due to asymmetric current sharing, asymmetric temperature, and asymmetric loss distribution between the individual power semiconductor chips. Alternative solutions include the use of gate resistors, which reduce switching speed and increase losses; a low-parasitic module design, which imposes space and power constraints; careful chip pre-selection, which is expensive; or combinations of the above; or the implementation of switching regulators in on-chip CMOS logic on the individual SiC power semiconductor chips, which would individually control the switching behavior of each chip to achieve a uniform junction temperature.

[0008] The operating method and semiconductor module described herein propose modulating information onto the gate signal used to adjust control parameters in the on-chip CMOS controller. This enables improved design flexibility and performance optimization of the parallel-connected power semiconductor chips.

[0009] In at least one embodiment, the operating method is intended for operating a semiconductor module and comprises, for example, the following steps in the specified order: - Providing the semiconductor module, wherein the semiconductor module comprises a plurality of power semiconductor components, wherein the power semiconductor components, seen in plan view, are arranged next to one another and the power semiconductor components are connected to one another by a bus line; - controlling a current through the power semiconductor components via a first voltage provided by the bus line; - Providing control signals for the power semiconductor components via the bus line, which are modulated as a second voltage onto the first modulated voltage.

[0010] Thus, gate signal modulation can be used to adjust control parameters of a chip-integrated CMOS control algorithm, which is implemented, for example, on SiC power semiconductor chips.

[0011] The approach presented here allows for greater flexibility in controller design. If control parameters such as thresholds and gains are hard-coded, the semiconductor module and / or converter designer cannot adjust these parameters and may have to accept a suboptimal design. If control parameters could be accessed and / or adjusted externally by the converter designer, additional interfaces for connecting wires must be provided, significantly increasing complexity, space requirements, and cost.

[0012] If the parameters of the on-chip CMOS controller are externally programmable during the inverter design phase, e.g., via the gate connection, which could be put into a programming mode, long-term on-chip energy storage would be required, which would be very limited due to the very small available space.

[0013] The method described here proposes a way to modulate control parameters onto the gate signal, which requires no additional wiring and / or interface and is efficient, cost-effective and robust.

[0014] In short, one idea is to modulate information onto the gate signal used for control parameter settings in the on-chip CMOS controller, i.e., the logic unit.

[0015] For example, a gate voltage for the turn-on circuit is typically chosen at around 15 V, but the use of slightly higher voltage levels would not change the switching and conduction behavior of the power semiconductor, see for example document “IKW50N65F5 650VDuoPack IGBT and Diode - High speed switching series fifth generation”, datasheet from Infineon, Rev. 2.1, May 5, 2015, in particular Fig. The desired information could therefore be obtained by adding a small voltage, which is subtracted, filtered, and amplified in a demodulator circuit within the on-chip CMOS logic unit. This would be very efficient and could limit the data to a parameter value. Alternatively, one could add signals with different frequencies, for example, over ten times the gate's switching frequency, and convey the parameter information via the amplitudes of these signals, which can be retrieved, for example, via bandpass filtering in the demodulator circuit.

[0016] Advantageous features of the operating method described herein include: - efficient, flexible and easy to use for the designer; - improved performance of the parallel-connected power semiconductor chips through operationally optimized parameter settings; - dynamic parameter changes during operation to optimize the behavior of parallel-connected chips, e.g. after load changes or at very low ambient temperatures that would increase switching overvoltages; - no need for additional wiring, which would increase complexity and be severely limited by space requirements; and / or - no need for long-term data storage in the chip-integrated CMOS logic of the power semiconductor device.

[0017] In brief, the proposed operating method uses, for example, semiconductor devices with a controller implemented as an on-chip CMOS logic unit of power semiconductor chips, where one or more signals are modulated onto the gate driver's on-signal and retrieved via a demodulator circuit of the on-chip CMOS logic unit, resulting in demodulated values. The demodulated values ​​are used as parameter values ​​for at least one algorithm of a switching regulator, which changes and / or delays the switching speed and outputs a switching signal for the respective power semiconductor chip to the gate electrode pad.

[0018] For example, the semiconductor module comprises at least four or at least ten of the semiconductor components. Alternatively or additionally, there are at most 150 or at most 100 or at most 30 of the semiconductor components. For example, the semiconductor module comprises at least ten and at most 30 of the semiconductor components, such as 16 semiconductor components.

[0019] According to at least one embodiment, one or some or each of the power semiconductor devices comprise a power semiconductor chip, a logic unit, and a gate pad. The gate pads are interconnected via the bus line. One or some or each of the respective power semiconductor chips comprise a gate electrode contact area. The logic unit is electrically positioned between the gate electrode contact area and the associated gate pad. In the following, the power semiconductor devices may be referred to as semiconductor devices for short.

[0020] For example, the logic units are CMOS components. The logic units do not have to be mechanically self-supporting chips, but can be mechanically supported by the power semiconductor chips. Therefore, it is possible for the logic units to be comparatively thin and comprise only a small number of electrical elements such as resistors, transistors, and capacitors. For example, the logic units each comprise a maximum of 10 5 or a maximum of 10 4 or a maximum of 10 3 such electrical elements. The thickness of the logic units can be at least 0.2 µm and / or at most 10 µm or at most 3 µm.

[0021] For example, the gate pad and / or the gate electrode contact area are metallizations. This means that the gate pad and / or the gate electrode contact area can consist of one or more metals; for example, at least 98% by mass of the gate pad and / or the gate electrode contact area is metal.

[0022] According to at least one embodiment, the gate pad is configured to provide the gate electrode contact pads of the semiconductor devices with a bus gate voltage. Thus, the gate pad can be connected to the gate electrode contact pads via the respective logic unit. Therefore, there may be no direct electrical contact between the gate electrode contact pads and the gate pad. For example, at least one active electrical component, such as a variable resistor and / or a switch, is located between the gate electrode contact pads and the gate pad.

[0023] According to at least one embodiment, in each of the semiconductor devices, the logic unit is configured to modify the bus-gate voltage applied to the gate pad. Therefore, the bus-gate voltage may at least temporarily differ from a chip-gate voltage applied to the gate electrode pad, at least when the corresponding logic unit is powered and / or active.

[0024] According to at least one embodiment, in each of the semiconductor devices, the logic unit is configured for a unit current through it of at most 1% of a chip current through the power semiconductor chip. For example, this value is at most 0.1%. For example, the unit current through the logic units in the on-state is at least 0.1 mA and / or at most 0.02 A.

[0025] According to at least one embodiment, in each of the semiconductor devices, the logic unit is geometrically located partially or completely between the gate electrode contact area and the gate pad. For example, at least 50%, at least 80%, or at least 95% of a volume of the respective logic unit is located between the associated gate pad and the gate electrode contact area. Otherwise, the logic unit can be placed outside a gap between the gate pad and the associated gate electrode contact area.

[0026] According to at least one embodiment, the power semiconductor chips are each selected from the following group: a metal-insulator-semiconductor field-effect transistor, MISFET, a metal-oxide-semiconductor field-effect transistor, MOSFET, an insulated-gate bipolar transistor, IGBT, or a reverse-conducting insulated-gate bipolar transistor, RC-IGBT.

[0027] All power semiconductor chips in the semiconductor module can be of the same type, or there can be different types of power semiconductor chips. The same applies to the logic units.

[0028] According to at least one embodiment, the power semiconductor chips are each configured for a voltage between a first electrode and a second electrode of the respective power semiconductor chip of at least 0.6 kV or of at least 1.2 kV and / or of at most 15 kV. Alternatively or additionally, the power semiconductor chips are each configured for a current between the first electrode and the second electrode of at least 1 A or of at least 0.01 kA or of at least 0.1 kA and / or of at most 100 kA or of at most 10 kA or of at most 1 kA. This means that a current flow through the semiconductor component can be controlled by means of the gate electrode and by the respective voltages between the first and second electrodes and can be switched on and off in particular by switching a voltage at the gate electrode on and off.

[0029] According to at least one embodiment, the first electrode in each of the semiconductor components is a source or emitter electrode. Accordingly, the second electrode is a drain electrode or a collector electrode of the respective power semiconductor chip.

[0030] According to at least one embodiment, the bus line provides a bus gate voltage as the first voltage to all semiconductor devices simultaneously. "Simultaneously" means without any significant delay between the semiconductor devices; a significant delay is, for example, at most 10 -3 or a maximum of 10 -4 or a maximum of 10 -5 of 1 / f, where f is the switching frequency of the gate signal at the gate pad. The delay is, for example, at most 0.1 µs, at most 10 ns, or at most 1 ns. This delay can be determined by a propagation time difference of the gate signal between the semiconductor components.

[0031] According to at least one embodiment, the bus line consists of a single line and / or a single channel. The bus line consists, for example, of multiple bond wires electrically connected in series across the gate pads. The bus line may be free of any branches or may otherwise have at least one branch to reduce the overall length of the bus line, for example, depending on an arrangement pattern of the semiconductor components.

[0032] According to at least one embodiment, the bus line is the only direct electrical connection between all gate pads. However, an indirect electrical connection between the gate pads may be provided via internal power supplies of the semiconductor devices and a ground line, such as a source line or an emitter line.

[0033] According to at least one embodiment, which can be seen in the top view of the semiconductor devices, the logic unit is smaller than or equal to the size of the associated gate pad. Therefore, the logic units can be comparatively small, viewed in a top view.

[0034] According to at least one embodiment, the gate pad completely covers the associated logic unit. This means that the logic units can be completely buried beneath the associated metallic gate pad.

[0035] According to at least one embodiment, the second voltage averages at most 1% of the first voltage over time. By modulating the second voltage to the first voltage, the first voltage remains virtually unchanged. Accordingly, the second voltage does not, or only slightly, influence the switching behavior of the associated power semiconductor chip.

[0036] According to at least one embodiment, the second voltage is at most 0.5 V or at most 0.2 V or at most 0.1 V. Alternatively or additionally, the second voltage is, on average over time, at least 1 mV or at least 5 mV.

[0037] According to at least one embodiment, a peak voltage of the first voltage is at least 3 V or at least 10 V. Alternatively or additionally, the peak voltage is at most 30 V or at most 20 V. It is possible for the first voltage to be at least 2 V or at least 6 V and / or at most 15 V or at most 10 V on average over time.

[0038] According to at least one embodiment, the semiconductor components also receive and transmit signals via the bus line. In other words, bidirectional communication can occur via the bus line. For example, the semiconductor components receive the control signal and transmit sensor signals.

[0039] According to at least one embodiment, the semiconductor module (10) further comprises one or more control units. The at least one control unit is located outside the semiconductor components, i.e., it is a component that is separate from the semiconductor components. Otherwise, the control unit can be an external component that is not part of the semiconductor module; in this case, the control unit is connected to the semiconductor module and / or the semiconductor components via the bus line. Otherwise, the control unit can be contained in at least one of the semiconductor components.

[0040] According to at least one embodiment, the at least one control unit supplies the control signals to the semiconductor components. For example, the at least one control unit collects the sensor signals from all relevant semiconductor components and calculates a corresponding control signal, for example based on the sensor signals.

[0041] It is possible for each of the semiconductor components to be provided with an individual control signal, which can be individualized by an address transmitted in the control signal. Otherwise, there may be a common control signal for all semiconductor components.

[0042] According to at least one embodiment, the logic units each comprise a demodulator. The demodulator receives a superposition of the first and second voltages and demodulates a control voltage signal corresponding to the second voltage from this superposition. It is possible for the demodulator to also be a modulator that can modulate a sensor signal to the first voltage.

[0043] According to at least one embodiment, the logic units each comprise a switching regulator. The switching regulator receives the control voltage signal from the demodulator. For example, the switching regulator outputs a chip gate voltage to a gate of the respective power semiconductor chip based on the control voltage signal and the sensor signal.

[0044] According to at least one embodiment, the logic units each comprise one or more sensors. The switching regulator receives at least one sensor signal from the at least one sensor.

[0045] According to at least one embodiment, the respective logic unit is configured to output the sensor signal on the bus line. Accordingly, one sensor signal can be present on the bus line per sensor. The sensor signals, e.g., one sensor signal per semiconductor component, can be output simultaneously, so that an averaged or superimposed signal is present on the bus line. Otherwise, it is also possible for the sensor signals to be output using a time-division multiplexing method, i.e., with a time delay.

[0046] According to at least one embodiment, the chip gate voltage also includes the second voltage. In other words, the second voltage must not be filtered out from the chip gate voltage applied to the gate electrode contact area. However, the second voltage can be attenuated, for example, by a resistor. Since the first voltage can be attenuated by the same resistor, a quotient of the first voltage and the second voltage at the gate pad and at the gate electrode contact area can be the same. Otherwise, the second voltage can be filtered out, so that only the first voltage is present at the gate electrode contact area, possibly attenuated by a resistor.

[0047] According to at least one embodiment, the sensor is a temperature sensor. For example, the at least one sensor comprises or is a temperature-dependent electrical resistor. The resistor can have a positive or negative temperature characteristic, i.e., the electrical resistance can either increase or decrease with increasing temperature.

[0048] According to at least one embodiment, the switching regulators control a switching behavior of the gates of the respective power semiconductor chips such that the junction temperatures of the power semiconductor chips are all the same with a tolerance of at most 10 K or at most 20 K

[0049] Therefore, the logic unit in one or some or each of the semiconductor devices is configured to adjust a junction temperature of the corresponding power semiconductor chip. This is done, for example, by adjusting a turn-on time of the power semiconductor chip. The turn-on time and also a turn-off time can be adjusted by providing a variable resistor between the gate pad and the gate electrode contact area, wherein the variable resistor is part of the respective logic unit and can be adjusted, for example, by the logic unit.

[0050] Additionally, a semiconductor module is provided. The operating method operates a semiconductor module as specified in connection with at least one of the above-mentioned embodiments. Features of the semiconductor module are therefore also disclosed for the operating method, and vice versa.

[0051] In at least one embodiment, the semiconductor module comprises: - a plurality of semiconductor components, wherein the semiconductor components are arranged next to one another in plan view, and - a bus line that connects all of the semiconductor components, where - the semiconductor components are configured to receive a superposition g1 of a first voltage Vg,bus and a second voltage Ucont, the superposition g1 is provided by the bus line, and the first voltage Vg,bus is intended to control a current through the respective semiconductor component and the second voltage Ucont is intended to adjust a switching behavior of the respective semiconductor component, - each of the semiconductor components is configured to demodulate the control signal Ucont from the superposition g1. A switching signal g2 is optionally generated in the semiconductor components and output to the corresponding gate.

[0052] Furthermore, a method for manufacturing the power semiconductor module is provided. The method produces a semiconductor module as specified in connection with at least one of the above-mentioned embodiments. Features of the semiconductor module are therefore also disclosed for the manufacturing method and the operating method, and vice versa.

[0053] In at least one embodiment, the method is intended for manufacturing a semiconductor module and comprises, for example, at least the following steps in the specified order: - Providing the power semiconductor chips and logic units, - bonding at least one logic unit to the corresponding power semiconductor chip, e.g. by wafer bonding, - Attaching at least one gate pad above the corresponding logic unit, - Attaching the semiconductor components to a common carrier, and - Connecting the gate pads together via the bus line.

[0054] An operating method, a semiconductor module, and a manufacturing method are explained in more detail below with reference to the drawings. Elements that are the same in the individual figures are designated by the same reference numerals. The relationships between the elements are not shown to scale; instead, individual elements may be exaggerated to facilitate understanding.

[0055] The figures show: Fig. 1 a schematic perspective view of an embodiment of a semiconductor module comprising semiconductor components described herein, Fig. 2 to 4 are schematic sectional views of embodiments of semiconductor devices described herein, Fig. 5 is a schematic perspective view of an embodiment of a semiconductor device described herein, Fig. 6 to 11 are schematic sectional views of process steps of an exemplary method for manufacturing semiconductor devices described herein, and Fig. 12 and Fig. 13 schematic circuit diagrams of embodiments of power semiconductor devices described herein.

[0056] In Fig. 1 shows an embodiment of a semiconductor module 10. The semiconductor module 10 comprises a plurality of semiconductor components 1. For example, in Fig. 1 only three of the semiconductor components 1 are shown, but the semiconductor module 10 may comprise many more of the semiconductor components 1. For example, if more of the semiconductor components 1 are present, they may be arranged in a two-dimensional array, such as a 4 x 4 array. Although in Fig. 1 all of the semiconductor components 1 are constructed the same, it is also possible to combine different types of semiconductor components 1 within the semiconductor module 10.

[0057] For example, the semiconductor components 1 are all mounted with their second electrodes 62 on a common second power line 72 of the semiconductor module 10. The second power line 72 can, for example, be a spatial metallization of a printed circuit board, such as a metal-insulator-metal board. The second power line 72 may be a contact for a drain D. First electrodes 61 of the semiconductor components 1 on sides facing away from the second power line 72 are electrically connected to a first power line 71, which can also be arranged on the printed circuit board and which can be a contact for a source S. For example, the first power line 71 is each connected to the first electrodes 61 by a pair of bond wires. Viewed in plan view, the first electrodes 61 can be L-shaped. In a free corner of the L, there is a gate pad 4, which is realized, for example, by metallization.

[0058] All gate pads 4 are interconnected by a bus line 5. A voltage Vg,bus is provided for the gates G of the semiconductor components 1 via the bus line 5. Furthermore, a control signal Ucont is provided for the logic units 3 of the semiconductor components 1 via the bus line 5. It is possible for the bus line 5 to transmit at least one sensor signal sent by the semiconductor components 1. The bus line 5 can be implemented by a chain of bond wires interconnected via the gate pads 4. Therefore, each bus line 5 can consist of a single electrical line.

[0059] A control unit 9 is optionally present. The control unit 9 can be part of the semiconductor module 10 or an external component. Furthermore, the control unit 9 can alternatively be integrated into at least one of the semiconductor components 1. The control unit 9 is connected via the bus line 5. It is possible for a control signal Ucont and the voltage Vg,bus to be generated in the control unit 9 or provided by it.

[0060] For example, a fill factor of the semiconductor components 1 on the second power line 72 is at least 20% or at least 50% and / or at most 90% or at most 70%. The fill factor is, for example, a quotient of the combined area of ​​all semiconductor components 1 and the area within a shortest closed line enclosing all semiconductor components 1, and is shown in a plan view. This means that the semiconductor components 1 can be arranged relatively close to one another.

[0061] Some examples of internal configurations of the semiconductor devices 1 are shown in the Fig. 2 to 4. The semiconductor components 1 each comprise a power semiconductor chip 2 with a gate electrode contact area 24 and the first and second electrodes 61, 62. Furthermore, the semiconductor components 1 each comprise a logic unit 3, such as a CMOS component, where CMOS stands for complementary metal oxide semiconductor. For example, the gate pads 4 are arranged entirely or partially on the associated gate electrode contact area 24.

[0062] The logic units 3 are geometrically positioned partially or completely between the associated gate pad 4 and gate electrode contact area 24. However, it is alternatively possible for the logic units 3 to be placed outside a space between the pairs of gate electrode contact areas 24 and gate pads 4, and furthermore, it is alternatively or additionally possible for the gate pads 4, as seen in plan view, not to cover the associated gate electrode contact areas 24.

[0063] Unlike in the Fig. 1 to 4, the gate pads 4 do not have to be positioned at a corner of the semiconductor component 1, as seen in the plan view, but can also be positioned centrally on the power semiconductor chip 2, so that the first electrode 61 can surround the respective gate pad 4.

[0064] According to Fig. 2, the logic unit 3 covers only a portion of the gate electrode contact area 24. Furthermore, the logic unit 3 is embedded in an electrically insulating material 81. The electrically insulating material 81 and the logic unit 3 can be flush with one another on a side facing away from the power semiconductor chip 2. The gate pad 4 is located on top of the logic unit 3 and the electrically insulating material 81. The gate pad 4 and the gate electrode contact area 24 can be congruent, as seen in plan view.

[0065] Contrary to what is shown, it is also possible for the gate pad 4 to be positioned entirely on the logic unit 3. Furthermore, it is possible for the gate pad 4, as seen in plan view, to be located entirely within the gate electrode contact area 24, while the gate electrode contact area 24 is larger than the gate pad 4. Alternatively, the gate pad 4 may be larger than the gate electrode contact area 24, so that the gate electrode contact area 24, as seen in plan view, may be located entirely within the gate pad 4.

[0066] In addition, as always in Fig. 2, viewed in cross-section, the gate pad 4 protrudes beyond the first electrode 61. This means that a thickness of the first electrode 61 may be smaller than a thickness of the stack of components 24, 3, 4. Optionally, the second electrode 62 may completely or practically completely cover a side of the power semiconductor chip 2 remote from the logic unit 3.

[0067] In the embodiment of Fig. 3, the logic unit 3, seen in plan view, is congruent with the gate electrode contact surface 24. Thus, the electrically insulating material 81 of Fig. 2 are omitted. Furthermore, the stack of the gate electrode contact area 24, the logic unit 3, and the gate pad 4 may have the same thickness as the first electrode 61, so that the gate pad 4 and the first electrode 61 are flush with each other. The gate pad 4 may be positioned entirely on the logic unit 3. It is possible that the second electrode 62 on a bottom side of the power semiconductor chip 2 does not reach the edges of the bottom side. These modifications are also shown in the semiconductor device 1 in Fig. 2 possible.

[0068] According to Fig. 4, the logic unit 3 is located next to the gate electrode contact area 24, so that the logic unit 3 and the gate electrode contact area 24 do not overlap, as seen in plan view. Optionally, the gate pad 4 is located on the logic unit 3 and on the electrically insulating material 81.

[0069] Otherwise, the same as in Fig. 1 also for the Fig. 2 to 4 apply and vice versa.

[0070] In Fig. 5 shows the construction of the semiconductor device 1 from a manufacturing perspective. On the left in Fig. 5 shows the power semiconductor chip 2. The gate electrode contact area 24 and the first electrode 61 can be flush with one another in a direction pointing away from a semiconductor body of the power semiconductor chip 2.

[0071] Then, see Fig. 5 right, the electrically insulating material 81 is applied completely over the power semiconductor chip 2. The logic unit 3 is applied on the electrically insulating material 81. The gate pad 4 is shown in Fig. 5 not shown.

[0072] Furthermore, the logic unit 3 and the gate electrode contact area 24 can be connected by means of one or more electrical vias 82 through the electrically insulating material 81. Not shown, several electrical vias 82 can also be present on the first electrode 61 to connect the first electrode 61 to the first power line 71, as shown in Fig. 1 is shown.

[0073] In the Fig. 6 to 11, a manufacturing method of the semiconductor components 1 for the semiconductor module 10 is shown in more detail. According to Fig. 6, the logic unit 3 is provided. For example, the logic unit 3 comprises a first carrier 83, which may be made of Si and can be considered a donor. The first carrier 83 is followed by a first insulation layer 84, which is, for example, a buried oxide layer, such as a silicon dioxide layer. Then there is a functional semiconductor layer 85 of the logic unit, which is made of Si, for example. At least one logic structure 86 is formed in this layer 85. The logic structure 86 comprises, for example, a plurality of FETs. Finally, a second insulation layer 87, for example made of silicon dioxide, is located on the logic structure 86.

[0074] As in Fig. 7, a second carrier 88, such as a silicon handling substrate, is mounted on the second insulation layer 87. Then, see Fig. 8, the first carrier 83 is removed so that the first insulation layer 84 is exposed.

[0075] In the step of Fig. 9, a first connecting layer 89 is applied to the first insulation layer 84. For example, the first connecting layer 89 consists of silicon nitride and thus shares a main component of the crystal lattices of the power semiconductor chip 2 and the logic unit 3, which are made of SiC and Si, respectively, for example.

[0076] In the step of Fig. 10, the power semiconductor chip 2 is provided. In this exemplary embodiment, the power semiconductor chip 2 comprises a functional semiconductor layer 27 of the power chip, which consists, for example, of 4H-SiC. The functional semiconductor layer 27 of the power chip is provided with a chip structure 26, which comprises, for example, transistor units, which, like the logic structure 86, are only schematically illustrated in a very simplified manner. For example, the functional semiconductor layer 27 of the power chip and the chip structure 26 each comprise a source region, a plug region, a well region, a drift region, a gate insulator, a gate electrode structure, and a first electrode structure corresponding to the first electrode 61 (not shown), so that the chip structure 26 can correspond to an FET or an IGBT.

[0077] On a side of the functional semiconductor layer 27 of the power chip that is remote from the chip structure 26, there is optionally at least one additional semiconductor layer 28, which may be, for example, a buffer layer and a drain layer or collector layer. Furthermore, the second electrode 62 (not shown) may be located on the side of the additional semiconductor layer 28.

[0078] The chip structure 26 is covered by an upper insulating layer 25, like a silicon dioxide layer. The upper insulating layer 25 is followed by a second connecting layer 22. The first and second connecting layers 22, 89 are made of the same material, for example. These layers 22, 89 are to be connected to each other at a common interface, shown as a dashed line, for example, by wafer bonding.

[0079] The resulting semiconductor device 1 is in Fig. 11. Therefore, the power semiconductor chip 2 and the logic unit 3 are interconnected by the entire interconnect layer 23, which consists of the first and second interconnect layers 22, 89.

[0080] In Fig. 11, neither the electrical vias 82 nor the electrodes 61, 62, 24 nor a gate pad 4 are shown. However, the gate pad 4 and the first electrode 61 may be present on a side of the second insulation layer 87 remote from the chip structure 26, and there may be electrical vias 82 from the first electrode 61 to the chip structure 26, as well as at least one further electrical via 82 from the gate pad 4 to the logic structure 86.

[0081] To manufacture the semiconductor module 10, in a further process step (not shown), several of the semiconductor components 1 are mounted on a circuit board, and the semiconductor components 1 are connected to one another by the bus line 5. Optionally, the semiconductor components 1 and the bus line 5 can then be covered with a plastic material, for example, in a casting or molding step.

[0082] Otherwise, the same as in the Fig. 1 to 5 also for the Fig. 6 and Fig. 11 apply and vice versa.

[0083] In Fig. Figure 12 shows an exemplary circuit structure of the semiconductor component 1. The gate line G, which provides the bus-gate voltage Vg,bus as a first voltage and the control signal Ucont as a second voltage, is provided as an input for the logic unit 3. These voltages Vg,bus and Ucont are provided as a superposition g1. This signal g1 is received by a modulator / demodulator 37 and optionally also by a switching regulator 34. The modulator / demodulator 37 extracts the control signal Ucont from the superposition g1, so that values ​​gx are sent to the switching regulator 34.

[0084] The switching regulator 34 adjusts the bus gate voltage Vg,bus based on the control signal Ucont, which is represented by the values ​​gx, resulting in a chip gate voltage g2. The chip gate voltage g2 can be an attenuated or even amplified version of the superposition g1, so that the control signal Ucont is still present in some form in the chip gate voltage g2.

[0085] Optionally, the logic unit 3 comprises a sensor 31 that can supply the switching regulator 34 with a sensor signal Us. The chip gate voltage g2 can thus be a function of both the control signal Ucont, via the values ​​gx, which can be voltage values, and the sensor signal Us.

[0086] The logic unit 3 is supplied, for example, via an internal power supply 35, which may include an auxiliary capacitor Caux and an auxiliary diode Daux, generating an auxiliary voltage Uaux. The internal power supply 35 is supplied by the bus gate voltage Vg,bus against the source S, which may be, for example, ground voltage.

[0087] For example, as in all other embodiments, the power semiconductor chip 2 can be a power FET or a power IGBT based on SiC, Si, or GaN and configured for a current Ichip between the first and second electrodes 61, 62, corresponding to S and D, of approximately 0.1 kA at a voltage Vce of, for example, 1.2 kV. A current Iunit through the logic unit 3 is, for example, approximately 10 mA. A maximum bus gate voltage Vg,bus is, for example, approximately 15 V. The control signal Ucont has an average voltage of, for example, approximately 0.1 V.

[0088] Thus, single-value parameter information is added to the gate signal, such as a 15V signal. The demodulator can subtract such a signal, perform low-pass filtering, and amplify the resulting signal. Alternatively, multivalue parameter information is added to the gate signal in the form of amplitudes at various frequency signals, all of which can be at least an order of magnitude higher than the switching frequency. The demodulator again uses bandpass filtering and rectification to retrieve the original parameter information.

[0089] Optionally, the controller parameters can be changed dynamically during converter operation, e.g., in response to a load change. Another option is to dynamically change the controller parameters depending on the junction temperature. This would enable slower switching at lower temperatures, e.g., when starting the converter in cold environments, reducing switching overvoltages at low temperatures and leading to a longer converter lifetime and / or improved reliability.

[0090] In Fig. Figure 13 shows a more detailed example of the logic unit 3. In this example, the bus gate voltage Vg,bus is adjusted using a variable internal gate resistor RGi to become the chip gate voltage g2. A resistance of the gate resistor RGi is adjusted using a sensor signal UTj representing a junction temperature Tj of the power semiconductor chip 2, by the sensor 31, which is, for example, a temperature-dependent resistor.

[0091] A function F2 converts the temperature-dependent resistance of sensor 31 into a voltage, i.e., the sensor signal Us. For example, the sensor signal Us is fed to the switching regulator 37 and / or to an adder / subtractor 36, which can output a junction temperature deviation ΔUTj, which is converted by a function F1 into a resistance change Δr, which is applied to the internal gate resistor RGi. Otherwise, the function of the adder / subtractor 36 can be completely taken over by the switching regulator 37, so that the adder / subtractor 36 can be omitted.

[0092] Furthermore, Fig. 13 shows that the sensor signal Us is an output value of the switching regulator 37 on the bus line 5, so that other semiconductor components 1 of the semiconductor module 10 can also use the sensor signal Us to adapt their switching behavior.

[0093] Otherwise, the same as in the Fig. 1 to 11 also for the Fig. 12 and Fig. 13 apply and vice versa.

[0094] Unless otherwise stated, the components shown in the figures follow one another directly above the other in the order shown, by way of example. Components that are not in contact in the figures are separated from each other by way of example. If lines are drawn parallel to each other, the corresponding surfaces may be aligned parallel to each other. Likewise, unless otherwise indicated, the relative positions of the drawn components are correctly represented in the figures.

[0095] The invention described here is not limited by the description based on the exemplary embodiments. Rather, the invention encompasses any novel feature and any combination of features, including, in particular, any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the claims or exemplary embodiments. List of reference symbols 1 semiconductor component 2 power semiconductor chips 22 second connection layer 23 entire connection layer 24 Gate electrode contact area 25 upper insulation layer 26 Chip structure 27 functional semiconductor layer of the power chip 28 additional semiconductor layer 3 Logic unit 31 Sensor 34 switching regulators 35 internal power supply 36 adders / subtractors 37 Modulator / Demodulator 4 Gate Pad 5 Bus line 61 first electrode (source electrode or emitter electrode) 62 second electrode (drain electrode or collector electrode) 71 first power line 72 second power line 81 electrically insulating layer 82 electrical through connection 83 first carrier 84 first insulation layer 85 functional semiconductor layer of the logic unit 86 Logic structure 87 second insulation layer 88 second carrier 89 first connection layer 9 Control unit 10 semiconductor modules Caux auxiliary capacitor D Drain Daux auxiliary diode FX function G Gate G.. Voltage signal Ice current between the first and second electrode Ichip Chip current through the power semiconductor chip Iunit Unit current through the logic unit Rgi variable gate input resistance Rs sensor resistance S Source Tj junction temperature Uaux auxiliary voltage Ucont control signal Us sensor signal Vce voltage between the first and second electrode Vg,bus Bus gate voltage Δr resistance change ΔUtj junction temperature deviation QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 2015 / 0333737 A1

[0002] US 2013 / 0200927 A1

[0003] Cited non-patent literature

[0000] IKW50N65F5 650VDuoPack IGBT and Diode - High speed switching series fifth generation“, data sheet from Infineon, Rev. 2.1, May 5, 2015

[0015]

Claims

[1] Operating method for a semiconductor module (10), comprising: - Providing the semiconductor module (10), wherein the semiconductor module (10) comprises a plurality of power semiconductor components (1), wherein the power semiconductor components (1), seen in plan view, are arranged next to one another and the power semiconductor components (1) are connected to one another by a bus line (5), - controlling a current through the power semiconductor components (1) via a first voltage (Vg,bus) provided by the bus line (5), - Providing control signals (Ucont) for the power semiconductor components (1) via the bus line (5), which are modulated as a second voltage onto the first modulated voltage (Vg,bus). [2] Method according to the preceding claim, wherein each of the power semiconductor components (1) comprises a power semiconductor chip (2), a logic unit (3) and a gate pad (4), where - the gate pads (4) are connected to each other via the bus line (5), - the power semiconductor chips (2) each comprise a gate electrode contact area (24), - the logic unit (3) is placed electrically between the gate electrode contact surface (24) and the gate pad (4). [3] Method according to the preceding claim, wherein the power semiconductor chips (2) are each selected from the group comprising a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), wherein the power semiconductor chips (2) are each configured for a voltage (Vce) between a first electrode (61) and a second electrode (61) of the respective power semiconductor chip (2) of at least 0.6 kV and of at most 15 kV and are further configured for a current (Ice) between the first electrode (61) and the second electrode (62) of at least 1 A, and wherein in each case the first electrode (61) is a source electrode or an emitter electrode and the second electrode (62) is a drain electrode or a collector electrode of the respective power semiconductor chip (2). [4] Method according to one of the two preceding claims, wherein - in each of the power semiconductor components (1), the logic unit (3) is geometrically positioned at least partially between the gate electrode contact area (24) and the gate pad (4), and - the bus line (5) provides a bus gate voltage as the first voltage (Vg,bus) simultaneously for all of the power semiconductor components (1). [5] Method according to one of claims 2 to 4, wherein the bus line (5) consists of a single line and represents the only direct electrical connection between all gate pads (4). [6] Method according to one of claims 2 to 5, wherein the logic unit (3), seen in the plan view of the power semiconductor components (1), is smaller than or equal to the size of the gate pad (4) and the gate pad (4) completely covers the logic unit (3). [7] Method according to one of the preceding claims, wherein the second voltage (Us) is, on average over time, at most 1% of the first voltage (Vg,bus). [8] Method according to one of the preceding claims, wherein the second voltage (Us) is at most 0.2 V and a peak voltage of the first voltage (Vg,bus) is at least 3 V and at most 30 V. [9] Method according to one of the preceding claims, wherein the power semiconductor components (1) send and receive signals via the bus line (5) so that a two-directional communication takes place via the bus line (5). [10] Method according to one of the preceding claims, wherein the semiconductor module (10) further comprises at least one control unit (9) outside the power semiconductor components (1) or the bus line (5) of the semiconductor module (10) is connected to at least one external control unit (9), wherein the at least one control unit (9) provides the control signals (Ucont). [11] Method according to one of claims 1 to 9, wherein at least one of the power semiconductor components (1) provides the control signals (Ucont) for all other power semiconductor components (1). [12] Method according to one of the preceding claims, wherein - the logic units (23) each comprise a demodulator (37) which receives a superposition (g1) of the first and second voltages (Vg,bus, Ucont) and which demodulates a control voltage signal (gx) corresponding to the second voltage (Ucont) from the superposition (g1), - the logic units (23) each comprise a switching regulator (34) which receives the control voltage signal (gx) from the demodulator (37), - the logic units (23) each comprise a sensor (31) and the switching regulator (34) receives a sensor signal (Us) from the sensor (31), and - the switching regulator (34) outputs a chip gate voltage (g2) to a gate of the respective power semiconductor chip (2) based on the control voltage signal (gx) and the sensor signal (Us). [13] Method according to the preceding claim, wherein the chip gate voltage (g2) also comprises the second voltage (Ucont). [14] Method according to one of the preceding claims, wherein the sensor (31) is a temperature sensor, wherein the switching regulators (34) control a switching behavior of the gates of the respective power semiconductor chips (2) such that the junction temperatures of the power semiconductor chips (2) are all the same with a tolerance of at most 10 K. [15] Semiconductor module (10) comprising: - a plurality of power semiconductor components (1), wherein the power semiconductor components (1) are arranged next to one another as seen in plan view, and - a bus line (5) which connects all of the power semiconductor components (1) to one another, wherein - the semiconductor components (1) are configured to receive a superposition (g1) of a first voltage (Vg,bus) and a second voltage (Ucont), the superposition (g1) is provided by the bus line (5), and the first voltage (Vg,bus) is intended to control a current through the respective power semiconductor component (1) and the second voltage (Ucont) is intended to adjust a switching behavior of the respective power semiconductor component (1), - each of the power semiconductor components (1) is configured to demodulate control signals (Ucont) from the superposition (g1), so that the semiconductor module (10) is configured to carry out the method according to one of the preceding claims. [16] A method of manufacturing a semiconductor module (10) according to the preceding claim and configured for a method according to claim 2, the method comprising: - Providing the power semiconductor chips (2) and the logic units (3), - bonding a logic unit (3) to the associated power semiconductor chip (2), in particular by wafer bonding, - attaching a gate pad (4) above each logic unit (3), - mounting the power semiconductor components (1) on a common carrier (72), and - Connecting the gate pads (4) via the bus line (5).

Images