NUCLEAR ORDER AND ARCHITECTURE WITH BUS ARBITRATION BARRIER

Abstract

A production item includes a non-transitory, machine-readable medium. This medium contains instructions. When read and executed by a processor, these instructions cause the processor to identify a first input instruction in an executable code stream, determine that the first input instruction contains an atomic operation tag, and selectively block interrupts for the execution duration of the first input instruction and a second input instruction. The second input instruction is intended to immediately follow the first input instruction in the code stream.

Description

PRIORITY

[0001] This application claims priority over the preliminary US patent application No. 63 / 333,143 filed on April 21, 2022, the contents of which are hereby incorporated in full. AREA OF INVENTION

[0002] The present disclosure relates to processor instruction sets and in particular to an atomic instruction set and an atomic instruction architecture with bus arbitration lock. BACKGROUND

[0003] During instruction execution, processors running programs can interrupt these programs. Some processors use different operating modes, such as a "user" mode and a "supervisor" mode, where interrupts can only be selectively controlled or suppressed by entering supervisor mode. The inventors of examples in this disclosure have found that invoking such supervisor modes can increase latency and overhead and is unsuitable for embedded or real-time systems. Interrupts can cause the program's execution flow to be modified to address the interrupt. The inventors of examples in this disclosure have discovered that embedded systems can benefit from this, with some code segments operating without interrupts.An example of this is performing an operation that uses a two-byte or more write operation to fully address an I / O device. When the first byte is sent, an interrupt could change the execution flow, and the interrupt routine could write to the same device and output a different address. The device, which already contains the first address byte from before the interrupt, interprets the first byte of the interrupt routine as the second address byte of the original instruction sequence.

[0004] The inventors of examples in this disclosure have discovered that controlling interrupts in an embedded system can involve significant overhead. Furthermore, the inventors of examples in this disclosure have found that allowing user programs to control interrupts can be risky and may lead to both obvious and subtle errors. The inventors of examples in this disclosure have also found that some program latency can arise from the programming overhead involved in controlling system controls such as interrupts.

[0005] The inventors of examples of the present disclosure have demonstrated instruction sets and mechanisms for controlling interrupts and buses to solve one or more of the problems mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is an illustration of a system with an atomic instruction set and an architecture with interrupt and bus arbitration blocking, according to examples in the present disclosure. Fig. Figure 2 illustrates the further functioning of the system according to examples in the present disclosure. Fig. Figure 3 illustrates the further functioning of the system according to examples in the present disclosure. Fig. Figure 4 is an illustration of the operation of the system with an interrupt mask, according to the examples in the present disclosure. Fig. Figure 5 illustrates the more detailed operation of the system with an interrupt mask, according to examples in the present disclosure. Fig. Figure 6 is a more detailed illustration of the system for blocking buses and bus paths, according to examples in the present disclosure. Fig. Figure 7 is a further, more detailed illustration of the system for blocking buses and bus paths, according to examples in the present disclosure. Fig. Figure 8 is a further, more detailed illustration of the system for blocking buses, according to examples in the present disclosure. Fig. Figure 9 illustrates an exemplary procedure for selectively blocking interrupts according to examples in the present disclosure. Fig. Reference 10 is an illustration of an exemplary procedure for handling interrupts that are selectively blocked, according to examples in the present disclosure. Fig. Figure 11 illustrates another exemplary method for handling interrupts that are selectively blocked, according to examples in the present disclosure. Fig. Figure 12 is an illustration of an exemplary method for selectively blocking a bus or bus path, according to examples in the present disclosure. DETAILED DESCRIPTION

[0006] Fig. Figure 1 is an illustration of a System 100 with an atomic instruction set and an architecture with interrupt and bus arbitration lock, according to examples in the present disclosure.

[0007] System 100 can include a processor 102. The processor 102 can be implemented in any suitable way, for example, by a microcontroller or microprocessor. The processor 102 can be configured to load and execute instructions from any suitable source. The processor 102 can be configured to load and execute instructions using a suitable architecture or execution pipeline. The figures illustrated here show a simplified, conceptual representation of a possible architecture and execution pipeline. The processor 102 can be configured to operate according to suitable instructions, such as microcode, digital logic, or other suitable instructions. Such instructions can be implemented in a production item 104, such as a machine-readable medium, memory, or firmware. The production item 104 can be implemented as a separate device or as part of the processor 102.The production item 104 can define an instruction set that includes instructions which can be processed by the processor 102.

[0008] System 100 can contain a codestream 108. The codestream 108 can be implemented in any suitable way, for example, in memory or a production item. For instance, the codestream 108 can be implemented in the production item 104. The codestream 108 can contain instructions to be executed by the processor 102 to perform any operation. The codestream 108 can be object code, which is the result of compiling source code. The codestream 108 can also contain instructions defined by the instruction set of the production item 104.

[0009] Codestream 108 can contain any suitable number and type of instructions. In the example of Fig. Figure 1 shows a first input command 110 and a second input command 112, although additional input commands such as a third input command 114 (not shown) may be included.

[0010] Instructions in code stream 108, when executed by processor 102, can cause an interrupt or bus arbitration lock. Instructions in code stream 108 can include any suitable identifier indicating that the given instruction is to be executed atomically, selectively blocking interrupts or selectively locking buses during the execution of the given instruction. Furthermore, instructions in code stream 108 can include any suitable identifier indicating that an instruction immediately following the given instruction is to be executed atomically, selectively blocking interrupts or selectively locking buses during the execution of the instruction immediately following the given instruction.For example, instructions in code stream 108 can include an atomic operation (AO) flag, indicating that the instruction and the immediately following instruction should be executed atomically, without interrupts or while the buses used by the instruction are locked for use by other instructions. The AO flag can be assigned, for example, by a bit or a flag. The flagged instruction can include an opcode specifying another operation—the operation during which interrupts, buses, or bus paths are selectively locked. In another example, instructions to be assigned for such an AO operation can have a separate, special opcode for the other operation assigned as an AO operation. For example, a MOV instruction can be implemented in AO fashion with an AO flag or as a special opcode assigned to AO fashion, such as MOVAO.The commands may include any other suitable fields, such as initiator or target fields, or address mode fields.

[0011] In one example, a subset of the total number of possible instructions that processor 102 can execute can be assigned the described AO operation. For instance, the AO operation can be available for certain classes of instructions, but not for flow control instructions. Such flow control instructions may contain conditional branches. For example, instructions of type BRANCH, CALL, RETURN, and SOFTWARE INTERRUPT cannot be equipped with the AO operation. By not implementing the AO operation for these instructions, deadlock and system shortage problems can be avoided.

[0012] By allowing the AO operation to be specified for an instruction, multiple consecutive instructions can form an atomic execution sequence, where the instructions can be executed without interruption or program flow changes until the atomic execution sequence is complete. In various examples, there may be multiple layers or levels of interrupts, some of which may be allowed or disallowed depending on the AO operation.

[0013] Some systems provide operating system-level interrupt control through interrupt masking, where system-generated interrupts pass through an interrupt controller with a mask to determine whether the interrupt should be blocked or allowed to proceed. Some of these systems do not allow interrupt masking or blocking in a "user" mode, but only in a higher-priority mode such as "system," "supervisor," "privileged," or "admin" mode. Software often needs to issue a software interrupt to switch between user mode and one of these other modes to enable masking or selectively blocking interrupts that might otherwise alter the flow of a software program sequence. Implementing atomic operations at the instruction level can eliminate the need to switch user modes.Examples from this disclosure may eliminate the need to switch the operating mode (user to system or privileged) to control interrupt detection.

[0014] In one example, interrupts can be selectively blocked, and a bus or bus path used by an initiator and a target of the instruction can be locked, at least for the duration of the instruction's execution and the immediately following instruction, if the AO flag of a particular instruction is set to "true," either by a bit or by an inherent specification in the opcode. If the immediately following instruction is also assigned with an AO flag set to true, interrupts can be selectively blocked, and the bus or bus path used by the initiator and target of the instruction can be locked, at least for the duration of the instruction's execution, the immediately following instruction, and any further immediately following instruction. This can apply to as many consecutive instructions as are assigned with an AO flag set to true. This allows instructions to be grouped and executed as a single instruction.This eliminates the overhead that arises when executing a software interrupt to change the operating system mode multiple times and to suppress interrupts for a specific instruction sequence.

[0015] This process is in Fig. Figure 1 illustrates this. Processor 102 can read instructions from code stream 108. Processor 102 can read the first instruction INSTR1 110 in code stream 108. Processor 102 can identify INSTR1 110 at (1). At (2), processor 102 can recognize that INSTR1 110 is assigned as an AO instruction, for example, by an AO bit set to TRUE or by the inherent assignment of INSTR1 110. Fig. Figure 1 illustrates an execution time history. In (3), interrupts can be selectively blocked. The operations of (1), (2), and (3) can be performed before the execution of INSTR1 110, for example, during a load or other suitable pre-execution phase. In various examples, such a load or other suitable pre-execution phase can occur concurrently with the execution of a preceding instruction (not shown). Furthermore, the execution of INSTR1 110 can occur concurrently with such a load or other suitable pre-execution phase of a subsequent instruction such as INSTR2 112, although the execution of INSTR1 110 terminates before such a load or other suitable pre-execution phase of INSTR 112.

[0016] Interrupts can be selectively blocked for the duration of the execution of INSTR1 110 and the execution of the immediately following instruction, INSTR2 112. Furthermore, such selective blocking can occur at least for the duration of the execution of INSTR1 110 and the execution of the immediately following instruction, INSTR2 112, since the selective blocking of interrupts, depending on the AO status of INSTR2 112, can be further extended to the execution of additional instructions, as discussed below in the context of Fig. 2 will be explained in more detail.

[0017] Interrupts can be generated by any suitable part of System 100, in Fig. 1 is represented by system elements 120. The system elements 120 can include, for example, processor peripherals, software running on the processor 102, memory, memory controllers, or any suitable hardware. The system elements 120 that generate the interrupt can be located within the processor 102 itself. The processor 102 can be configured to block interrupts with a suitable setting, for example, by assigning AO to a specific instruction or subsequent instructions.

[0018] At (4) INSTR1 110 can be executed.

[0019] Fig. Figure 2 is an illustration of the further functioning of System 100 according to the examples in the present disclosure.

[0020] Processor 102 can read a second instruction INSTR2 112 in code stream 108. At (5), processor 102 can recognize that INSTR2 112 is assigned for AO operation, e.g., by an AO bit set to TRUE or by the inherent assignment of INSTR2 112. Fig. Figure 2 illustrates an execution timeline. In (6), interrupts can be selectively blocked. Interrupts can be selectively blocked at least for the duration of the execution of an instruction immediately following INSTR2 112, such as INSTR3 114. Interrupts can be selectively blocked for the duration of instructions following INSTR3 114, depending on whether INSTR3 114 includes an AO flag.

[0021] At (7) INSTR2 112 can be executed.

[0022] Fig. Figure 3 illustrates the further functioning of System 100 according to the examples in the present disclosure. Fig. Figure 3 shows an alternative operation as in Fig. 2, where INSTR2 112 is not assigned for AO operation, e.g., by an AO bit set to FALSE or by the inherent assignment of INSTR2 112. This can be detected at (5). At (6), interrupt blocking can be removed after the execution of INSTR2 112. Interrupt blocking can be resumed, but only if a subsequent instruction such as INSTR3 114 is assigned to operate in an AO manner.

[0023] At (7) INSTR2 112 can be executed.

[0024] Fig. Figure 4 illustrates the operation of system 100 with an interrupt mask 122 according to the examples in this disclosure. The interrupt mask 122 can be implemented in any suitable way, e.g., in memory, in a special function register, or in other suitable units. Access to the interrupt mask 122 can be performed by the processor 102 or any other suitable unit that performs interrupt blocking.

[0025] Interrupt mask 122 can be configured to define which interrupts can be affected by an AO flag and subsequent interrupt blocking. This means that even if interrupt blocking has been enabled, it can be overridden, allowing an interrupt to occur. The interrupt blocking can be overridden by a single instruction. It can be overridden by the interrupt's identifier or class. Or it can be overridden by a combination of the instruction and the interrupt's identity or class.

[0026] For example, instructions of type BRANCH, CALL, RETURN, and SOFTWARE INTERRUPT can mask some interrupts, but not high-priority or timeout interrupts. Other instructions may be able to mask all interrupts. In other examples, one and the same protected code segment of chained instructions with successive AO declarations can allow a program sequence to use different levels of interrupt masking without modifying the code segment through priority levels defined in interrupt mask 122.

[0027] In Fig. 4, at (8), an interrupt “INT1” can be generated by a system element 120. The processor 102, or an interrupt controller contained within it or communicatively coupled to the processor 102, can then compare the interrupt and any other suitable information with the information in the interrupt mask 122. Based on the information in the interrupt mask 122, which may include an evaluation of the interrupt or the instruction that blocked interrupts, the override of the AO at (10) can be allowed or denied. At (11), the processor 102 can either remove the interrupt blocking and allow INT1, or deny INT1 and maintain the execution of the instruction.

[0028] Fig. Figure 5 illustrates the more detailed operation of the system 100 with an interrupt mask 122, according to the examples in the present disclosure.

[0029] At (12) an interrupt such as “INTI” can be received from a system element 132 in the processor 102.

[0030] At (13) the processor 102 or an interrupt handler INT1 can compare with the interrupt mask 122.

[0031] Interrupt mask 122 can define different categories of interrupts. For example, interrupt mask 122 can define a first category of interrupts, referred to as CAT1 interrupts. These can include, for example, timeout interrupts. Such timeout interrupts can be generated by any suitable system element 132, for example, when attempting to use a system resource that is not responding. In another example, timeout interrupts can be generated by timers such as countdown timers when the defined timer period has expired. Interrupt mask 122 can define a second category of interrupts. Such a second category can include, for example, any category other than timeout interrupts. The second category can include, for example, memory interrupts, analog-to-digital conversion interrupts, digital-to-analog conversion interrupts, processor peripheral interrupts, or external interrupts.More categories can be used than are shown here. The list of categories can be presented in a priority order with respect to overriding interrupt blocking. Interrupts of the first category are allowed to override interrupt blocking, while interrupts of the second and lower categories can be prevented from overriding interrupt blocking.

[0032] In (14) the interrupt mask 122 can define that INT1 may override the AO and selective interrupt blocking, since it belongs to a first category of interrupts because it is a timeout interrupt.

[0033] At (15) the processor 102 or an interrupt handler can remove the selective interrupt blocking and allow the execution of INT1.

[0034] In (16), a second interrupt “INT2” can be generated by a system resource 132. INT2 can, for example, be an external interrupt.

[0035] In (17), INT2 can be compared with the contents of interrupt mask 122. Since INT2 belongs to the second category of interrupts (or a lower one), interrupt mask 122 in (18) can define that INT2 must not override AO and selective interrupt blocking.

[0036] In (19) the processor 102 or an interrupt handler can therefore maintain selective interrupt blocking and prohibit the execution of INT2.

[0037] Interrupt mask 122 and the ones in the Fig. The operational examples shown in 4-5 can also be applied to the bus or bus path lock, whereby the bus lock can be overridden for certain interrupts according to the interrupt priority.

[0038] Fig. Figure 6 is a more detailed illustration of System 100 for blocking buses and bus paths according to the examples in this disclosure. Buses can be blocked according to the same AO specification criteria described above for interrupt blocking.

[0039] Buses can be restricted, for example, according to specific bus routes. Fig. Figure 6 represents a bus path from an initiator, such as the processor (Figure 102), to a destination, such as a memory, read-only memory, bridge, microcontroller peripheral, or special function register bridge. System 100 can have multiple initiators (Figure 612), which may include elements such as processors, central processing units, direct memory access controllers, special function registers, controller area network controllers, or microcontroller peripherals. System 100 can have multiple destinations (Figure 606, Figure 610), which may include any suitable destination as described above.

[0040] A bus matrix 608, or bus structure, can be used to selectively route data communication paths, such as bus path 604, between a specific initiator and a specific destination in the system 100. The processor 102 can lock the specific bus path 604 between itself and a destination targeted in an instruction of the code stream 110, for its exclusive use with respect to other initiators, such as the initiators 612.

[0041] In (1), processor 102 can identify INSTR1 110, which is to be executed in code stream 108. In (2), processor 102 can indicate that INSTR1 110 contains an AO flag set to TRUE, such as an AO bit or inherently through the opcode of INSTR1 110.

[0042] In (3), processor 102 can determine that INSTR1 110 otherwise involves an access to a target 606 by an initiator 602. Such an access can involve a move, the storage of the result of a mathematical operation, or any other suitable access. The target 606 and the initiator 602 can be defined, for example, by the parameters used by INSTR1 110.

[0043] In (4), processor 102 can lock a bus path 604 between initiator 602 and destination 606. Other transmissions using bus path 604 can be redirected, or these other transmissions can be denied access to bus path 604. Typically, a bus or bus path can be locked only for the duration of the execution of a specific instruction. As in Fig. As shown in Figure 6, bus path 604 can be blocked for the duration of the execution of INSTR1 110 and INSTR2 112, based on the AO specification in INSTR1 110. Depending on the AO specification in INSTR2 112 (not shown), bus path 604 can also be blocked after the execution of INSTR2 112.

[0044] Fig. Figure 7 is a more detailed illustration of System 100 for locking buses or bus paths according to the examples in this disclosure. In (6), INSTR2 112 can be identified by Processor 102. In (7), INSTR2 112 can have an AO flag that is set to TRUE. In (8), bus path 604 can remain locked for the duration of an immediately following instruction such as INSTR3 114. In various examples, INSTR2 112 might not have the specification of initiator 602 and destination 606 that was included in INSTR1 110, but bus path 604 can still remain blocked during the execution of INSTR2 112. Furthermore, INSTR3 114 might not have the initiator 602 and target 606 identifier assigned in INSTR1 110, but the bus path 604 may still be blocked during the execution of INSTR3 114.

[0045] Fig. Figure 8 is a more detailed illustration of the system 100 for locking buses or bus paths according to the examples in this disclosure. In (6), INSTR2 112 can be flagged by the processor 102. In (7), INSTR2 112 can be identified as not having an AO flag assigned to TRUE and can be set to FALSE or simply not be present. In (8), bus path 604 can no longer be blocked after the execution of the INSTR2 112 instruction. In various examples, INSTR2 112 might not have the initiator 602 and target 606 specification that was included in INSTR1 110, but bus path 604 can still remain blocked during the execution of INSTR2 112. Bus path 604 can be locked starting with the execution of INSTR3 114, depending on which AO flag was assigned to INSTR3 114.

[0046] The blocking of bus path 604 can be carried out in any suitable way, e.g., by instruction from processor 102. The blocking of bus 605 can be carried out, e.g., by the control logic of processor 102. In addition, the blocking of bus path 604 can be exported or communicated to other elements (not shown) of system 100.

[0047] Accordingly, examples in this disclosure include an instruction set for a processor that enables the non-interrupted—that is, atomic—execution of groups of instructions. A per-instruction identifier, a bit, or some other specification can free the firmware from the need to manipulate the processor's interrupts to block interruptions in execution caused by entering or exiting modes. Such an assignment can eliminate the need to switch in and out of supervisor mode. Examples in this disclosure can provide blocking signals for bus structures to prevent instruction interleaving from other initiators (such as other processors, direct-access controllers, CAN controllers, etc.). Examples in this disclosure can enable the creation of complex instructions by continuously executing groups of instructions with an AO identifier.Examples from this disclosure can provide guaranteed timing for instruction groups. Examples from this disclosure can be used to prevent instruction nesting due to context switching. Examples from this disclosure can be restricted to a subset of possible instructions to prevent CPU hazards such as starvation or deadlock. Examples from this disclosure can be used when accessing internal or external hardware that requires seamless transactions, such as generating firmware for multi-phase interactions. Examples from this disclosure can be used to generate signal patterns or instructions that require consistent timing, such as bit-banging.Examples from this disclosure can be used to generate guaranteed sequential patterns where output data or addresses cannot be interrupted or nested with other commands.

[0048] Fig. Figures 9-12 are illustrations of exemplary procedures 900, 1000, 1100, and 1200 for selectively blocking interrupts and locking buses or bus paths, as shown in the examples in this disclosure. Procedures 900, 1000, 1100, and 1200 can be implemented by any suitable element, such as System 100 of the Fig. 1-8 or the processor 102 contained therein. Procedures 900, 1000, 1100, and 1200 can be executed with more or fewer steps than shown. Procedures 900, 1000, 1100, and 1200 can begin with any suitable step. The steps of procedures 900, 1000, 1100, and 1200 can be performed in any suitable order, including deviations from the order shown in the figures. The steps of procedures 900, 1000, 1100, and 1200 can optionally be repeated, omitted, executed in parallel, or recursively. Furthermore, procedures 900, 1000, 1100, and 1200 can be executed in parallel.

[0049] Fig. Figure 9 illustrates an exemplary method 900 for selectively blocking interrupts according to the examples in the present disclosure.

[0050] At 905, the first input command in a code stream to be executed can be identified.

[0051] At step 910, it can be determined whether the first input command includes an atomic operation. If the first input command includes an atomic operation flag, procedure 900 can proceed to 915. Otherwise, procedure 900 can continue to 925.

[0052] In procedure 915, interrupts can be selectively blocked for the duration of the execution of the first input instruction and a second input instruction. The second input instruction can immediately follow the first input instruction in the code stream. The first input instruction can be executed. Procedure 900 can be continued up to 930.

[0053] At 925, interrupts can be selectively blocked for the duration of the execution of the first input instruction. The first input instruction can then be executed. Procedure 900 can continue with 945.

[0054] Procedure 930 determines whether the second input command includes an atomic operation. If the second input command includes an atomic operation flag, procedure 900 can proceed to 935. Otherwise, procedure 900 can continue to 940.

[0055] In procedure 935, interrupts can still be selectively blocked for the duration of the execution of a third input instruction. The third input instruction can immediately follow the second input instruction in the code stream. The second input instruction can be executed. Procedure 900 can be continued up to 945.

[0056] At 940, the selective blocking of interrupts can be lifted after the execution of the second input instruction. The second input instruction. Procedure 900 can continue with 950.

[0057] At 945, the steps of 930, 935, and 940 can be performed for further input commands. Such a fourth input command can, for example, be evaluated in another instance of 930 for an atomic operation identifier, with the fourth input command immediately following the third input command in the code stream.

[0058] In procedure 950, which can be performed on any suitable part of procedure 900, the blocking of interrupts and the release of interrupts after execution can be performed without changing the operation between a first mode and a second mode of processor operation of the processor, the second mode being a more privileged mode than the first mode.

[0059] Fig. Figure 10 illustrates an exemplary procedure 1000 for handling interrupts that are selectively blocked, according to the examples in this disclosure. Procedure 1000 can be executed within the framework of procedure 900 whenever an interrupt is received while interrupts are selectively blocked.

[0060] In 1005, interrupts can be selectively blocked, e.g. by 915, 925, 935 or 940 in procedure 900.

[0061] At 1010, an interrupt can be received during selective blocking.

[0062] At 1015, the interrupt can be compared to an interrupt mask. The interrupt mask can specify whether the interrupt is allowed to interrupt an instruction assigned with an atomic operation. If so, procedure 1000 can continue with 1020. Otherwise, procedure 1000 can continue with 1025.

[0063] At 1020, the selective blocking of interrupts can be overridden, and the interrupt can be allowed to interrupt the executing instruction. Procedure 1000 can revert to 1005.

[0064] At 1025, selective interrupt disabling can be retained, preventing the interrupt from interrupting the executing instruction. Procedure 1000 can revert to 1005.

[0065] Fig. Figure 11 illustrates a further exemplary method 1100 for handling interrupts that are selectively blocked, according to the examples in this disclosure. Method 1100 can be performed within the framework of method 900 when an interrupt is received while interrupts are being selectively blocked.

[0066] At 1105, interrupts can be selectively blocked, e.g. by 915, 925, 935 or 940 in procedure 900.

[0067] At 1110, an interrupt can be received during selective blocking.

[0068] At 1115, the interrupt can be compared to an interrupt mask. The interrupt mask can contain categories of interrupts. These categories can include a first category and a second category. The first category can have a higher priority than the second category. The first category can, for example, include timeout interrupts. It can be determined whether the received interrupt falls into the first or second category. If the received interrupt belongs to the first category, procedure 1100 can continue with 1120. Otherwise, procedure 1100 can continue with 1125.

[0069] At 1120, the selective blocking of interrupts can be overridden, and the interrupt can be allowed to interrupt the executing instruction. Procedure 1100 can revert to 1105.

[0070] In procedure 1125, selective interrupt disabling can be retained, preventing the interrupt from interrupting the executing instruction. Procedure 1100 can revert to 1105.

[0071] Fig. Figure 12 illustrates an exemplary method 1200 for selectively blocking a bus or bus path according to the examples in this disclosure. Method 1200 can be used in conjunction with the methods of Fig. 9-11 are used to block interrupts.

[0072] At 1205, the first input instruction in an executable code stream can be identified. It can be determined that the input instruction involves accessing a target by an initiator, such as processor 102.

[0073] At step 1210, it can be determined whether the first input command includes an atomic operation label. If the first input command includes an atomic operation label, procedure 1200 can proceed to step 1215. Otherwise, procedure 900 can proceed to step 1220.

[0074] At 1215, a bus or bus path between the initiator and the destination can be locked for the duration of the execution of the first input instruction and a second input instruction. The second input instruction can immediately follow the first input instruction in the code stream. The first input instruction can be executed. Procedure 1200 can continue up to 1230.

[0075] At procedure 1220, a bus or bus path between the initiator and the destination can be locked for the duration of the execution of the first input command. The first input command can then be executed. Procedure 1200 can continue with procedure 1205.

[0076] At step 1230, it can be determined whether the second input command includes an atomic operation label. If the second input command includes an atomic operation label, procedure 1200 can proceed to step 1235. Otherwise, procedure 1200 can proceed to step 1240.

[0077] At 1235, the bus or bus path may remain locked for the duration of the execution of a third input instruction. The third input instruction may immediately follow the second input instruction in the code stream. The second input instruction may be executed. Procedure 1200 may continue until 1245.

[0078] At 1240, the selective blocking of interrupts can be lifted after the execution of the second input instruction. The second input instruction. Procedure 1200 can continue with 1205.

[0079] At 1245, the steps of 1230, 1235, and 1240 can be performed for further input commands. Such a fourth input command can, for example, be evaluated in another instance of 1230 for an atomic operation label, with the fourth input command immediately following the third input command in the code stream.

[0080] Examples of this disclosure may include a production article. The article may include a non-transitory machine-readable medium. The medium may contain instructions. When read and executed by a processor, the instructions may cause the processor to identify a first input instruction in a code stream to be executed. The instructions may cause the processor to determine that the first input instruction contains an atomic operation tag. Based on the determination that the first input instruction contains the atomic operation tag, the instructions may cause the processor to selectively block interrupts for the duration of the execution of the first input instruction and a second input instruction. The second input instruction may immediately follow the first input instruction in the code stream. The instructions may cause the processor to execute the first input instruction.The specification of the atomic operation can be assigned to the input command or be a parameter of the input command, such as a bit or a flag.

[0081] In combination with one of the examples above, the processor can determine that the second input instruction contains the atomic operation flag. Based on this determination, the processor can then proceed with the selective interrupt block for the duration of the execution of the second input instruction and a third input instruction. The third input instruction can immediately follow the second input instruction in the code stream. Alternatively, the processor can execute the second input instruction.

[0082] In combination with one of the above examples, the processor can determine that the second input instruction does not include the atomic operation flag, execute the second input instruction, and, based on the determination that the second input instruction does not include the atomic operation flag, remove the selective blocking of interrupts after the execution of the second input instruction.

[0083] In combination with one of the above examples, the processor can receive an interrupt, compare the identity of the interrupt with an interrupt mask, and, based on the finding that the comparison with the interrupt mask assigns that the interrupt should interrupt an instruction with the atomic operation tag, override the selective blocking of interrupts for the duration of the execution of the first input instruction and the second input instruction, and allow the interrupt.

[0084] In combination with one of the above examples, the processor can receive an interrupt, compare the interrupt's identity with an interrupt mask, and, based on the finding that the comparison with the interrupt mask indicates that the interrupt belongs to a first category of interrupts, override the selective blocking of interrupts for the duration of the execution of the first and second input instructions and allow the interrupt.

[0085] In combination with one of the examples above, the processor can also, based on the finding that the interrupt mask indicates it belongs to a second category of interrupts, selectively block interrupts for the duration of the execution of the first and second input instructions and block the interrupt. The first category of interrupts may have a higher priority than the second category of interrupts.

[0086] In combination with one of the examples above, the first category of interrupts can also include timeout interrupts.

[0087] In combination with one of the examples above, the processor can operate in a first mode and a second mode, with the second mode being a more privileged operating mode than the first. The processor can block interrupts for the duration of the execution of the first and second input instructions and release interrupts after the execution of the second input instruction without changing the operation between the first and second modes.

[0088] Examples of the present disclosure may include a production article. The article may include a non-transitory machine-readable medium. The medium may contain instructions. When read and executed by a processor, the instructions may cause the processor to identify a first input instruction in a code stream to be executed, determine that the first input instruction includes an atomic operation tag, determine that the first input instruction involves an initiator accessing a target, and, based on a determination that the first input instruction includes the atomic operation tag, lock a bus or bus path between the initiator and the target for the duration of the execution of the first input instruction and a second input instruction. The second input instruction may immediately follow the first input instruction in the code stream.The processor can be responsible for executing the first input instruction. The processor can be implemented in the same processor as in one of the examples mentioned above. The bus can be partially blocked by blocking a bus path between the initiator and the target on it.

[0089] In combination with one of the examples above, the processor can determine that the second input instruction contains the atomic operation flag and, based on this determination, continue selectively locking the bus or bus path between the initiator and the destination for the duration of the execution of the second input instruction and a third input instruction. The third input instruction can immediately follow the second input instruction in the code stream. In combination with one of the examples above, the processor can execute the second input instruction.

[0090] In combination with one of the examples above, the processor can determine that the second input instruction does not include the atomic operation flag and, based on this determination, release the selective lock on the bus or bus path between the initiator and the destination after the second input instruction has been executed. In combination with one of the examples above, the processor can then execute the second input instruction.

[0091] Although the examples above have been described, other variations and examples can be derived from this revelation without deviating from the spirit and scope of protection of these examples. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 333,143

[0001]

Claims

[1] A production article comprising a non-transitory, machine-readable medium, the medium comprising instructions, the instructions, when read and executed by a processor, causing the processor to: identify a first input instruction in a code stream to be executed; determine that the first input instruction contains an atomic operation identifier; based on the determination that the first input instruction includes the atomic operation identifier, selectively block interrupts for the duration of the execution of the first input instruction and a second input instruction, wherein the second input instruction immediately follows the first input instruction in the code stream; and to execute the first input command. [2] The article of claim 1, wherein the processor is arranged to: determine that the second input instruction contains the atomic operation identifier; based on the determination that the second input instruction includes the atomic operation identifier, continue the selective interrupt block for the duration of the execution of the second input instruction and a third input instruction, the third input instruction immediately following the second input instruction in the code stream; and to execute the second input command. [3] Article according to one of claims 1 to 2, wherein the processor is arranged to: determine that the second input instruction does not contain the atomic operation identifier; execute the second input command; and based on the determination that the second input instruction does not include the atomic operation designation, to remove the selective blocking of interrupts after the execution of the second input instruction. [4] Article according to one of claims 1 to 3, wherein the processor is arranged to: to receive an interrupt; to compare an interrupt identity with an interrupt mask; and based on a determination that the comparison with the interrupt mask indicates that the interrupt is intended to interrupt an instruction with the atomic operation designation, to override the selective blocking of interrupts for the duration of the execution of the first input instruction and the second input instruction and to allow the interrupt. [5] Article according to one of claims 1 to 4, wherein the processor is arranged to: to receive an interrupt; to compare an interrupt identity with an interrupt mask; based on a determination that the comparison with the interrupt mask indicates that the interrupt belongs to a first category of interrupts, to override the selective blocking of interrupts for the duration of the execution of the first input instruction and the second input instruction and to allow the interrupt; based on a determination that the comparison with the interrupt mask indicates that the interrupt belongs to a second category of interrupts, maintain the selective blocking of interrupts for the duration of the execution of the first input instruction and the second input instruction and block the interrupt; where the first category of interrupts has a higher priority than the second category of interrupts. [6] The article of claim 5, wherein the first category of interrupts includes timeout interrupts. [7] Article according to one of claims 1 to 6, wherein the processor is arranged to: to operate in a first mode and in a second mode, the second mode being a more privileged operating mode than the first mode; and To block interrupts for the duration of the execution of the first input instruction and the second input instruction and to enable interrupts after the execution of the second input instruction without changing operation between the first mode and the second mode. [8] A production article comprising a non-transitory, machine-readable medium, the medium comprising instructions, the instructions, when read and executed by a processor, causing the processor to: identify a first input instruction in a code stream to be executed; determine that the first input instruction contains an atomic operation identifier; determine that the first input command involves access by an initiator to a target; based on a determination that the first input instruction includes the atomic operation identifier, disabling a bus between the initiator and the target for a duration of the execution of the first input instruction and a second input instruction, wherein the second input instruction is to immediately follow the first input instruction in the code stream; and to execute the first input command. [9] Article according to claim 8, wherein the processor is arranged to: determine that the second input instruction contains the atomic operation identifier; based on the determination that the second input instruction includes the atomic operation designation, continue the selective disabling of the bus between the initiator and the target for the duration of the execution of the second input instruction and a third input instruction, wherein the third input instruction is to immediately follow the second input instruction in the code stream; and to execute the second input command. [10] Article according to one of claims 8 to 9, wherein the processor is arranged to: determine that the second input instruction does not contain the atomic operation identifier; based on the determination that the second input instruction does not include the atomic operation designation, release the selective lock on the bus between the initiator and the target after the execution of the second input instruction; and to execute the second input command. [11] Method comprising in a processor: identifying a first input instruction in a code stream to be executed; Determine that the first input instruction contains an atomic operation identifier; based on a determination that the first input instruction includes the atomic operation identifier, selectively blocking interrupts for an execution duration of the first input instruction and a second input instruction, wherein the second input instruction immediately follows the first input instruction in the code stream; and Execute the first input command. [12] A method according to claim 11, comprising: Determine that the second input command contains the atomic operation identifier; based on a determination that the second input instruction includes the atomic operation identifier, continuing to selectively block interrupts for an execution duration of the second input instruction and a third input instruction, the third input instruction immediately following the second input instruction in the code stream; and Execute the second input command. [13] A method according to any one of claims 11 to 12, comprising: Determine that the second input command does not contain the atomic operation identifier; based on a determination that the second input instruction does not include the atomic operation designation, discontinuing the selective blocking of interrupts after execution of the second input instruction; and Execute the second input command. [14] A method according to any one of claims 11 to 13, comprising: Receiving an interrupt; Comparing an identity of the interrupt with an interrupt mask; and based on a determination that the comparison with the interrupt mask indicates that the interrupt is to interrupt an instruction with the atomic operation designation, removing the selective blocking of interrupts for the duration of the execution of the first input instruction and the second input instruction, and allowing the interrupt. [15] A method according to any one of claims 11 to 14, comprising: Receiving an interrupt; Comparing an interrupt identity with an interrupt mask; Cancelling the selective blocking of interrupts for the duration of the execution of the first input instruction and the second input instruction and allowing the interrupt if the comparison with the interrupt mask indicates that the interrupt belongs to a first category of interrupts; and Maintaining selective blocking of interrupts for the duration of the execution of the first input instruction and the second input instruction and blocking the interrupt if the comparison with the interrupt mask indicates that the interrupt belongs to a second category of interrupts; where the first category of interrupts has a higher priority than the second category of interrupts. [16] The method of claim 15, wherein the first category of interrupts includes timeout interrupts. [17] A method according to any one of claims 11 to 16, wherein: the processor operates in a first mode and in a second mode, the second mode being a more privileged mode of operation than the first mode; and blocking interrupts for the duration of the execution of the first input command and the second input command and enabling interrupts after the execution of the second input command without changing the operation between the first mode and the second mode. [18] Method comprising: identifying a first input instruction in a code stream to be executed; Determine that the first input command involves an initiator accessing a target: Determine that the first input instruction contains an atomic operation identifier; based on a determination that the first input instruction includes the atomic operation identifier, disabling a bus between the initiator and the target for a duration of execution of the first input instruction and a second input instruction, the second input instruction immediately following the first input instruction in the code stream; and Execute the first input command. [19] A method according to claim 18, comprising: Determine that the second input command contains the atomic operation identifier; based on a determination that the second input instruction includes the atomic operation identifier, continuing to disable the bus between the initiator and the target for a duration of execution of the second input instruction and a third input instruction, the third input instruction immediately following the second input instruction in the code stream; and Execute the second input command. [20] A method according to any one of claims 18 to 19, comprising: Determine that the second input command does not contain the atomic operation identifier; based on a determination that the second input instruction does not include the atomic operation identifier, releasing a lock on the bus between the initiator and the target after execution of the second input instruction; and Execute the second input command.

Images