Semiconductor Device and Method for Manufacturing a Semiconductor Device

Abstract

A semiconductor device is provided comprising a semiconductor substrate with a chemical oxygen concentration of 1 × 1016 atoms / cm3 or more, comprising the volume donor and an elevated donor, a buffer region of a first conductivity type having a doping concentration higher than that of the drift region, and a thermal donor concentration that is 10% or less than the concentration of the elevated donor at the same depth position over an entire first region from a lower end of the buffer region to the deepest peak.

Description

BACKGROUND 1. TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. 2. STATE OF THE ART

[0002] A technique for forming a semiconductor device such as a transistor on a semiconductor substrate is known (see, for example, Patent Documents 1 and 2). State of the artPatent documents Patent Document 1: Specification of US Patent Application Publication No. 2020 / 0194550 Patent Document 2: Specification of US Patent Application Publication No. 2016 / 0329401 TASK TO BE SOLVED

[0003] In the semiconductor device, it is preferable to precisely control the doping concentration in the semiconductor substrate. GENERAL REVELATION

[0004] To achieve the above object, in the first aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate comprising an upper surface and a lower surface, a volume donor and a thermal donor, and having a chemical oxygen concentration of 1 × 10 16 atoms / cm 3or more. The semiconductor device may include a drift region of a first conductivity type disposed on the semiconductor substrate and comprising the bulk donor and the thermal donor. Each of the semiconductor devices described above may include a buffer region of a first conductivity type disposed between the drift region and the bottom surface of the semiconductor substrate, comprising the bulk donor and a raised donor, and having a doping concentration higher than that of the drift region. In each of the semiconductor devices described above, the buffer region may include one or more peaks of doping concentration in a depth direction of the semiconductor substrate.In each of the semiconductor devices described above, the one or more peaks of the doping concentration may include a deepest peak located farthest from the bottom surface of the semiconductor substrate. In each of the semiconductor devices described above, the enhanced donor may include the thermal donor. In each of the semiconductor devices described above, a concentration of the thermal donor may be 10% or less of a concentration of the enhanced donor at a same depth position over an entire first range from a bottom end of the buffer region to the deepest peak.

[0005] In any of the semiconductor devices described above, the elevated donor may comprise a CiOi-H donor.

[0006] In each of the semiconductor devices described above, a concentration of the thermal donor may be 1% or more of a concentration of the elevated donor at a same depth position throughout the entire first region.

[0007] In each of the semiconductor devices described above, a chemical oxygen concentration of the semiconductor substrate may be 1 × 10 17 atoms / cm 3 or more and 5 × 10 17 atoms / cm 3 or less.

[0008] In each of the semiconductor devices described above, a concentration of the thermal donor in the drift region may be equal to or less than 0.0001 times the chemical oxygen concentration.

[0009] In each of the semiconductor devices described above, a doping concentration of the drift region may be equal to or less than 1.5 times a concentration of the bulk donor.

[0010] In each of the semiconductor devices described above, a concentration of the thermal donor may be equal to or less than 0.1 times a doping concentration at a local maximum position of the lowest peak.

[0011] In each of the semiconductor devices described above, the buffer region may include a maximum peak among the other doping concentration peaks except the lowest peak at which a doping concentration is maximum. In each of the semiconductor devices described above, a thermal donor concentration may be equal to or less than 0.01 times a doping concentration at a local maximum position of the maximum peak.

[0012] In each of the semiconductor devices described above, the buffer region may include a shallowest peak closest to the bottom surface of the semiconductor substrate. In each of the semiconductor devices described above, a thermal donor concentration may be equal to or less than 0.001 times a doping concentration at a local maximum position of the shallowest peak.

[0013] In each of the semiconductor devices described above, in a region located on one side of the upper surface of the semiconductor substrate relative to the buffer region, a concentration distribution of the thermal donor may include a decreasing portion in which it decreases toward the upper surface of the semiconductor substrate.

[0014] In each of the semiconductor devices described above, the sensing portion may include a region in which a logarithmic gradient of a concentration of the thermal donor toward the upper surface side of the semiconductor substrate is equal to or greater than 0.5 times and equal to or less than 10 times a logarithmic gradient of the chemical oxygen concentration.

[0015] In the second aspect of the present invention, there is provided a manufacturing method for manufacturing a semiconductor device using a semiconductor substrate comprising an upper surface and a lower surface, a volume donor, and a chemical oxygen concentration of 1 × 10 16 atoms / cm 3or more. The semiconductor device may include a drift region of a first conductivity type disposed on the semiconductor substrate and comprising the bulk donor and the thermal donor. The semiconductor device may include a buffer region of a first conductivity type disposed between the drift region and the bottom surface of the semiconductor substrate, comprising the bulk donor and a raised donor, and having a doping concentration higher than that of the drift region. In each of the semiconductor devices described above, the buffer region may include one or more peaks of doping concentration in a depth direction of the semiconductor substrate. In each of the semiconductor devices described above, the one or more peaks of doping concentration may include a deepest peak located farthest from the bottom surface of the semiconductor substrate.In any of the semiconductor devices described above, the enhanced donor may include the thermal donor. The manufacturing method may anneal the semiconductor substrate such that a concentration of the thermal donor is 10% or less of a concentration of the enhanced donor at a same depth position across an entire first region from a lower end of the buffer region to the deepest peak.

[0016] In each of the manufacturing methods described above, in each process for annealing the semiconductor substrate, a time period during which a temperature of the semiconductor substrate passes through a temperature range of 400 °C or more and 500 °C or less may be 20 minutes or less per pass.

[0017] In each of the manufacturing methods described above, in each process for annealing the semiconductor substrate, a time period during which a temperature of the semiconductor substrate passes through a temperature range of 425 °C or more and 475 °C or less may be 10 minutes or less per pass.

[0018] In each of the manufacturing methods described above, an accumulated period of periods during which a temperature of the semiconductor substrate passes through a temperature range of 400 °C or more and 500 °C or less in each process for annealing the semiconductor substrate may be 120 minutes or less.

[0019] In each of the manufacturing methods described above, an accumulated period of periods during which a temperature of the semiconductor substrate passes through a temperature range of 425 °C or more and 475 °C or less in each process for annealing the semiconductor substrate may be 60 minutes or less.

[0020] In each of the manufacturing processes described above, a metal electrode can be formed over the top surface of the semiconductor substrate. In each of the manufacturing processes described above, a process is performed at less than 400 °C after the metal electrode is formed.

[0021] The summary section does not necessarily describe all necessary features of the embodiments of the present invention. The invention may also include a subcombination of the features described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. Figure 2 illustrates an enlarged view of an area D in Fig. 1. Fig. Figure 3 illustrates an example of a cross section ee in Fig. 2. Fig. Figure 4 illustrates a reference example of a distribution 210 of doping concentrations on the line ff of Fig. 3. Fig. 5 illustrates a distribution 210 of doping concentrations according to the example. Fig. 6 illustrates an example of a distribution of the chemical oxygen concentration and a distribution of the thermal donor concentration in a region on the upper surface 21 side relative to the buffer region 20 (a region from a depth position Zb to a depth position Zu). Fig. 7 is a flowchart describing an example of a manufacturing method of the semiconductor device 100. Fig. 8 illustrates an exemplary temporal change in the temperature of the semiconductor substrate 10 in each annealing step. Fig. 9 is a flowchart showing a more detailed example of the manufacturing method of the semiconductor device 100. Fig. 10 is a flowchart showing operations similar to those of Fig. 9 follow. DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0022] The invention will be described below using specific embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are essential to the solution of the invention.

[0023] As used herein, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as the "upper" side, and the other side is referred to as the "lower." One of two main surfaces of a substrate, layer, or other element is referred to as an upper surface, and the other surface is referred to as a lower surface. "Upper" and "lower" directions are not limited to a direction of gravity or a direction in which a semiconductor device is mounted.

[0024] In this specification, technical matters may be described using orthogonal coordinate axes of an X-axis, a Y-axis, and a Z-axis. The orthogonal coordinate axes merely specify relative positions of components and do not restrict a specific direction. For example, the Z-axis is not limited to indicating the height direction relative to the ground. Note that a +Z-axis direction and a -Z-axis direction are opposite directions. When the Z-axis direction is described without describing the symbols, it means that the direction is parallel to the +Z-axis and the -Z-axis.

[0025] In this specification, orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are referred to as the X-axis and the Y-axis. Further, an axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is referred to as the Z-axis. In this specification, the Z-axis direction may be referred to as the depth direction. Further, in this specification, a direction parallel to the upper surface and the lower surface of the semiconductor substrate may be referred to as a horizontal direction, including an X-axis direction and a Y-axis direction.

[0026] A region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as an upper surface side. Similarly, a region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as a lower surface side.

[0027] In this specification, a case where a term such as "same" or "equal" is mentioned may include a case where an error is included due to a manufacturing change or the like. The error is, for example, within 10%.

[0028] In this specification, the conductivity type of a doping region in which an impurity has been doped is described as P-type or N-type. In this specification, the impurity may specifically mean either an N-type donor or a P-type acceptor and may be described as a dopant. In this specification, doping means introducing the donor or acceptor into the semiconductor substrate and converting it into a semiconductor having an N-type conductivity type or a semiconductor having a P-type conductivity type.

[0029] In this specification, a doping concentration refers to a concentration of the donor or an acceptor concentration in a thermal equilibrium state. In this specification, a net doping concentration refers to a net concentration obtained by adding the donor concentration, which is set as a positive ion concentration, to the acceptor concentration, which is set as a negative ion concentration, taking charge polarities into account. For example, if the donor concentration N D and the acceptor concentration N A is the net doping concentration at any position as N D - N A In this specification, the net doping concentration may simply be referred to as the doping concentration.

[0030] The donor has a function of supplying electrons to a semiconductor. The acceptor has a function of receiving electrons from the semiconductor. The donor and acceptor are not limited to the defects themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in the semiconductor, serves as the donor that supplies electrons. The hydrogen donor can be a donor obtained by combining at least one vacancy (V) and hydrogen (H). Alternatively, interstitial Si-H, in which interstitial silicon (Si-i) in a silicon semiconductor is bonded to hydrogen, and CiOi-H, in which interstitial carbon (Ci) is bonded to interstitial oxygen (Oi) and hydrogen, also serve as a donor that supplies electrons.In the present description, the VOH defect, the CiOi-H or the interstitial Si-H may be referred to as the hydrogen donor.

[0031] In the semiconductor substrate of the present description, N-type volume donors are distributed throughout. The volume donor is a dopant donor that is substantially uniformly contained in an ingot during the production of the ingot from which the semiconductor substrate is made. The volume donor of this example is an element other than hydrogen. The dopant donor of the volume donor is, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but the invention is not limited to these. The volume donor of this example is phosphorus. The volume donor is also contained in a P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot or may be a chip obtained by dicing the wafer.The semiconductor ingot can be manufactured using either a Czochralski process (CZ process), a Czochralski process with applied magnetic field (MCZ process), or a float zone process (FZ process). The ingot in this example is manufactured using the MCZ process. The oxygen concentration contained in the substrate manufactured using the MCZ process is 1 × 10-6. 17 up to 7 × 10 17 / cm 3 . The oxygen concentration contained in the substrate produced by the FZ process is 1 × 10 16 up to 5 × 10 16 / cm 3When the oxygen concentration is high, hydrogen donors tend to be easily generated. The concentration of the volume donor can use a chemical concentration of volume donors distributed throughout the semiconductor substrate, or it can be a value between 90% and 100% of the chemical concentration. Furthermore, an undoped substrate that does not contain a dopant such as phosphorus can be used as the semiconductor substrate. In this case, the concentration (D0) of the volume donor of the undoped substrate is, for example, 1 × 10 10 / cm 3 or more and 5 × 10 12 / cm 3 or less. The concentration (D0) of the volume donor of the undoped substrate is preferably 1 × 10 11 / cm 3 or more. The concentration (D0) of the volume donor of the undoped substrate is preferably 5 × 10 12 / cm 3or less. Each concentration in the present invention may be a value at room temperature. As an example, a value at 300 K (Kelvin) (about 26.9 degrees C) may be used as the value at room temperature.

[0032] In this specification, P + -like or N + -type has a higher doping concentration than that of P-type or N-type, and P - -like or N - -type means a lower doping concentration than that of P-type or N-type. Furthermore, in the description, P ++ -like or N ++ -like a higher doping concentration than that of P + -like or N + -like. In the description, a system of units is the SI base unit system unless otherwise stated. Although a unit of length is represented using cm, it can be converted to meters (m) before calculations.

[0033] A chemical concentration in the present specification indicates an atomic density of an impurity, which is measured independently of an electrical activation state. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance profiling (CV profiling). Furthermore, a carrier concentration measured by spreading resistance profiling (SRP) can be set as the net doping concentration. The carrier concentration measured by the CV profiling or the SRP method can be a value in a thermal equilibrium state. Furthermore, in an N-type region, the donor concentration is sufficiently higher than the acceptor concentration, and thus the carrier concentration of the region can be set as the donor concentration.Similarly, in a P-type region, the carrier concentration of the region can be set as the acceptor concentration. In this specification, the doping concentration of the N-type region can be referred to as the donor concentration, and the doping concentration of the P-type region can be referred to as the acceptor concentration.

[0034] When a concentration distribution of donor, acceptor, or net doping has a peak in a region, a value of the peak may be set as the concentration of donor, acceptor, or net doping in the region. In a case where the concentration of donor, acceptor, or net doping is substantially uniform in a region, or the like, an average value of the concentration of donor, acceptor, or net doping in the region may be set as the concentration of donor, acceptor, or net doping. In the present specification, atoms / cm 3 or / cm 3 Used to indicate a concentration per unit volume. This unit is used for the concentration of a donor or acceptor in a semiconductor substrate, or for a chemical concentration. Atoms may be omitted.

[0035] The carrier concentration measured by the SRP method may be lower than the concentration of the donor or acceptor. In a region where a current flows, when measuring a spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in a crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to a disruption of the crystal structure caused by a lattice defect or the like.

[0036] The concentration of the donor or acceptor calculated from the carrier concentration measured by CV profiling or the SRP method may be lower than the chemical concentration of an element indicative of the donor or acceptor. For example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic, which serves as a donor, or the acceptor concentration of boron, which serves as an acceptor, is approximately 99% of their chemical concentrations. On the other hand, in the silicon semiconductor, the donor concentration of hydrogen, which serves as a donor, is approximately 0.1% to 10% of the chemical concentration of hydrogen.

[0037] Fig. 1 illustrates a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows a position where each element is projected onto an upper surface of a semiconductor substrate 10. Fig. 1 shows only some elements of the semiconductor device 100 and omits illustrations of some elements.

[0038] The semiconductor device 100 includes the semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed from a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has one end face 162 in a plan view. When referred to simply as the plan view in the present description, this means that the semiconductor substrate 10 is viewed from a top surface side. The semiconductor substrate 10, in this example, has two sets of end faces 162 that are opposite each other in a plan view. Fig. 1, the X-axis and the Y-axis are parallel to any one of the end faces 162. Furthermore, the Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0039] The semiconductor substrate 10 is provided with an active portion 160. The active portion 160 is a region in which a main current flows in a depth direction between the upper surface and a lower surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode is provided above the active portion 160, but is in Fig. 1 is omitted. The active portion 160 may refer to a region that overlaps with the emitter electrode in a plan view. Furthermore, a region located between active portions 160 in a plan view may also be included in the active portion 160.

[0040] The active section 160 is provided with at least one of a transistor section 70 containing a transistor element such as an insulated gate bipolar transistor (IGBT), and a diode section 80 containing a diode element such as a freewheeling diode (FWD). Fig. In the example shown in Figure 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse conducting IGBT (RC-IGBT).

[0041] In Fig. 1, a region in which each of the transistor sections 70 is arranged is indicated by a symbol "I", and a region in which each of the diode sections 80 is arranged is indicated by a symbol "F". In the present description, a direction perpendicular to the arrangement direction in the plan view may be referred to as an extension direction (the Y-axis direction in Fig. 1). Each of the transistor sections 70 and the diode sections 80 may have a longitudinal length in the extension direction. In other words, the length of each of the transistor sections 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of each of the diode sections 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 and the longitudinal direction of each trench section described below may be the same.

[0042] Each of the diode sections 80 comprises an N + -like cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In the present description, a region in which the cathode region is provided is referred to as the diode portion 80. In other words, the diode portion 80 is a region that overlaps with the cathode region in plan view. On the lower surface of the semiconductor substrate 10, a P + -like collector region may be provided in a region other than the cathode region. In the description, the diode section 80 may also include an extension region 81 in which the diode section 80 extends to a gate rotor described below in the Y-axis direction. The collector region is provided on a lower surface of the extension region 81.

[0043] The transistor section 70 has the P +-type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Further, in the transistor section 70, an N-type emitter region, a P-type base region, and a gate structure including a gate line portion and a gate dielectric film are periodically arranged on the upper surface side of the semiconductor substrate 10.

[0044] The semiconductor device 100 may include one or more arrays above the semiconductor substrate 10. The semiconductor device 100 of this example includes a gate array 164. The semiconductor device 100 may include arrays such as an anode array, a cathode array, and a current detection array. Each array is arranged in a region near the end face 162. The region near the end face 162 refers to a region between the end face 162 and the emitter electrode in plan view. When the semiconductor device 100 is mounted, each array may be connected to an external circuit via wiring such as a wire.

[0045] A gate potential is applied to the gate array 164. The gate array 164 is electrically connected to a conductive portion of a gate trench portion of the active portion 160. The semiconductor device 100 includes a gate runner connecting the gate array 164 and the gate trench portion. Fig. 1 the gate runner is hatched with diagonal lines.

[0046] The gate runner of the present example includes an outer peripheral gate runner 130 and an active-side gate runner 131. The outer peripheral gate runner 130 is disposed between the active portion 160 and the end face 162 of the semiconductor substrate 10 in a plan view. In this example, the outer peripheral gate runner 130 encloses the active portion 160 in a plan view. A region enclosed by the outer peripheral gate runner 130 in a plan view can be defined as the active portion 160. Furthermore, a well region is formed under the gate runner. The well region is a P-type region with a higher concentration than the base region described below and is formed to a position deeper than a position of the base region from the upper surface of the semiconductor substrate 10. An area enclosed by the tub area in a plan view may be the active portion 160.

[0047] An outer peripheral gate runner 130 is connected to the gate array 164. The outer peripheral gate runner 130 is disposed above the semiconductor substrate 10. The outer peripheral gate runner 130 may be a metal wiring including aluminum or the like.

[0048] The active-side gate runner 131 is provided in the active portion 160. Providing the active-side gate runner 131 in the active portion 160 can reduce variation in a wiring line length from the gate array 164 for each region of the semiconductor substrate 10.

[0049] The outer peripheral gate runners 130 and the active-side gate runner 131 are connected to the gate trench portion of the active section 160. The outer peripheral gate runners 130 and the active-side gate runner 131 are arranged above the semiconductor substrate 10. The outer peripheral gate runner 130 and the active-side gate runner 131 may be a wiring formed from a semiconductor, such as polysilicon doped with an impurity.

[0050] The active-side gate runner 131 may be connected to the outer-circumferential gate runner 130. The active-side gate runner 131 of this example is provided to extend in the X-axis direction to cross the active portion 160 from one outer-circumferential gate runner 130 to the other outer-circumferential gate runner 130 substantially at the center of the Y-axis direction, with the outer-circumferential gate runner 130 enclosing the active portion 160. When the active portion 160 is divided by the active-side gate runner 131, the transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction in each divided region.

[0051] The semiconductor device 100 may include a temperature sensing portion (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detecting portion (not shown) that simulates an operation of the transistor portion provided in the active portion 160.

[0052] The semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the end face 162 in plan view. The edge termination structure portion 90 of this example is arranged between the outer peripheral gate rotor 130 and the end face 162. The edge termination structure portion 90 reduces an electric field strength on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 may include a guard ring, a field plate, and / or a RESURF provided in a ring shape to enclose the active portion 160.

[0053] Fig. Figure 2 illustrates an enlarged view of an area D in Fig. 1. Region D is a region including the transistor portion 70, the diode portion 80, and the active-side gate slider 131. The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided within the upper surface side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of the trench portion. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and the active-side gate slider 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate slider 131 are provided insulated from each other.

[0054] An interlayer dielectric film is provided between the emitter electrode 52 and the active-side gate rotor 131 and the upper surface of the semiconductor substrate 10, but the interlayer dielectric film is in Fig. 2 is omitted. In the interlayer dielectric film of this example, a contact hole 54 is provided which passes through the interlayer dielectric film. In Fig. 2, each contact hole 54 is hatched with the diagonal lines.

[0055] The emitter electrode 52 is provided on top of the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is in contact with the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. Further, the emitter electrode 52 is connected to a dummy wiring portion in the dummy trench portion 30 through the contact hole provided in the interlayer dielectric film. The emitter electrode 52 may be connected to the dummy wiring portion of the dummy trench portion 30 at an edge of the dummy trench portion 30 in the Y-axis direction.The dummy wiring portions of the dummy trench portions 30 may not be connected to the emitter electrode 52 and a gate wiring portion, and may be controlled to be at a potential different from a potential of the emitter electrode 52 and a potential of the gate wiring portion.

[0056] The active-side gate runner 131 is connected to the gate trench portion 40 through the contact hole provided in the interlayer dielectric film. The active-side gate runner 131 may be connected to a gate line portion of the gate trench portion 40 at an edge portion 41 of the gate trench portion 40 in the Y-axis direction. The active-side gate runner 131 is not connected to the dummy line portion in the dummy trench portion 30.

[0057] The emitter electrode 52 is formed of a material including a metal. Fig. 2 shows a region where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy, for example, a metal alloy such as AlSi, AlSiCu. The emitter electrode 52 may include a barrier metal formed of titanium, a titanium compound, or the like under a region formed of aluminum or the like. Further, a plug formed by embedding tungsten or the like to be in contact with the barrier metal and aluminum or the like may be included in the contact hole.

[0058] The well region 11 is provided overlapping the active-side gate slider 131. The well region 11 is provided to extend with a predetermined width even in a region that does not overlap the active-side gate slider 131. The well region 11 of this example is provided away from one end of the contact hole 54 in the Y-axis direction to the side of the active-side gate slider 131. The well region 11 is a region of a second conductivity type in which the doping concentration is higher than that of the base region 14. The base region 14 of this example is P--type, and the well region 11 is P + -like.

[0059] Each of the transistor section 70 and the diode section 80 includes a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are provided alternately along the arrangement direction. In the diode section 80 of this example, the plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, the gate trench section 40 is not provided.

[0060] The gate trench portion 40 of this example may include two straight portions 39 extending along the extension direction perpendicular to the arrangement direction (portions of a trench that are straight along the extension direction), and the edge portion 41 connecting the two straight portions 39. The extension direction in Fig. 2 is the Y-axis direction.

[0061] At least a portion of the edge portion 41 is desirably provided in a curved shape in a plan view. By connecting the end portions of the two straight portions 39 in the Y-axis direction through the edge portion 41, it is possible to reduce the electric field strength at the end portions of the straight portions 39.

[0062] In the transistor section 70, the dummy trench sections 30 are provided between the respective straight sections 39 of the gate trench sections 40. Between the respective straight sections 39, one dummy trench section 30 may be provided, or a plurality of dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight shape extending in the extension direction, or it may have straight sections 29 and an edge section 31 similar to the gate trench section 40. The Fig. The semiconductor device 100 shown in Fig. 2 includes both the straight dummy trench portion 30 having no edge portion 31 and the dummy trench portion 30 having the edge portion 31.

[0063] A diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The end portions in the Y-axis direction of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 in a plan view. In other words, the bottom in the depth direction of each trench portion is covered with the well region 11 at the end portion in the Y-axis direction of each trench portion. With this configuration, the electric field strength at the bottom portion of each trench portion can be reduced.

[0064] A mesa portion is provided between the respective trench portions in the arrangement direction. The mesa portion refers to a region located between the trench portions within the semiconductor substrate 10. As an example, an upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion of this example is provided to extend in the extension direction (the Y-axis direction) along the trench portion on the upper surface of the semiconductor substrate 10. In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80.In the event that the present description simply mentions “mesa section,” the section refers to the mesa section 60 and the mesa section 61, respectively.

[0065] Each mesa section is provided with the base region 14. In the mesa section, a region located closest to the active-side gate slider 131 in the base region 14 exposed on the upper surface of the semiconductor substrate 10 is to be a base region 14-e. Fig. While Fig. 2 shows the base region 14-e arranged at one end portion of each mesa portion in the extension direction, the base region 14-e is also arranged at the other end portion of each mesa portion. Each mesa portion may be provided with at least one of a first conductivity type of the emitter region 12 and a second conductivity type of the contact region 15 in a region located between the base regions 14-e in plan view. The emitter region 12 of this example is N + -like, and the contact area 15 is P + -like. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0066] The mesa portion 60 of the transistor portion 70 includes the emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with the contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0067] Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact region 15 and the emitter region 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portion (the Y-axis direction).

[0068] In another example, the contact region 15 and the emitter region 12 may be provided in the mesa portion 60 in a stripe shape along the extension direction of the trench portion (the Y-axis direction). For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region located between the emitter regions 12.

[0069] The mesa portion 61 of the diode portion 80 is not provided with the emitter region 12. The base region 14 and the contact region 15 may be provided on an upper surface of the mesa portion 61. In the region located between the base regions 14-e on the upper surface of the mesa portion 61, the contact region 15 may be provided in contact with each base region 14-e. The base region 14 may be provided in a region located between the contact regions 15 on the upper surface of the mesa portion 61. The base region 14 may be arranged in the entire region located between the contact regions 15.

[0070] The contact hole 54 is provided above each mesa portion. The contact hole 54 is located in the region located between the base regions 14-e. The contact hole 54 of this example is provided above respective regions of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in regions corresponding to the base region 14-e and the well region 11. The contact hole 54 may be located at the center of the mesa portion 60 in the arrangement direction (the X-axis direction).

[0071] In the diode section 80 there is an N + -like cathode region 82 is provided in a region in direct contact with the lower surface of the semiconductor substrate 10. On the lower surface of the semiconductor substrate 10, a P +-like collector region 22 may be arranged in a region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between a lower surface 23 of the semiconductor substrate 10 and a buffer region 20. In Fig. 2, a boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0072] The cathode region 82 is located away from the well region 11 in the Y-axis direction. With this configuration, the distance between the P-type region (the well region 11), which has a relatively high doping concentration and is formed to the deep position, and the cathode region 82 is ensured, so that the breakdown voltage can be improved. The end portion in the Y-axis direction of the cathode region 82 of this example is located farther from the well region 11 than the end portion in the Y-axis direction of the contact hole 54. In another example, the end portion in the Y-axis direction of the cathode region 82 may be located between the well region 11 and the contact hole 54.

[0073] Fig. Figure 3 illustrates an example of a cross section ee in Fig. 2. The cross section ee is the XZ plane passing through an emitter region 12 and a cathode region 82. A semiconductor device 100 in this example includes a semiconductor substrate 10, an interlayer dielectric film 38, an emitter electrode 52, and a collector electrode 24 in cross section.

[0074] The interlayer dielectric film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer dielectric film 38 is a film including at least one layer of a dielectric film such as silicate glass to which an impurity such as boron or phosphorus is added, a thermal oxide film, and other dielectric films. The interlayer dielectric film 38 is coated with the Fig. 2 described contact hole 54 is provided.

[0075] The emitter electrode 52 is provided on top of the interlayer dielectric film 38. The emitter electrode 52 is in contact with an upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer dielectric film 38. The collector electrode 24 is provided on a lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In the description, the direction in which the emitter electrode 52 is connected to the collector electrode 24 (the Z-axis direction) is referred to as a depth direction.

[0076] The semiconductor substrate 10 includes an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0077] In the mesa section 60 of the transistor section 70, an N +-like emitter region 12 and a P - -like base region 14 is arranged in order from one side of the upper surface 21 of the semiconductor substrate 10. The drift region 18 is provided under the base region 14. The mesa section 60 may have an N + -like collection region 16. The collection region 16 is arranged between the base region 14 and the drift region 18.

[0078] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0079] The base region 14 is provided below the emitter region 12. The base region 14 of this example is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0080] The collection area 16 is provided below the base area 14. The collection area 16 is an N + -like region with a higher doping concentration than the drift region 18. That is, the collection region 16 has a higher donor concentration than the drift region 18. By providing the collection region 16 with the high concentration between the drift region 18 and the base region 14, it is possible to improve a carrier injection enhancement (IE) effect and reduce a turn-on voltage. The collection region 16 can be provided to cover an entire lower surface of the base region 14 in each mesa section 60.

[0081] The mesa section 61 of the diode section 80 is connected to the P - -like base region 14 is arranged in contact with the upper surface 21 of the semiconductor substrate 10. The drift region 18 is provided below the base region 14. In the mesa section 61, the collection region 16 can be arranged below the base region 14.

[0082] In each transistor section 70 and diode section 80, an N +-type buffer region 20 may be arranged below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak that has a higher doping concentration than the doping concentration of the drift region 18. The doping concentration of the concentration peak indicates a doping concentration at the local maximum of the concentration peak. Furthermore, an average value of doping concentrations in the region where the doping concentration distribution is substantially flat may be used as the doping concentration of the drift region 18.

[0083] The buffer region 20, in this example, may have two or more concentration peaks in the depth direction (the Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be provided at the same depth position, such as a peak of the chemical concentration of hydrogen (a proton) or phosphorus. The buffer region 20 may function as a field stopper layer that prevents a depletion layer extending from the lower end of the base region 14 from affecting the P + -like collector area 22 and the N + -like cathode region 82 is reached.

[0084] In the transistor section 70, the P +-like collector region 22 is arranged below the buffer region 20. An acceptor concentration of the collector region 22 is higher than an acceptor concentration of the base region 14. The collector region 22 may include an acceptor that is the same as or different from an acceptor of the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0085] Under the buffer region 20 in the diode section 80 is the N +-like cathode region 82 is arranged. A donor concentration of the cathode region 82 is higher than a donor concentration of the drift region 18. A donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that an element serving as a donor and an acceptor in each region is not limited to the above-described example. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0086] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each of the trench portions is provided from the upper surface 21 of the semiconductor substrate 10 through the base region 14 to below the base region 14. In a region where at least one of the emitter region 12, the contact region 15, and the collection region 16 is provided, each trench portion also penetrates the impurity regions thereof. The configuration of the trench portion penetrating the impurity region is not limited to that formed in the order of forming the impurity region and then forming the trench portion. The configuration of the trench portions penetrating the impurity region also includes a configuration of forming the trench portions and then forming the impurity region between the trench portions.

[0087] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. In the diode section 80, the dummy trench section 30 is provided, and the gate trench section 40 is not provided. The boundary in the X-axis direction between the diode section 80 and the transistor section 70 is the boundary between the cathode region 82 and the collector region 22 in this example.

[0088] The gate trench portion 40 includes a gate trench provided in the upper surface 21 of the semiconductor substrate 10, a gate dielectric film 42, and a gate line portion 44. The gate dielectric film 42 is provided to cover the inner wall of the gate trench. The gate dielectric film 42 can be formed by oxidizing or nitriding a semiconductor on the inner wall of the gate trench. The gate line portion 44 is provided within the gate dielectric film 42 in the gate trench. That is, the gate dielectric film 42 insulates the gate line portion 44 from the semiconductor substrate 10. The gate line portion 44 is formed of a conductive material such as polysilicon.

[0089] The gate line section 44 may be provided longer than the base region 14 in the depth direction. The gate trench section 40 in cross section is covered by the interlayer dielectric film 38 on the upper surface 21 of the semiconductor substrate 10. The gate line section 44 is electrically connected to the gate rotor. When a predetermined gate voltage is applied to the gate line section 44, a channel is formed by an electron inversion layer in a surface layer of the base region 14 at a boundary in contact with the gate trench section 40.

[0090] The dummy trench portions 30 may have the same structure as the gate trench portions 40 in cross section. The dummy trench portion 30 includes a dummy trench provided in the upper surface 21 of the semiconductor substrate 10, a dummy dielectric film 32, and a dummy wiring portion 34. The dummy wiring portion 34 is electrically connected to the emitter electrode 52. The dummy dielectric film 32 is provided to cover an inner wall of the dummy trench. The dummy wiring portion 34 is provided in the dummy trench and is provided within the dummy dielectric film 32. The dielectric dummy film 32 insulates the dummy line portion 34 from the semiconductor substrate 10. The dummy line portion 34 may be formed from the same material as the gate line portion 44. For example, the dummy line portion 34 is formed from a conductive material such as polysilicon or the like.The dummy line section 34 may have the same length as the gate line section 44 in the depth direction.

[0091] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered with the interlayer dielectric film 38 on the upper surface 21 of the semiconductor substrate 10. Note that the bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be formed convexly downward in a curved surface shape (a curved shape in cross section).

[0092] Fig. Figure 4 illustrates a reference example of a distribution 210 of doping concentrations on the line ff of Fig. 3. In the graphs, such as Fig. 4, of concentration distributions, a carrier concentration measured by the SRP method or the like is represented as the doping concentration. The line ff is a line parallel to the Z-axis passing through the buffer region 20. A horizontal axis in Fig. 4 shows a depth position (a position in the Z-axis direction) in the semiconductor substrate 10. In the graphs, such as Fig. 4, of concentration distributions, the lower end position of the buffer region 20 is defined as a reference position (0) in the Z-axis direction, and a distance from the reference position is defined as a position in the Z-axis direction. At the lower end position of the buffer region 20, a valley of the doping concentration distribution is present due to the PN junction of the collector region 22 and the buffer region 20, although the valley in Fig. 4 or the like is omitted.

[0093] Oxygen is contained throughout the semiconductor substrate 10. Fig. 4 shows the distribution 210 when the semiconductor device 100 is formed on each of two semiconductor substrates 10 with different chemical oxygen concentrations. In Fig. 4, a dashed line distribution represents an example in which the chemical oxygen concentration in the semiconductor substrate 10 is relatively high (for example, 4 × 10 17 atoms / cm 3 ), whereas a solid line distribution represents an example in which the chemical oxygen concentration in the semiconductor substrate 10 is relatively low (for example, 1 × 10 17 atoms / cm 3A comparison of the chemical oxygen concentrations of the semiconductor substrates 10 can be performed using an average value of the chemical oxygen concentration in the entire substrate or a maximum value of the chemical oxygen concentration. In respective examples, the dose amount and acceleration energy of dopant locally implanted into the buffer region 20 are the same. The dopant implanted into the buffer region 20 is, for example, a proton, but is not limited thereto.

[0094] In each example, one or more peaks 201 of the doping concentration are provided in the buffer region 20. In the example of Fig. 4, five peaks 201-1 to 201-5 of the doping concentration are provided in the buffer region 20. In the present description, among the peaks 201 of the doping concentration in the buffer region 20, the peak 201 of the doping concentration that is farthest from the bottom surface 23 of the semiconductor substrate 10 (in Fig. 4 the peak 201-5 of the doping concentration) is called the deepest peak, and the peak 201 of the doping concentration which is closest to the lower surface 23 (in Fig. 4, the peak 201-1 of the doping concentration) may be referred to as the shallowest peak. Moreover, the depth position at the local maximum of the peak 201-1 of the doping concentration is defined as Z1, and the depth position at the local maximum of the peak 201-5 of the doping concentration is defined as Z5. An intermediate peak region 301 is provided between adjacent peaks 201 of the doping concentration in the buffer region 20. A plurality of intermediate peak regions 301 may be provided. In the present description, among the intermediate peak regions 301 in the buffer region 20, the intermediate peak region 301 that is farthest from the bottom surface 23 of the semiconductor substrate 10 (in Fig. 4 the intermediate peak region 301-4), in some cases referred to as the deepest intermediate peak region, and the intermediate peak region 301 closest to the lower surface 23 (in Fig. 4 the peak 301-1 of the doping concentration), can be described as the shallowest intermediate peak region.

[0095] The drift region 18 is provided above the buffer region 20. The depth position at the boundary between the buffer region 20 and the drift region 18 is defined as Zb. The depth position Zb is a position where the doping concentration first becomes identical to the doping concentration (Dd1 or Dd2) in the drift region 18 in the direction from the buffer region 20 to the drift region 18. No local dopant has been implanted into the drift region 18. The doping concentration of the drift region 18 may be substantially constant. The thermal donor has been formed throughout the semiconductor substrate 10 due to the influence of heat applied to the semiconductor substrate 10. The distribution of the thermal donor is substantially uniform throughout the semiconductor substrate 10. Thus, the doping concentration of the drift region 18 becomes slightly higher than the bulk donor concentration BD.The oxygen contained in the semiconductor substrate 10 forms an unstable oxygen complex in the course of the temperature rise or fall of the semiconductor substrate 10. The oxygen complex acts as a dopant in the semiconductor substrate 10. In the present specification, the oxygen complex is referred to as the thermal donor.

[0096] The concentration of the thermal donor formed in each position of the semiconductor substrate 10 varies according to the concentration of oxygen contained in the semiconductor substrate 10 and the condition of temperature rise and fall of the semiconductor substrate 10. As shown in Fig. 4, the concentration of the thermal donor formed is different and the doping concentration is varied throughout the semiconductor substrate 10 between the two examples with different chemical oxygen concentrations of the semiconductor substrate 10.

[0097] The doping concentration of the drift region 18 in the solid line distribution 210 of the semiconductor substrate 10 with the relatively low chemical oxygen concentration is defined as Dd1, whereas the doping concentration of the drift region 18 in the dashed line distribution 210 of the semiconductor substrate 10 with the relatively high chemical oxygen concentration is defined as Dd2. As the doping concentration of each drift region 18, an average value thereof in the entire drift region 18 or a minimum value may be used.

[0098] The concentration of the thermal donor in the solid line distribution 210 of the semiconductor substrate 10 with the relatively low chemical oxygen concentration is defined as Nth1, whereas the concentration of the thermal donor in the dashed line distribution 210 of the semiconductor substrate 10 with the relatively high chemical oxygen concentration is defined as Nth2. A difference (Dd1 - BD or Dd2 - BD) between the doping concentration (Dd1 or Dd2) in the drift region 18 and the bulk donor concentration BD corresponds to the concentration (Nth1 or Nth2) of the thermal donor formed in respective semiconductor substrates 10. In each example described in the present specification, the difference between the doping concentration of the drift region 18 and the bulk donor concentration BD is defined as the thermal donor concentration.The concentration of the thermal donor may be the same throughout the semiconductor substrate 10.

[0099] As the volume donor concentration BD, a minimum value of the chemical concentration of the volume donor in the semiconductor substrate 10 can be used, the chemical concentration of the volume donor at a central position in the depth direction of the semiconductor substrate 10 can be used, or an average value of the chemical concentration of the volume donor in the drift region 18 can be used. The volume donor is a dopant other than oxygen and is distributed throughout the semiconductor substrate 10. For example, the volume donor can be phosphorus, arsenic, or antimony, but is not limited to these. When both the P-type volume acceptor and the N-type volume donor are distributed throughout the semiconductor substrate 10, the volume donor concentration BD is the net concentration determined by the difference between the concentration of the volume donor and the concentration of the volume acceptor.As the concentrations of the volume donor and the volume acceptor, a value measured by the SIMS method or the like can be used.

[0100] Buffer region 20 includes a raised donor in addition to the bulk donor. The raised donor is a different donor than the bulk donor. The raised donor includes an implanted donor formed by locally implanting ions into buffer region 20 and the thermal donor described above. When a hydrogen ion is locally implanted into buffer region 20, the implanted donor is the hydrogen donor. When phosphorus or the like is locally implanted into buffer region 20, the implanted donor is the phosphorus donor.

[0101] The concentration of the thermal donor varies according to the oxygen concentration in the semiconductor substrate 10. When a ratio of the thermal donor concentration contained in the increased donor is high, the concentration of the increased donor varies according to the oxygen concentration in the semiconductor substrate 10. Accordingly, as shown by the dashed line and the solid line distribution 210 in Fig. 4, the doping concentration of the buffer region 20 according to the oxygen concentration in the semiconductor substrate 10.

[0102] In the buffer region 20, a region from the lower end of the buffer region 20 to the deepest peak (the peak 201-5 of the doping concentration in the present example) is defined as a first region 200. In the solid line distribution 210, the minimum value of the doping concentration of the first region 200 is defined as Nmin1, and the concentration of the increased donor at this depth position is defined as ID1. The minimum value Nmin1 of the doping concentration in the first region 200 of the present example is the doping concentration Nmin1 at the deepest inter-peak region (the inter-peak region 301-4 in the present example). The concentration ID1 of the increased donor is a difference (Nmin1-BD) between the doping concentration Nmin1 and the volume donor concentration BD.Furthermore, in the dashed line distribution 210, the minimum value of the doping concentration in the first region 200 is defined as Nmin2, and the concentration of the increased donor at this depth position is defined as ID2. The depth position at which the doping concentration becomes Nmin1 in the solid line distribution 210 is substantially the same as the depth position at which the doping concentration becomes Nnmin2 in the dashed line distribution 210. The concentration ID2 of the increased donor is a difference (Nmin2 - BD) between the doping concentration Nmin2 and the bulk donor concentration BD. Note that some of the intermediate peak regions 301 may, in some cases, have a doping concentration lower than the bulk donor concentration BD.In such a case, the doping concentration of the intermediate peak region 301 having the minimum doping concentration among the intermediate peak regions 301 having the doping concentrations higher than the volume donor concentration BD may be defined as Nmin1.

[0103] The minimum value of the increased donor concentration in the first region 200 can be represented as the concentrations ID1 and ID2 of the increased donor. The concentrations Nth1 and Nth2 of the thermal donor are essentially constant at each depth position in the buffer region 20, and thus the ratio of the concentrations Nth1 and Nth2 of the thermal donor relative to the concentrations ID1 and ID2 of the increased donor represents the maximum value of the thermal donor / enhanced donor ratio in the first region 200.An average value of the thermal donor concentrations in the drift region 18 can be used as the thermal donor concentration of the buffer region 20, the maximum value of the thermal donor concentrations in the drift region 18 can be used as the thermal donor concentration of the buffer region 20, or the thermal donor concentration at the depth position Zb can be used as the thermal donor concentration of the buffer region 20.

[0104] In the solid line distribution 210, the concentration ID1 of the increased donor is 7 × 10 13 / cm 3 and the concentration Nth1 of the thermal donor is 2 × 10 13 / cm 3 The ratio Nth1 / ID1 of the thermal donor relative to the elevated donor is 29%. In the dashed line distribution 210, the concentration ID2 of the elevated donor is 1 × 10 14 / cm 3and the concentration Nth2 of the thermal donor is 5 × 10 13 / cm 3 The NTh2 / ND2 ratio of the thermal donor relative to the enhanced donor is 50%. Thus, a larger ratio of the thermal donor relative to the enhanced donor causes a significant dispersion in the enhanced donor concentration according to the oxygen concentration of the semiconductor substrate 10. This causes, for example, the properties of the semiconductor device 100, such as the breakdown voltage, to vary. When the breakdown voltage of the solid line distribution example 210 is normalized to 1, the breakdown voltage of the dashed line distribution example 210 is 1.15.

[0105] Fig. Figure 5 illustrates a distribution 210 of doping concentrations according to the example. In the example of Fig. 5, the concentration of the thermal donor formed in the semiconductor substrate 10 is lower than that in the example of Fig. 4. Thus, the doping concentration and the concentration of the increased donor at the respective depth positions also differ from those in the example of Fig. 4. Other structures are similar to those of the Fig. 4 shown example. Again in Fig. 5, a dashed line represents a distribution 210 of the example in which the chemical oxygen concentration in the semiconductor substrate 10 is relatively high (for example, 4 × 10 17 atoms / cm 3 ), whereas a solid line represents a distribution 210 of the example in which the chemical oxygen concentration in the semiconductor substrate 10 is relatively low (for example, 1 × 10 17 atoms / cm 3 ). In the example of Fig. 5, although the chemical oxygen concentration contained in the semiconductor substrate 10 is similar to that in the example of Fig. 4, the concentration of the thermal donor is controlled to be low by controlling the thermal profile relative to the semiconductor substrate 10.

[0106] As described above, the volume donor and the thermal donor are contained in the semiconductor substrate 10. The volume donor and the thermal donor can be distributed throughout the semiconductor substrate 10. The drift region 18 includes the volume donor and the thermal donor. No other donors can be distributed in the drift region 18.

[0107] The buffer region 20 comprises the volume donor and the raised donor. As described above, the raised donor comprises the implanted donor and the thermal donor. The implanted donor may be a hydrogen donor, a phosphorus donor, or other donors. The hydrogen donor may comprise a CiOi-H donor. The hydrogen donor may comprise a VOH defect or an interstitial Si-H.

[0108] In the present example, the thermal donor concentration Nth is 10% or less of the concentration ID of the elevated donor at the same depth position over the entire first region 200 in both the solid line distribution and the dashed line distribution 210. Again in the example of Fig. 5, in the solid line distribution 210, the minimum value of the doping concentration in the first region 200 is defined as Nmin1, and the concentration of the increased donor at this depth position is defined as ID1. The concentration ID1 of the increased donor is a difference (Nmin1 - BD) between the doping concentration Nmin1 and the volume donor concentration BD. Furthermore, in the dashed line distribution 210, the minimum value of the doping concentration in the first region 200 is defined as Nmin2, and the concentration of the increased donor at this depth position is defined as ID2.

[0109] As an example, in the solid line distribution 210, the concentration ID1 of the increased donor is 5 × 10 13 / cm 3 and the concentration Nth1 of the thermal donor is 3 × 10 12 / cm 3The ratio Nth1 / ID1 of the thermal donor relative to the elevated donor is 6%. In the dashed line distribution 210, the concentration ID2 of the elevated donor is 5 × 10 13 / cm 3 and the concentration Nth2 of the thermal donor is 5 × 10 12 / cm 3 The ratio NTh2 / ND2 of the thermal donor relative to the elevated donor is 10%. This means that in both examples, the concentration Nth of the thermal donor is 10% or less of the concentration ID of the elevated donor at the same depth position across the entire first region 200.

[0110] In the present example, reducing the thermal donor ratio enables suppression of the dispersion of the increased donor concentration caused by the oxygen concentration in the semiconductor substrate 10. Thus, changes in the properties, such as the breakdown voltage, of the semiconductor device 100 can be suppressed. In the example of Fig. 5, when the breakdown voltage of the solid line distribution example 210 is defined as 1, the breakdown voltage of the dashed line distribution example 210 is 1.02.

[0111] Across the entire first region 200, the concentration Nth of the thermal donor may be 10% or less, 8% or less, 6% or less, or 5% or less of the concentration ID of the raised donor at the same depth position. By reducing the ratio of the thermal donor, the dispersion of the doping concentration of the buffer region 20 can be suppressed, and thus the characteristic variation of the semiconductor device 100 can be suppressed. Across the entire first region 200, the concentration Nth of the thermal donor may be 0.1% or more, 0.5% or more, 1% or more, 2% or more, 3% or more, or 5% or more of the concentration ID of the raised donor at the same depth position.

[0112] The chemical oxygen concentration of the semiconductor substrate 10 is 1 × 10 16 atoms / cm 3or more. In the present example, even if the chemical oxygen concentration of the semiconductor substrate 10 is high, the variation in the characteristics, such as the breakdown voltage, of the semiconductor device 100 can be suppressed by suppressing the generation of the thermal donor. Thus, there is no need to prepare the substrate with a low chemical oxygen concentration, which enables a reduction in the manufacturing cost of the semiconductor device 100. In addition, by using the semiconductor substrate 10 with a high chemical oxygen concentration, the hydrogen donor is more easily formed, and the doping concentration of the buffer region 20 is more easily increased. The chemical oxygen concentration of the semiconductor substrate 10 may be 3 × 10 16 atoms / cm 3 or more, 5 × 10 16 atoms / cm 3 or more or 1 × 10 17 atoms / cm 3or more. The chemical oxygen concentration of the semiconductor substrate 10 may be 1 × 10 18 atoms / cm 3 or less or 5 × 10 17 atoms / cm 3 or less.

[0113] The concentration (Nth1 or Nth2) of the thermal donor in the drift region 18 can be equal to or less than 0.0001 times (1 × 10 -4-times) of the chemical oxygen concentration of the drift region 18. As the chemical oxygen concentration of the drift region 18, an average value in the drift region 18, a minimum value, or a value in the middle in the depth direction of the drift region 18 can be used. This allows a reduction in the ratio of the thermal donor relative to the increased donor in the buffer region 20, and thus the characteristic variation of the semiconductor device 100 can be suppressed. The concentration (Nth1 or Nth2) of the thermal donor in the drift region 18 can be equal to or less than 0.00005 times (5 × 10 -5 times) or equal to or less than 0.00001 times (1 × 10 -5 times) of the chemical oxygen concentration of the drift region 18. The concentration (Nth1 or Nth2) of the thermal donor in the drift region 18 can be equal to or greater than 1 × 10-8 times, equal to or greater than 5 × 10 -8 times or equal to or greater than 1 × 10 -7 -times the chemical oxygen concentration of the drift region 18.

[0114] The doping concentration (Dd1 or Dd2) in the drift region 18 can be equal to or less than 1.5 times the concentration BD of the bulk donor. This allows a reduction in the ratio of the thermal donor relative to the elevated donor in the buffer region 20, and thus the characteristic variation of the semiconductor device 100 can be suppressed. The doping concentration (Dd1 or Dd2) in the drift region 18 can be equal to or less than 1.3 times or equal to or less than 1.1 times the concentration BD of the bulk donor. The doping concentration (Dd1 or Dd2) in the drift region 18 is higher than the concentration BD of the bulk donor.

[0115] The concentration (Nth1 or Nth2) of the thermal donor in the drift region 18 can be equal to or less than 0.5 times the concentration BD of the bulk donor. This allows a reduction in the ratio of the thermal donor relative to the elevated donor in the buffer region 20, and thus the characteristic variation of the semiconductor device 100 can be suppressed. The concentration (Nth1 or Nth2) of the thermal donor in the drift region 18 can be equal to or less than 0.3 times, or equal to or less than 0.1 times the concentration BD of the bulk donor. The concentration (Nth1 or Nth2) of the thermal donor in the drift region 18 is greater than 0.

[0116] At the depth position Z5 of the local maximum of the deepest peak (the doping concentration peak 201-5 in the present example), the thermal donor concentration Nth can be equal to or less than 0.1 times the doping concentration Np5. In the solid and dashed line distributions 210, the values ​​of the doping concentration Np5 are substantially the same. This allows the ratio of the thermal donor to be reduced relative to the increased donor at the deepest peak in the buffer region 20, and thus the characteristic variation of the semiconductor device 100 can be suppressed. For example, the dispersion of the oscillation of the voltage waveform when the space charge region (or a depletion layer) spreading from the top surface 21 side reaches the buffer region 20 can be suppressed at the time of turn-off or the like of the semiconductor substrate 10.At the depth position Z5, the concentration Nth of the thermal donor can be equal to or less than 0.05 times or equal to or less than 0.01 times the doping concentration Np5.

[0117] The buffer region 20 includes a maximum peak (the doping concentration peak 201-1 in the present example) at which the doping concentration is maximum, among the other doping concentration peaks 201 except the deepest peak. A peak other than the doping concentration 201-1 may be the maximum peak. For example, the doping concentration peak 201-2 may be the maximum peak. The concentration of the thermal donor at the depth position Z1 of the local maximum of the maximum peak may be equal to or less than 0.01 times the doping concentration Np1. This enables a reduction in the ratio of the thermal donor relative to the increased donor at the maximum peak in the buffer region 20, and thus the characteristic variation of the semiconductor device 100 can be suppressed.At the depth position Z1, the concentration of the thermal donor can be equal to or less than 0.005 times or equal to or less than 0.001 times the doping concentration Np1.

[0118] The buffer region 20 includes the shallowest peak (the doping concentration peak 201-1 in the present example) closest to the bottom surface 23 of the semiconductor substrate 10. The thermal donor concentration at the depth position Z1 of the local maximum of the shallowest peak may be equal to or less than 0.001 times the doping concentration Np1. This allows a reduction in the ratio of the thermal donor relative to the increased donor at the shallowest peak in the buffer region 20, and thus the characteristic variation of the semiconductor device 100 can be suppressed. At the depth position Z1, the thermal donor concentration may be equal to or less than 0.0005 times, or equal to or less than 0.0001 times the doping concentration Np1.

[0119] Fig. 6 illustrates an example of the distribution of the chemical oxygen concentration and the distribution of the thermal donor concentration in a region on the upper surface 21 side (a region from a depth position Zb to a depth position Zu) relative to the buffer region 20. A value measured by the SIMS method or the like can be used as the chemical oxygen concentration. In this example, the depth position Zb is a boundary position between the buffer region 20 and the drift region 18, and the depth position Zu is an upper end position of the drift region 18.

[0120] In the present example, the concentration of the thermal donor is not constant in the depth direction. The concentration of the thermal donor at each depth position in the drift region 18 can be calculated from the difference between the dopant concentration and the volume donor concentration BD. Note that the concentration of the thermal donor in the buffer region 20, as shown in Fig. 5 or the like, an average value of the thermal donor in the drift region 18, as in Fig. 6, or a value of the thermal donor at the depth position Zb can be used.

[0121] The chemical oxygen concentration distribution of the present example includes a decreasing section 220 in which the chemical oxygen concentration decreases toward the upper surface 21 of the semiconductor substrate 10 in the range from the depth position Zb to the depth position Zu. In the decreasing section 220, the chemical oxygen concentration decreases as the distance to the upper surface 21 decreases. The decreasing section 220 does not include a region in which the chemical oxygen concentration increases as the distance to the upper surface 21 decreases.

[0122] The oxygen inside the semiconductor substrate 10 may be released to the outside of the semiconductor substrate 10 during the manufacturing process or the like of the semiconductor device 100. Thus, the chemical oxygen concentration near the surface of the semiconductor substrate 10 decreases significantly, and the chemical oxygen concentration may decrease smoothly toward the substrate surface even at a position far from the surface of the semiconductor substrate 10. Note that in the semiconductor device 100 of the present example, a region where the chemical oxygen concentration decreases toward the bottom surface 23 was ground during the manufacturing process. The decrease portion 220 may be provided in the entire range from the depth position Zb to the depth position Zu.

[0123] The concentration of the thermal donor at each depth position varies according to the chemical oxygen concentration at each depth position. The thermal donor concentration distribution of the present example includes a decreasing portion 230 in which the thermal donor concentration decreases toward the upper surface 21 of the semiconductor substrate 10 in the range from the depth position Zb to the depth position Zu. In the decreasing portion 230, the thermal donor concentration decreases as the distance from the upper surface 21 is reduced. The decreasing portion 230 does not include a region in which the thermal donor concentration increases as the distance from the upper surface 21 is reduced. The decreasing portion 230 may be provided in part or the entire range from the depth position Zb to the depth position Zu.In the decreasing section 230, the concentration of the thermal donor at the depth position Zu may decrease to be equal to or less than half, equal to or less than 1 / 4, equal to or less than 1 / 10 of the concentration of the thermal donor at the depth position Zb, or to be 0.

[0124] The removal portion 230 of the present example includes a region 240 in which a logarithmic gradient αth of the thermal donor concentration toward the upper surface 21 side of the semiconductor substrate 10 is equal to or greater than 0.5 times and equal to or less than 10 times a logarithmic gradient αox of the chemical oxygen concentration. This enables a reduction in the ratio of the thermal donor relative to the doping concentration of the drift region 18 or the buffer region 20, and thus the characteristic variation of the semiconductor device 100 can be suppressed. The depth position at the lower end of the region 240 is defined as Xa, and the depth position at the upper end is defined as Xb. The center position in the depth direction of the semiconductor substrate 10 is defined as Zc. The depth position Xa can be located in a range from the depth position Zc to Zb.The depth position Xa may be identical to the depth position Zb. The depth position Xb may be located in a range from the depth position Zc to Zb, or may be located in a range from the depth position Zc to Zu. The depth position Xb may be located on the lower surface 23 side relative to a region where the chemical oxygen concentration changes greatly. The depth position Xb may be away from the upper surface 21 of the semiconductor substrate 10 by 10 µm or more, 20 µm or more, or 30 µm or more. The region 240 may have a length of 10 µm or more or 20 µm or more in the depth direction.

[0125] The chemical oxygen concentration at depth position Xa is defined as Noxa, and the thermal donor concentration at depth position Xa is defined as Ntha. The chemical oxygen concentration at depth position Xb is defined as Noxb, and the thermal donor concentration at depth position Xb is defined as Nthb. The logarithmic gradient αth of the thermal donor concentration and the logarithmic gradient αox of the chemical oxygen concentration of region 240 are defined in the following expressions. αth=|log10(Ntha)−log10(Nthb)| / |Xa−Xb| αox=|log10(Noxa)−log10(Noxb)| / |Xa−Xb|

[0126] In region 240, the logarithmic gradient αth of the thermal donor concentration may be equal to or greater than 0.8 times, or equal to or greater than 1 times, the logarithmic gradient αox of the chemical oxygen concentration. In region 240, the logarithmic gradient αth of the thermal donor concentration may be equal to or less than 7 times, or equal to or less than 4 times, the logarithmic gradient αox of the chemical oxygen concentration.

[0127] Fig. 7 is a flowchart describing an example of a manufacturing method of the semiconductor device 100. The manufacturing method includes one or more operations for annealing the semiconductor substrate 10. The manufacturing method includes operations after cutting a semiconductor wafer from a semiconductor ingot until the completion of the semiconductor device 100. The manufacturing method in the example of Fig. 7 includes a first annealing step S701 and a second annealing step S702, although the annealing step may be one or three or more in the manufacturing process. In each annealing step, the semiconductor substrate 10 is heated to a temperature equal to or higher than room temperature (25°C). In at least one annealing step, the semiconductor substrate 10 may be heated to a temperature equal to or higher than 400°C.

[0128] As described above, the concentration of the thermal donor formed in the semiconductor substrate 10 can be controlled by the thermal history relative to the semiconductor substrate 10. In the manufacturing method of the present example, the semiconductor substrate 10 is annealed so that the concentration Nth of the thermal donor is 10% or less of the concentration ID of the raised donor at the same depth position over the entire first region 200 formed in Fig. 5 is shown.

[0129] Fig. Figure 8 illustrates an exemplary temporal change in the temperature of the semiconductor substrate 10 in each annealing step. The horizontal axis represents time, and the vertical axis represents temperatures (°C) of the semiconductor substrate 10 in Fig. 8. In each annealing step, the semiconductor substrate 10 is heated from room temperature (RT = 25 °C) to a predetermined temperature. In the example of Fig. 8, the semiconductor substrate 10 is heated to 500 °C or more in both the first annealing step S701 and the second annealing step S702.

[0130] In the semiconductor substrate 10, such as silicon, the thermal donor is likely to be formed when the temperature of the semiconductor substrate 10 is approximately 450°C. Thus, by controlling a time period during which the semiconductor substrate 10 passes through a predetermined first temperature range in each annealing step, the formation of the thermal donor can be suppressed. In the example of Fig. 8, the lower limit temperature of the first temperature range is defined as 400 °C and the upper limit temperature is defined as 500 °C. In each process for annealing the semiconductor substrate 10, a time period during which the temperature of the semiconductor substrate 10 passes through the first temperature range of 400 °C or more and 500 °C or less may be 20 minutes or less per pass. In the example of Fig. 8, in the first annealing step S701, a time period during which the temperature of the semiconductor substrate 10 passes through the first temperature range is defined as T11 in the temperature increase process, and a time period during which it passes through the first temperature range is defined as T21 in the temperature decrease process. In the second annealing step S702, a time period during which it passes through the first temperature range is defined as T31 in the temperature increase process, and a time period during which it passes through the first temperature range is defined as T41 in the temperature decrease process. T11, T21, T31, and T41 may each be 20 minutes or less. This can suppress the formation of the thermal donor in the semiconductor substrate 10 when it passes through the first temperature range. T11, T21, T31, and T41 may each be 10 minutes or less or 5 minutes or less.Alternatively, the average duration of T11, T21, T31 and T41 may be 10 minutes or less or 5 minutes or less.

[0131] An accumulated time of the time durations of all processes from the beginning to the end of the manufacturing process of the semiconductor device 100, during which the temperature of the semiconductor substrate 10 passes through the first temperature range (400 °C or more and 500 °C or less), in each process for annealing the semiconductor substrate 10 may be 120 minutes or less. In the example of Fig. 8, the sum of T11, T21, T31, and T41 is 120 minutes or less. This can suppress the total amount of thermal donors to be formed in the semiconductor substrate 10. The accumulated time period of the time periods during which the temperature of the semiconductor substrate 10 passes through the first temperature range can be 60 minutes or less or 40 minutes or less.

[0132] The temperature range of 425°C or more and 475°C or less is defined as a second temperature range. In the second temperature range, the thermal donor is more likely to be formed in the semiconductor substrate 10. In each process for annealing the semiconductor substrate 10, a time period during which the temperature of the semiconductor substrate 10 passes through the second temperature range of 425°C or more and 475°C or less may be 10 minutes or less per pass. In the example of Fig. 8, in the first annealing step S701, a time period during which the temperature of the semiconductor substrate 10 passes through the second temperature range is defined as T12 in the temperature increase process, and a time period during which it passes through the second temperature range is defined as T22 in the temperature decrease process. In the second annealing step S702, a time period during which it passes through the second temperature range is defined as T32 in the temperature increase process, and a time period during which it passes through the second temperature range is defined as T42 in the temperature decrease process. T12, T22, T32, and T42 may each be 10 minutes or less. This can suppress the formation of the thermal donor in the semiconductor substrate 10 when it passes through the second temperature range. T12, T22, T32, and T42 may each be 5 minutes or less or 3 minutes or less.Alternatively, the average duration of T12, T22, T32 and T42 may be 5 minutes or less or 3 minutes or less.

[0133] An accumulated time duration of the time durations of all processes from the beginning to the end of the manufacturing process of the semiconductor device 100, during which the temperature of the semiconductor substrate 10 passes through the second temperature range (425°C or more and 475°C or less), in each process for annealing the semiconductor substrate 10 may be 60 minutes or less. In the example of Fig. 8, the sum of T12, T22, T32, and T42 is 60 minutes or less. This can suppress the total amount of thermal donors to be formed in the semiconductor substrate 10. The accumulated time period of the time periods during which the temperature of the semiconductor substrate 10 passes through the second temperature range can be 30 minutes or less, or 20 minutes or less.

[0134] Fig. 9 is a flowchart showing a more detailed example of the manufacturing method of the semiconductor device 100. Specific example of the manufacturing method of the semiconductor device 100. In the example of Fig. 9, some processes of the manufacturing method are omitted. In the present example, a dielectric interlayer film 38 is formed on the upper surface 21 of the semiconductor substrate 10 (S901). In processes before S901, the method may include a plurality of processes for heating the semiconductor substrate 10 to a temperature higher than room temperature (25°C). In S901, the semiconductor substrate 10 may be heated to a temperature of 400°C or more and 900°C or less. The time period during which the temperature of the semiconductor substrate 10 passes through the first temperature range and the second temperature range, as shown in Fig. 7 and Fig. 8, includes the time durations of all processes in which the temperature of the semiconductor substrate 10 passes through the first temperature range and the second temperature range.

[0135] After the interlayer dielectric film 38 is formed, a contact hole 54 is formed in the interlayer dielectric film 38. After the contact hole 54 is formed, barrier metal may be formed within the contact hole 54 (S902). In S902, the semiconductor substrate 10 may be heated to a temperature of 400°C or more and 700°C or less. The barrier metal may include a film made of at least one of titanium and titanium nitride.

[0136] After the barrier metal is formed, a metal electrode (an emitter electrode 52 in the present example) is formed over the upper surface 21 of the semiconductor substrate 10 by sputtering (S903). After the emitter electrode 52 is formed, the semiconductor substrate 10 is placed in an annealing furnace or the like to be annealed (S904). Unless specifically explained otherwise, when heating the semiconductor substrate 10, the entire semiconductor substrate 10 is heated in the annealing furnace or the like. In S904, the semiconductor substrate 10 may be heated to a temperature of less than 400°C.

[0137] After the emitter electrode 52 is formed, a protective film is formed on the emitter electrode 52 (S905). The protective film is formed, for example, from polyimide or the like. After the protective film is formed, the semiconductor substrate 10 is heated to a curing temperature of the protective film (S906). In S906, the semiconductor substrate 10 may be heated to a temperature of less than 400°C.

[0138] After the protective film is formed, the semiconductor substrate 10 is thinned according to a breakdown voltage that the semiconductor device 100 should have (S907). In S907, the thickness of the semiconductor substrate 10 is adjusted by grinding the bottom surface 23 of the semiconductor substrate 10.

[0139] After the semiconductor substrate 10 is thinned, the collector region 22 is formed (S908), and the cathode region 82 is formed in the bottom surface 23 of the semiconductor substrate 10 (S909). Any of S908 and S909 can be performed first. In S908 and S909, dopant ions are implanted into each region.

[0140] After the dopant ions have been implanted into the collector region 22 and the cathode region 82, the semiconductor substrate 10 is annealed to activate the dopants (S910). In S910, the semiconductor substrate 10 may be locally heated by laser annealing or the like.

[0141] Fig. 10 is a flowchart showing operations similar to those of Fig. 9. After the collector region 22 and the cathode region 82 have been formed, a buffer region 20 is formed (S911). In S911, dopant ions, such as protons, are implanted into the buffer region 20.

[0142] After the dopant ions have been implanted into the buffer region 20, the semiconductor substrate 10 is annealed to activate the dopants (S912). In S912, the semiconductor substrate 10 may be heated to a temperature of less than 400°C.

[0143] After the buffer region 20 is formed, the semiconductor substrate 10 may be irradiated with charged particles such as helium to form a lifetime killer (S913). The lifetime killer is a recombination center of a lattice defect or the like, and shortens the lifetime of a carrier by combining with the carrier of the semiconductor substrate 10. For example, the upper surface 21 side of the diode portion 80 may be irradiated with the charged particles such as helium. After being irradiated with the charged particles such as helium, the semiconductor substrate 10 is annealed (S914). In S914, the semiconductor substrate 10 may be heated to a temperature of less than 400°C.

[0144] After the lifetime killers have been formed, the collector electrode 24 is formed by sputtering (S915). After the collector electrode 24 has been formed, the semiconductor substrate 10 is annealed (S916). In S916, the semiconductor substrate 10 may be heated to a temperature of less than 300°C. After the collector electrode 24 has been formed, the semiconductor wafer may be singulated and separated into semiconductor chips.

[0145] In the manufacturing method of the present example, the processes after the formation of the emitter electrode 52 (the processes of S905 and thereafter) are performed at less than 400°C. This can suppress the formation of the thermal donor in the semiconductor substrate 10. The processes after the formation of the emitter electrode 52 can be performed at 390°C or less or 380°C or less. In the manufacturing method of the present example, the semiconductor substrate 10 is heated to a temperature of 400°C or higher in S901 and S902. The temperature of the semiconductor substrate 10 in S901 and S902 can be the temperature specified in Fig. 7 and Fig. 8 described conditions.

[0146] The annealing condition of the manufacturing process can be determined based on the chemical oxygen concentration of the semiconductor substrate 10 used. Changes in the thermal donor concentration when at least one of an annealing time, a temperature rise rate, a temperature drop rate, or an annealing temperature is changed can be measured in advance for each chemical oxygen concentration of the semiconductor substrate 10. Based on this measurement result, at least one of the annealing time, the temperature rise rate, the temperature drop rate, or the annealing temperature can be adjusted in each annealing step, and the concentration of the thermal donor to be formed in the semiconductor substrate 10 can be controlled.

[0147] Although the present invention has been described with the embodiments, the technical scope of the present invention is not limited to the above-described embodiments. It is obvious to those skilled in the art that various modifications and improvements can be added to the above-described embodiments. It is also obvious from the scope of the claims that the embodiments added with such modifications or improvements can be included within the technical scope of the present invention.

[0148] The operations, procedures, steps, stages, or the like of each process performed by an apparatus, system, program, and method shown in the claims, embodiments, or diagrams may be implemented in any order, as long as the order is not specified by "previous," "before," or the like, and as long as the output from a previous process is not used in a subsequent process. Even if the process flow is described using terms such as "first" or "next" in the claims, embodiments, or diagrams, this does not necessarily mean that the process must be performed in that order. LIST OF REFERENCE SYMBOLS 10 Semiconductor substrate 11 Bath area 12 Emitter area 14 Basic area 15 Contact area 16 Collection area 18 Drift area 20 Buffer area 21 upper surface 22 Collector area 23 lower surface 24 Collector electrode 29 straight section 30 Dummy trench section 31 marginal section 32 dielectric dummy film 34 Dummy line section 38 dielectric interlayer film 39 straight section 40 gate ditch section 41 marginal section 42 dielectric gate film 44 gate line section 52 Emitter electrode 54 contact hole 60, 61 Mesa section 70 transistor section 80 diode section 81 Expansion area 82 Cathode area 90 edge finish structure section 100 semiconductor devices 130 outer circumference gate runner 131 active-side gate runner 160 active section 162 End page 164 Gatterfeld 200 first area 201 Peak of doping concentration 210 Distribution 220 Acceptance section 230 Acceptance section 240 area. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 2020 / 0194550

[0002] US 2016 / 0329401

[0002]

Claims

[1] A semiconductor device comprising a semiconductor substrate comprising a top surface and a bottom surface, a volume donor and a thermal donor, and having a chemical oxygen concentration of 1 × 10 16 atoms / cm 3 or more, wherein the semiconductor device comprises: a drift region of a first conductivity type disposed on the semiconductor substrate and comprising the volume donor and the thermal donor; a buffer region of a first conductivity type arranged between the drift region and the lower surface of the semiconductor substrate, comprising the bulk donor and a raised donor, and having a doping concentration higher than that of the drift region, wherein the buffer region comprises one or more peaks of the doping concentration in a depth direction of the semiconductor substrate, the one or more peaks of the doping concentration comprise a lowest peak located furthest from the lower surface of the semiconductor substrate, the increased donor comprises the thermal donor, and a concentration of the thermal donor is 10% or less of a concentration of the elevated donor at a same depth position over an entire first region from a lower end of the buffer region to the deepest peak. [2] The semiconductor device of claim 1, wherein the increased donor comprises a CiOi-H donor. [3] The semiconductor device according to claim 1, wherein a concentration of the thermal donor is 0.1% or more of a concentration of the increased donor at a same depth position over the entire first region. [4] A semiconductor device according to claim 1, wherein a chemical oxygen concentration of the semiconductor substrate is 1 × 1017 atoms / cm 3 or more and 5 × 10 17 atoms / cm 3 or less. [5] The semiconductor device according to claim 1, wherein a concentration of the thermal donor in the drift region is equal to or less than 0.0001 times the chemical oxygen concentration. [6] The semiconductor device according to claim 1, wherein a doping concentration of the drift region is equal to or less than 1.5 times a concentration of the bulk donor. [7] A semiconductor device according to any one of claims 1 to 6, wherein a concentration of the thermal donor is equal to or less than 0.1 times a doping concentration at a local maximum position of the lowest peak. [8] A semiconductor device according to any one of claims 1 to 6, wherein the buffer region includes a maximum peak among the other peaks of the doping concentration except the lowest peak at which a doping concentration is maximum, and a concentration of the thermal donor is equal to or less than 0.01 times a doping concentration at a local maximum position of the maximum peak. [9] A semiconductor device according to any one of claims 1 to 6, wherein the buffer region includes a deepest peak closest to the bottom surface of the semiconductor substrate, and a concentration of the thermal donor is equal to or less than 0.001 times a doping concentration at a local maximum position of the lowest peak. [10] The semiconductor device according to any one of claims 1 to 6, wherein in a region located on a side of the upper surface of the semiconductor substrate relative to the buffer region, a concentration distribution of the thermal donor includes a decreasing portion in which a concentration of the thermal donor decreases toward the upper surface of the semiconductor substrate. [11] The semiconductor device according to claim 10, wherein the removal portion includes a region in which a logarithmic gradient of a concentration of the thermal donor toward the upper surface side of the semiconductor substrate is equal to or greater than 0.5 times and equal to or less than 10 times a logarithmic gradient of the chemical oxygen concentration. [12] A method of manufacturing a semiconductor device using a semiconductor substrate comprising an upper surface and a lower surface, a volume donor, and a chemical oxygen concentration of 1 × 10 16 atoms / cm 3 or more, wherein the semiconductor device comprises: a drift region of a first conductivity type disposed on the semiconductor substrate and comprising the volume donor and a thermal donor; a buffer region of a first conductivity type arranged between the drift region and the lower surface of the semiconductor substrate, comprising the bulk donor and a raised donor, and having a doping concentration higher than that of the drift region, wherein the buffer region comprises one or more peaks of the doping concentration in a depth direction of the semiconductor substrate, the one or more peaks of the doping concentration comprise a lowest peak located furthest from the lower surface of the semiconductor substrate, the increased donor comprises the thermal donor, and the semiconductor substrate is annealed such that a concentration of the thermal donor is 10% or less of a concentration of the increased donor at a same depth position over an entire first region from a lower end of the buffer region to the deepest peak. [13] A manufacturing method of a semiconductor device according to claim 12, wherein in each process of annealing the semiconductor substrate, a time period during which a temperature of the semiconductor substrate passes through a temperature range of 400°C or more and 500°C or less is 20 minutes or less per pass. [14] A manufacturing method of a semiconductor device according to claim 12, wherein in each process of annealing the semiconductor substrate, a time period during which a temperature of the semiconductor substrate passes through a temperature range of 425°C or more and 475°C or less is 10 minutes or less per pass. [15] A manufacturing method of a semiconductor device according to any one of claims 12 to 14, wherein an accumulated time period of periods during which a temperature of the semiconductor substrate passes through a temperature range of 400°C or more and 500°C or less in each process of annealing the semiconductor substrate is 120 minutes or less. [16] A manufacturing method of a semiconductor device according to any one of claims 12 to 14, wherein an accumulated time period of time periods during which a temperature of the semiconductor substrate passes through a temperature range of 425 °C or more and 475 °C or less in each process of annealing the semiconductor substrate is 60 minutes or less. [17] A manufacturing method of a semiconductor device according to any one of claims 12 to 14, wherein a metal electrode is formed over the upper surface of the semiconductor substrate, and a process carried out after the metal electrode has been formed at less than 400 °C.

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