Pulse signal processing method, device and matching circuit

Abstract

The present application provides a pulse signal processing method, apparatus, and matching circuit. The method is applied to a memory control unit of a matching circuit, the matching circuit comprising the memory control unit and a read control unit, the memory control unit being used to detect a power supply signal from a power supply and write it into an internal preset memory area, the read control unit being used to read a power supply signal stored in the preset memory area from the memory control unit and transmit it to a load;The method comprises: detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; maintaining a power supply signal in the high-level state and writing it to the preset memory area if this is not the case; writing a power supply signal in the low-level state to the preset memory area if this is the case. The embodiment of the present application is conducive to improving the reliability of the operation of the matching circuit.

Description

FIELD OF THE INVENTION

[0001] The application belongs to the technical field of electronic circuit technology and relates in particular to a pulse signal processing method, a device and a matching circuit. STATE OF THE ART

[0002] In the power supply system, it is usually necessary to establish a matching circuit between the load and the power supply. The power supply signal from the power supply is transmitted to the load through the matching circuit. Due to the delay in the operation of a device, when the power supply signal is transmitted to the load by the matcher, there is usually a problem that the pulse signal waveform cannot be accurately read and a pulse signal trough is misread. The matching circuit cannot actively judge whether it is a pulse off-state or a continuous off-state, which leads to the matching circuit being unable to transmit the pulse signal to the load and the problem of working reliability. DISCLOSURE OF THE INVENTION

[0003] The object of the present application is to overcome the deficiencies of the above-mentioned prior art and to provide a pulse signal processing method, apparatus and matching circuit to improve the reliability of the operation of the matching circuit.

[0004] To achieve the object, the application provides a pulse signal processing method applied to a memory control unit of a matching circuit, the matching circuit comprising the memory control unit and a read control unit, the memory control unit being used to detect a power supply signal from a power supply and write it into an internal preset memory area, the read control unit being used to read a power supply signal stored in the preset memory area from the memory control unit and transmit it to a load; the method comprising: Detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; Maintaining a power supply signal in the high level state, which is written to the preset memory area when this is not the case, Writing a power supply signal in the low level state to the preset memory area if this is the case.

[0005] It is further provided that the method comprises: maintaining a power supply signal in the high level state, which is written into the preset memory area, within the second preset duration when the power supply signal comprising high level pulse information is received from the power supply, wherein the second preset duration is not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time;

[0006] It is further provided that the reading control unit reads a power supply signal from the memory control unit at an interval of a third preset duration; wherein the second preset duration is not less than the greater of the third preset duration and a fourth preset duration, wherein the fourth preset duration is the operating duration of the device from the start of the reading of the power supply signal by the reading control unit until the actual reading of the power supply signal by the reading control unit.

[0007] The present application further provides a pulse signal processing method applied to a memory control unit of a matching circuit, the matching circuit comprising the memory control unit and a read control unit, the memory control unit being used to detect a power supply signal from a power supply and store it in an internal preset memory area, the read control unit being used to read a power supply signal stored in the preset memory area from the memory control unit and send it to a load;the method comprising: maintaining a power supply signal in the high level state written into the preset memory area within the second preset duration when the power supply signal including high level pulse information is received from the power supply, the second preset duration being not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time;

[0008] It is further provided that the reading control unit reads a power supply signal from the memory control unit at an interval of a third preset duration; wherein the second preset duration is not less than the greater of the third preset duration and a fourth preset duration, wherein the fourth preset duration is the operating duration of the device from the start of the reading of the power supply signal by the reading control unit until the actual reading of the power supply signal by the reading control unit.

[0009] It is further contemplated that the method further comprises: detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; maintaining a power supply signal in the high-level state, which is written to the preset memory area, if this is not the case; writing a power supply signal in the low-level state to the preset memory area, if this is the case.

[0010] The present application further provides a pulse signal processing device applied to a memory control unit of a matching circuit, the matching circuit comprising the memory control unit and a read control unit, the memory control unit being used to detect a power supply signal from a power supply and write it into an internal preset memory area, the read control unit being used to read a power supply signal stored in the preset memory area from the memory control unit and transmit it to a load;the device comprising: a detection module for detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; a first write module for maintaining a power supply signal in the high-level state, which is written to the preset memory area, if this is not the case; a second write module for writing a power supply signal in the low-level state to the preset memory area, if this is the case;

[0011] The present application further provides a pulse signal processing device applied to a memory control unit of a matching circuit, wherein the matching circuit includes the memory control unit and a read control unit, wherein the memory control unit is used to detect a power supply signal from a power supply and store it in an internal preset memory area, and wherein the read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and send it to a load;the apparatus comprising: a writing module for maintaining a power supply signal in the high-level state written into the preset memory area within a second preset duration when a power supply signal including high-level pulse information is received from the power supply, the second preset duration being not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time;

[0012] The present application further provides a matching circuit comprising a memory control unit and a read control unit electrically connected to each other; wherein the memory control unit is arranged to detect whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; to maintain a high-level power supply signal written into the preset memory area if this is not the case; and to write a low-level power supply signal into the preset memory area if this is the case;wherein the read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and send it to a load;

[0013] The present application further provides another matching circuit comprising a memory control unit and a read control unit electrically connected to each other; wherein the memory control unit is used to maintain a power supply signal in the high-level state, which is written into the preset memory area within the memory control unit, within a second preset duration when a power supply signal including high-level pulse information is received from the power supply, the second preset duration being not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time; wherein the read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and send it to a load.

[0014] It can be seen that in the embodiment of the present application, the memory control unit in the matching circuit is used to detect a power supply signal from a power supply and write it into an internal preset memory area, and the read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and transmit it to a load. When the read control unit receives a power supply signal containing low-level pulse information from the power supply, it can detect whether the duration of the power supply signal containing low-level pulse information is longer than the first preset duration. If it is not longer than the first preset duration, the power supply signal is always maintained in the high-level state and written into the preset memory area.The power supply signal in the low-level state is written to the preset memory area only when the duration of the power supply signal containing low-level pulse information is longer than the first preset duration. This ensures that the read control unit can stably read the high-level pulse information when reading the power supply signal, so that the obtained power supply signal can be stably transmitted to the load to perform pulse operation. This is beneficial to improving the reliability of the matching circuit. DESCRIPTION OF THE INVENTION

[0015] The present application is further described by the drawings, however, the embodiments in the drawings do not constitute a limitation of the present application, and other drawings can be obtained from the following drawings for those skilled in the art without inventive steps. Fig. 1 is a schematic structural diagram of the components of a power supply system according to the present application; Fig. 2 is a schematic structural diagram of the components of a matching circuit according to the present application; Fig. 3 is a schematic flow diagram of a pulse signal processing method according to the present application; Fig. 4 is a schematic diagram of a power supply signal according to an embodiment of the present application; Fig. 5 is a schematic diagram of the transmission of the power supply signal in a power system according to an embodiment of the present application; Fig. 6 is a schematic diagram of the transmission of the power supply signal in another power system according to an embodiment of the present application; Fig. 7 is a schematic flow diagram of another pulse signal processing method according to an embodiment of the present application; Fig. 8 is a functional module block diagram of a pulse signal processing apparatus according to an embodiment of the present application; Fig. 9 is a functional module block diagram of another pulse signal processing apparatus according to an embodiment of the present application. CONCRETE EMBODIMENTS

[0016] In the following, embodiments of the present application will be fully and clearly explained with reference to the accompanying drawings. It should be understood that the described embodiments represent only a portion of the embodiments, not all of the embodiments of the application. All other embodiments that can be obtained by those of ordinary skill in the art from the embodiments of the application without inventive steps are also within the scope of the application.

[0017] It is to be understood that in the description of the present application, the terms "center", "top", "bottom", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are used in each case with reference to the illustrated orientation or positional relationship in the respective illustration, in order merely to describe the application and, where appropriate, to simplify the description. In other words, these terms neither implicitly nor explicitly indicate the positioning, design, and operation of the device or element in question in a predetermined position, so that this does not limit the application either. Furthermore, it should be pointed out that the terms "first", "second", and "third" are not to be understood as an implicit or explicit reference to relative importance. Rather, they serve merely as a descriptive purpose.The singular forms of "a," "an," "the," and "these" used in the embodiment and appended claims of the present application are intended to include plural forms unless the context clearly indicates other meanings. It should further be understood that the term "and / or" as used herein encompasses any or all possible combinations of one or more of the related listed elements.

[0018] It will be Fig. 1, which shows a schematic structural diagram of the components of a power supply system according to the present application. The power supply system includes a matching circuit, as well as a power supply and a load connected to the matching circuit. The power supply is used to provide a power supply signal. After the matching circuit receives the power supply signal from the power supply, the load impedance between the power supply and the matching power supply and load is matched, and the power supply signal is simultaneously passed to the load. In the specific implementation, the power supply system may, for example, be a plasma power supply system, meaning that the load in the power supply system may, for example, be a plasma cavity load.

[0019] It will be Fig. 2, which shows a schematic structural diagram of the components of a matching circuit according to the present application. Specifically, the matching circuit can be based on the Fig. 1 can be applied. The matching circuit includes a memory control unit and a read control unit. The memory control unit is used to detect a power supply signal from a power supply and write it into an internal preset memory area. The read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and transmit it to a load.

[0020] In one conceivable embodiment, the memory control unit is specifically used for the following: detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; maintaining a power supply signal in the high-level state that is written to the preset memory area if this is not the case; writing a power supply signal in the low-level state to the preset memory area if this is the case.

[0021] In another conceivable embodiment, it is provided that the memory control unit is specifically used for the following: maintaining a power supply signal in the high-level state, which is written into the preset memory area, within a second preset duration when a power supply signal comprising high-level pulse information is received from the power supply, wherein the second preset duration is not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time.

[0022] Here, in the above embodiment, when the memory control unit detects high-level or low-level pulse information, the power supply signal can be stored with reference to the relevant contents of the subsequent method embodiment, and a detailed explanation is omitted herein.

[0023] Thus, it can be seen that, in the embodiment of the present application, the memory control unit included in the matching circuit writes a low-level power supply signal into the preset memory area only when the duration of the power supply signal containing low-level pulse information is greater than the first preset duration. Otherwise, the power supply signal is continuously written into the preset memory area in the high-level state; alternatively, when the memory control unit receives a power supply signal containing high-level pulse information from the power supply, the high-level state stored in the preset memory area is maintained within the second preset duration, which is not less than the time interval between the next reading of the power supply signal by the read control unit and the current time.The above-mentioned embodiment can cause the read control unit to read the power supply signal from the memory control unit and stably read the power supply signal into the high level state to obtain pulse information and stably transmit the power supply signal to the load, which is conducive to improving the reliability of the operation of the matching circuit.;

[0024] It will be Fig. 3, which shows a schematic flow diagram of a pulse signal processing method according to the present application. The pulse signal processing method can be applied to a memory control unit of a matching circuit as in Fig. 2. The adaptation circuit comprises the memory control unit and a read control unit, wherein the memory control unit is used to detect a power supply signal from a power supply and write it into an internal preset memory area, wherein the read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and transmit it to a load; the method comprising: Step 201. Detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; In the specific implementation, the power supply may be a high-frequency power supply, and the first preset duration can be set according to the type of high-frequency power supply. If the high-frequency power supply is a fixed-frequency power supply, that is, the pulse frequency of the power supply is fixed, the first preset duration is not less than the time interval between the last high level of the previous pulse and the first high level of the next pulse, that is, the time interval between the end time of the high level of the first pulse and the start time of the high level of the next pulse. If the pulse frequency of the high-frequency power supply is a variable-frequency power supply, that is,when the pulse frequency of the power supply changes, the first preset duration shall not be less than the maximum value of the time interval between the end time of the previous high level of the previous pulse and the start time of the high level of the next pulse. Step 202. Maintaining a power supply signal in the high level state, which is written into the preset memory area if it is not; Step 203. Write a power supply signal in the low level state to the preset memory area, if so. In step 202 and step 203, the memory control unit writes a power supply signal into the preset memory area, that is, the memory control unit continuously updates the power supply signal stored in the preset memory area, and when the read control unit reads the power supply signal from the memory control unit, the read power supply signal is continuously updated.

[0025] It is specifically aimed at Fig. 4, which shows a schematic diagram of a power supply signal according to an embodiment of the present application. Fig. 4 shows the waveform diagram of the original power supply signal and the power supply signal in the preset memory area as a function of time, where the original power supply signal is the power supply signal supplied by the power supply in the memory area shown in Fig. 1 shown power supply system to the matching circuit. The power supply signal in the preset memory area in Fig. 4 is the power supply signal stored in the preset memory area when the power supply signal in the preset memory area is stored by the memory control unit in the manner shown in Fig. 2. In the legend of the power supply signal in the preset memory area, the solid line represents the actually stored power supply signal, and the area marked by the dashed line corresponds to the high-level pulse information in the original power supply signal.

[0026] As an example, the read control unit reads the power supply signal from the memory control unit at times t1, t2, and t3. When the memory control unit does not control the storage strategy of the power supply signal, that is, when the memory control unit detects the power supply signal containing low-level pulse information, it directly writes the power supply signal in the low-level state to the preset memory area. When the power supply signal containing high-level pulse information is detected, the power supply signal in the high-level state is written to the preset memory area. Then, the power supply signal stored in the preset memory area is consistent with the original power supply signal, as shown in Fig. 5. The process of energy signal transmission in the power system is shown in Fig. 5. The reading control unit incorrectly reads the pulse signal at times t1 and t3, so that the power supply signal cannot be stably transmitted to the load.

[0027] In steps 201 to 203, the read control unit does not write the power supply signal in the low-level state into the preset memory area if the duration of the power supply signal containing low-level pulse information is short (i.e., not longer than the first preset duration). Instead, the power supply signal in the high-level state is continuously written into the preset memory area. If the power supply signal containing low-level pulse information continues for a long time (i.e., longer than the first preset duration), the low-level pulse signal is written into the preset memory area, and the power supply signal stored in the preset memory area can be maintained in the high-level state at this time. Fig. 6. The power supply signal transmission process in the power supply system is Fig. 6. When the read control unit reads the power supply signal at times t1, t2, and t3, the power supply signal can be stably maintained in the high-level state, and the power supply signal can be stably transmitted to the load to maintain the load impedance. When the duration of the low-level pulse information is longer than the preset time, the power supply signal can also be written in the low-level state to allow the read control unit to correctly read the shutdown information, which contributes to improving the operational reliability of the matching circuit.

[0028] In a specific implementation, the memory controller may be, for example, a field-programmable gate array (FPGA). The preset memory area may be the FPGA's memory, and the read controller may be, for example, an STM32 core single-chip microcomputer. Of course, the device selection here is only an example illustration, and the specific device selection of the memory controller and read controller in practical applications is not limited to this.

[0029] In one conceivable example, the method further comprises: maintaining a power supply signal in the high level state written into the preset memory area within the second preset duration when the power supply signal comprising high level pulse information is received from the power supply, wherein the second preset duration is not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time.

[0030] In the specific implementation, it is provided that the memory control unit writes the power supply signal in the high-level state into the preset memory area only within the duration of the power supply signal of the reception of the high-level pulse information, and upon receiving no power supply signal of the high-level pulse information, the power supply signal in the high-level state is no longer written into the preset memory area, but writes the power supply information in the low-level state, so that if the duration of the power supply signal in the high-level state is shorter than the time at which the power supply signal is read from the preset memory area during the next reading by the control unit, then the power supply signal in the low-level state can be read during the next reading of the power supply signal by the reading control unit,thereby impairing the reliability of the matching circuit. By setting a second preset duration that is not less than the time interval between the next reading of the power supply signal by the read control unit and the current time, the time for writing the high-level power supply signal into the preset memory area after the read control unit detects the high-level pulse information is extended by the second preset duration, so that the end time of the high-level power supply signal stored in the preset memory area is later than the end time of the high-level pulse in the original power supply signal input by the power supply. The time interval between the end time of the high-level power supply signal stored in the preset memory areaand the end time of the high-level pulse in the original power supply signal input by the power supply is the second preset duration, and the power supply signal in the high-level state can still be accurately obtained when the reading control unit reads the power supply signal next time.

[0031] Thus, it can be seen that in the present example, when the memory control unit detects the power supply signal containing high-level pulse information, it continuously writes the power supply signal in the high-level state into the preset memory area within the second preset duration not less than the time interval between the next reading of the power supply signal by the read control unit and the current time, so that the power supply signal in the high-level state can be stably read when the read control unit reads the power supply signal next time to perform the pulse operation and improve the reliability of the operation of the matching circuit.

[0032] In one conceivable example, it is provided that the reading control unit reads a power supply signal from the memory control unit at an interval of a third preset duration; wherein the second preset duration is not less than the greater of the third preset duration and a fourth preset duration, wherein the fourth preset duration is the operating duration of the device from the start of the reading of the power supply signal by the reading control unit until the actual reading of the power supply signal by the reading control unit.

[0033] In the specific implementation, the read control unit may periodically read the power supply signal from the memory control unit. The second preset duration may be determined according to the time interval between each read of the power supply signal by the read control unit and the periodic operation delay when the read control unit reads the power supply signal.

[0034] At this time, if the reading period of the power supply signal read by the reading control unit (i.e., the third preset time) is longer than the operation delay of the reading control unit itself (i.e., the fourth preset time), then the period for writing the power supply signal in the high-level state (i.e., the second preset time) is extended to be not less than the reading period (i.e., the third preset time). Conversely, if the reading period of the power supply signal read by the reading control unit is shorter than the operation delay of the reading control unit itself, the time period for writing the power supply signal in the high-level state (the second preset period) is extended to be not less than the operation delay of the reading control unit itself (the fourth preset period).

[0035] In the specific implementation, the preset duration with the larger value in the third preset duration and the fourth preset duration can be set to be not less than N times the other preset duration (N is a positive integer greater than 1, and the specific value can be preset by the user), or, when the third preset duration and the fourth preset duration do not belong to the same order of magnitude, the second preset duration is not less than the preset duration of the third preset duration and the fourth preset duration, where the value of N can be set as needed, and there is no specific limitation here.That is, when the values ​​of the third preset duration and the fourth preset duration are very different, the delay caused by the smaller duration is negligible, simplifying the working strategy of the reading control unit. For example, if the third preset duration is in the microsecond range and the fourth preset duration is in the millisecond (ms) range, the second preset duration is set to no less than the fourth preset duration.

[0036] If the third preset duration and the fourth preset duration are of the same order of magnitude and the larger preset duration is not less than N times the smaller preset duration (e.g., if N is 9 and the duration of the fourth preset duration is 6 times the third preset duration), the second preset duration may be set to be not less than the sum of the third preset duration and the fourth preset duration.

[0037] It can be seen that in the present example, the read control unit reads a power supply signal from the memory control unit at an interval of a third preset duration, the second preset duration being not less than the greater of the third preset duration and the fourth preset duration, the fourth preset duration being the operating time of the device from the start of the read control unit reading the power supply signal to the actual reading of the power supply signal by the read control unit. This is conducive to ensuring that the read control unit stably reads the power supply signal in the high-level state and further improving the reliability of the matching circuit.

[0038] It will be Fig. 7, which shows a schematic flow diagram of another pulse signal processing method according to an embodiment of the present application. The pulse signal processing method can be applied to the matching circuit according to Fig. 2, wherein the adaptation circuit comprises the memory control unit and a read control unit, wherein the memory control unit is used to detect a power supply signal from a power supply and to write it into an internal preset memory area, wherein the read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and to transmit it to a load; the method comprising: Step S301. Maintaining a power supply signal in the high-level state written into the preset memory area within the second preset duration when the power supply signal including high-level pulse information is received from the power supply, wherein the second preset duration is not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time.

[0039] Thus, it can be seen that in the embodiment of the present application, when the memory control unit receives a power supply signal containing high-level pulse information from the power supply, it maintains writing a high-level state to the preset memory area within the second preset duration, which is not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time. That is,After the memory control unit receives the power supply signal containing high-level pulse information, it extends the time of writing the pulse signal in the high-level state into the preset memory area, so that the next time the read control unit reads the power supply signal from the preset memory area, it can still accurately read the power supply signal in the high-level state, which improves the reliability of the operation of the matching circuit.

[0040] In one conceivable example, it is provided that the reading control unit reads a power supply signal from the memory control unit at an interval of a third preset duration; wherein the second preset duration is not less than the greater of the third preset duration and a fourth preset duration, wherein the fourth preset duration is the operating duration of the device from the start of the reading of the power supply signal by the reading control unit until the actual reading of the power supply signal by the reading control unit.

[0041] It can be seen that in the present example, the read control unit reads a power supply signal from the memory control unit at an interval of a third preset duration, the second preset duration being not less than the greater of the third preset duration and the fourth preset duration, the fourth preset duration being the operating time of the device from the start of the read control unit reading the power supply signal to the actual reading of the power supply signal by the read control unit. This is conducive to ensuring that the read control unit stably reads the power supply signal in the high-level state and further improving the reliability of the matching circuit.

[0042] In one conceivable example, the method further comprises: detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; maintaining a power supply signal in the high-level state, which is written to the preset memory area, if this is not the case; writing a power supply signal in the low-level state to the preset memory area.

[0043] It can be seen that in this example, when the memory control unit reads the power supply signal containing low-level pulse information, only in the case of the duration of the power supply signal containing low-level pulse information higher than the first preset duration, the power supply signal in the low-level state is written into the preset memory area, which is conducive to ensuring that the read control unit can stably read the high-level pulse information when reading the power supply signal and further improving the reliability of the matching circuit.

[0044] It will be Fig. 8, which shows a functional module block diagram of a pulse signal processing device according to an embodiment of the present application. The pulse signal processing device 60 can be adapted to the matching circuit according to Fig. 2, wherein the matching circuit comprises the memory control unit and a read control unit, wherein the memory control unit is used to detect a power supply signal from a power supply and store it in an internal preset memory area, and wherein the read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and send it to a load; wherein the pulse signal processing device 60 comprises: a detection module 601 for detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; a first write module 602 for maintaining a power supply signal in the high level state, which is written into the preset memory area when this is not the case; a second write module 603 for writing a power supply signal in the low level state into the preset memory area, if so.

[0045] In one conceivable example, the pulse signal processing device 60 is further used for: maintaining a power supply signal in the high-level state, which is written into the preset memory area, within a second preset duration when a power supply signal including high-level pulse information is received from the power supply, wherein the second preset duration is not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time.

[0046] In one conceivable example, it is provided that the reading control unit reads a power supply signal from the memory control unit at an interval of a third preset duration; wherein the second preset duration is not less than the greater of the third preset duration and a fourth preset duration, wherein the fourth preset duration is the operating duration of the device from the start of the reading of the power supply signal by the reading control unit until the actual reading of the power supply signal by the reading control unit.

[0047] It will be Fig. 9, which shows a functional module block diagram of another pulse signal processing device according to an embodiment of the present application. The pulse signal processing device 70 can be adapted to the matching circuit according to Fig. 2, wherein the matching circuit comprises the memory control unit and a read control unit, wherein the memory control unit is used to detect a power supply signal from a power supply and store it in an internal preset memory area, and wherein the read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and send it to a load; wherein the pulse signal processing device 70 comprises: a writing module 701 for maintaining a power supply signal in the high-level state written into the preset memory area within a second preset duration when a power supply signal including high-level pulse information is received from the power supply, the second preset duration being not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time.

[0048] In one conceivable example, it is provided that the reading control unit reads a power supply signal from the memory control unit at an interval of a third preset duration; wherein the second preset duration is not less than the greater of the third preset duration and a fourth preset duration, wherein the fourth preset duration is the operating duration of the device from the start of the reading of the power supply signal by the reading control unit until the actual reading of the power supply signal by the reading control unit.

[0049] In one conceivable example, the pulse signal processing device 70 is further used for the following: detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; maintaining a power supply signal in the high-level state and writing it to the preset memory area if this is not the case; writing a power supply signal in the low-level state to the preset memory area if this is the case.

[0050] All relevant contents of the individual scenarios relating to the above method embodiments can be cited for functional description of the corresponding functional module and are not repeated here.

[0051] The above-mentioned pulse signal processing device 60 can perform the steps described by the memory control unit in the Fig. 3 above. The above-mentioned pulse signal processing device 70 can execute the steps that the memory control unit in the Fig. 7 above.

[0052] It should be understood that in the embodiments of the present disclosure, the size of the sequence numbers of the above processes does not imply the execution order, and the execution order of each process is determined by its function and internal logic and does not impose any limitation on the implementation of the embodiments of the present disclosure.

[0053] In the embodiments of the present application, it is understood that the disclosed methods, devices, and systems could be implemented in other ways. The above device embodiments have been described only schematically. For example, the subdivision of the modules is based solely on their logical functions. In practical implementation, the subdivision may be implemented in other ways. For example, several modules or assemblies may be combined with one another or integrated into another system. Alternatively, some features may be omitted or need not be implemented. Furthermore, a coupling or a direct coupling or communication connection between displayed or discussed objects may be an indirect coupling and communication connection or an electrical, mechanical, or other connection via some interfaces, devices, or modules.

[0054] Modules described as separate parts may, but need not, be physically separate. A component depicted as a module may, but need not, be a physical module. This means that both an arrangement at a single location and distribution across multiple network units are conceivable. Depending on actual needs, some or all of these modules may be selected to achieve the purpose of the embodiments.

[0055] Furthermore, in the embodiments of the invention, individual functional modules can be integrated into a processing module. Alternatively, the individual modules can be physically separate or integrated into a module in pairs or more. The integrated modules can be implemented both in the form of hardware and in the form of hardware and software functional modules.

[0056] Finally, it should be emphasized that the present application is not limited to the above-mentioned embodiments, and preferred embodiments of the present application have been described so far, which in no way serve to limit the application. Any modifications, equivalent substitutions, and improvements within the spirit and principle of the application are intended to be included within the scope of the application.

Claims

A pulse signal processing method, characterized in that it is applied to a memory control unit of a matching circuit, the matching circuit comprising the memory control unit and a read control unit, the memory control unit being used to detect a power supply signal from a power supply and write it into an internal preset memory area, the read control unit being used to read a power supply signal stored in the preset memory area from the memory control unit and transmit it to a load; the method comprising:detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply;Maintaining a power supply signal in the high-level state, which is written to the preset memory area if this is not the case, Writing a power supply signal in the low-level state to the preset memory area if this is the case, Wherein, if the power supply is a fixed-frequency power supply, the first preset duration is not less than the time interval between the high-level end time of the previous pulse generated by the fixed-frequency power supply and the high-level start time of the next pulse, and Wherein, if the power supply is a variable-frequency power supply, the first preset duration is not less than the maximum value in the time interval between the high-level end time of the previous pulse generated by the variable-frequency power supply and the high-level start time of the next pulse.; A method according to claim 1, characterized in that the method further comprises:maintaining a power supply signal in the high level state, which is written into the preset memory area, within a second preset duration when a power supply signal comprising high level pulse information is received from the power supply, wherein the second preset duration is not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time. A method according to claim 2, characterized in that the reading control unit reads a power supply signal from the memory control unit at an interval of a third preset duration; wherein the second preset duration is not less than the greater of the third preset duration and a fourth preset duration, wherein the fourth preset duration is the operating duration of the device from the start of the reading of the power supply signal by the reading control unit until the actual reading of the power supply signal by the reading control unit. A pulse signal processing method, characterized in that it is applied to a memory control unit of a matching circuit, the matching circuit comprising the memory control unit and a read control unit, the memory control unit being used to detect a power supply signal from a power supply and store it in an internal preset memory area, the read control unit being used to read a power supply signal stored in the preset memory area from the memory control unit and send it to a load;the method comprising:maintaining a power supply signal in the high-level state written into the preset memory area within the second preset duration when the power supply signal including high-level pulse information is received from the power supply, the second preset duration being not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time;wherein the read control unit reads a power supply signal from the memory control unit at an interval of a third preset duration;wherein the second preset duration is not less than the greater of the third preset duration and a fourth preset duration, wherein the fourth preset duration is the operating duration of the device from the start of the reading of the power supply signal by the reading control unit until the actual reading of the power supply signal by the reading control unit; wherein the greater of the third preset duration and the fourth preset duration is not less than N times the other preset duration, where N is greater than 1, or wherein the amounts of the third preset duration and the fourth preset duration are not of the same order of magnitude.; A method according to claim 4, characterized in that the method further comprises:writing a power supply signal in the low level state into the preset memory area if this is the case. A pulse signal processing device, characterized in that it is applied to a memory control unit of a matching circuit, the matching circuit comprising the memory control unit and a read control unit, the memory control unit being used to detect a power supply signal from a power supply and store it in an internal preset memory area, and the read control unit being used to read a power supply signal stored in the preset memory area from the memory control unit and send it to a load; the device comprising: a detection module for detecting whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply;a first write module for maintaining a power supply signal in the high level state, which is written into the preset memory area when this is not the case; a second write module for writing a power supply signal in the low level state into the preset memory area when this is the case; A pulse signal processing device, characterized in that it is applied to a memory control unit of a matching circuit, the matching circuit comprising the memory control unit and a read control unit, the memory control unit being used to detect a power supply signal from a power supply and store it in an internal preset memory area, and the read control unit being used to read a power supply signal stored in the preset memory area from the memory control unit and send it to a load;the apparatus comprising:a writing module for maintaining a power supply signal in the high-level state, which is written into the preset memory area, within a second preset duration when a power supply signal including high-level pulse information is received from the power supply, the second preset duration being not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time; Adaptation circuit, characterized in that it comprises a memory control unit and a read control unit that are electrically connected to each other; wherein the memory control unit serves to detect whether the duration of a power supply signal containing low-level pulse information is longer than a first preset duration when the power supply signal containing low-level pulse information is received from the power supply; to maintain a high-level power supply signal written into the preset memory area if this is not the case; and to write a low-level power supply signal into the preset memory area if this is the case; wherein the read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and to send it to a load;wherein, when the power supply is a fixed-frequency power supply, the first preset duration is not less than the time interval between the high-level end time of the previous pulse generated by the fixed-frequency power supply and the high-level start time of the next pulse, and wherein, when the power supply is a variable-frequency power supply, the first preset duration is not less than the maximum value in the time interval between the high-level end time of the previous pulse generated by the variable-frequency power supply and the high-level start time of the next pulse.; A matching circuit, characterized in that it comprises a memory control unit and a read control unit that are electrically connected to each other; wherein the memory control unit is used to maintain a power supply signal in the high-level state, which is written into the preset memory area within the memory control unit, within a second preset duration when a power supply signal including high-level pulse information is received from the power supply, the second preset duration being not less than the time interval between the time at which the power supply signal is next read by the control unit and the current time; wherein the read control unit is used to read a power supply signal stored in the preset memory area from the memory control unit and send it to a load;wherein the reading control unit reads a power supply signal from the memory control unit within an interval of a third preset duration; wherein the second preset duration is not less than the greater amount of the third preset duration and a fourth preset duration, wherein the fourth preset duration is the operating duration of the device from the start of reading the power supply signal by the reading control unit until the actual reading of the power supply signal by the reading control unit; wherein the greater amount of the third preset duration and the fourth preset duration is not less than N times the other preset duration, wherein N is greater than 1, or wherein the amounts of the third preset duration and the fourth preset duration do not belong to the same order of magnitude.;

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