Rear contact with flat placeholder and easy rear semiconductor removal

Abstract

A semiconductor structure comprises a first source-drain region; a second source-drain region; at least one channel region coupling the first and second source-drain regions together; and a gate adjacent to the at least one channel region. A lower dielectric isolation region is disposed inside the gate. First and second lower silicon regions are disposed inside the first and second source-drain regions, respectively. A backside contact extends through the second lower silicon region into the second source-drain region.

Description

BACKGROUND

[0001] The present invention relates generally to electrical, electronic and computer technologies and, more particularly, to backside contacts for use with backside power distribution networks (BSPDNs).

[0002] A power supply network provides power and reference voltage to the active components on a semiconductor chip; this power supply network is essentially a network of interconnects separate from the signal network. Historically, both power and signal networks were fabricated on the front side of the wafer using back-end-of-line (BEOL) processes. Recently, BSPDNs have been developed, which provide power from the back side of the wafer and are typically formed during back-side wafer processing. SUMMARY

[0003] Principles of the invention provide techniques for a shallow placeholder backside contact with simple backside semiconductor removal. In one aspect, an exemplary semiconductor structure includes a first source-drain region; a second source-drain region; at least one channel region coupling the first and second source-drain regions together; a gate adjacent to the at least one channel region; a lower dielectric isolation region inboard of the gate; first and second lower silicon regions disposed inboard of the first and second source-drain regions, respectively; and a backside contact extending through the second lower silicon region into the second source-drain region.

[0004] In another aspect, an exemplary semiconductor array structure comprises a plurality of field effect transistors, each comprising a first source-drain region, a second source-drain region, at least one channel region coupling the first and second source-drain regions together, a gate adjacent to the at least one channel region, a lower dielectric isolation region inside the gate, and first and second lower silicon regions each disposed inside the first and second source-drain regions, respectively.Also included are a backside power distribution network; a frontside wiring network; a plurality of contacts interconnecting the frontside wiring network and the plurality of first source-drain regions; and a plurality of backside contacts, each extending through a corresponding one of the second lower silicon regions into a corresponding one of the second source-drain regions and each connected to the backside power distribution network.

[0005] In yet another aspect, an exemplary method of fabricating a semiconductor structure comprises providing a precursor structure comprising a nanolayer stack exterior to an epitaxially grown high SiGe content layer and an epitaxially grown low SiGe content layer on an underlying substrate; removing the high SiGe content layer and forming a bottom dielectric isolation (BDI) region in a region exposed by the high SiGe content layer; forming two sacrificial dummy structures at least partially within the epitaxially grown low SiGe content layer and forming source-drain regions exterior to the two sacrificial dummy structures;and forming middle-of-line (MOL) and back-end-of-line (BEOL) structures outside the precursor structure and bonding a carrier wafer outside the BEOL structures. The method further comprises flipping the carrier wafer and removing the substrate, stopping on the low-SiGe content layer; removing the low-SiGe content layer selectively from the BDI and the sacrificial placeholder structure; forming a backside interlayer dielectric (ILD) region inside the BDI; forming a backside contact opening at least in the backside ILD to expose one of the sacrificial placeholder structures; and forming the backside contact within the backside contact opening.

[0006] As used herein, "facilitating" an act includes performing the act, facilitating the act, assisting in performing the act, or causing the act to be performed. Thus, for example, and not by way of limitation, software executing on a processor may facilitate an act to be performed by semiconductor manufacturing equipment by sending appropriate data or instructions to perform or assist in performing the act. If an actor facilitates an act without performing the act itself, the act is still performed by some entity or combination of entities.

[0007] The techniques disclosed herein may provide significant advantageous technical effects. Some embodiments may not have these potential advantages, and these potential advantages are not required for all embodiments. For example, and without limitation, one or more embodiments may provide one or more of the following advantages: ▪ the possibility of forming a relatively large back contact without short circuit; ▪ the backside contact can be formed without the need for difficult deep reactive ion etching processes; ▪ including a backside dielectric insulating layer to reduce sub-channel leakage currents and / or to increase the performance of a field effect transistor; ▪ easier removal of the substrate from the back; ▪ Source / Drain (S / D) epitaxial deposition is easier from a flat Si placeholder because now the S / D epitaxy grows not only from Si nanosheets but also from the top surface of the Si placeholder.

[0008] These and other features and advantages will become apparent from the following detailed description of exemplary embodiments, which should be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following drawings are given by way of example only and without limitation, with like reference numerals (where used) designating corresponding elements in the several views, namely: Fig. 1A, Fig. 1B and Fig. 1C are cross-sectional views of a semiconductor structure taken along lines X, Y1 and Y2, respectively, in Fig. 14D, according to one aspect of the invention; Fig. 2A, Fig. 2B and Fig. 2C are cross-sectional views of a precursor for fabricating the semiconductor structure taken along lines X, Y1 and Y2, respectively, in Fig. 2D, according to one aspect of the invention; Fig. 3A-12C show exemplary subsequent steps for fabricating the semiconductor structure, wherein views “A”, “B” and “C” are taken along lines X, Y1 and Y2, respectively, in Fig. 2D, according to aspects of the invention; Fig. 13A-13C show an exemplary subsequent step for manufacturing the semiconductor structure, wherein views “A”, “B” and “C” are taken along lines X, Y1 and Y2, respectively, in Fig. 13D, according to aspects of the invention; Fig. 14A-20C show exemplary subsequent steps for fabricating the semiconductor structure, wherein views “A”, “B” and “C” are taken along lines X, Y1 and Y2, respectively, in Fig. 14D, according to aspects of the invention; and Fig. Figure 21 shows exemplary signal and power connections according to aspects of the invention.

[0010] It should be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or required in a commercially viable embodiment may not be shown to provide a less obscured view of the illustrated embodiments. DETAILED DESCRIPTION

[0011] The inventive principles described herein are explained in the context of exemplary embodiments. Furthermore, those skilled in the art will appreciate, in light of the teachings herein, that numerous modifications may be made to the illustrated embodiments within the scope of the claims. That is, no limitations are intended or should be inferred with respect to the embodiments shown and described herein.

[0012] In modern semiconductor structures, a self-aligned backside contact is desirable to mitigate a tight overlay tolerance on the wafer backside. However, a self-aligned backside contact requires sophisticated process modules, such as forming a dummy structure, removing backside Si selectively from a dummy, and the like. One or more embodiments are advantageous for self-aligned direct backside contact (DBC) implementations of a BSPDN.

[0013] Fig. 20A, Fig. 20B and Fig. 20C are cross-sectional views of a semiconductor structure taken along lines X, Y1 and Y2, respectively, in Fig. 14D, according to one aspect of the invention. Line "X" indicates a transverse gate view, while lines "Y1" indicate a longitudinal gate view, and lines "Y2" indicate transverse source / drain (S / D) views. Below gate 243 is bottom dielectric isolation (BDI) region 229. Below epitaxially grown source / drain (S / D) regions 239 is an epitaxially grown Si layer 237 (commonly a sacrificial dummy structure, also referred to as Si epitaxy / Epi and first and second bottom silicon regions). The bottom surface of epitaxially grown Si layer 237 is deeper than that of BDI 229.A backside contact 265 has an asymmetric profile and includes a lower portion 265A (also referred to herein as a "narrow protruding cut region") that "cuts" into the epitaxially grown Si layer 237 as well as the overlying S / D epitaxy 239 (also referred to herein as "epitaxially grown source / drain (S / D) regions"). In one or more implementations, the top surface of the shallow trench isolation (STI) region 223 underlies the gate 243 above the bottom surface of the BDI 229 (see FIG. Fig. 1B). In some cases, the top of the STI 223 under the S / D epitaxy 239 lies below the bottom of the BDI 229 (compare Fig. 1C with Fig. 1B). In some embodiments, a portion of the backside interlayer dielectric (ILD) region 255 remains between the backside contact 265 and the BDI 229 (see Fig. 1A).

[0014] An exemplary process flow according to the invention is described below. In one or more embodiments, a method for fabricating a semiconductor structure comprises forming a nanolayer stack 207, 209, 211, 213, 215, 217 (also referred to herein as "nanosheets") over an epitaxially grown high SiGe content layer 205 and an epitaxially grown low SiGe content layer 203 (see, e.g., Fig. 2A) (here also referred to as SiGe55 layer and low-SiGe layer / SiGe30 respectively); the removal of the layer with high SiGe content (see e.g. Fig. 6A) and the training of the BDI 229 (see e.g. Fig. 7A); forming a sacrificial placeholder structure 237 under the S / D region within the low-SiGe layer 203 (see, e.g., Fig. 9A); forming middle-of-line (MOL) and back-end-of-line (BEOL) structures and connecting a carrier wafer 251 (see, e.g., Fig. 14A); turning the wafer over and removing the substrate 201, stopping on the low-SiGe layer 203 (see, e.g., Fig. 15A). The method further includes removing the low-SiGe layer 203 selectively from the BDI 229 and the sacrificial placeholder structure 237 (see, e.g., Fig. 16A); forming the backside ILD 255 (see e.g. Fig. 17A); forming a backside contact opening (also referred to herein as a "trench") 257 to expose a sacrificial placeholder structure 237 (see, e.g., Fig. 18A and Fig. 18C); the removal of the sacrificial placeholder structure (see e.g. Fig. 19A and Fig. 19C); and forming the back contact 265 (see, e.g., Fig. 20A and Fig. 20C).

[0015] Referring now to Fig. 2A-2D, an initial structure is shown comprising a silicon wafer / substrate 201. A SiGe30 (30% Ge) layer 203 is located outside the silicon wafer 201. A SiGe55 layer 205 is located outside the SiGe30 layer 203. Alternating layers of SiGe30 207, 211, 215 and Si 209, 213, 217 follow outside the SiGe55 (55% Ge) layer 205. Fig. 2A, Fig. 2B and Fig. 2C are views along the lines X, Y1 and Y2 respectively in Fig. 2D. The top view Fig. 2D shows polycrystalline silicon dummy gates 219 (see Fig. 4A and Fig. 4B) and the structured nanosheets 225 (see Fig. 3B and Fig. 3C). Regarding layer 203, it should be noted that known selective etching processes (such as wet etching processes) can remove more than 2 µm of Si thickness (i.e., change or delta in thickness), with less than 5 nm loss of SiGe30. The Ge percentage for all SiGe layers is exemplary. In general, layer 205 may contain SiGe with a Ge content of 40-75%, while layers 203, 207, 211, 215 may contain SiGe with a Ge content of 15-35%. One skilled in the art is familiar with the fabrication of nanosheet transistors, including preferential / selective etching of SiGe with different Ge contents, and can prepare precursor structures as described in Fig. 2A-2C. In general, layers 203, 207, 211, 215 have a sufficiently lower Ge content than layer 205 to enable preferential / selective etching.

[0016] Fig. 3A, Fig. 3B and Fig. 3C are views along the lines X, Y1 and Y2 respectively in Fig. 2D and show the structures from Fig. 2A-2C after nanosheet (NS) patterning and the formation of the shallow trench isolation (STI) region. Note the patterned nanosheets 225 and STI 223. One skilled in the art is familiar with the use of lithography and etching and can implement the desired patterning using the teachings provided herein. Suitable materials for STI 223 include, for example, silicon oxide (SiOx).

[0017] Fig. 4A, Fig. 4B and Fig. 4C are views along the lines X, Y1 and Y2 respectively in Fig. 2D and show the structures from Fig. 3A-3C after the formation of the dummy gates. Note the dummy gates 219 and the hard mask 227. For example, amorphous Si (a-Si) material for the dummy gates 219 is deposited and planarized; gate hard mask material 227 (may be a multilayer dielectric) is deposited; the hard mask 227 is patterned, and the a-Si is etched to form the dummy gates 219.

[0018] Fig. 5A, Fig. 5B and Fig. 5C are views along lines X, Y1 and Y2 respectively in Fig. 2D and show the structures from Fig. 4A-4C after oxide etching to reduce the height of the exposed shallow trench isolation region (as in Fig. 5C) (for example, using reactive ion etching (RIE)).

[0019] Fig. 6A, Fig. 6B and Fig. 6C are views along the lines X, Y1 and Y2 respectively in Fig. 2D and show the structures from Fig. 5A-5C after the selective removal of the SiGe55 205. For example, the SiGe55 205 is removed selectively from SiGe30 203, 207, 211, 215; Si 201, 209, 213, 217; the dummy gates 219; and the hard mask 227. A gas-phase HCl process, for example, can be used for this purpose. At this point, there are no gates; furthermore, the structure is not "floating"—all nanosheets 207, 209, 211, 213, 215, 217 are attached to the polycrystalline silicon dummy gates 219 located on the shallow trench isolation region 223, so they are stable.

[0020] Fig. 7A, Fig. 7B and Fig. 7C are views along the lines X, Y1 and Y2 respectively in Fig. 2D and show the structures from Fig. 6A-6C after spacer / BDI formation, nanosheet (NS) etchback, SiGe notching, and formation of the inner spacer liner 231. Specifically, the area left exposed by the selective removal of the SiGe55 205 is filled with the bottom dielectric isolation region 229; the nanosheets 207, 209, 211, 213, 215, 217 are etched back; the SiGe30 layers 207, 211, 215 are notched; the inner spacer liner 231 is introduced into the areas where the SiGe30 layers 207, 211, 215 were notched, and the gate spacers 233 are formed. Also noted are the trenches 235. Also noted is the “hat-shaped” form of the BDI 229 above the SiGe30 layer 203, as in Fig. 7C. Non-limiting examples of suitable materials for elements 229, 231, 233 are SiBCN, SiN, SiOCN, SiOC, SiON, and the like. Those skilled in the art who are familiar with the fabrication of nanosheet transistors can, based on the teachings herein, determine the structure from Fig. 6 to process the structure from Fig. 7. See further, for example, commonly assigned U.S. Patent 10,903,315 to Nicolas Loubet et al., FORMATION OF DIELECTRIC LAYER AS ETCH-STOP FOR SOURCE AND DRAIN EPITAXY DISCONNECTION.

[0021] Fig. 8A, Fig. 8B and Fig. 8C are views along the lines X, Y1 and Y2 respectively in Fig. 2D and show the structures from Fig. 7A-7C after etching through the trenches 235 of Fig. 7A-7C to open the BDI 229 and etch back the SiGe30 203, creating deeper trenches 235A. For example, RIE with appropriate chemistry can be used to etch the BDI selectively over elements 231 and 233, followed by a selective wet etch to etch the SiGe30.

[0022] Fig. 9A, Fig. 9B and Fig. 9C are views along the lines X, Y1 and Y2 respectively in Fig. 2D and show the structures from Fig. 8A-8C after epitaxial growth of Si 237 (doped or undoped) from bottom to top. The expert is familiar with techniques for epitaxial growth of silicon on SiGe30 and techniques for doping silicon.

[0023] Fig. 10A, Fig. 10B and Fig. 10C are views along the lines X, Y1 and Y2 respectively in Fig. 2D and show the structures from Fig. 9A-9C after epitaxial growth of the source-drain regions 239. The person skilled in the art is familiar with techniques for epitaxially growing source-drain regions on epitaxially grown Si as well as techniques for doping silicon.

[0024] Fig. 11A, Fig. 11B and Fig. 11C are views along lines X, Y1 and Y2 respectively in Fig. 2D and show the structures from Fig. 10A-10C after deposition of the interlayer dielectric (ILD) 241 and performing chemical mechanical polishing (CMP) or other suitable planarization. A non-limiting example of a suitable material for the ILD is silicon oxide.

[0025] Fig. 12A, Fig. 12B and Fig. 12C are views along lines X, Y1 and Y2 respectively in Fig. 2D and show the structures from Fig. 11A-11C after removal of the dummy gates and exposure of the SiGe30 layers 207, 211, 215. The person skilled in the art knows the removal of dummy (e.g., a-Si) gates and sacrificial SiGe layers 207, 211, 215. The Si nanosheets 209, 213, 217 do not “float,” but are anchored by the inner spacer liner 231, the gate spacers 233, and the S / D regions 239, as in Fig. 12A can be seen.

[0026] Fig. 13A, Fig. 13B and Fig. 13C are views along lines X, Y1 and Y2 respectively in Fig. 13D and show the structures from Fig. 12A-12C after the formation of high-K metal gate stacks (HKMG) 243 and the formation of gate cuts 245. Fig. 13D corresponds to Fig. 2D with the additional depiction of the gate cuts 245. Those skilled in the art will be familiar with the "dummy gate" process for forming HKMGs 243. The gate cuts 245 can be formed by lithography, etching, and filling. Suitable materials for the gate cuts 245 include SiN, SiO2, SiBCN, SiOCN, SiOC, SiC, or combinations thereof.

[0027] Fig. 14A, Fig. 14B and Fig. 14C are views along lines X, Y1 and Y2 respectively in Fig. 14D and show the structures from Fig. 13A-13C after the formation of middle-of-line (MOL) contacts 247, 248; after the formation of back-end-of-line (BEOL) layers 249; and after bonding a carrier wafer 251. Fig. 14D corresponds to Fig. 13D with the additional depiction of the MOL contacts 247, 248. The person skilled in the art is familiar with the formation of BEOL layers, including metallization, via, and dielectric layers. The person skilled in the art is familiar with the formation of MOL contacts using lithography, etching, and filling; a metal such as copper or the like is suitable. The person skilled in the art is familiar with devices and techniques for connecting a carrier wafer 251 (e.g., silicon, glass) to the BEOL layers 249, such as by oxide-oxide bonding.

[0028] Fig. 15A, Fig. 15B and Fig. 15C are views along lines X, Y1 and Y2 respectively in Fig. 14D and show the structures from Fig. 14A-14C after flipping the wafer and removing the Si substrate 201, stopping the removal on the shallow trench isolation region 223 and the SiGe30 layer 203. For illustration, the structures in Fig. 15A-15C in the same orientation as in Fig. 14A-14C, but as indicated by arrow 253, they have been "flipped" by 180 degrees; that is, in a typical process, the structures in Fig. 14A-14C the carrier wafer 251 above the Si substrate 201 with respect to the earth's gravity, while the structures in Fig. 15A-15C, the carrier wafer 251 is located below the other elements with respect to Earth's gravity, although wafer 251 is shown at the top of the drawings. Those skilled in the art are familiar with devices and techniques for flipping wafers and massively removing silicon material from substrate 201. Advantageously, in this step, all source-drain regions or gates are well protected by SiGe, which provides a good etch stop layer for Si removal (this prevents damage to the S / D epitaxy or gates during Si removal).

[0029] Fig. 16A, Fig. 16B and Fig. 16C are views along the lines X, Y1 and Y2 respectively in Fig. 14D and show the structures from Fig. 15A-15C after the selective removal of the SiGe30 layer 203 from the shallow trench isolation region 223, the BDI 229, and the Si epitaxy 237. Known techniques can be used for the selective removal of SiGe30 from Si.

[0030] Fig. 17A, Fig. 17B and Fig. 17C are views along the lines X, Y1 and Y2 respectively in Fig. 14D and show the structures from Fig. 16A-16C after deposition of the backside interlayer dielectric (FIG.) 255 and planarization such as CMP. A non-limiting example of a suitable material for the FIG. is silicon oxide.

[0031] Fig. 18A, Fig. 18B and Fig. 18C are views along lines X, Y1 and Y2 respectively in Fig. 14D and show the structures from Fig. 17A-17C after backside contact lithography, wherein trench 257 is etched into the IG 255 and the shallow trench isolation region 223. This may be done, for example, using suitable lithography and etching techniques such as reactive ion etching (RIE). Advantageously, the critical dimension (e.g., diameter) of the backside contact to be formed in trench 257 may be large (e.g., larger than the bottom dimension of Si epitaxy 237—in one non-limiting example, the size of the backside contact may be approximately half the gate pitch). In one or more embodiments, as long as the overlay is less than 15 nm, the backside contacts to be formed in trench 257 will not cause a short circuit to the adjacent Si epitaxy 237. Furthermore, lithography overlay means the ability of a lithography system to create precise structures on each layer exactly where they should be.In one or more embodiments, this is acceptable as long as trench 257 is not opened to the adjacent Si epi, thus not creating a short circuit between adjacent FETs. Furthermore, in one or more embodiments, the backside contact RIE does not need to be deep to reach BDI 229, which may be weak as a contact etch stop.

[0032] Fig. 19A, Fig. 19B and Fig. 19C are views along lines X, Y1 and Y2 respectively in Fig. 14D and show the structures from Fig. 18A-18C after optionally etching back the Si epitaxy 237 adjacent to the trench 257 (for example, if it is not heavily doped) to form additional recesses 261, 263 within the trench 257. A suitable method includes, for example, wet etching of Si. This etch-back process can increase the silicide area (i.e., the area of ​​the trench 257 that is lined with a silicide prior to contact formation). It should be noted that without this optional etch-back step, no "cut-in region" would be created. However, even without the "cut-in region," the critical dimension (CD) of the backside contact is advantageously increased, and the backside contact does not touch the BDI.

[0033] Fig. 20A, Fig. 20B and Fig. 20C are views along lines X, Y1 and Y2 respectively in Fig. 14D and show the structures from Fig. 19A-19C after backside contact metallization to form backside contact 265. In one or more embodiments, contact 265 includes a silicide liner, such as Ti, NiTi, NiPt, etc.; a thin metallic adhesion liner, such as TiN; and a low-resistance metallic fill, such as W, Co, Ru, etc.

[0034] Fig. 1A, Fig. 1B and Fig. 1C are views along the lines X, Y1 and Y2 respectively in Fig. 14D and show the structures from Fig. 20A-20C after formation of the backside power distribution network layers 267. In one or more embodiments, the BSPDN layers 267 include more than one layer of metal lines and vias therebetween. The metal lines and vias are filled with metals such as Co, Cu, Al, etc., and include adhesion liners such as TaN or TiN. Those skilled in the art are familiar with the formation of BSPDN layers, including metal wiring layers, vias, and dielectric material.

[0035] As a non-limiting example, conductive / metal structures may include a silicide liner, such as Ni, Ti, NiPt, etc.; a thin metallic adhesion layer, such as TiN or TaN; and a conductive metal fill, such as Ru, W, Co, or Cu. Suitable materials for STI liners include, for example, SiCO, SiOCN, and silicon nitride (SiN). Suitable materials for the STI include, for example, silicon oxide (SiOx); the STI may be deposited using, for example, high-density plasma (HDP) deposition, chemical vapor deposition (CVD), etc.

[0036] For example, with reference to Fig. 1A, a field-effect transistor (FET) includes a first source-drain region (left 239), a second source-drain region (right 239), one or more channel regions (e.g., Si nanosheets 209, 213, 217), and a gate 243 surrounding the channel regions. The FET may be a nanosheet FET and may have n-type (with n-type S / D regions) or p-type (with p-type S / D regions) characteristics. An array of FETs may be provided; for example, both n-type and p-type (complementary metal oxide semiconductor or CMOS).

[0037] For clarification, each source-drain region 239 in Fig. 1C belongs to another device that runs in a perpendicular direction (into or out of the sheet). Accordingly, aspects of the invention include a semiconductor array structure having a plurality of field-effect transistors, for example, arranged in rows. In one non-limiting example, as explained above, a CMOS array is provided with adjacent n-type and p-type FETs. Inverters or other types of CMOS logic gates may be formed. Those skilled in the art will be familiar with CMOS inverters and other CMOS logic gates. In such an inverter, a pFET source is connected to the power rail VDD and a pFET drain is connected to the drain of an nFET. The source of the nFET is connected to ground / VSS. The gates of the nFET and pFET are coupled and form an input that receives a signal. The coupled drains of the nFET and pFET form the output node.One or more embodiments further include a signal source coupled to the front-side wiring network and a power supply coupled to the rear-side power distribution network. A non-limiting specific example is shown in FIG. Fig. 21: In one or more embodiments, the array structure includes a first signal source (e.g., clock signal 2406), a logic signal source 2408, and a power supply (e.g., power supply 2402 (VDD) and ground terminal 2404 (VSS)). Element 2400 generally represents a single device or an array of devices according to any of the disclosed embodiments. Power connections are generally provided via appropriate contact structures to source / drain terminals, while signal connections are generally provided via appropriate contact structures to gates. The power supply may, for example, come from the BSPDN layers 267. Signals may, for example, be provided from the front-side wiring network 249, which may also include power supply lines. VDD, for example, denotes the power pin connection to pFETs, while VSS, for example, denotes the power pin connection to nFETs.

[0038] In one or more embodiments, the front metal structures taper toward the front with a larger cross-section, while the back metal structures taper toward the back with a larger cross-section.

[0039] As mentioned above, with Si epitaxial layer 237, the critical dimension of the backside contact can be large, and as long as the overlay is less than 15 nm, there will be no short circuit to the neighboring Si epi. Furthermore, the RIE for forming the backside contact does not need to be deep to reach BDI 229, which can be weak as a contact etch stop. Advantageously, BDI 229 is provided to improve semiconductor operation by reducing sub-channel leakage currents and increasing performance. Furthermore, with SiGe layer 203 beneath the nanosheets and SiGe55 layer, the process for removing the backside Si substrate can be better controlled, with less risk of damage to the S / D and gate if the BDI has a pinhole.In fact, the SiGe layer 203 beneath the BDI 229 serves as a buffer layer during Si substrate removal to prevent potential damage to the S / D and gate in case a pinhole is present in the BDI. Advantageously, the "cut-in" profile of the backside contact can increase the silicide area.

[0040] Based on the previous explanation and with reference to Fig. 1A-1C, it can be seen that, in one aspect, an exemplary semiconductor structure comprises a first source-drain region (left 239), a second source-drain region (right 239), and at least one channel region 209, 213, 217 coupling the first and second source-drain regions together. Also included are a gate 243 adjacent to the at least one channel region, a lower dielectric isolation region 229 inboard of the gate, and first and second lower silicon regions 237 disposed inboard of the first and second source-drain regions, respectively. The structure further comprises a backside contact 265 extending through the second lower silicon region into the second source-drain region.

[0041] In one or more embodiments, the back contact 265 has an asymmetric profile when viewed in cross-section ( Fig. 1A and Fig. 1C).

[0042] In one or more embodiments, the semiconductor structure further comprises a backside power distribution network 267 inside the backside contact. The backside contact is connected to the backside power distribution network.

[0043] In at least some cases, the semiconductor structure further comprises a front-side wiring network 249 on a front side of the semiconductor structure (which may be formed, for example, using BEOL processes and therefore bears the same reference numeral as the BEOL layers) and a contact 247 interconnecting the front-side wiring network and the first source-drain region.

[0044] In one or more embodiments, the bottom surface of the Si epitaxial layer 237 is deeper than the BDI 229. In other words, an innermost surface of each of the first and second lower silicon regions extends further toward the inside than an innermost surface of the lower dielectric isolation region

[0045] In this context, "inside" means toward the bottom of the view, while "outside" means toward the top of the view.

[0046] One or more embodiments further include a shallow trench isolation region 223 inboard of the gate and the first and second source-drain regions. In at least some cases, the STI height below the gate 243 is above the bottom of the BDI 229. In other words, an outermost surface of the shallow trench isolation region 223 inboard of the gate 243 extends farther outward than the innermost surface of the bottom dielectric isolation region.

[0047] In at least some cases, the STI height under the S / D epitaxy is below the bottom of the BDI. In other words, an outermost surface of the shallow trench isolation region 223 inside the first and second source-drain regions 239 is further toward the inside than the innermost surface of the bottom dielectric isolation region 229.

[0048] In one or more embodiments, a portion of the backside interlayer dielectric region 255 remains between the backside contact and the BDI. One or more embodiments further include the backside interlayer dielectric region 255 inside the lower dielectric isolation region 229. In one or more embodiments, the backside contact has an inner wide region and a narrow protruding kerf region 265A that protrudes through the second lower silicon region into the second source-drain region. A portion of the backside interlayer dielectric region 255 is located between an outermost surface of the inner wide region and the innermost surface of the lower dielectric isolation region, as shown in Fig. 1A. The incision region is offset from a central axis of the inner broad area when viewed in cross section, as in Fig. 1A and Fig. 1C can be seen.

[0049] In some cases, the first and second lower silicon regions 237 extend inwardly into the backside interlayer dielectric region 255.

[0050] The gate 243 may, for example, be a gate-all-around high-K metal gate forming the at least one channel region provided by the nanosheets 209, 213, 217 (the channel region acts as a conductive channel when the gate is driven).

[0051] In one or more embodiments, the back contact 265 does not contact the lower dielectric isolation region 229.

[0052] In one or more embodiments, the backside contact 265 has a maximum diameter that is larger than a maximum diameter of the second lower silicon region 237.

[0053] In another aspect, an exemplary semiconductor array structure comprises a plurality of field effect transistors, each comprising a first source-drain region, a second source-drain region, at least one channel region coupling the first and second source-drain regions, a gate adjacent to the at least one channel region, a lower dielectric isolation region inside the gate, and first and second lower silicon regions each disposed inside the first and second source-drain regions, respectively, as just described.The plurality of field-effect transistors is arranged, for example, in rows, and the array further comprises a backside power distribution network 267; a frontside wiring network 249; a plurality of contacts 247 interconnecting the frontside wiring network and the plurality of first source-drain regions; and a plurality of backside contacts 265, each extending through a corresponding one of the second lower silicon regions 237 into a corresponding one of the second source-drain regions 239 and each connected to the backside power distribution network 267. One or more embodiments further comprise a signal source coupled to the frontside wiring network and a power supply coupled to the backside power distribution network (see FIG. Fig. 21).

[0054] In one or more embodiments, each back contact has an asymmetric profile when viewed in cross section.

[0055] In one or more embodiments, the plurality of backside contacts 265 do not contact the lower dielectric isolation region 229 and / or the plurality of backside contacts 265 each have a maximum diameter that is greater than a maximum diameter of the second lower silicon region 237.

[0056] In one or more embodiments, a maximum diameter of the plurality of backside contacts is approximately half the distance between adjacent gates (thus, the size of the backside contact may be approximately half the gate pitch).

[0057] In another aspect, an exemplary method of fabricating a semiconductor structure includes providing a precursor structure comprising a nanolayer stack 207, 209, 211, 213, 215, 217 outside an epitaxially grown high SiGe content layer 205 and an epitaxially grown low SiGe content layer 203 on an underlying substrate 201 (see, e.g., Fig. 2A). A further step involves removing the layer with high SiGe content (see e.g. Fig. 6A) and forming the bottom dielectric isolation region (BDI) 229 in an area left vacant by the high SiGe content layer (see, e.g., Fig. 7A). A still further step comprises forming two sacrificial placeholder structures 237 at least partially within the epitaxially grown low SiGe content layer 203 and forming source-drain regions 239 outside the two sacrificial placeholder structures 237 (see, e.g., Fig. 9A and Fig. 10A).

[0058] A further step comprises the formation of middle-of-line (MOL) contacts (e.g. 247) and back-end-of-line (BEOL) structures 249 outside the precursor structure and the connection of a carrier wafer 251 outside the BEOL structures (see e.g. Fig. 14A). With reference to Fig. 15A-15C, the carrier wafer is flipped and the substrate 201 is removed, stopping on the low SiGe content layer 203. The low SiGe content layer 203 is removed selectively from the BDI 229 and the sacrificial placeholder structure 237 (see, e.g., Fig. 16A). The backside interlayer dielectric (ILD) 255 (see e.g. Fig. 17A).

[0059] A further step comprises forming a backside contact opening 257 at least in the backside ILD to expose one of the sacrificial placeholder structures 237 (see, e.g., Fig. 18A and Fig. 18C). Optionally, at least part of the exposed sacrificial placeholder structure is removed (see, e.g., Fig. 19A and Fig. 19C). The rear contact 265 (see e.g. Fig. 20A and Fig. 20C) is formed within the back contact opening.

[0060] In one or more embodiments, in the step of forming the backside contact openings and in the step of removing the at least partially exposed sacrificial placeholder part, a central axis of the at least partially exposed sacrificial placeholder part is offset from a central axis of the backside contact openings (cf. Fig. 1A and Fig. 1C).

[0061] One or more embodiments further include forming gates 243 between the source-drain regions surrounding channel portions of the nanolayer stacks (see Fig. 13A-13C).

[0062] The fabrication of semiconductor devices involves various steps of patterning and structuring processes. For example, the fabrication of a semiconductor chip may begin with a plurality of CAD (computer-aided design)-generated device patterns, followed by an effort to replicate these device patterns in a substrate. The replication process may involve the use of various exposure techniques as well as a variety of subtractive (etching) and / or additive (deposition) material processing steps. For example, in a photolithographic process, a layer of photoresist material may first be applied to a substrate and then selectively exposed according to a predetermined device pattern or patterns. Areas of the photoresist exposed to light or other ionizing radiation (e.g., UV, electron beams, X-rays, etc.) may experience changes in their solubility in certain solutions.The photoresist can then be developed in a developer solution, removing the unexposed (for negative resists) or exposed (for positive resists) areas of the resist layer to create a photoresist pattern or photomask. The photoresist pattern or photomask can then be transferred to the underlying substrate.

[0063] There are numerous techniques used by those skilled in the art to remove material during various stages of semiconductor structure fabrication. Throughout this document, these processes are generally referred to as "etching." For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques; all of these are well-known methods for removing selected materials during semiconductor structure formation. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. The techniques and applications of etching are well known to those skilled in the art, so a more detailed description of these processes is not provided here.

[0064] Although the overall manufacturing process and the structures formed thereby are novel, certain individual process steps required to carry out the process may utilize conventional semiconductor manufacturing techniques and equipment. These techniques and equipment will be familiar to those skilled in the art based on the teachings herein. For example, those skilled in the art will be familiar with epitaxial growth, the formation of self-aligned contacts, the formation of high-K metal gates, and the like. The term "high-K" has a distinct meaning for those skilled in the art in the context of high-K metal gate (HKMG) stacks and is not merely a relative term. In addition, one or more of the process steps and equipment used in the manufacture of semiconductor devices are also described in a number of readily available publications, including: James D.Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1. st Edition, Prentice Hall, 2001, and PH Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, both of which are hereby incorporated by reference. It should be emphasized that the individual process steps given here are merely examples, and those skilled in the art will recognize several equally suitable alternatives that could be applied.

[0065] It should be acknowledged that the various layers and / or areas depicted in the attached figures are not necessarily drawn to scale. Fig. 1A, Fig. 1B and Fig.However, in Figure 1C, for example, the relative heights / thicknesses of the various layers are representative throughout the figures. Furthermore, one or more semiconductor layers of the type commonly used in such integrated circuit devices may not be explicitly depicted in a given figure for ease of explanation. This does not imply that the semiconductor layers not explicitly depicted are absent from the actual integrated circuit device.

[0066] Those skilled in the art will appreciate that the exemplary structures discussed above may be distributed in raw form (i.e., a single wafer with multiple unpackaged chips), as bare die, in packaged form, or as components of intermediate or final products.

[0067] An integrated circuit according to aspects of the present inventions may be used in substantially any application and / or electronic system. Given the teachings provided herein, those skilled in the art will be able to contemplate further implementations and applications of the embodiments disclosed herein.

[0068] The illustrations of the embodiments described herein are provided for a general understanding of the various embodiments and are not intended to be a complete description of all elements and features of devices and systems that may employ the circuits and techniques described herein. Many other embodiments will be apparent to those skilled in the art from the teachings provided herein; other embodiments are utilized and derived therefrom, so that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. It should also be noted that in some alternative implementations, some of the steps of the example methods need not occur in the order presented in the figures.For example, two steps shown in sequence may actually be performed almost simultaneously, or certain steps may sometimes be performed in reverse order depending on the functionality involved. Furthermore, the drawings are merely schematic and not to scale. Accordingly, the description and drawings should be considered illustrative rather than restrictive.

[0069] Embodiments are referred to herein individually and / or collectively with the term "embodiment" merely for convenience and without intent to limit the scope of this application to a single embodiment or inventive concept if more than one is actually shown. Although specific embodiments have been illustrated and described herein, it is to be understood that an arrangement achieving the same purpose may be substituted for the specifically shown embodiment(s); thus, this disclosure is intended to cover any adaptations or modifications of the various embodiments. Combinations of the foregoing embodiments and other embodiments not expressly described herein will become apparent to those skilled in the art from the teachings provided herein.

[0070] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly requires otherwise. Further, it is understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of the stated features, steps, operations, elements, and / or components without excluding the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Terms such as "below," "above," "over," "on," "below," and "below" are used to indicate the relative arrangement of elements or structures to one another, not an absolute elevation.When a layer of a structure is described herein as being "on top of" another layer, it is understood that one or more intermediate elements or layers may or may not be present between the two specified layers. When a layer is described as being "directly on top of" another layer, this means direct contact of the two layers. As used herein and in the appended claims, "about" means within plus or minus ten percent.

[0071] The corresponding structures, materials, steps, and equivalents of any means or step-plus-function elements in the following claims are intended to include any structure, material, or act that performs the function in combination with the other claimed elements as expressly claimed. The description of the various embodiments has been presented for purposes of illustration and description and is not exhaustive or limited to the forms disclosed. Many changes and variations will be apparent to those skilled in the art without departing from the scope thereof. The embodiments were chosen and described in order to best explain principles and practical applications and to enable others skilled in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.

[0072] The abstract is provided to satisfy the requirements of 37 CFR § 1.76(b), which requires an abstract that enables the reader to quickly appreciate the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Further, the foregoing detailed description indicates that various features are grouped together in a single embodiment to streamline the disclosure. This manner of disclosure should not be construed to imply that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims indicate, the claimed subject matter may include fewer than all of the features of a single embodiment.Therefore, the following claims are hereby incorporated into the Detailed Description, with each claim being considered as separately claimed subject matter.

[0073] Given the teachings provided herein, one skilled in the art will be able to contemplate further implementations and applications of the techniques and disclosed embodiments. Although exemplary embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the exemplary embodiments are not limited to these embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the appended claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 10 903 315

[0020] Cited non-patent literature

[0000] James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1 st Edition, Prentice Hall, 2001

[0064] PH Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008

[0064]

Claims

[1] A semiconductor structure comprising: a first source-drain region; a second source-drain region; at least one channel region coupling the first and second source-drain regions together; a gate adjacent to the at least one channel region; a lower dielectric isolation region inside the gate; first and second lower silicon regions, each disposed inside the first and second source-drain regions, respectively; and a backside contact extending through the second lower silicon region into the second source-drain region. [2] The semiconductor structure of claim 1, wherein the backside contact has an asymmetric profile when viewed in cross section. [3] The semiconductor structure of claim 2, further comprising a backside power distribution network inside the backside contact, wherein the backside contact is connected to the backside power distribution network. [4] The semiconductor structure of claim 3, further comprising: a front-side wiring network on a front side of the semiconductor structure; and a contact connecting the front-side wiring network and the first source-drain region. [5] The semiconductor structure of claim 4, wherein an innermost surface of each of the first and second lower silicon regions extends further toward the inside than an innermost surface of the lower dielectric isolation region. [6] The semiconductor structure of claim 5, further comprising a shallow trench isolation region inside the gate and the first and second source-drain regions, wherein an outermost surface of the shallow trench isolation region inside the gate extends further to the outside than the innermost surface of the lower dielectric isolation region. [7] The semiconductor structure of claim 5, further comprising a shallow trench isolation region inside the gate and the first and second source-drain regions, wherein an outermost surface of the shallow trench isolation region inside the first and second source-drain regions is further inside than the innermost surface of the lower dielectric isolation region. [8] The semiconductor structure of claim 5, further comprising a backside interlayer dielectric region inboard of the lower dielectric isolation region, wherein the backside contact has an inner wide region and a narrow protruding kerf region protruding through the second lower silicon region into the second source-drain region, wherein a portion of the backside interlayer dielectric region is disposed between an outermost surface of the inner wide region and the innermost surface of the lower dielectric isolation region, and wherein the narrow protruding kerf region is offset from a central axis of the inner wide region when viewed in cross section. [9] The semiconductor structure of claim 8, wherein the first and second lower silicon regions extend into the backside interlayer dielectric region. [10] The semiconductor structure of claim 5, wherein the gate comprises a gate-all-around high-K metal gate surrounding the at least one channel region. [11] The semiconductor structure of claim 1, wherein the backside contact does not contact the lower dielectric isolation region. [12] The semiconductor structure of claim 1, wherein the backside contact has a maximum diameter that is larger than a maximum diameter of the second lower silicon region. [13] A semiconductor array structure comprising: a plurality of field-effect transistors, each comprising a first source-drain region; a second source-drain region; at least one channel region coupling the first and second source-drain regions together; a gate adjacent to the at least one channel region; a lower dielectric isolation region inside the gate; and first and second lower silicon regions disposed inside the first and second source-drain regions, respectively; a rear power distribution network; a front-panel wiring network; a plurality of contacts interconnecting the front-side wiring network and the plurality of first source-drain regions; and a plurality of backside contacts, each of which extends through a corresponding one of the second lower silicon regions into a corresponding one of the second source-drain regions and is each connected to the backside power distribution network. [14] The semiconductor array structure of claim 13, wherein each backside contact has an asymmetric profile when viewed in cross section. [15] The semiconductor array structure of claim 13, wherein the plurality of backside contacts does not touch the lower dielectric isolation region; and the plurality of backside contacts each has a maximum diameter that is greater than a maximum diameter of the second lower silicon regions. [16] The semiconductor array structure of claim 13, wherein a maximum diameter of the plurality of backside contacts is half the distance between adjacent gates. [17] The semiconductor array structure of claim 13, further comprising: a signal source coupled to the front-panel wiring network; and a power supply coupled to the rear power distribution network. [18] A method of manufacturing a semiconductor structure, comprising: Providing a precursor structure comprising a nanolayer stack outside an epitaxially grown high SiGe content layer and an epitaxially grown low SiGe content layer on an underlying substrate; Removing the high SiGe layer and forming a bottom dielectric isolation region, BDI, in an area left vacant by the high SiGe layer; Forming two sacrificial placeholder structures at least partially within the epitaxially grown low SiGe content layer and forming source-drain regions outside the two sacrificial placeholder structures; Forming middle-of-line (MOL) structures and back-end-of-line (BEOL) structures outside the precursor structure and connecting a carrier wafer outside the back-end-of-line (BEOL) structures; Turning the carrier wafer over and removing the substrate, stopping on the low SiGe content layer; Removing the low SiGe content layer selectively from the lower dielectric isolation region, BDI, and the sacrificial placeholder structures; Forming a backside interlayer dielectric region, ILD, inside the bottom dielectric isolation region, BDI; Forming a backside contact opening at least in the backside interlayer dielectric region, ILD, to expose one of the sacrificial placeholder structures; and Forming the back contact within the back contact opening. [19] The method of claim 18, further comprising removing at least a portion of the exposed sacrificial placeholder structure, wherein in the step of forming the backside contact openings and in the step of removing the at least partially exposed sacrificial placeholder portion, a central axis of the at least partially exposed sacrificial placeholder portion is offset from a central axis of the backside contact openings. [20] The method of claim 19, further comprising forming gates between the source-drain regions surrounding channel portions of the nanolayer stacks.

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