METHOD FOR SEPARATING SEMICONDUCTOR DIES

Abstract

Methods for separating semiconductor dies are described. The method allows individual semiconductor dies (115) to be separated from a semiconductor wafer (110) without using a blade. The methods include a plasma etching process (155) using metal structures (145) formed on a backside of the wafer (110) as masks to remove a portion of the semiconductor wafer (110) from the backside. The portion removed by the plasma etching process (155) corresponds to the scribe lines (120) between the semiconductor dies (115). The plasma etching process (155) ends at a dielectric layer (125) formed on a frontside of the wafer (110). The dielectric layer (125) can be separated to complete the separation process. Furthermore, an ultrasonic waterjet process can be used to remove flash from the separated dielectric layer (125).

Description

The description relates generally to the field of semiconductor packaging and, in particular, to methods for separating semiconductor dies. BACKGROUND A semiconductor package is a metal, plastic, glass, or ceramic enclosure containing one or more semiconductor dies. The package provides conductive elements (e.g., leads) that connect the semiconductor dies to an external environment, such as a printed circuit board. Furthermore, the package protects the semiconductor dies from hazards such as mechanical shock or chemical contamination. Semiconductor dies are fabricated on semiconductor wafers before being singulated into individual dies and packaged. The singulation process requires that certain areas be reserved between the semiconductor dies, which may be referred to as scribe lines. The scribe lines are configured to accommodate different results related to the type of techniques used in singulation.Mechanical dicing techniques typically use a blade and face several challenges in reducing the area of a semiconductor wafer occupied by the scribe lines. SUMMARY Methods for separating semiconductor dies are described. This summary is not a comprehensive overview of the disclosure and is not intended to identify key or critical elements of the disclosure, nor to delimit the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the disclosure in a simplified form as a prelude to a more detailed description presented later. In some examples, a method comprises dividing a metal layer formed on a backside of a semiconductor substrate including a plurality of dies on a backside opposite the frontside, wherein a scribe region of the semiconductor substrate is exposed by dividing the metal layer; applying a plasma etching process configured to remove the scribe region, wherein a portion of a dielectric layer disposed on the frontside of the semiconductor substrate is exposed as a result of applying the plasma etching process; and separating the exposed portion of the dielectric layer. In some examples, a method comprises forming a sacrificial structure on a backside of a semiconductor substrate including a plurality of dies at a backside opposite the frontside, wherein the sacrificial structure covers a scribe region of the semiconductor substrate; forming a metal layer on the sacrificial structure and the backside of the semiconductor substrate uncovered by the sacrificial structure; removing the sacrificial structure and a portion of the metal layer formed on the sacrificial structure, wherein the scribe region is exposed as a result of removing the sacrificial structure; removing the scribe region of the semiconductor substrate, wherein a portion of a dielectric layer located on the frontside of the semiconductor substrate is exposed by removing the scribe region of the semiconductor substrate from the backside; and breaking off the exposed portion of the dielectric layer. In some examples, a semiconductor die comprises a semiconductor substrate including an integrated circuit arrangement on a front side of the semiconductor substrate; and a metal structure formed on a back side of the semiconductor substrate opposite the front side, wherein a sidewall profile of the semiconductor substrate includes a plurality of ridges. BRIEF DESCRIPTION OF THE DRAWINGS 1A to 1L illustrate steps of separating semiconductor dies in examples of the description; FIG. 2 is a three-dimensional schematic representation of a sacrificial structure formed on a semiconductor substrate in examples of the description; FIGS. 3A and 3B are a top view and a cross-sectional side view of a semiconductor substrate, respectively, in examples of the description; FIG. 4 is a three-dimensional schematic representation of semiconductor dies in examples of the description; FIGS. 5A and 5B are schematic cross-sectional representations of semiconductor dies in examples of the description; and FIGS. 6 and 7 are flowcharts illustrating methods of separating semiconductor dies, according to aspects of the description. DETAILED DESCRIPTION OF EXAMPLES OF WORKING MODES This specification is described with reference to the appended figures. The components in the figures are not drawn to scale. Instead, emphasis is placed on clearly illustrating the general features and principles of the specification. Numerous specific details and relationships are set forth with reference to exemplary examples of the figures in order to provide an understanding of the disclosure. The figures and examples are not intended to limit the scope of the specification to such exemplary examples, and other examples are possible by substituting or modifying at least some of the described or illustrated elements or process steps.Further, where elements of the description can be implemented partially or completely using known components or process steps, those parts of these components or process steps are described which facilitate an understanding of the description, and detailed descriptions of other parts of these components or process steps are omitted in order not to obscure the understanding of the disclosure. As used herein, terms such as "first" and "second" are used to arbitrarily distinguish between the elements those terms describe. These terms in the description and claims therefore do not indicate a temporal or other prioritization of such elements. Furthermore, terms such as "front," "back," "top," "bottom," "above," "below," "vertical," "horizontal," "lateral," "downward," "upward," "upper," "lower," or the like are used to describe the relative directions or positions of features in the semiconductor devices with respect to the orientation shown in the figures. For example, "top" or "uppermost" may refer to a feature that is closer to the top edge of a side than other features.The terms so used are interchangeable under appropriate circumstances, so that, for example, examples of the technology described herein may be used in orientations other than those illustrated or otherwise described herein. Semiconductor dies or devices, integrated circuit assemblies, or integrated circuit (IC) components described herein may be formed on a semiconductor substrate (or die) containing various semiconductor materials such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, silicon carbide, or the like. In some cases, the substrate refers to a semiconductor wafer. Various structures described herein may be formed using semiconductor process techniques. Layers containing various materials may be formed over a semiconductor substrate, for example, using deposition techniques (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating), thermal process techniques (e.g., oxidation, nitriding, epitaxy), and / or other suitable techniques.Similarly, some parts of the layers can be selectively removed, e.g., by etching techniques (e.g., plasma (or dry) etching, wet etching), chemical-mechanical planarization, and / or other suitable techniques, some of which can be combined with photolithography steps. Methods for separating semiconductor dies are described. The methods can separate (single or dice) individual semiconductor dies from a semiconductor wafer without using a blade (or saw) or a laser. Furthermore, the methods facilitate the formation of a metal layer on a backside of a semiconductor die (which may be referred to as backside metal (BSM)), which may be advantageous for certain semiconductor devices or applications—e.g., power field effector (FET) devices or applications. The methods do not require modifications to various structures present in the scribe lines, which may be referred to as scribe line structures. Furthermore, the methods can reduce the width of the scribe lines to be smaller than typical mechanical dicing processes require.The methods can enable the final substrate thickness to be reduced to less than typical mechanical dicing processes require to maintain the structural integrity of semiconductor dies. Reducing substrate thickness can be beneficial for certain semiconductor devices, e.g., reducing the electrical resistance between the source and drain (RDS) of a power FET. 1A to 1L illustrate various steps in separating semiconductor dies in examples of the description. Fig. 1A shows a semiconductor substrate 110 having a first surface 111 (top surface, front surface, top, front side) and a second surface 112 (bottom surface, back surface, bottom, back side) opposite the first surface 111. The semiconductor substrate 110 may be a semiconductor wafer with a thickness (denoted as T1) of about 600 to about 800 micrometers. The semiconductor substrate 110 may include a plurality of semiconductor dies 115 (also individually referred to as semiconductor dies 115a-c). Although the semiconductor substrate 110 is shown to include three semiconductor dies 115 for illustrative purposes, the semiconductor substrate 110 may include many more semiconductor dies 115, for example, several hundred semiconductor dies 115 or even more.The semiconductor substrate 110 (or the individual semiconductor dies 115) includes integrated circuitry (not shown) on the first surface 111. In some examples, the integrated circuitry includes a power FET or a circuit including one or more power FETs. The semiconductor substrate 110 includes scribe lines 120 (also individually referred to as scribe lines 120a / b)) between the semiconductor dies 115. The scribe lines (which may also be referred to as streets, dicing lanes, or the like) may have a width "W," as shown in Figure 1A. The scribe line width may be configured to accommodate various aspects of wafer dicing techniques. For example, mechanical dicing techniques that utilize a blade may require the scribe line width to be at least 80 micrometers or larger to accommodate a kerf width created by the blade and to account for undesirable mechanical effects on the semiconductor dies 115—e.g., cracks propagating toward integrated circuit assemblies or chipping at the edges of semiconductor dies.Chips during the mechanical dicing process can reach a size of about 30 micrometers or more. As described in more detail herein, the methods can separate the semiconductor dies 115 from the semiconductor substrate 110 with scribe line widths of about 50 micrometers, 30 micrometers, 20 micrometers, or even less (e.g., 10 micrometers or less). Fig. 1A also shows a dielectric layer 125 formed on the first surface 111 of the semiconductor substrate 110. The dielectric layer 125 may include one or more interlevel metallization or multilevel metallization (MLM) layers. For example, the dielectric layer 125 includes one or more conductive layers (e.g., 4 or 5 metallization layers), including aluminum or copper, and via structures (e.g., tungsten vias, copper vias) connecting the one or more conductive layers. The dielectric layer 125 also includes various dielectric layers that provide electrical insulation between the conductive layers, such as silicon oxides (e.g., SiO2), tetraethoxysilanes (TEOS), silicon nitrides (e.g., Si3N4), silicon oxynitrides (e.g., SiOxNy), or the like.The MLM layers of the dielectric layer 125 are connected to the integrated circuit arrangement of the corresponding dies 115. The dielectric layer 125, which corresponds to the scribe lines 120, may include various structures (which may also be referred to as scribe line structures) constructed with the MLM layers. For example, the scribe line structures may include inline electrical test structures, process monitoring structures (e.g., measuring critical dimensions or overlaps between layers, measuring thicknesses of different layers), and dummy fill features for process uniformity (e.g., during dry etching process steps, during chemical mechanical polishing process steps). Accordingly, the scribe line structures may include various metal layers or structures. The metal layers or structures present in the dielectric layer 125 may pose a challenge for using a laser or plasma process (e.g., laser dicing techniques, plasma dicing techniques) because the metal layers (or metal structures) may significantly hinder the laser or plasma dicing process. The laser or plasma dicing techniques may be considered advantageous over the mechanical dicing techniques (e.g., in reducing the scribe line width), but may require process modifications to remove the metal layers in the scribe line structures. As described in more detail herein, the methods may provide separation of the semiconductor dies 115 despite the scribe line structures (with or without metal layers). Fig. 1B shows the semiconductor substrate 110 thinned from the backside 112 to a final thickness (denoted as T2). In some examples, a first adhesive tape 130 (attached to a frame ring, not shown) may be attached to the dielectric layer 125. Subsequently, the semiconductor substrate 110 may be thinned (e.g., abraded) from the backside 112. The first adhesive tape 130 may be referred to as a sand-back (BG) tape. The final thickness of the semiconductor substrate 110 may be determined using dicing techniques used to separate individual semiconductor dies 115 from the semiconductor substrate 110. As with mechanical dicing techniques using a blade, the final thickness may be about 4 mils (i.e., about 100 micrometers) or greater to maintain various mechanical forces applied to the semiconductor substrate 110 during the mechanical dicing process. As described in more detail herein, the methods may provide a reduction in the final thickness of the semiconductor substrate 110 (e.g., less than 4 mils), at least in part due to the absence of the blade used to separate the semiconductor dies 115. For example, the final thickness (T2) of the semiconductor substrate 110 may be 3 mils, 2 mils, 1 mil, or even less. The reduced final thickness of the semiconductor substrate 110 (e.g., compared to the final thickness in mechanical dicing) may be advantageous for certain semiconductor devices or processes—e.g., B. a power FET device or a circuit containing one or more power FETs. Figs. 1C to 1F illustrate methods for forming BSM structures, each covering the backside of semiconductor die 115. The scribe lines 120 between semiconductor dies 115 are uncovered by the BSM structures, as shown in Fig. 1F. In other words, the scribe lines 120 are subjected to subsequent process steps—e.g., the plasma etching step described with reference to Fig. 1H. Fig. 1C shows that a second adhesive tape 135 (attached to a frame ring 136) is attached to the first adhesive tape 130. Subsequently, a sacrificial structure 140 may be formed on the backside 112 of the semiconductor substrate 110, as shown in Fig. 1D. The sacrificial structure 140 may be configured to cover the scribe lines 120. Fig. 2 illustrates a schematic three-dimensional (3D) representation of the sacrificial structure 140 covering the scribe area. In some examples, the sacrificial structure 140 may be formed based on a photolithography process. In such examples, the sacrificial structure 140 may include a photoresist. Fig. 1E shows that the first and second adhesive tapes 130 and 135 have been removed (peeled off) in preparation for the subsequent process steps. Fig. 1F shows that the BSM structures 145 (also individually identified as BSM structures 145a-c) are formed based on the sacrificial structure 140 on the backside 112 of the semiconductor substrate 110. For example, a metal layer may be deposited on the backside 112 of the semiconductor substrate 110 with the sacrificial structure 140. In other words, a metal layer may be formed on the sacrificial structure 140 and on the backside 112 of the semiconductor substrate 110, which is uncovered by the sacrificial structure 140. Subsequently, the sacrificial structure 140 may be removed, such that a portion of the metal layer formed on the sacrificial structure 140 is removed. In this way, the BSM structures 145 may be formed on the backside 112 of individual semiconductor dies 115. In some examples, the BSM structures 145 may be approximately one (1) to three (3) micrometers thick. The scribe lines 120 are exposed as a result of removing the sacrificial structure 140 (ie,are uncovered by BSM structures 145). The term "approximately" as used herein may in some cases refer to deviations of ±5% to ±10% of the stated values. In other cases, the term "approximately" may refer to deviations of ±10% to ±20% of the stated values. Although the above example process steps use a sacrificial structure (e.g., a photoresist structure) to divide the metal layer deposited on the backside 112 of the semiconductor substrate 110, the description is not limited thereto. For example, a capping metal layer may be deposited on the backside 112 of the semiconductor substrate 110 without forming a sacrificial structure. Subsequently, a photolithography process may be performed on the capping metal layer to cover the capping metal layer corresponding to the individual semiconductor dies 115. An etching process (e.g., a dry etching process) may be applied to the capping metal layer to remove a portion of the metal layer, thus exposing the scribe lines. Thereafter, the photoresist covering the metal layer corresponding to the individual semiconductor dies 115 may be removed to create the BSM structures 145 on the backside 112 of the semiconductor substrate 110, as shown in Fig. 1F.Fig. 1G shows that the semiconductor substrate 110 with the BSM structures 145 on its backside 112 is mounted on a third adhesive tape 150 (attached to a frame ring 151). Fig. 1H shows that a portion of the semiconductor substrate 110 is removed using a plasma etching process. The plasma etching process may have an etch selectivity configured to preserve the BSM structure 145. Furthermore, the plasma etching process may have an etch selectivity configured to preserve the dielectric layer 125. By applying the plasma etching process to the semiconductor substrate 110 from the backside 112, individual semiconductor dies 115 are separated (separated, singulated) from the semiconductor substrate 110. In other words, a portion of the semiconductor substrate 110 corresponding to the scribe lines 120 is removed by the flux 155 of the plasma etching process. However, the semiconductor dies 115 are interconnected by the dielectric layer 125.In this regard, the plasma etching process uses the BSM structures 145 as masks based on the etch selectivity to the BSM structures 145, which protect the semiconductor substrate 110 corresponding to the semiconductor dies 115 during the plasma etching process. Accordingly, one or more edges of the BSM structures 145 may be aligned with corresponding edges of the semiconductor substrate 110 of the semiconductor dies 115, as shown in Fig. 1H. In other words, one or more edges of the semiconductor substrate 110 of the semiconductor dies 115 may be self-aligned with the corresponding edges of the BSM structures 145. Furthermore, the semiconductor substrate 110 of the semiconductor dies 115 may have a cross-sectional area (i.e., a cross-sectional area substantially parallel to the backside 112 of the semiconductor substrate 110, a base area) that substantially corresponds to the cross-sectional area of the BSM structures 145—e.g.,no more than 5% difference, no more than 10% difference, no more than 15% difference or the like. Given the etch selectivity configured to preserve the dielectric layer 125, it may be assumed that the plasma etching process has been stopped when the dielectric layer 125 is exposed from the backside 112 as a result of removing the semiconductor substrate 110 from the main scribe line region. The etch selectivity toward the dielectric layer 125 may facilitate the handling of variations in the final thickness of the semiconductor substrate 110—e.g., variations in the final thickness T2 after the grind-back step, as shown in Fig. 1B. For example, it may be assumed that the plasma etching process has been stopped locally in a first region of the semiconductor substrate 110, while the plasma etching process is still actively proceeding in a second region of the semiconductor substrate 110, wherein the first region has a lower final thickness than the second region.In some examples, the plasma etching process may be applied for a predetermined time, e.g., a timed etching process. In other examples, the time for applying the plasma etching process may be dynamically determined based on determining a certain percentage of the exposed dielectric layer 125—e.g., an endpoint-controlled etching process. The plasma etching process may include alternating deposition steps and etching steps. The etching steps may be primarily configured to remove the semiconductor material of the semiconductor substrate 110, for example, by forming byproducts of the plasma etching process including the semiconductor material. Furthermore, the deposition steps may be primarily configured to deposit certain byproducts (which may be referred to as polymers) of the plasma etching process on the sidewalls of the semiconductor substrate 110. In this way, the sidewalls of the semiconductor substrate 110 that remain beneath the BSM structures 145 may be maintained substantially perpendicular to the backside 112 of the semiconductor substrate 110. In some examples, the plasma etching process includes fluorine (F)—e.g., a fluorine-based plasma etching process that generates the flux 155 containing F atoms. By alternating the etching steps and the deposition steps, the sidewall profiles of the semiconductor substrate 110 may be non-uniform (not shown in Fig. 1H), as described in more detail in Fig. 3B. In some examples, the non-uniform sidewall profiles include a plurality of raised lines that are substantially parallel to the backside 112 of the semiconductor substrate 110. In some examples, the non-uniform sidewall profiles include ribbed surfaces, wave-shaped surfaces, land-like surfaces, ridge-like surfaces, or a combination thereof. Fig. 1I shows that a fourth adhesive tape 160 (attached to a frame ring 161) is attached to the BSM structures 145 after completion of the plasma etching process described above with reference to Fig. 1H. Fig. 1I also shows the cutting of the third adhesive tape 150 (as shown by two triangles) to remove the frame ring 151. Fig. 1J shows that the remaining portion of the third adhesive tape 150 is removed (e.g., peeled off) from the dielectric layer 125. After removal of the third adhesive tape 150, the dielectric layer 125 exposed from the backside 112 is the only structure connecting individual semiconductor dies 110 together. Fig. 1K shows that the exposed portion of the dielectric layer 125 may be separated (broken off) by pulling the fourth adhesive tape 160, as indicated by two lateral arrows in opposite directions. The physical separation (breaking off) of the exposed portion of the dielectric layer 125 may be independent of whether the dielectric layer 125 corresponding to the scribe lines 120 includes any scribe line structures or whether the scribe line structures (if any) include a metal layer. Accordingly, the methods may provide for the separation of individual semiconductor dies 115 independent of any metal layers or structures in the scribe lines 120. As a result of separating (breaking off) the exposed portion of the dielectric layer 125, the dielectric layer 125 may include one or more portions 126 that extend beyond the edges of the semiconductor substrate 110 of individual semiconductor dies 115. The portions 126 may be considered freestanding beyond the edge of the semiconductor substrate 110 or overhanging a space not supported by the semiconductor substrate 110. In some cases, the portions 126 may be referred to as a ridge of the dielectric layer 125. In some examples, the semiconductor dies 115, including the burr 126, as shown in Fig. 1K, may be considered ready for the remaining steps of the assembly process—e.g., picking up from the adhesive tape 160 for mounting on a lead frame, forming wire bonds, forming a mold structure to protect the semiconductor dies 115, etc. For example, if the width of the scribe lines 120 is about 10 micrometers or less, the burr 126 may remain with the semiconductor dies 115—e.g., the ultrasonic waterjet process described with reference to Fig. 1L may be omitted. Furthermore, the approximately 10 micrometer (or less) wide scribe lines may not include scribe line structures (with or without a metal layer). Fig. 1L shows that the flash 126 of the dielectric layer 125 (or remnants of expansion residues) may be removed. Additionally, Fig. 4 shows a schematic 3D representation of the semiconductor dies 115 after the flash 126 has been removed. For example, an ultrasonic waterjetting process 165 may be used to remove the flash 126 of the dielectric layer 125. In some examples, the ultrasonic waterjetting process 165 includes subjecting a water stream to ultrasonic vibrations and pressure. In some examples, the ultrasonic vibrations may be approximately between 500 and 3,000 Hertz (Hz). In some examples, the pressure may be approximately between 10 and 40 pounds per square inch (psi). The semiconductor dies 115 shown in Fig. 1L are ready for the remaining steps of the assembly process, e.g.,Picking up the adhesive tape 160 for mounting on a lead frame, forming wire bonds, forming a mold structure to protect the semiconductor dies 115, etc. As described herein, separating the semiconductor dies 115 from the semiconductor substrate 110 eliminates the need for mechanical sawing (singling) of the semiconductor substrate 110 in examples of the description. Accordingly, the final thickness of the semiconductor substrate 110 may be reduced (thinner) to less than the typical thicknesses required by mechanical dicing techniques (e.g., about 4 mils to withstand mechanical stress). For example, the final thickness of the semiconductor substrate 110 (e.g., T2, described with reference to Fig. 1B) may be 3 mils, 2 mils, 1 mil, or even less. Furthermore, the thinner final thickness of the semiconductor substrate 110 is expected to provide additional benefits. For example, the thinner final thickness tends to reduce the aspect ratio for the plasma etching process described with reference to Fig. 1H—e.g., when the width of the scribe lines 120 is fixed. The reduced aspect ratio may make it easier to keep the sidewall profile substantially perpendicular to the backside of the semiconductor substrate 110. Furthermore, the thinner final thickness may help reduce the scribe line width, shorten the turnaround time for the plasma etching process, reduce the source-to-drain resistance of power FETs, or the like. Fig. 2 is a schematic three-dimensional (3D) illustration of a sacrificial structure (e.g., sacrificial structure 140) formed on a semiconductor substrate (e.g., semiconductor substrate 110) in examples of the description. As described above with reference to Fig. 1E, sacrificial structure 140 covers scribe lines 120 (a scribe area, a scribe surface) of semiconductor substrate 110. In some examples, sacrificial structure 140 includes a photoresist. As described above with reference to Fig. 1F, BSM structures may be formed on the backside 112 of semiconductor substrate 110 uncovered by sacrificial structure 140—i.e., the areas corresponding to semiconductor dies 115. 3A and 3B are a top view and a cross-sectional side view, respectively, of a semiconductor substrate (e.g., semiconductor substrate 110) in examples of the description. FIG. 3A can be considered a top view of the backside 112 of semiconductor dies 115 after completion of the plasma etching process described with reference to FIG. 1H. FIG. 3A shows two semiconductor dies 115a and 115b and the scribe line 120 therebetween. A portion of the semiconductor substrate 110 corresponding to the scribe line 120 has been removed by the plasma etching process. The backside 112 of the semiconductor dies 115a / b is covered with the BSM structures 145a and 145b, respectively. FIG. 3A also shows chips 370 formed on the BSM structures 145a / b as a result of the plasma etching process. The chips 370 may include an undercut of the BSM structures 145a / b.The chips 370 may extend unevenly from the edge of the BSM structures 145a / b inward toward the center of the semiconductor dies 115 to a distance C, as indicated in Figure 3A. In some examples, the distance C may vary between 1 and 3 micrometers after completion of the plasma etching process. Fig. 3B can be viewed as a cross-sectional side view near the backside 112 of the semiconductor substrate 110 after completion of the plasma etching process described with reference to Fig. 1H. Fig. 3B shows the BSM structure 145 and a portion of the semiconductor substrate 110 that is covered (protected) by the BSM structure 145 during the plasma etching process. Accordingly, at least one edge of the BSM structure 145 is aligned with a corresponding edge of the semiconductor substrate 110. Furthermore, the plasma etching process may form uneven sidewall profiles of the semiconductor substrate 110. The uneven sidewall profiles may be viewed as a result of the plasma etching process progressing (progressing) through the semiconductor substrate 110 by alternating multiple cycles of etching steps and deposition steps. The irregular sidewall profiles include valleys 375 (grooves) and lands 376 (ridges or raised lines relative to the valleys 375).Accordingly, the uneven sidewall profiles can be considered as ribbed surfaces and / or wavy surfaces. Fig. 4 is a schematic 3D representation of semiconductor dies (e.g., semiconductor die 115) in examples of the description. Fig. 4 can be viewed as a 3D perspective view showing the front side 111 of semiconductor dies 115 after completion of the ultrasonic waterjetting process described with reference to Fig. 1L. Fig. 4 shows corners of four semiconductor dies 115 and the scribe lines 120 therebetween. A portion of semiconductor substrate 110 corresponding to scribe lines 120 was removed by the plasma etching process described with reference to Fig. 1H. Furthermore, the burr 126 of dielectric layer 125 was removed by the ultrasonic waterjetting process described with reference to Fig. 1L. Accordingly, one or more edges of the dielectric layer 125 are aligned with the corresponding edges of the semiconductor substrate 110 of the semiconductor dies 115. The semiconductor die 115 of Fig.4 includes sealing ring structures 480 (which may be referred to as etch ring structures), each configured to surround the semiconductor die 115. After completion of the ultrasonic waterjet process, the semiconductor dies 115 are only attached to the fourth adhesive tape 160, as described with reference to FIG. 1L. Accordingly, the bottom of the scribe lines 120 may be considered the fourth adhesive tape 160. The uneven sidewall profiles of the semiconductor dies 115 are omitted from FIG. 4. 5A and 5B are schematic cross-sectional views of semiconductor dies (e.g., semiconductor die 115) in examples of the description. Fig. 5A can be viewed as a view of semiconductor die 115 shown in Fig. 1L separated from adhesive tape 160 after completion of the ultrasonic waterjet process to remove burr 126. Semiconductor die 115 includes a semiconductor substrate (e.g., semiconductor substrate 110) including integrated circuitry on a front side (e.g., front side 111) of the semiconductor substrate and a metal structure (e.g., BSM structure 145) formed on a back side (e.g., back side 112) of the semiconductor substrate opposite the front side. The semiconductor substrate includes a sidewall profile having a series of ridges (e.g., ridges 376). In some examples, the ridges run substantially parallel to the backside of the semiconductor substrate. In some examples, the ridges surround the semiconductor substrate. Furthermore, the sidewall profile may run substantially perpendicular to the backside of the semiconductor substrate. In some examples, the sidewall profile includes a ribbed surface, a wave-shaped surface, a raised surface, a crest-and-valley surface, or a combination thereof. In some examples, the metal structure includes at least one edge aligned with a corresponding edge of the semiconductor substrate. In some examples, the semiconductor substrate has a first cross-sectional area (base area) and the metal structure has a second cross-sectional area (base area) substantially corresponding to the first cross-sectional area. In some examples, the semiconductor die also includes a dielectric layer (e.g., dielectric layer 125) on the front side of the semiconductor substrate. The dielectric layer includes one or more interlevel metallization (MLM) layers. The MLM layers may be coupled to the integrated circuitry of the semiconductor die. In some examples, at least one edge of the dielectric layer is aligned with a corresponding edge of the semiconductor substrate. In some examples, the integrated circuitry includes a power FET. Fig. 5B can be viewed as a representation of the semiconductor die 115 shown in Fig. 1K separated from the adhesive tape 160 without the ultrasonic waterjetting process. Accordingly, the semiconductor die 115 shown in Fig. 5B includes at least one edge of the dielectric layer extending beyond a corresponding edge of the semiconductor substrate. Fig. 6 is a flowchart 600 illustrating methods for separating semiconductor dies according to aspects of the description. The flowchart 600 includes aspects of the methods described with reference to Figs. 1A through 4. The method includes dividing a metal layer formed on a backside of a semiconductor substrate including a plurality of dies on a frontside opposite the backside, wherein a scribe region of the semiconductor substrate is exposed as a result of dividing the metal layer (box 610). The method further includes applying a plasma etch process configured to remove the exposed scribe region, wherein a portion of a dielectric layer disposed on the frontside of the semiconductor substrate is exposed as a result of applying the plasma etch process (box 615). The method further includes separating the exposed portion of the dielectric layer (box 620). In some examples, the plasma etching process has an etch selectivity configured to preserve the metal layer. In some examples, the plasma etching process has an etch selectivity configured to preserve the dielectric layer. In some examples, the plasma etching process includes alternating deposition steps and etching steps. In some examples, the dielectric layer includes one or more interlevel metallization layers. In some examples, subdividing the metal layer forms a plurality of metal structures corresponding to the plurality of dies. In some examples, the plasma etching process uses the metal structures as masks that protect the semiconductor substrate. In some examples, each of the metal structures includes at least one edge aligned with an edge of a corresponding one of the dies. In some examples, non-uniform sidewall profiles of individual dies of the plurality are formed by applying the plasma etching process. In some examples, the non-uniform sidewall profiles include a plurality of raised lines that are substantially parallel to the backside of the semiconductor substrate. In some examples, the non-uniform sidewall profiles are substantially perpendicular to the backside of the semiconductor substrate. In some examples, the non-uniform sidewall profiles include ridged surfaces, wavy surfaces, land-like surfaces, crest-and-valley surfaces, or a combination thereof. In some examples, the method further includes applying an ultrasonic waterjetting process configured to remove flash of the dielectric layer based on separating the exposed portion of the dielectric layer. In some examples, the ultrasonic waterjetting process includes subjecting a water stream to ultrasonic vibrations and pressure, wherein the ultrasonic vibrations are between about 500 and 3000 Hertz (Hz) and the pressure is between about 10 and 40 pounds per square inch (psi). In some examples, the method further includes attaching an adhesive tape to a first surface of the dielectric layer opposite a second surface exposed to the plasma etching process, wherein separating the exposed portion of the dielectric layer includes expanding the adhesive tape attached to the first surface of the dielectric layer.In some examples, the method further includes thinning the semiconductor substrate from the backside prior to forming the metal layer on the backside of the semiconductor substrate. In some examples, dividing the metal layer includes removing a sacrificial structure located between the metal layer and the scribe region of the semiconductor substrate. In some examples, the sacrificial structure includes a photoresist. In some examples, dividing the metal layer includes forming a plurality of mask patterns on the metal layer corresponding to the plurality of dies, and removing a portion of the metal layer uncovered by the plurality of mask patterns to expose the scribe region of the semiconductor substrate. Fig. 7 is a flowchart 700 illustrating methods for separating semiconductor die according to aspects of the description. The flowchart 700 includes aspects of the methods described with reference to Figs. 1A through 4. The method includes forming a sacrificial structure on a backside of a semiconductor substrate including a plurality of dies at a front side opposite the backside, wherein the sacrificial structure covers a scribe region of the semiconductor substrate (box 710). The method further includes forming a metal layer on the sacrificial structure and the backside of the semiconductor substrate uncovered by the sacrificial structure (box 715). The method further includes removing the sacrificial structure and a portion of the metal layer formed on the sacrificial structure, wherein the scribe region is exposed as a result of removing the sacrificial structure (box 720).The method further includes removing the scribe region of the semiconductor substrate, wherein a portion of a dielectric layer located on the front side of the semiconductor substrate is exposed as a result of removing the scribe region of the semiconductor substrate from the back side (box 725). The method further includes breaking off the exposed portion of the dielectric layer (box 730). In some examples, the sacrificial structure includes a photoresist. In some examples, removing the portion of the metal layer forms a plurality of metal structures corresponding to the plurality of dies. In some examples, each of the metal structures includes at least one edge aligned with an edge of a corresponding one of the dies. In some examples, removing the scribe region of the semiconductor substrate includes applying a plasma process having alternating deposition steps and etching steps. In some examples, removing the scribe region of the semiconductor substrate forms non-uniform sidewall profiles of individual dies of the plurality. In some examples, the non-uniform sidewall profiles include a plurality of raised lines that run substantially parallel to the backside of the semiconductor substrate. In some examples, the uneven sidewall profiles are substantially perpendicular to the backside of the semiconductor substrate. In some examples, the exposed portion of the dielectric layer includes one or more interlevel metallization layers. In some examples, the method further includes removing flash from the broken-off portion of the dielectric layer. In some examples, removing the flash includes using an ultrasonic water jetting process that applies ultrasonic vibrations and pressure to a water stream, where the ultrasonic vibrations are between about 500 and 3000 Hertz (Hz) and the pressure is between about 10 and 40 pounds per square inch (psi). In some examples, the method further includes thinning the semiconductor substrate from the backside prior to forming the sacrificial structure on the backside of the semiconductor substrate. In some examples, the method further includes attaching an adhesive tape to the dielectric layer after removing the scribe region of the semiconductor substrate, wherein breaking off the exposed portion of the dielectric layer includes expanding the adhesive tape attached to the dielectric layer. Although various examples of the specification have been described above, they have been presented only by way of example and not by way of limitation. Numerous changes to the described examples may be made in the present disclosure without departing from the spirit or scope of the specification. Moreover, while various features or components have been shown to have particular arrangements or configurations in the illustrated examples, other arrangements and configurations are possible. Furthermore, aspects of current technology described in connection with the exemplary examples may be combined or omitted in other examples. Therefore, the breadth and scope of the specification should not be limited by any of the examples described above.

Claims

[1] Method comprising: Dividing a metal layer formed on a back side of a semiconductor substrate including a plurality of dies on a front side opposite to the back side, wherein a scribe region of the semiconductor substrate is exposed as a result of dividing the metal layer; Applying a plasma etching process configured to remove the exposed scribe region, wherein a portion of a dielectric layer disposed on the front side of the semiconductor substrate is exposed as a result of applying the plasma etching process; and Separating the exposed portion of the exposed dielectric layer. [2] The method of claim 1, wherein the plasma etching process has an etch selectivity configured to preserve the metal layer. [3] The method of claim 1, wherein the plasma etching process has an etch selectivity configured to preserve the dielectric layer. [4] The method of claim 1, wherein the plasma etching process includes alternating deposition steps and etching steps. [5] The method of claim 1, wherein the dielectric layer includes one or more interlevel metallization layers. [6] The method of claim 1, wherein dividing the metal layer forms a plurality of metal structures corresponding to the plurality of dies. [7] The method of claim 6, wherein the plasma etching process uses the metal structures as masks that protect the semiconductor substrate. [8] The method of claim 6, wherein each of the metal structures includes at least one edge aligned with an edge of a corresponding one of the dies. [9] The method of claim 1, wherein the application of the plasma etching process forms non-uniform sidewall profiles of individual dies of the plurality. [10] The method of claim 9, wherein the non-uniform sidewall profiles include a plurality of raised lines substantially parallel to the backside of the semiconductor substrate. [11] The method of claim 9, wherein the non-uniform sidewall profiles are substantially perpendicular to the backside of the semiconductor substrate. [12] The method of claim 9, wherein the irregular sidewall profiles include ribbed surfaces, wave-shaped surfaces, land surfaces, crest and valley surfaces, or a combination thereof. [13] The method of claim 1, further comprising: Applying an ultrasonic waterjet process configured to remove burrs of the dielectric layer based on separating the exposed portion of the dielectric layer. [14] The method of claim 13, wherein the ultrasonic water jetting process includes subjecting a water stream to ultrasonic vibrations and pressure, the ultrasonic vibrations being between about 500 and 3000 Hertz (Hz) and the pressure being between about 10 and 40 pounds per square inch (psi). [15] The method of claim 1, further comprising: Attaching an adhesive tape to a first surface of the dielectric layer opposite a second surface exposed as a result of the plasma etching process, wherein separating the exposed portion of the dielectric layer includes expanding the adhesive tape attached to the first surface of the dielectric layer. [16] The method of claim 1, further comprising: Thinning the semiconductor substrate from the back side before forming the metal layer on the back side of the semiconductor substrate. [17] The method of claim 1, wherein dividing the metal layer includes removing a sacrificial structure located between the metal layer and the scribe region of the semiconductor substrate. [18] The method of claim 17, wherein the sacrificial structure includes a photoresist. [19] The method of claim 1, wherein dividing the metal layer includes: Forming a plurality of mask patterns on the metal layer, each mask pattern corresponding to each of the dies; and Removing a portion of the metal layer exposed by the plurality of mask structures so that the scribe region of the semiconductor substrate is exposed. [20] Method comprising: Forming a sacrificial structure on a backside of a semiconductor substrate including a plurality of dies at a front side opposite the backside, the sacrificial structure covering a scribe region of the semiconductor substrate; Forming a metal layer on the sacrificial structure and the back side of the semiconductor substrate uncovered by the sacrificial structure; Removing the sacrificial structure and a part of the metal layer formed on the sacrificial structure, wherein the scribe region is exposed as a result of the removal of the sacrificial structure; Removing the scribe region of the semiconductor substrate, wherein a part of a dielectric layer located on the front side of the semiconductor substrate is exposed as a result of removing the scribe region of the semiconductor substrate from the back side; Breaking off the exposed part of the dielectric layer. [21] The method of claim 20, wherein the sacrificial structure includes a photoresist. [22] The method of claim 20, wherein removing the portion of the metal layer forms a plurality of metal structures corresponding to the plurality of dies. [23] The method of claim 22, wherein each of the metal structures includes at least one edge aligned with an edge of a corresponding one of the dies. [24] The method of claim 20, wherein removing the scribe region of the semiconductor substrate includes applying a plasma process having alternating deposition steps and etching steps. [25] The method of claim 20, wherein removing the scribe region of the semiconductor substrate forms non-uniform sidewall profiles of individual dies of the plurality. [26] The method of claim 25, wherein the non-uniform sidewall profiles include a plurality of raised lines substantially parallel to the backside of the semiconductor substrate. [27] The method of claim 25, wherein the non-uniform sidewall profiles are substantially perpendicular to the backside of the semiconductor substrate. [28] The method of claim 20, wherein the exposed portion of the dielectric layer includes one or more interlevel metallization layers. [29] The method of claim 20, further comprising: Removing burrs from the broken part of the dielectric layer. [30] The method of claim 29, wherein removing the burr includes using an ultrasonic water jetting process that applies ultrasonic vibrations and pressure to a water stream, the ultrasonic vibrations being between about 500 and 3000 Hertz (Hz) and the pressure being between about 10 and 40 pounds per square inch (psi). [31] The method of claim 20, further comprising: Thinning the semiconductor substrate from the back side before forming the sacrificial structure on the back side of the semiconductor substrate. [32] The method of claim 20, further comprising: Attaching an adhesive tape to the dielectric layer after removing the scribe region of the semiconductor substrate, wherein breaking off the exposed portion of the dielectric layer includes expanding the adhesive tape attached to the dielectric layer. [33] Semiconductor die, comprising: a semiconductor substrate including an integrated circuit arrangement on a front side of the semiconductor substrate; and a metal structure formed on a backside of the semiconductor substrate opposite the frontside, wherein a sidewall profile of the semiconductor substrate has a plurality of ridges. [34] The semiconductor die of claim 33, wherein the ridges of the plurality are substantially parallel to the backside of the semiconductor substrate. [35] The semiconductor die of claim 33, wherein the ridge of the plurality surrounds the semiconductor substrate. [36] The semiconductor die of claim 33, wherein the sidewall profile is substantially perpendicular to the backside of the semiconductor substrate. [37] The semiconductor die of claim 33, wherein the sidewall profile includes a ribbed surface, a wavy surface, a surface with raised portions, a surface with crests and valleys, or a combination thereof. [38] The semiconductor die of claim 33, wherein the metal structure includes at least one edge aligned with a corresponding edge of the semiconductor substrate. [39] A semiconductor die according to claim 33, wherein: the semiconductor substrate has a first cross-sectional area; and the metal structure has a second cross-sectional area substantially corresponding to the first cross-sectional area. [40] The semiconductor die of claim 33, further comprising: a dielectric layer on the front side of the semiconductor substrate, wherein the dielectric layer includes one or more interlevel metallization layers. [41] The semiconductor die of claim 40, wherein at least one edge of the dielectric layer is aligned with a corresponding edge of the semiconductor substrate. [42] The semiconductor die of claim 40, wherein at least one edge of the dielectric layer extends beyond a corresponding edge of the semiconductor substrate. [43] The semiconductor die of claim 33, wherein the integrated circuit arrangement includes a power field effect transistor (power FET).

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