Multilayer capacitor

Abstract

The present invention relates to a multilayer capacitor, a printed circuit board containing the multilayer capacitor, and an integrated circuit package containing the multilayer capacitor. A multilayer capacitor comprises a body having upper, lower, opposite side, and opposite end surfaces, which alternately contains dielectric layers and internal electrode layers. Each internal electrode layer comprises at least one terminal tab extending from a respective upper edge and a lower edge of a main body of the internal electrode layer. The capacitor also comprises external terminals electrically connected to the internal electrode layers and arranged linearly on the upper surface and / or the lower surface.The external terminals are spaced from the side edges of the body such that only dielectric material is present between the external terminals and the side edges of the body.

Description

Related registration

[0001] This application is based upon and claims priority from U.S. Provisional Patent Application Serial No. 63 / 420,722, filed October 31, 2022, which is hereby incorporated by reference. BACKGROUND OF THE INVENTION

[0002] Multilayer capacitors are generally constructed with a plurality of dielectric layers and internal electrode layers arranged in a stack. During manufacturing, the stacked dielectric layers and internal electrode layers are pressed and sintered to achieve a substantially uniform capacitor body. In an attempt to improve the performance of these capacitors, various configurations and designs are used for the dielectric layers and internal electrode layers.

[0003] However, because rapid changes are taking place in the electronics industry that require new performance criteria, these configurations are frequently tampered with. In particular, various application design considerations have created a need to redefine capacitor parameters and their performance in high-speed environments, especially in light of faster and denser integrated circuits. For example, higher current ratings, denser printed circuit boards, and spiraling costs have all served to focus on the need for better and more efficient capacitors. Furthermore, the design of various electronic components is driven by a general industry trend toward miniaturization and increased functionality.

[0004] In this regard, there is a need to provide a capacitor with improved operating characteristics. BRIEF DESCRIPTION OF THE INVENTION

[0005] According to one embodiment of the present invention, a multilayer capacitor is disclosed. The multilayer capacitor comprises a body having a top surface, a bottom surface opposite the top surface, a pair of side surfaces opposite each other along a transverse direction, and a pair of end surfaces opposite each other along a longitudinal direction. The body also has side edges defining lateral boundaries of the top and bottom surfaces and including a first top side edge, a second top side edge, a first bottom side edge, and a second bottom side edge, each extending between the pair of end surfaces along the longitudinal direction. The first top side edge and the second top side edge are opposite each other along the transverse direction, and the first bottom side edge and the second bottom side edge are opposite each other along the transverse direction.The body contains alternating dielectric layers and internal electrode layers. The internal electrode layers include first internal electrode layers and second internal electrode layers. Each internal electrode layer includes a main body having an upper edge, a lower edge opposite the upper edge, and two side edges extending between the upper edge and the lower edge, and at least one terminal tab extending from the upper edge of the main body of the internal electrode layer and at least one terminal tab extending from the lower edge of the main body of the internal electrode layer.The multilayer capacitor also includes external terminals, including a first external terminal disposed on the top and / or bottom surface and electrically connected to the first internal electrode layers, and a second external terminal disposed on the top and / or bottom surface and electrically connected to the second internal electrode layers. The external terminals are linearly disposed on the top and / or bottom surface of the body and are spaced from the side edges of the body at such a distance that only dielectric material is present between the external terminals and the side edges of the body.

[0006] Further features and aspects of the present invention are set forth in more detail below. Brief description of the drawings

[0007] In the remainder of the specification and with reference to the accompanying drawings, a full and reproducible disclosure of the present invention, including the best mode thereof, is particularly set forth for those skilled in the art, in which: Fig. 1A is an external perspective view, generally from above and from the sides, of one embodiment of a capacitor including two external terminals in accordance with the present invention; Fig. 1B a side view of the internal electrode layers of the capacitor of Fig. 1A; Fig. 1C a three-dimensional external perspective top and side view of the internal electrode layers of the capacitor of the Fig. 1A and Fig. 1B; Fig. 1D an external plan view of the capacitor of the Fig. 1A to 1C; Fig. 2A is an external perspective view, generally from above and from the sides, of another embodiment of a capacitor including four external terminals in accordance with the present invention; Fig. 2B is a side view of the internal electrode layers of the capacitor of Fig. 2A; Fig. 2C a three-dimensional external perspective top and side view of the internal electrode layers of the capacitor of the Fig. 2A and Fig. 2B; Fig. 2D an external plan view of the capacitor of the Fig. 2A to 2C; Fig. 3A is an external perspective view, generally from above and from the sides, of one embodiment of a capacitor including two external terminals in accordance with the present invention; Fig. 3B is a side view of the internal electrode layers of the capacitor of Fig. 3A; Fig. 3C an external plan view of the capacitor of the Fig. 3A and Fig. 3B; Fig. 4 a perspective view of the capacitor of Fig. 3A mounted on a mounting surface according to the present invention; and Fig. 5 is a side view of a package for a printed circuit board and an integrated circuit incorporating a capacitor according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] Those skilled in the art should appreciate that the present discussion is only a description of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0009] Generally speaking, the present invention relates to a multilayer capacitor. The multilayer capacitor (or simply capacitor) includes a body having alternating dielectric layers and internal electrode layers. The body has at least one pair of end faces and one pair of side faces. External terminals are formed on the body of the capacitor and are spaced from at least the pair of side faces of the body. The external terminals are linearly arranged in a single dimension such that only dielectric material is present between at least two sides of each external terminal and the adjacent edges of the capacitor surface on which the external terminal is disposed.

[0010] The particular arrangement of the capacitor's elements can provide several advantages. For example, the capacitor of the present invention can be mounted on a printed circuit board as a surface-mount capacitor and can require less space on the circuit board. This, in turn, can also enable a downsizing of the circuit board.

[0011] Furthermore, in certain applications, it is desirable to keep inductance (e.g., parasitic inductance) as low as possible. The use of the capacitor of the present invention enables a significant reduction in inductance. In particular, minimizing the distance or path for a ground connection can help reduce inductance. In general, the use of the capacitor of the present invention can enable a reduction in inductance of at least an order of magnitude compared to the use of a plurality of individual multilayer ceramic capacitors. For example, the use of the capacitor of the present invention can result in an inductance on the order of picohenry or even femtohenry compared to prior art capacitors having inductance of larger orders of magnitude. In general, the inductance can be less than 1 nanohenry.In particular, the inductance may be 900 picohenry or less, such as 750 picohenry or less, such as 500 picohenry or less, such as 400 picohenry or less, such as 250 picohenry or less, such as 100 picohenry or less, such as 50 picohenry or less, such as 25 picohenry or less, such as 15 picohenry or less, such as 10 picohenry or less. The inductance may be 1 femtohenry or more, such as 25 femtohenry or more, such as 50 femtohenry or more, such as 100 femtohenry or more, such as 250 femtohenry or more, such as 500 femtohenry or more, such as 750 femtohenry or more. Minimizing this inductance can contribute to good performance, especially good decoupling performance, especially under transient high-speed conditions.

[0012] In addition, the capacitor can provide a desired capacitance. Specifically, the capacitance can be 1000 µF or less, such as 750 µF or less, such as 500 µF or less, such as 250 µF or less, such as 100 µF or less, such as 50 µF or less, such as 25 µF or less, such as 20 µF or less, such as 15 µF or less, such as 10 µF or less, such as 5 µF or less, such as 2.5 µF or less, such as 1 µF or less, such as 0.75 µF or less, such as 0.5 µF or less. The capacitance can be 1 pF or more, such as 10 pF or more, such as 25 pF or more, such as 50 pF or more, such as 100 pF or more, such as 250 pF or more, such as 500 pF or more, such as 750 pF or more, such as 900 pF or more, such as 1 µF or more, such as 2 µF or more, such as 3 µF or more, such as 5 µF or more, such as 8 µF or more, such as 10 µF or more. The capacitance can be measured using general techniques as known in the art.

[0013] Furthermore, the capacitor can provide a desired resistance. In particular, the resistance can be 100 mOhm or less, such as 75 mOhm or less, such as 50 mOhm or less, such as 40 mOhm or less, such as 30 mOhm or less, such as 25 mOhm or less, such as 20 mOhm or less, such as 15 mOhm or less, such as 10 mOhm or less, such as 5 mOhm or less. The resistance can be 0.01 mOhm or more, such as 0.1 mOhm or more, such as 0.25 mOhm or more, such as 0.5 mOhm or more, such as 1 mOhm or more, such as 1.5 mOhm or more, such as 2 mOhm or more, such as 5 mOhm or more, such as 10 mOhm or more. The resistance can be measured using general techniques as known in the art.

[0014] As stated, the present invention comprises a multilayer capacitor comprising a body having an upper surface and a lower surface opposite the upper surface. The body of the capacitor also comprises at least one side surface, in particular at least two side surfaces, extending between the upper surface and the lower surface. The capacitor may also comprise at least one end surface, in particular at least two end surfaces extending between the upper surface and the lower surface. Generally, the side surfaces extend in the longitudinal or length direction (L) and have a generally longer dimension than the end surfaces, which extend in the lateral or width direction (W) and have a generally shorter dimension. In one embodiment, the capacitor comprises at least six total surfaces (e.g., one top, one bottom, two sides, and two at the ends).For example, the capacitor can have the shape of a parallelepiped, like a cuboid.

[0015] Furthermore, the capacitor can have a desired height. For example, the height can be 10 µm or more, such as 25 µm or more, such as 50 µm or more, such as 100 µm or more, such as 200 µm or more, such as 250 µm or more, such as 300 µm or more, such as 350 µm or more, such as 400 µm or more, such as 450 µm or more, such as 500 µm or more, such as 1000 µm or more, such as 2000 µm or more. The height can be 5000 µm or less, such as 4000 µm or less, such as 2500 µm or less, such as 2000 µm or less, such as 1000 µm or less, such as 750 µm or less, such as 600 µm or less, such as 500 µm or less, such as 450 µm or less. When surrounded by a ball grid array, the height of the capacitor can be within 10%, such as within 7%, such as within 5%, such as within 3%, such as within 2%, such as within 1%, of the height (or diameter) of the balls of the ball grid array.For example, this height can be the original height before reflow soldering.

[0016] The capacitor can have a desired length. For example, the length can be 10 µm or more, such as 25 µm or more, such as 50 µm or more, such as 100 µm or more, such as 200 µm or more, such as 250 µm or more, such as 300 µm or more, such as 350 µm or more, such as 400 µm or more, such as 450 µm or more, such as 500 µm or more, such as 1000 µm or more, such as 1500 µm or more, such as 2000 µm or more, such as 2500 µm or more, such as 3000 µm or more, such as 3500 µm or more, such as 4000 µm or more. The length may be 10000 µm or less, such as 8000 µm or less, such as 6000 µm or less, such as 5000 µm or less, such as 4000 µm or less, such as 3000 µm or less, such as 2500 µm or less, such as 2000 µm or less, such as 1000 µm or less, such as 750 µm or less, such as 600 µm or less, such as 500 µm or less, such as 450 µm or less.

[0017] The capacitor can also have a desired width. For example, the width can be 10 µm or more, such as 25 µm or more, such as 50 µm or more, such as 100 µm or more, such as 200 µm or more, such as 250 µm or more, such as 300 µm or more, such as 350 µm or more, such as 400 µm or more, such as 450 µm or more, such as 500 µm or more, such as 750 µm or more, such as 1000 µm or more, such as 1500 µm or more, such as 2000 µm or more, such as 2500 µm or more, such as 3000 µm or more. The width may be 5000 µm or less, such as 4000 µm or less, such as 3000 µm or less, such as 2500 µm or less, such as 2000 µm or less, such as 1500 µm or less, such as 1000 µm or less, such as 750 µm or less, such as 600 µm or less, such as 500 µm or less, such as 450 µm or less.

[0018] Generally, the multilayer capacitor includes a set of alternating dielectric layers and internal electrode layers. Generally, the capacitor includes at least one set of alternating dielectric layers and internal electrode layers. The capacitor may also include a second set of alternating dielectric layers and internal electrode layers. In this regard, the capacitor may include at least two, such as at least three, such as at least four, sets of alternating dielectric layers and internal electrode layers. However, it should be understood that the present invention may include any number of sets of alternating dielectric layers and internal electrode layers and is not necessarily limited.Furthermore, the respective sets of alternating dielectric layers and internal electrode layers may be separated from an adjacent set by a certain distance. For example, this distance is greater than the thickness of any single dielectric layer in the set. In particular, the distance may be at least two, such as at least three, such as at least five, such as at least ten, times the thickness of any dielectric layer in the set.

[0019] The set or sets of alternating dielectric layers and internal electrode layers may form at least part of the main body of the capacitor. By arranging the dielectric layers and the internal electrode layers in a stacked or laminated configuration, the capacitor may be referred to as a multilayer capacitor, and in particular as a multilayer ceramic capacitor, for example, when the dielectric layers comprise a ceramic.

[0020] The capacitor also includes external terminals electrically connected to the internal electrode layers. The external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposite the top surface of the capacitor. In some embodiments, the external terminals may include a first-end external terminal and a second-end external terminal, and the first-end and / or second-end external terminal may also be formed on the respective end surface adjacent to the respective end external terminal.

[0021] The alternating dielectric layers and internal electrode layers comprise dielectric layers arranged alternately with internal electrode layers. Specifically, the internal electrode layers comprise first internal electrode layers and second internal electrode layers interleaved in an opposing and spaced relationship with a dielectric layer located between each two internal electrode layers.

[0022] In general, the thickness of the dielectric layers and the internal electrode layers is not limited and can be any thickness depending on the performance characteristics. For example, the thickness of the internal electrode layers can be, but is not limited to, about 500 nm or more, such as about 1 µm or more, such as about 2 µm or more, to about 10 µm or less, such as about 5 µm or less, such as about 4 µm or less, such as about 3 µm or less, such as about 2 µm or less. For example, the internal electrode layers can have a thickness of about 1 µm to about 2 µm.

[0023] Furthermore, the present invention is not necessarily limited by the number of internal electrode layers per set of alternating dielectric layers and internal electrode layers or in the entire capacitor. For example, each set may include 10 or more, such as 25 or more, such as 50 or more, such as 100 or more, such as 200 or more, such as 300 or more, such as 500 or more, such as 600 or more, such as 750 or more, such as 1,000 or more internal electrode layers. Each quantity may have 5000 or less, such as 4000 or less, such as 3000 or less, such as 2000 or less, such as 1500 or less, such as 1000 or less, such as 750 or less, such as 500 or less, such as 400 or less, such as 300 or less, such as 250 or less, such as 200 or less, such as 175 or less, such as 150 or less, internal electrode layers. Furthermore, the entire capacitor may comprise the above-mentioned number of electrode layers.

[0024] The internal electrode layers have an upper edge and a lower edge opposite the upper edge. The internal electrode layers also have two side edges extending between the upper edge and the lower edge. In one embodiment, the side edges, the upper edge, and the lower edge define a main body of the internal electrode layers. Generally, the main body of the internal electrode layers may have a rectangular configuration or shape.

[0025] In general, the top edge and the bottom edge may have the same dimension (e.g., in the length direction - L). The side edges may have the same dimension (e.g., in the height direction - T). In general, the side edges may have a dimension (e.g., height direction T) that is shorter than a dimension (e.g., longitudinal direction L) of the top edge and / or bottom edge. In this regard, the height of a side edge of the internal electrode layer, as it extends between the top and bottom surfaces of the capacitor, may be less than the length of the top edge and / or the bottom edge of the internal electrode layer, as it extends between end surfaces of the capacitor. In other words, the internal electrode layers may have a top edge and / or a bottom edge with a larger dimension than the side edges with the smaller dimension.In this respect, the “short” sides of the layers can coincide with the height direction of the capacitor.

[0026] The internal electrode layers have terminal tabs that extend away from the main body of the respective internal electrode layer. The terminal tabs extend from a top edge and a bottom edge. In other words, the internal electrode layers may have terminal tabs that extend from the "long" sides or edges of the internal electrode layers. The terminal tabs may extend to an edge of a dielectric layer and / or a surface of the capacitor. For example, in a staggered configuration, a leading edge of the terminal tab may extend to an edge of a dielectric layer. Such a leading edge may be used to form the external terminals.In addition, the upper edge and the lower edge of a layer may have at least one terminal tab, such as at least two terminal tabs, such as at least three terminal tabs, such as at least four terminal tabs extending therefrom.

[0027] Each upper edge and lower edge of the internal electrode layers may have an equal number of terminal tabs extending therefrom. For example, each upper edge and lower edge may have at least one terminal tab extending therefrom. In another embodiment, each upper edge and lower edge may have at least two terminal tabs extending therefrom. However, it should be understood that the present invention may include any number of terminal tabs extending from the internal electrode layers and is not necessarily limited.

[0028] In one embodiment, at least one terminal tab extends from a top edge and a bottom edge of the main body of the internal electrode layer, and an edge of the terminal tab is aligned with a side edge of the main body of the internal electrode layer. For example, at least one lateral edge (i.e., an edge that coincides in a height direction) of the terminal tabs may be substantially aligned with a respective side edge of the main body of the internal electrode layer. In this regard, at least one terminal tab may not be offset from the side edge of the internal electrode layer.

[0029] However, in some embodiments, the at least one terminal tab may be offset from a side edge of the internal electrode layer. For example, an edge of a respective terminal tab runs parallel to, but spaced from, a side edge of the main body of the internal electrode layer along the longitudinal or L-direction. For example, at least one lateral edge (i.e., an edge that coincides in a height direction) of the terminal tabs may be substantially aligned with a respective side edge of the main body of the internal electrode layer, but offset from the side edge of the internal electrode layer along the length of the main body of the internal electrode layer.

[0030] Additionally or alternatively, where more than one terminal tab may be present along an edge, a respective terminal tab may extend from an inner part of an upper edge and a lower edge of the main body of the internal electrode layer. In this regard, the terminal tab may not extend directly from a side edge of an internal electrode layer. In other words, the terminal tab may be offset from a side edge of the internal electrode layer, for example, in the longitudinal or L-direction. The offset may be such that it is offset and positioned between the side edges of the internal electrode layer, in particular at a position that is at least 50% of the length of the internal electrode layer (i.e., beyond the center of the internal electrode layer).

[0031] The terminal tabs extending from a top edge of a respective internal electrode layer and a bottom edge of the same internal electrode layer may be offset by the same distance from a side edge. In this regard, at least one side edge (i.e., edge that coincides in a height direction) of the terminal tabs may be substantially aligned. In one embodiment, both side edges of the respective terminal tabs may be substantially aligned.

[0032] Likewise, the length (i.e., extending in the longitudinal direction from one end face to another end face) of a terminal tab extending from the upper edge may be the same as the length of a corresponding terminal tab extending from the lower edge.

[0033] The length of each terminal lug may be 0.3 mm or more, such as 0.4 mm or more, such as 0.5 mm or more, such as 0.6 mm or more, such as 0.7 mm or more. The length of each terminal lug may be 1.1 mm or less, such as 0.9 mm or less, such as 0.8 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less. If more than one terminal lug is present along an edge, each terminal lug may have the same length.

[0034] In another embodiment, each terminal tab may have a different length. For example, to have more than one terminal tab extending from the top or bottom edge of an internal electrode layer, a terminal tab that is substantially aligned with the side edge of the internal electrode layer may have a length greater than the offset of the terminal tab from the side edges of the internal electrode layer. In this regard, the ratio of the length of the terminal tab aligned with the side edge of the internal electrode layer to the length of the terminal tab offset from the side edges of the internal electrode layer may be 0.3 or more, such as 0.5 or more, such as 0.7 or more, such as 0.9 or more, such as 1 or more, such as 1.1 or more, such as 1.2 or more, such as 1.3 or more, such as 1.4 or more, such as 1.5 or more.The ratio may be 5 or less, such as 4 or less, such as 3 or less, such as 2 or less, such as 1.8 or less, such as 1.7 or less, such as 1.6 or less, such as 1.5 or less, such as 1.4 or less.

[0035] “Substantially aligned” means that the offset from a side edge of a lateral edge of a first terminal tab and / or second terminal tab at a top edge is within + / -10%, such as within + / -5%, such as within + / -4%, such as within + / -3%, such as within + / -2%, such as within + / -1%, such as within + / -0.5% of the offset from a side edge of a corresponding lateral edge of a first terminal tab and / or second terminal tab at a bottom edge.

[0036] When the dielectric layers and internal electrode layers are stacked on top of one another as described herein, aligned terminal tabs form what may be referred to as a column of terminal tabs or electrode tabs. The spacing between adjacent exposed terminal tabs of the internal electrode layers in a given column may be specifically designed to ensure guided terminal formation. This spacing between exposed terminal tabs of the internal electrode layers in a given column may be about 10 µm or less, such as about 8 µm or less, such as about 5 µm or less, such as about 4 µm or less, such as about 2 µm or less, such as about 1.5 µm or less, such as about 1 µm or less. The spacing may be about 0.25 µm or more, such as about 0.5 µm or more, such as about 1 µm or more, such as about 1.5 µm or more, such as about 2 µm or more, such as about 3 µm or more.However, it should be noted that this distance does not necessarily have to be limited.

[0037] Additionally, the spacing between adjacent columnar stacks of electrode tabs may be, although not limited, at least a factor of two greater than the spacing between adjacent electrode tabs in a given column to ensure that different terminals do not merge. In some embodiments, the spacing between adjacent columnar stacks of exposed metallization is approximately four times the spacing between adjacent exposed electrode tabs in a given stack. However, this spacing may vary depending on the desired capacitance performance and board configuration.

[0038] The pitch may be 0.1 mm or more, such as 0.2 mm or more, such as 0.3 mm or more, such as 0.4 mm or more, such as 0.5 mm or more, such as 0.6 mm or more. The pitch may be 1.5 mm or less, such as 1.3 mm or less, such as 1 mm or less, such as 0.9 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less, such as 0.4 mm or less. This pitch may, in one embodiment, be determined based on the center point of each terminal tab. In another embodiment, the pitch may be based on the distance between adjacent lateral edges of the terminal tabs. Additionally, this pitch may correspond to the separation distance of the balls on a ball grid array.

[0039] A terminal tab of a first internal electrode layer and a terminal tab of a second internal electrode layer within a set of alternating dielectric layers and internal electrode layers are offset from one another in the longitudinal or lengthwise direction. This means that the terminal tabs of the respective internal electrode layers can be offset by a certain distance symmetrically from a centerline (e.g., a longitudinal centerline or approximately a vertical line) of the internal electrode layers and / or dielectric layer. This means that the terminal tabs of the respective internal electrode layers can be offset symmetrically about a vertical line of the internal electrode layers and / or dielectric layer. Regardless of this, a gap region is created between the terminal tabs of the respective internal electrode layers.

[0040] Furthermore, the internal electrode layers may be symmetrical in a given direction, regardless of the number of terminal tabs extending therefrom. For example, the terminal tabs may be symmetrical about a horizontal line (i.e., a line extending from the center of one side edge to the center of the other side edge of the internal electrode layer) through the center of the main body of the internal electrode layer.

[0041] Furthermore, as stated herein, each internal electrode layer includes at least two side edges. When stacked on top of one another to form the body of the capacitor, such side edges of the alternating internal electrode layers may be substantially non-aligned. For example, the side edges may be offset from one another. In at least some embodiments, the side edges may also be offset from the side surfaces of the body of the capacitor.

[0042] The capacitor of the present invention also includes external terminals on the top surface and the bottom surface of the capacitor body. The external terminals are spaced from the side surfaces of the capacitor body such that only dielectric material is disposed between the external terminals and the side surfaces of the body. In some embodiments, the capacitor also includes external terminals on opposite end surfaces of the capacitor body, but in other embodiments, the external terminals are not only spaced from the side surfaces but also spaced from at least one of the opposite end surfaces such that only dielectric material is disposed between the external terminals and the at least one side surface.

[0043] The external terminals comprise at least one terminal of a first polarity and at least one terminal of a second, opposite polarity. The capacitor may comprise at least one, such as at least two, such as at least four, such as at least six, such as at least eight, terminals of a first polarity and / or terminals of a second, opposite polarity on an upper surface of the capacitor body. Furthermore, the capacitor may also comprise the above-mentioned number of terminals on a lower surface of the capacitor body.

[0044] The capacitor may include an equal number of terminals of a first polarity and / or terminals of a second polarity on the top surface and the bottom surface. The number of terminals of the first polarity may be equal to the number of terminals of the second, opposite polarity on an top surface. The number of terminals of the first polarity may be equal to the number of terminals of the second, opposite polarity on the bottom surface. The total number of terminals present on an top surface of the capacitor may be equal to the total number of terminals present on a bottom surface of the capacitor.The total number of terminals of the first polarity present on an upper surface and a lower surface of the capacitor may be equal to the total number of terminals of the second, opposite polarity present on an upper surface and a lower surface of the capacitor.

[0045] In general, the like-polarity terminals on the bottom surface of the capacitor, corresponding to a certain set of alternating dielectric layers and internal electrode layers, are electrically connected to the like-polarity terminals on the top surface of the capacitor. The like-polarity terminals located on an upper surface and a lower surface of a capacitor may not interdigitate. In this regard, corresponding like-polarity terminals on an upper and lower surface may not be offset by one terminal position, but may instead be located directly above or below another like-polarity terminal on the opposite upper or lower surface, respectively. In other words, corresponding like-polarity terminals corresponding to a certain set of terminal tabs may be substantially aligned.“Substantially aligned” means that the offset from a side edge of a terminal of one polarity on a top surface is within + / -10%, such as within + / -5%, such as within + / -4%, such as within + / -3%, such as within + / -2%, such as within + / -1%, such as within + / -0.5% of the offset from a side edge of a terminal of the corresponding polarity on a bottom surface.

[0046] In general, the pitch (i.e., the nominal center-to-center spacing, also called center-to-center spacing) of the external terminals may be fixed by a particular board configuration. The pitch between external terminals in one direction (i.e., the x- or y-direction) may be the same as the pitch between adjacent external terminals in the other direction (i.e., the y- or x-direction, respectively). That is, the pitch between any two adjacent external terminals may be substantially the same as the pitch between any two other adjacent external terminals.

[0047] The regular pitch may be about 0.1 mm or more, such as about 0.2 mm or more, such as about 0.3 mm or more, such as about 0.4 mm or more, such as about 0.5 mm or more, such as about 0.6 mm or more, such as about 0.7 mm or more, such as about 0.8 mm or more, such as about 0.9 mm or more, such as about 1.0 mm or more. The regular pitch may be about 2.0 mm or less, such as about 1.5 mm or less, such as about 1.4 mm or less, such as about 1.3 mm or less, such as about 1.2 mm or less, such as about 1.1 mm or less, such as about 1.0 mm or less. For example, the regular pitch may be about 0.2 mm, about 0.4 mm, about 0.6 mm, about 0.8 mm, about 1.0 mm, about 1.2 mm, etc. In particular, the regular spacing may be 0.6 mm, 0.8 mm, or 1.0 mm. In one embodiment, the regular spacing may be approximately 0.6 mm, such as 0.6 mm + / - 10%, such as + / - 5%, such as + / - 2%, such as + / - 1%.In another embodiment, the regular spacing may be approximately 0.8 mm, such as 0.8 mm + / - 10%, such as + / - 5%, such as + / - 2%, such as + / - 1%. In another embodiment, the regular spacing may be approximately 1 mm, such as 1 mm + / - 10%, such as + / - 5%, such as + / - 2%, such as + / - 1%.

[0048] The ratio of the length of the capacitor body to the regular pitch may be 1.1 or more, such as 2 or more, 5 or more, 10 or more, 20 or more, 100 or more, or 500 or more. For example, the ratio of the length of the capacitor body to the regular pitch may be in a range of 1.1 to 1000, such as in a range of 2 to 500, in a range of 5 to 100, or in a range of 10 to 50.

[0049] As mentioned, extending a leading edge of a terminal tab can assist in the formation of external terminals. In this regard, the regular spacing between a terminal tab on a first internal electrode layer and a terminal tab on a second internal electrode layer can be the same as mentioned above. That is, the regular spacing between a terminal tab on a first internal electrode layer and a terminal tab on a second internal electrode layer can be substantially the same as the regular spacing between the corresponding external terminals for which the terminal tabs are used.

[0050] Furthermore, the external terminals can be placed similarly to the configuration of a ball grid array. For example, the external terminals can be provided to make contacts as typically employed in a ball grid array, particularly in a surrounding ball grid array. In this respect, the regular spacing of the external terminals can be the same as the regular spacing of a surrounding ball grid array. That is, the regular spacing can be within 10%, within 5%, within 2%, within 1%, within 0.5%, or within 0.1% of the regular spacing of a surrounding ball grid array.

[0051] Furthermore, the external terminals may be provided in a single row with a number of columns, which in a row-by-column notation may be referred to as a 1xn configuration of external terminals, where n is the number of columns. For example, the external terminals may be provided in one row and at least two columns. For example, the external terminals may be provided in at least two columns, such as at least three columns, such as at least four columns. The number of columns may be fixed by the number of different column-like tabs of the internal electrodes.

[0052] Furthermore, the length of an external terminal extending in the longitudinal or lengthwise direction L along the upper surface may be the same as the length of a corresponding external terminal extending along the lower surface. The length of an external terminal may be measured from one terminal end face to the other terminal end face, which are opposite to each other in the longitudinal direction.

[0053] The length of an external terminal may be 0.3 mm or more, such as 0.4 mm or more, such as 0.5 mm or more, such as 0.6 mm or more, such as 0.7 mm or more. The length of the external terminal may be 1.1 mm or less, such as 0.9 mm or less, such as 0.8 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less. If more than one external terminal is present along a surface, each external terminal may have the same length. Furthermore, the length of the external terminal may be shorter than the length of the capacitor, such as 50% or less, such as 40% or less, such as 30% or less, such as 25% or less, such as 20% or less, such as 15% or less of the length of the capacitor.

[0054] In another embodiment, each external terminal may have a different length. For example, the external terminal adjacent to an end face may have a length greater than the offset of the external terminal from the end face. In this regard, the ratio of the length of the external terminal adjacent to an end face to the length of the external terminal offset from the end face may be 0.3 or more, such as 0.5 or more, such as 0.7 or more, such as 0.9 or more, such as 1 or more, such as 1.1 or more, such as 1.2 or more, such as 1.3 or more, such as 1.4 or more, such as 1.5 or more. The ratio may be 5 or less, such as 4 or less, such as 3 or less, such as 2 or less, such as 1.8 or less, such as 1.7 or less, such as 1.6 or less, such as 1.5 or less, such as 1.4 or less.

[0055] Furthermore, the width of an external terminal extending in the lateral or transverse direction W may be the same on the top surface and the bottom surface. The width of an external terminal may be measured from one terminal side surface to another end side surface opposite each other in the transverse direction.

[0056] The width of an external terminal can be 0.3 mm or more, such as 0.4 mm or more, such as 0.5 mm or more, such as 0.6 mm or more, such as 0.7 mm or more. The width of the external terminal can be 1.1 mm or less, such as 0.9 mm or less, such as 0.8 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less. If there is more than one external terminal along a surface, each external terminal can have the same width. Furthermore, the width of the external terminal can be smaller than the width of the capacitor.

[0057] Additionally, the external terminals may be spaced from each other and from the sides and / or ends of the capacitor such that dielectric material is located between adjacent external terminals. The external terminals may include a first external end terminal located adjacent to or closest to a first end face of the capacitor body and a second external end terminal located adjacent to or closest to a second end face of the capacitor body. The first outer end terminal and the second outer end terminal may be spaced from each other in the longitudinal direction by an outer end terminal spacing. The ratio of the length of the capacitor body to the spacing between the external end terminals may be 1.1 or more, such as 2 or more, 5 or more, 10 or more, 20 or more, 100 or more, or 500 or more.For example, the ratio of the length of the capacitor body to the distance between the external end terminals may be in a range of 1.1 to 1000, such as in a range of 2 to 500, in a range of 5 to 100, or in a range of 10 to 50.

[0058] The adjacent external terminals may also be spaced apart longitudinally on the top surface of the capacitor by an adjacent external terminal pitch, for example, between adjacent lateral sides of the external terminals. For example, for a pair of adjacent external terminals whose sides face the other of the pair of adjacent external terminals, the side of one external terminal of the pair is spaced from the side of the other external terminal of the pair by the adjacent external terminal pitch. The ratio of the length of the capacitor body to the distance between the external terminals may be 1.1 or more, such as 2 or more, 5 or more, 10 or more, 20 or more, 100 or more, or 500 or more.For example, the ratio of the length of the capacitor body to the distance between the external terminals may be in a range of 1.1 to 1000, such as in a range of 2 to 500, in a range of 5 to 100, or in a range of 10 to 50.

[0059] The capacitor of the present invention can be further constructed according to the embodiments shown in the Fig. 1A to 1D, 2A to 2D and 3A to 3C.

[0060] Fig. 1A shows a capacitor 100 in a 1-by-2 configuration. That is, the capacitor 100 includes two external terminals arranged linearly in a single dimension on a top and bottom surface of the capacitor. In the depicted embodiment, the capacitor 100 includes external terminals arranged linearly or in a single row along a longitudinal direction L, which may be referred to as a linear terminal arrangement.

[0061] In this regard, the capacitor 100 comprises a body 116 having external terminals 112, 114, including a first external terminal 112 disposed on the top surface 118 and / or the bottom surface 120 and electrically connected to first internal electrode layers 1005 ( Fig. 1B, Fig. 1C), and a second external terminal 114 disposed on the upper surface 118 and / or the lower surface 120 and electrically connected to second internal electrode layers 1015 ( Fig. 1B, Fig. 1C). In particular, in the illustrated embodiment, the capacitor 100 includes a first external terminal 112 and a second external terminal 114 disposed on the upper surface 118 of the body 116, and two corresponding external terminals 112, 114 (not shown) on the lower surface 120 of the body 116, which may be referred to as the third external terminal 112 and the fourth external terminal 114.

[0062] The external terminals 112, 114 on the upper surface 118 are electrically connected to the corresponding external terminals 112, 114 on the lower surface 120. Therefore, the capacitor 100, as shown in Fig. 1A, at least one terminal of a first polarity and at least one terminal of a second, opposite polarity on the upper surface 118, and although not shown, the lower surface 120 includes at least one terminal of a first polarity and one terminal of a second, opposite polarity. Furthermore, the first and third external terminals 112 are electrically connected to the first internal electrode layers 1005 ( Fig. 1B, Fig. 1C), and the second and fourth external terminals 114 are electrically connected to the second internal electrode layers 1015 ( Fig. 1B, Fig. 1C).

[0063] The body 116 includes the upper surface 118 and the lower surface 120 opposite the upper surface 118 along a height direction T. The body also includes a first side surface 122 extending between the upper surface 118 and the lower surface 120 along the height direction T, and a second side surface 124 opposite the first side surface 122 along a lateral or width direction W and extending between the upper surface 118 and the lower surface 120. The body further includes a first end surface 126 extending between the upper surface 118 and the lower surface 120 along the height direction T, and a second end surface 128 opposite the first end surface 126 along a longitudinal or length direction L and extending between the upper surface 118 and the lower surface 120. The body 116 has a body length of 115 and a body width of 125.

[0064] As continued in Fig. 1A, the body 116 includes end edges 130, 132 defining longitudinal boundaries of the top and bottom surfaces 118, 120, and side edges 134, 136 defining lateral boundaries of the top and bottom surfaces 118, 120. For example, the top surface 118 has a first top end edge 130a and a second top end edge 132a extending along the lateral direction W between the pair of side surfaces 122, 124. The first top end edge 130a and the second top end edge 132a oppose each other along the longitudinal direction L. The top surface 118 also has a first top surface edge 134a and a second top surface edge 136a extending along the longitudinal direction L between the pair of end surfaces 126, 128. The first upper side edge and the second upper side edge are opposite each other along the transverse direction W.The upper end edges 130a, 132a define a longitudinal boundary of the upper surface 118 and the upper side edges 134a, 136a define the lateral boundary of the upper surface 118.

[0065] Similarly, the lower surface 120 has a first lower end edge 130b and a second lower end edge 132b extending along the lateral direction W between the pair of side surfaces 122, 124. The first lower end edge 130b and the second lower end edge 132b are opposite each other along the longitudinal direction L. The upper surface 120 also has a first upper side edge 134b and a second upper side edge 136b extending along the longitudinal direction L between the pair of end surfaces 126, 128. The first lower side edge 134b and the second lower side edge 136b are opposite each other along the transverse direction W. The lower end edges 130b, 132b define a longitudinal boundary of the lower surface 120, and the lower side edges 134b, 136b define the lateral boundary of the lower surface 120.

[0066] It should be noted that the lower surface 120 may be configured similarly to the upper surface 118, although not shown in the figures. That is, the lower surface 120 may also have a first end edge and a second end edge extending along the transverse direction W between the pair of side surfaces 122, 124 and opposite each other along the longitudinal direction L. The lower surface 120 may also have a first side edge and a second side edge extending along the longitudinal direction L between the pair of end surfaces 126, 128 and opposite each other along the transverse direction W. The end edges and the side edges may define the longitudinal and transverse boundaries of the lower surface 120, respectively.

[0067] The external terminals 112, 114 of the capacitor 100 are offset from the sides and ends of the capacitor 100. As shown in the Fig. 1A and Fig. 1D, the external terminals 112, 114 are spaced from the first side edge 134 and the second side edge 136 of both the top surface 118 and the bottom surface 120, respectively, such that only dielectric material is located between the side surfaces 134, 136 and the external terminals 112, 114. For example, the external terminals 112, 114 are spaced from the first side edge 134a on the top surface 118 and the first side edge 134b on the bottom surface 120 to define a first edge gap 138 between the external terminals 112, 114 and each of the first side edges 134a, 134b. Furthermore, the external terminals 112, 114 are spaced from the second side edge 136a on the upper surface 118 and the second side edge 136b on the lower surface 120 to define a second edge gap 140 between the external terminals 112, 114 and each of the second side edges 136a, 136b.

[0068] The edge gaps 138, 140 may be larger than the thickness of a single layer, for example, larger than a single dielectric layer or a single internal electrode layer 1010 ( Fig. 1B, Fig. 1C). For example, each edge gap 138, 140 may be at least twice, at least three times, at least five times, or at least ten times the thickness of a single dielectric layer or a single internal electrode layer. In some embodiments, the first edge gap 138 and the second edge gap 140 may be the same (e.g., the external electrodes 112, 114 may be equidistant from the respective first side edge 134 and from the respective second side edge 136 for a given surface 118, 120), but in other embodiments, the first edge gap 138 and the second edge gap 140 may be different (e.g., the external electrodes 112, 114 may be closer to the respective first side edge 134 or the respective second side edge 136 for a given surface 118, 120 than to the other side edge of the respective surface 118, 120).

[0069] Similarly, the external terminals 112, 114 of the capacitor 100 are spaced from the end edges 130, 132 of the upper and lower surfaces 118, 120. As shown in the Fig. 1A and Fig. 1D, the external terminals 112, 114 are spaced from the first end edge 130 and the second end edge 132 of the upper surface 118 and the lower surface 120, respectively, to define a first end gap 142 between the external terminal 112 and the first end edges 130a, 130b and a second end gap 144 between the external terminal 114 and the second end edges 132a, 132b.

[0070] The end gaps 142, 144 may be larger than the thickness of a single layer, such as larger than a single dielectric layer or a single internal electrode layer 1010 ( Fig. 1B, Fig. 1C). For example, each end gap 142, 144 may be at least twice, such as at least three times, such as at least five times, or at least ten times the thickness of a single dielectric layer or a single internal electrode layer. In some embodiments, the first end gap 142 and the second end gap 144 may be the same (e.g., for a given area 118, 120, the external terminal 112 may be the same distance from the respective first end edge 130 as the external terminal 114 is from the respective second end edge 132), but in other embodiments, the first end gap 142 and the second end gap 144 may be different (e.g., for a given area 118, 120, one of the external terminals 112, 114 may be closer to its adjacent end edge 130, 132 than the other external electrode 112, 114 is to its adjacent end edge 130, 132).

[0071] If we focus on the Fig. 1A and Fig. 1B, the capacitor 100 comprises Fig. 1A external terminals 112, 114 and a set of alternating dielectric layers and internal electrode layers 1010. If we focus in particular on Fig. 1B, the set of alternating dielectric layers and internal electrode layers 1010 includes internal electrode layers 1005, 1015 and dielectric layers (not shown) in an alternating arrangement.

[0072] Generally, the internal electrode layers 1005, 1015 include at least one terminal tab 1020, 1030, 1040, 1050 extending from a top edge and a bottom edge of a main body of the internal electrode layers. Generally, the terminal tabs 1020, 1030, 1040, 1050 of the internal electrode layers 1005, 1015 extend to the top surface and the bottom surface of the capacitor and assist in forming the external terminals 112, 114. In this regard, the terminal tabs 1020, 1030, 1040, 1050 may be exposed on the top surface 118 and the bottom surface 120 of the capacitor and enable connection between the main body of the internal electrode layers and the external terminals 112, 114.For example, the terminal tabs 1020, 1030, 1040, 1050 may include leading edges 1023, 1033, 1043, 1053 that extend to an edge of a dielectric layer and enable the formation of the external terminals 112, 114 on the top surface 118 and the bottom surface 120.

[0073] As in the Fig. 1B and Fig. 1C, a first internal electrode layer 1005 includes a terminal tab 1020 extending from the main body 1035 along a top edge 1005c and a terminal tab 1020 extending from the main body 1035 along a bottom edge 1005d. A second internal electrode layer 1015 includes a terminal tab 1040 extending from the main body 1035 along a top edge and a terminal tab 1050 extending from the main body 1035 along a bottom edge.

[0074] The terminal tabs 1020, 1030 at the upper edge 1005c and the lower edge 1005d of the first internal electrode layer 1005 may be aligned in the vertical or height direction T. That is, a lateral edge 1021, 1022 of a first terminal tab 1020 along an upper edge 1005c may be aligned with a lateral edge 1031, 1032 of a first terminal tab 1030 along a lower edge 1005d opposite the upper edge 1005c. In other words, a lateral edge 1021, 1022 of a first terminal tab 1020 along an upper edge 1005c may be offset from a lateral edge 105a-b by the same amount as a lateral edge 1031, 1032 of a first terminal tab 1030 along a lower edge 1005d opposite the upper edge 1005c (indicated by "O").

[0075] However, it should be understood that both lateral edges 1021, 1022 of the first terminal tab 1020 along an upper edge 1005c may be aligned with the lateral edges 1031, 1032 of a first terminal tab 1030 along a lower edge 1005d opposite the upper edge 1005c. In other words, both lateral edges 1021, 1022 of a first terminal tab 1020 along an upper edge 1005c may be offset from a lateral edge 1005a-b by the same amount as both lateral edges 1031, 1032 of a first terminal tab 1030 along a lower edge 1005d opposite the upper edge 1005c.

[0076] Likewise, the terminal tabs 1040, 1050 may be aligned in a perpendicular direction at the top and bottom edges of the second internal electrode layer 1015. That is, a lateral edge 1041, 1042 of a first terminal tab 1040 along an upper edge may be aligned with a lateral edge 1051, 1052 of a first terminal tab 1050 along a lower edge opposite the upper edge. In one embodiment, both lateral edges 1041, 1042 of the first terminal tab 1040 along an upper edge may be aligned with the lateral edges 1051, 1052 of a first terminal tab 1050 along a lower edge opposite the upper edge. The relationship between lateral edges of a first terminal tab at an upper edge and a first terminal tab at a lower edge, as mentioned with respect to the internal electrode layer 1005, may also apply to the internal electrode layer 1015.

[0077] With such an arrangement, a tab gap 1016 can be created between terminal tab 1020 of the first internal electrode layer 1005 and terminal tab 1040 of the second internal electrode layer 1015. Likewise, a tab gap 1018 can be created between terminal tab 1030 of the first internal electrode layer 1005 and terminal tab 1050 of the second internal electrode layer 1015. The size of the respective tab gaps 1016, 1018 can be substantially the same.

[0078] The terminal tabs 1020 and 1040 may be arranged parallel to the terminal tabs 1030 and 1050, respectively, extending from the internal electrode layers 1005 and 1015, such that the terminal tabs extending from alternating electrode layers 1005 and 1015 may be aligned in a respective column. For example, the terminal tabs 1020 and 1030 of the internal electrode layer 1005 may be arranged in a corresponding stacked configuration, while the terminal tabs 1040 and 1050 of the internal electrode layer 1015 may be arranged in a corresponding stacked configuration.

[0079] It should be noted that terminal tabs 1020 are connected to external terminal 112, while terminal tabs 1040 are connected to external terminal 114. Accordingly, the respective terminal tabs 1020 interlock with the respective terminal tabs 1040 in a manner similar to the external terminals 112 and 114. The interlocking terminal tabs can provide multiple adjacent current injection points on the associated main electrode portions.

[0080] Fig. 1D shows a top view of the top surface 118 of the capacitor 100. It should be noted that the bottom surface 120 may be configured substantially similarly to the top surface 118, so that the description of the top surface 118 may equally describe the bottom surface 120.

[0081] As in Fig. 1D, the external terminals 112, 114 may be spaced from each other and from the sides and ends of the top surface 118 and the bottom surface 120 of the capacitor 100. As one example, the external terminals 112, 114 may include a first external end terminal 112 disposed on the top surface 118 adjacent the first end surface 126 and the first end edge 130a, and a second external end terminal 114 disposed on the top surface 118 adjacent the second end surface 128 and the second end edge 132a. The first external end terminal 112 and the second external end terminal 114 are spaced from each other in the longitudinal direction L by an external end terminal spacing 150.

[0082] As previously described, the body 116 has a body length 115 in the longitudinal direction L. The ratio of the body length 115 to the distance 150 between the external end connections is 1.1 or more. For example, the ratio of the body length 115 to the distance 150 between the external end connections may be 1.1 or more, such as 2 or more, 5 or more, 10 or more, 20 or more, 100 or more, or 500 or more.

[0083] As continued in Fig. As shown in Figure 1D, a regular pitch 152 is defined between adjacent external terminals 112, 114. As previously described, the regular pitch 152 is the nominal distance between the centers of adjacent external terminals; the regular pitch 152 may also be referred to as the center-to-center spacing of the external terminals. The ratio of the body length 115 to the pitch 152 is 1.1 or more, such as 2 or more, 5 or more, 10 or more, 20 or more, 100 or more, or 500 or more.

[0084] As in the Fig. 1A-1D, the capacitor 100 includes two external terminals 112, 114 on each surface, and each internal electrode layer 1010 includes at least one terminal tab extending from a top edge and a bottom edge. However, as previously stated, the present invention is not limited by the number of external terminals and / or the number of terminal tabs extending from a top edge and / or a bottom edge.

[0085] For example, Fig. 2A, a capacitor 200 including four external terminals on each face and two terminal tabs extending respectively from the top face and the bottom face of the internal electrode layers.

[0086] As in Fig. As shown in Figure 2A, capacitor 200 has a 1-by-4 configuration. That is, capacitor 200 includes four external terminals arranged linearly in a single dimension on a top and bottom surface of the capacitor. In the depicted embodiment, capacitor 200 includes external terminals arranged linearly, or in a single row, along a longitudinal direction L, which may be referred to as a linear terminal arrangement.

[0087] In this regard, the capacitor 200 comprises a body 216 having external terminals 212a, 212b, 214a, 214b, including a first external terminal 212a disposed on the top surface 218 and / or the bottom surface 220 and electrically connected to first internal electrode layers 2005 ( Fig. 2B, Fig. 2C), and a second external terminal 214a disposed on the upper surface 218 and / or the lower surface 220 and electrically connected to second internal electrode layers 2015 ( Fig. 2B, Fig. 2C). More specifically, in the illustrated embodiment, the capacitor 200 includes a first external terminal 212a, a second external terminal 214a, a third external terminal 212b, and a fourth external terminal 214b disposed on the top surface 218 of the body 216, and four corresponding external terminals 212a, 212b, 214a, 214b (not shown) on the bottom surface 220 of the body 216, which may be referred to as the fifth external terminal 212a, the sixth external terminal 214a, the seventh external terminal 212b, and the eighth external terminal 214b.

[0088] The external terminals 212a, 212b, 214a, 214b on the upper surface 218 are electrically connected to the corresponding external terminals 212a, 212b, 214a, 214b on the lower surface 220. Therefore, the capacitor 200, as shown in Fig. 2A, at least two terminals of a first polarity and at least two terminals of a second, opposite polarity are provided on the upper surface 218, and although not shown, the lower surface 220 also includes at least two terminals of the first polarity and two terminals of the second, opposite polarity. Furthermore, the first, third, fifth, and seventh external terminals 212a, 212b are electrically connected to the first internal electrode layers 2005 ( Fig. 2B, Fig. 2C), and the second, fourth, sixth and eighth external terminals 214a, 214b are electrically connected to the second internal electrode layers 2015 ( Fig. 2B, Fig. 2C).

[0089] In the Fig. 2A-2D similar reference numerals are used as in the Fig. 1A-1D. Generally, similar reference numerals throughout the figures refer to the same or similar features or components. Accordingly, it should be noted that the body 216 of the capacitor 200 is configured similarly to the body 116 of the capacitor 100.For example, the body 216 includes the upper surface 218, the lower surface 220 opposite the upper surface 218 along a height direction T, a first side surface 222 extending between the upper surface 218 and the lower surface 220 along the height direction T, a second side surface 224 opposite the first side surface 222 along a transverse or width direction W and extending between the upper surface 218 and the lower surface 220, a first end surface 226 extending between the upper surface 218 and the lower surface 220 along the height direction T, and a second end surface 228 opposite the first end surface 226 along a longitudinal or length direction L and extending between the upper surface 218 and the lower surface 220. The body 216 has a body length 2015 and a body width 225.

[0090] Furthermore, the upper surface 218 has first and second end edges 230, 232 extending along the lateral direction W between the pair of side surfaces 222, 224. The upper surface 218 also includes first and second side edges 234, 236 extending along the longitudinal direction L between the pair of end surfaces 226, 228. Although not shown in the figures, it should be noted that the lower surface 220 may be configured similarly to the upper surface 218 and have first and second end edges and first and second side edges.

[0091] The external terminals 212, 214 of the capacitor 200 are offset from the sides and ends of the capacitor 200. As shown in the Fig. 2A and Fig. 2D, the external terminals 212a, 212b, 214a, 214b are spaced from the first side edge 234 and the second side edge 236 of both the top surface 218 and the bottom surface 220, respectively, such that only dielectric material is located between the external terminals 212a, 212b, 214a, 214b and the side edges 234, 236. For example, in the upper surface 218 and the lower surface 220, the external terminals 212a, 212b, 214a, 214b are spaced from the first side edge 234a, 234b and the second side edge 236a, 236b, respectively, to define a first edge gap 238 between the external terminals 212a, 212b, 214a, 214b and the first side edge 234a, 234b and a second edge gap 240 between the external terminals 212a, 212b, 214a, 214b and the second side edge 236a, 236b.Likewise, the external terminals 212a, 214b are spaced from the first end edge 230a, 230b and the second end edge 232a, 232b of the upper surface 218 and the lower surface 220, respectively, to define a first end gap 242 between the external terminal 212a and the first end edge 230a, 230b and a second end gap 244 between the external terminal 214b and the second end edge 232a, 232b.

[0092] The edge gaps 238, 240 and the end gaps 242, 244 may be greater than the thickness of a single layer, such as greater than a single dielectric layer or a single internal electrode layer 1010 ( Fig. 1B, Fig. 1C). For example, each edge gap 238, 240 and each end gap 242, 244 may be at least twice, such as at least three times, such as at least five times, or at least ten times the thickness of a single dielectric layer or a single internal electrode layer. In some embodiments, the first edge gap 238 and the second edge gap 240 may be the same (e.g., for a given area 218, 220, the external electrodes 212a, 212b, 214a, 214b may be equidistant from the respective first side edge 234a, 234b as from the respective second side edge 236a, 236b), but in other embodiments, the first edge gap 238 and the second edge gap 240 may be different (e.g.,the external electrodes 212a, 212b, 214a, 214b may be located closer to the respective first side edge 234 or the respective second side edge 236 for a given surface 218, 220 than to the other side edge of the respective surface 218, 220). Likewise, in some embodiments, the first end gap 242 and the second end gap 244 may be the same (e.g., for a given area 218, 220, the external terminal 212a may be the same distance from the respective first end edge 230a, 230b as the external terminal 214b is from the respective second end edge 232a, 232b), but in other embodiments, the first end gap 242 and the second end gap 244 may be different (e.g., for a given area 218, 220, one of the external terminals 212a, 214b may be closer to its adjacent end edge 230, 232 than the other external electrode 212a, 214b is to its adjacent end edge 230, 232).

[0093] The capacitor 200 from Fig. 2A includes external terminals 212a, 212b, 214a, 214b and a set of alternating dielectric layers and internal electrode layers 2010, as shown in Fig. 2B. As shown in Fig. 2B, the set of alternating dielectric layers and internal electrode layers 2010 includes internal electrode layers 2005, 2015 and dielectric layers (not shown) in an alternating arrangement.

[0094] Generally, the internal electrode layers 2005, 2015 include at least one terminal tab 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, 2050b extending from an upper edge and a lower edge of the main body of the internal electrode layers. Generally, the terminal tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, 2050b of the internal electrode layers 2005, 2015 extend to the upper surface and the lower surface of the capacitor and assist in forming the external terminals. In this regard, the terminal tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, 2050b may be exposed on the top surface and the bottom surface of the capacitor and enable a connection between the main body of the internal electrode layers and the external terminals.For example, the terminal tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, 2050b may include leading edges 2023a-b, 2033a-b, 2043a-b, 2053a-b that extend to an edge of a dielectric layer and enable the formation of the external terminals.

[0095] As in the Fig. 2B and Fig. 2C, the internal electrode layers 2005, 2015 comprise at least two terminal tabs 2020a, 2020b, 2030a, 2030b, 2040a, 2040b, 2050a, 2050b along an upper edge and a lower edge. As shown in the Fig. 2B and Fig. As shown in Figure 2C, a first internal electrode layer 2005 includes two terminal tabs 2020a, 2020b, 2030a, 2030b, each along an upper edge 2005c and a lower edge 2005d, extending away from the main body 235. A second internal electrode layer 2015 includes two terminal tabs 2040a, 2040b, 2050a, 2050b, each along an upper edge, extending away from the main body 245.

[0096] The terminal tabs 2020a, 2020b, 2030a, 2030b at the upper edge 2005c and the lower edge 2005d of the first internal electrode layer 2005 may be aligned in a perpendicular direction. That is, a lateral edge 2021a, 2022a of a first terminal tab 2020a along an upper edge 2005c may be aligned with a lateral edge 231a, 232a of a first terminal tab 2030a along a lower edge 2005d opposite the upper edge 2005c. In other words, a lateral edge 2021a, 2022a of a first terminal tab 2020a along an upper edge 2005c may be offset from a lateral edge 2005a-b by the same amount as a lateral edge 231a, 232a of a first terminal tab 2030a along a lower edge 2005d opposite the upper edge 2005c (indicated by "O").Furthermore, both lateral edges 2021a, 2022a of the first connecting tab 2020a along an upper edge 2005c can be aligned with the lateral edges 231a, 232a of a first connecting tab 2030a along a lower edge 2005d opposite the upper edge 2005c. That is, both lateral edges can be offset by the same distance from a lateral edge 2005a-b.

[0097] When an upper edge 2005c and a lower edge 2005d include at least two terminal tabs 2020a, 2020b, 2030a, 2030b, at least one lateral edge of each terminal tab on an upper edge 2005c may be aligned with a corresponding lateral edge of a terminal tab on the lower edge 2005d. Furthermore, both lateral edges of each terminal tab on an upper edge 2005c may be aligned with a corresponding lateral edge of the terminal tabs on the lower edge 2005d.

[0098] Likewise, the terminal tabs 2040a, 2040b, 2050a, 2050b may be aligned in a perpendicular direction at the top and bottom edges of the second internal electrode layer 2015. That is, a lateral edge 2041a, 2042a of a first terminal tab 2040a along an upper edge may be aligned with a lateral edge 2051a, 2052a of a first terminal tab 2050a along a lower edge opposite the upper edge. Both lateral edges 2041a, 2042a of the first terminal tab 2040a along an upper edge may be aligned with the lateral edges 2051a, 2052a of a first terminal tab 2050a along a lower edge opposite the upper edge.The relationship between lateral edges of a first terminal tab at an upper edge and a first terminal tab at a lower edge, as mentioned with respect to the internal electrode layer 2005, may also apply to the internal electrode layer 2015.

[0099] With such an arrangement, a tab gap may be formed between any of the terminal tabs along a top edge 2005c of the first internal electrode layer 2005, the second internal electrode layer 2015, or both. For example, a tab gap may be formed between any terminal tabs 2020a-b, 2040a-b extending from the top edges of the respective internal electrode layers. Furthermore, a tab gap may be formed between any of the terminal tabs along a top edge 2005d of the first internal electrode layer 2005, the second internal electrode layer 2015, or both. For example, a tab gap may be formed between any terminal tabs 2030a-b, 2050a-b extending from the top edges of the respective internal electrode layers.Furthermore, the size of a tab gap between two respective tabs extending from a top edge, whether from the same internal electrode layer or from adjacent internal electrode layers, may be substantially the same as the size of a gap between the corresponding two respective tabs extending from a bottom edge. For example, a first tab gap 2016a between terminal tabs 2020a and 2020b may be substantially the same as a first tab gap 2018a between terminal tabs 2030a and 2030b. Likewise, a second tab gap 2016b between terminal tabs 2020a and 2040a may be substantially the same as a second tab gap 2018b between terminal tabs 2030a and 2050a.

[0100] Any or all of the terminal tabs 2020a, 2020b, 2040a, 2040b may be arranged parallel to the respective terminal tabs 2030a, 2030b, 2050a, 2050b extending from the layers 2005 and 2015, such that the terminal tabs extending from alternating electrode layers 2005 and 2015 may be aligned in a respective column. For example, the terminal tabs 2020a, 2020b and 2030a, 2030b of the inner electrode layer 2005 may be arranged in a corresponding stacked configuration, while the terminal tabs 2040a, 2040b and 2050a, 2050b of the inner electrode layer 2015 may be arranged in a corresponding stacked configuration.

[0101] It should be noted that the terminal tabs 2020a, 2020b are connected to the external terminals 22a and 22b, respectively, while the terminal tabs 2040a, 2040b are connected to the external terminals 24a and 24b, respectively. Accordingly, the respective terminal tabs 2020a, 2020b interlock with the respective terminal tabs 2040a, 2040b in a manner similar to the external terminals 22a-b and 24a-b. The interlocking terminal tabs can provide multiple adjacent current injection points on the associated main electrode portions.

[0102] As in Fig. 2D, the external terminals 212a, 212b, 214a, 214b may be spaced from each other and from the sides and ends of the top surface 218 and the bottom surface 220 of the capacitor 200. The external terminals 212a, 212b, 214a, 214b may include a first external end terminal 212q disposed adjacent the first end surface 226 and the first end edge 230, and a second external end terminal 214a disposed adjacent the second end surface 228 and the second end edge 232. The first external end terminal 212a and the second external end terminal 214a are spaced from each other in the longitudinal direction L by an external end terminal spacing 250.

[0103] As already described, the body 216 has a body length 215 in the longitudinal direction L. The ratio of the body length 215 to the distance 250 between the external end terminals is 1.1 or more, such as 2 or more, 5 or more, 10 or more, 20 or more, 100 or more, or 500 or more.

[0104] As continued in Fig. As shown in Figure 2D, a regular pitch 252 is defined between adjacent external terminals 212a, 212b, 214a, 214b, such as between adjacent external terminals 212a and 214b, between adjacent terminals 214b and 212b, or between adjacent terminals 212b and 214a. As previously described, the regular pitch 252 is the nominal distance between the centers of adjacent external terminals; the regular pitch 252 may also be referred to as the center-to-center spacing of the external terminals. The ratio of the body length 215 to the pitch 252 is 1.1 or more, such as 2 or more, 5 or more, 10 or more, 20 or more, 100 or more, or 500 or more.

[0105] The adjacent external terminals 212a, 212b, 214a, 214b are also spaced apart in the longitudinal direction L on the upper surface 228 by an adjacent external terminal spacing 254 between adjacent transverse sides of the external terminals. As shown, for example, in Fig. As shown in Figure 2D, a first lateral side 201a of the external terminal 212b (the first lateral side 201a facing the external terminal 214a) is spaced from a first lateral side 201b of the external terminal 214a (the first lateral side 201b facing the external terminal 212b) by the distance 254 of adjacent external terminals. The ratio of the body length 215 to the distance 254 between adjacent external terminals is 1.1 or more, such as 2 or more, 5 or more, 10 or more, 20 or more, 100 or more, or 500 or more.

[0106] As in Fig. 2A, the capacitor 200 of the Fig. 2A to 2D also include at least one terminal of a first polarity and at least one terminal of a second, opposite polarity on an upper surface. Although not shown, the lower surface includes at least one terminal of a first polarity and one terminal of a second, opposite polarity. In particular, Fig. 2A two positive terminals 212a-b and two negative terminals 214a-b on an upper surface.

[0107] As in the Fig. As shown in Figures 2A-2D, the capacitor includes four external terminals on each face, and each internal electrode layer of the capacitor includes two terminal tabs extending from the top and bottom edges of the internal electrode layer, respectively. However, as previously stated, the present invention is not limited by the number of external terminals and / or the number of terminal tabs of the internal electrode layers.

[0108] By now focusing on the Fig. Referring to Figures 3A through 3C, a capacitor 300 having a 1x2 configuration is shown. That is, the capacitor 300 includes two external terminals arranged in a linear fashion in a single dimension on a top and bottom surface of the capacitor. In the depicted embodiment, the capacitor 300 includes external terminals arranged linearly or in a single row along a longitudinal direction L, which may be referred to as a linear terminal arrangement.

[0109] In this regard, the capacitor 300 comprises a body 316 having external terminals 312, 314, including a first external terminal 312 disposed on the top surface 318 and / or the bottom surface 320 and electrically connected to first internal electrode layers 3005 ( Fig. 3B, Fig. 3C), and a second external terminal 314 disposed on the upper surface 318 and / or the lower surface 320 and electrically connected to second internal electrode layers 3015 ( Fig. 3B, Fig. 3C).

[0110] It should be noted that the Fig. 3A-3C shown capacitor 300 to the capacitor 100 of the Fig. 1A-1D is largely similar, and in the Fig. 3A-3C, the same reference numerals are used as in the Fig. 1A-1D to denote the same or similar features. However, unlike the external terminals 112, 114 of the capacitor 100, the external terminals 312, 314 of the capacitor 300 are not spaced from the end surfaces 326, 328 of the capacitor body 316. Instead, the external terminal 312 is formed along a first end of the body 316 from the top surface 318 to the bottom surface 320 such that a portion of the external terminal 312 extends along the first end surface 326. Likewise, the external terminal 314 is formed along a second end of the body 316 from the top surface 318 to the bottom surface 320 such that a portion of the external terminal 314 extends along the second end surface 328. Accordingly, the first external electrode 312, instead of external terminals formed separately on the upper and lower surfaces as in the Fig. 1A and Fig. 1D, from the upper surface 318 to the lower surface 320 such that the first external electrode 312 is disposed on the upper surface 318, the first end surface 326, and the lower surface 320, and the second external electrode 314 wraps from the upper surface 318 to the lower surface 320 such that the first external electrode 314 is disposed on the upper surface 318, the first end surface 328, and the lower surface 320.

[0111] Furthermore, the terminal lugs 3020, 3030, 3040, 3050 of the electrode layers 3005, 3015 are in contrast to the terminal lugs 1020, 1030, 1040, 1050 of the electrode layers 1005, 1015, which are offset from the side edge 100a (as indicated by “O” in Fig. 1B), not offset from the side edge 3005a. Thus, the side edges 3021, 3031, 3042, 3052 of the terminal tabs 3020, 3030, 3040, 3050 and the side edges 3005a of the electrode layers 3005, 3015 extend to the ends 326, 328 of the capacitor body 316 and can assist in the formation of the external electrodes 312, 314, for example, along the end surfaces 326, 328.

[0112] Furthermore, in the embodiments of the figures, only two internal electrode layers are used in the stack of alternating dielectric layers and internal electrode layers. However, it should be understood that the present invention may include any number of internal electrode layers, as stated herein, and is not necessarily limited.

[0113] In general, the present invention provides a capacitor having a unique configuration that provides various benefits and advantages. In this regard, it should be understood that the materials used in constructing the capacitor are not limited and may be any materials commonly used in the art, and may be formed using any method commonly used in the art.

[0114] In general, the dielectric layers are typically formed of a material having a relatively high dielectric constant (K), such as about 10 to about 40,000, in some embodiments about 50 to about 30,000, and in some embodiments about 100 to about 20,000.

[0115] In this regard, the dielectric material may be a ceramic. The ceramic may be provided in a variety of forms, such as a wafer (e.g., pre-fired) or as a dielectric material fired within the component itself.

[0116] Specific examples of high-dielectric-constant materials include NPO (COG) (up to about 100), X7R (about 3000 to about 7000), X7S, Z5U, and / or Y5V materials. It should be understood that the above materials are described by their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), and as such, they should be recognized by those skilled in the art. For example, such a material may include a ceramic. Such materials may include a perovskite, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, etc.In a particular embodiment, for example, barium strontium titanate (“BSTO”) of the formula Ba. x Sr 1-x TiO3, where x = 0 to 1, in some embodiments about 0.15 to about 0.65, and in some embodiments about 0.25 to about 0.6. Other suitable perovskites are, for example, Ba x Ca 1-x TiO3, where x is about 0.2 to about 0.8, and in some embodiments is about 0.4 to about 0.6, Pb x Zr 1-x TiO3 (“PZT”), where x ranges from about 0.05 to about 0.4, lead lanthanum zirconium titanate (“PLZT”), lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4. Other complex perovskites include A[B1 1 / 3 B2 2 / 3] O3 materials, where A = Ba x Sr 1-x is (x can have a value from 0 to 1); B1 = Mg y Zn 1-yis (y can have a value from 0 to 1); B2 = Ta z Nb 1-z (z can have a value from 0 to 1). In a particular embodiment, the dielectric layers may comprise a titanate.

[0117] The internal electrode layers may be made of any of a variety of different metals known in the art. The internal electrode layers may be made of a metal, such as a conductive metal. The materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as the respective sputtered layers of chromium, nickel, and gold, may also be suitable. In a particular embodiment, the internal electrode layers may comprise nickel or an alloy thereof.

[0118] The external terminals may be made of any of a variety of different metals known in the art. The external terminals may be made of a metal, such as a conductive metal. The materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. In a particular embodiment, the external terminals may comprise copper or an alloy thereof.

[0119] The external terminals can be formed using any method well known in the art. The external terminals can be formed using methods such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spraying, etc.

[0120] The external terminals may be formed such that the external terminal is a thin-film metallization. Such a thin-film metallization may be formed by depositing a conductive material, such as a conductive metal, on an exposed portion of an internal electrode layer. For example, a leading edge of an internal electrode layer may be exposed to allow the formation of a metallized terminal.

[0121] The external terminals may have an average thickness of about 50 µm or less, such as about 40 µm or less, such as about 30 µm or less, such as about 25 µm or less, such as about 20 µm or less, to about 5 µm or more, such as about 10 µm or more, such as about 15 µm or more. For example, the external terminals may have an average thickness of about 5 µm to about 50 µm, such as about 10 µm to about 40 µm, such as about 15 µm to about 30 µm, such as about 15 µm to about 25 µm.

[0122] In general, the external terminal may comprise a metallized terminal. For example, the external terminal may comprise a galvanized terminal, an electroless plated terminal, or a combination thereof. For example, a galvanized terminal may be formed by electrolytic deposition. An electroless plated terminal may be formed by electroless deposition.

[0123] If the external terminal is constructed from multiple layers, the external terminal can comprise a plated terminal and an electroless plated terminal. For example, electroless plating can be used first to deposit an initial material layer. Then, the metallization technique can be switched to a plating system, which can enable faster material buildup.

[0124] When forming the metallized terminals using either metallization process, a leading edge of the terminal tabs of the internal electrode layers, which is exposed from the body of the capacitor, is exposed to a metallization solution. This exposure allows the capacitor, in one embodiment, to be immersed in the metallization solution.

[0125] The metallization solution contains a conductive material, such as a conductive metal, and is used to form the metallized terminal. This conductive material can be any of the materials mentioned above or any material generally known in the art. The metallization solution can be a nickel sulfamate bath solution or another nickel solution. Alternatively, the metallization solution can also be a copper acid bath or another suitable copper solution.

[0126] Furthermore, it should be noted that the metallization solution may also include other additives well known in the art. For example, the additives may include other organic additives and media that can assist the metallization process. Furthermore, additives may be used to maintain the metallization solution at a desired pH. In one embodiment, resistance-reducing additives may be used in the solutions to promote complete metallization coverage and bonding of the metallization materials to the capacitor and the exposed leading edges of the terminal tabs of the internal electrode layers.

[0127] The capacitor may be exposed to, submerged in, or immersed in the metallization solution for a predetermined period of time. This exposure time is not necessarily limited, but it may be a sufficient period of time to allow enough metallization material to deposit to form the metallized terminal. In this regard, the time should be sufficient to allow the formation of a continuous connection between the desired exposed adjacent leading edges of terminal tabs of a given polarity of the respective internal electrode layers within a set of alternating dielectric layers and internal electrode layers.

[0128] In general, the difference between electroplating and electroless plating is that electroplating involves an electrical bias, such as using an external power source. The electroplating solution can typically be exposed to a high current density range, for example, 10 to 15 amps / ft 2 (rated at 9.4 volts). A connection can be formed with a negative connection to the capacitor, which requires the formation of the metallized terminals, and a positive connection to a solid material (e.g., Cu in Cu metallization solution) in the same metallization solution. This means that the capacitor is biased to a polarity opposite to that of the metallization solution. With such a process, the conductive material of the metallization solution is attracted to the metal of the exposed leading edge of the terminal tabs of the internal electrode layers.

[0129] Before the capacitor is immersed in or exposed to a metallization solution, various pretreatment steps can be used. Such steps can be performed for a variety of purposes, including catalyzing, accelerating, and / or improving the adhesion of the metallization materials to the leading edges of the terminal tabs.

[0130] Additionally, a preliminary cleaning step may be employed prior to metallization or any other pretreatment steps. Such a step may be employed to remove any accumulated oxide that may form on the exposed terminal tabs of the internal electrode layers. This cleaning step may be particularly useful in assisting in the removal of any accumulation of nickel oxide when the internal electrodes or other conductive elements are made of nickel. Cleaning of the components may be accomplished by full immersion in a pre-cleaning bath, such as one comprising an acid cleaner. In one embodiment, exposure may be for a predetermined time, such as on the order of about 10 minutes. Alternatively, cleaning may be accomplished by chemical polishing or harperization steps.

[0131] In addition, a step for activating the exposed metallic leading edges of the terminal tabs of the internal electrode layers may also be performed to facilitate the deposition of the conductive materials. Activation can be achieved by immersion in palladium salts, photopatterned palladium-organic precursors (via mask or laser), screen-printed or inkjet-deposited palladium compounds, or electrophoretic palladium deposition. It should be understood that palladium-based activation is disclosed herein merely as an example of activation solutions that often work well with exposed tab parts made of nickel or an alloy thereof. However, it should be understood that other activation solutions may also be used and are therefore not necessarily limited.

[0132] Furthermore, instead of or in addition to the above-mentioned activation step, the activation dopant can also be introduced into the conductive material when forming the internal electrode layers of the capacitor. For example, if the internal electrode layer comprises nickel and the activation dopant comprises palladium, the palladium dopant can be introduced into the nickel ink or composition forming the internal electrode layers. This can eliminate the palladium activation step. It should also be noted that some of the above activation methods, such as organometallic precursors, are also suitable for the co-deposition of glass formers for enhanced adhesion to the generally ceramic body of the capacitor.When activation steps are undertaken as described above, traces of the activator material may often remain on the exposed conductive parts before and after the terminals are metallized.

[0133] In addition, post-treatment steps can also be used after metallization if desired or necessary. Such steps can be performed for a variety of purposes, including strengthening and / or improving the adhesion of the materials. For example, a heating (or annealing) step can be used after the metallization step. This heating can be achieved by baking, laser irradiation, UV exposure, microwave exposure, arc welding, etc.

[0134] As stated, the external terminal may comprise at least one metallization layer. In one embodiment, the external terminal may comprise only a single metallization layer. However, it should be understood that the external terminals may also comprise a plurality of metallization layers. For example, the external terminals may comprise a first metallization layer and a second metallization layer. Furthermore, the external terminals may also comprise a third metallization layer. Furthermore, the materials for these metallization layers may be any of those mentioned above and those generally known in the art.

[0135] For example, a metallization layer, such as a first metallization layer, may comprise copper or an alloy thereof. Another metallization layer, such as a second metallization layer, may comprise nickel or an alloy thereof. Alternatively, another metallization layer, such as the second metallization layer, may comprise copper or an alloy thereof. Another metallization layer, such as a third metallization layer, may comprise tin, lead, gold, or a combination thereof, such as an alloy. Alternatively, an initial metallization layer may also comprise nickel, followed by metallization layers of tin or gold. In another embodiment, an initial metallization layer of copper and then a nickel layer may be formed.

[0136] In one embodiment, the initial or first metallization layer may consist of a conductive metal (e.g., copper). This region may be covered with a second layer containing a polymeric resistive material for sealing. The region may then be polished to selectively remove polymeric resistive material and then re-metallized with a third layer containing a conductive metallic material (e.g., copper).

[0137] The above-mentioned second layer above the initial metallization layer may correspond to a solder barrier layer, for example, a nickel solder barrier layer. In some embodiments, the above-mentioned layer may be formed by electroplating an additional layer of metal (e.g., nickel or copper) over an electrolessly deposited or electroplated initial layer (e.g., deposited copper). Other exemplary materials for the above-mentioned solder barrier layer are nickel-phosphorus, gold, and silver. A third layer on the above-mentioned solder barrier layer may, in some embodiments, correspond to a conductive layer, such as deposited Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or another suitable deposited solder metal.

[0138] Additionally, a metallization layer may be formed, followed by an electroplating step to obtain a resistive alloy or a coating of a higher-resistivity metal alloy, such as an electroless Ni-P alloy, over such metallization. However, it should be understood that any metal coating may be used, as will be understood by those skilled in the art from the full disclosure herein.

[0139] It should be noted that each of the above steps can be performed as a volume process, such as drum metallization, fluidized bed metallization, and / or flow metallization termination methods, all of which are well known in the art. Such volume processes allow multiple components to be processed at once, resulting in an efficient and rapid termination process. This is a particular advantage over conventional termination methods, such as thick-film termination printing, which require individual processing of components.

[0140] As described here, the formation of the external terminals is generally guided by the position of the exposed leading edges of the terminal tabs of the internal electrode layers. Such phenomena can be described as "self-determining," since the formation of the external metallized terminals is determined by the configuration of the exposed conductive metal of the internal electrode layers at the selected peripheral locations on the capacitor.

[0141] Additional aspects of the above-described technique for forming thin-film metallized terminals are described in U.S. Patent Nos. 7,177,137 (Ritter et al.) and 7,463,474 (Ritter et al.), which are incorporated herein by reference for all purposes. It should be understood that additional methods for forming capacitor terminals may also be within the scope of the present technique. Exemplary alternatives include, but are not limited to, forming terminals by metallization, magnetism, masking, electrophoresis / electrostatics, sputtering, vacuum deposition, printing, or other methods for forming both thick-film and thin-film conductive layers.

[0142] Furthermore, the capacitor can then be subjected to a solder mask. For example, this can enable coating of the capacitor. Without wishing to be bound, such a mask can help prevent oxidation of the metallization layers, such as the copper plating layer, particularly if this layer is the final metallization layer of the external terminal. Such solder mask material is not necessarily limited by the present invention. For example, this material can comprise any of those mentioned above with respect to the solder barrier layer. Additionally or alternatively, this material can also comprise an epoxy resin, such as a liquid epoxy resin, which is then cured.

[0143] When such a material is provided on the capacitor, it may be necessary to gain access to the metallization layer and the external terminal to form an electrical connection. In this regard, a laser can be used to create a hole through the mask layer. This hole can then be filled with a conductive material, such as copper. This can then be used to form an electrical connection to the capacitor.

[0144] If we focus on the Fig. 4 and Fig. 5, the capacitor as disclosed herein can be mounted using various methods. For example, the capacitor can be mounted on a printed circuit board that includes a substrate (e.g., insulating layer) having a top surface and a bottom surface. When we refer to Fig. 4, a capacitor 300 as shown in Fig. 3A, may be mounted on a circuit board 450 having a top surface 452 and a bottom surface 454. The circuit board 450 has a plurality of electrical traces defined therein. The external terminals 312, 314 of the capacitor 300 are in respective electrical communication with the predetermined traces of the circuit board 450. Additionally, the external terminals 312, 314 of the capacitor 300 may be physically connected to the circuit board 450 using any method well known in the art, such as general soldering techniques. It should be noted that the capacitor 300 is used only as an example; in other embodiments, the capacitor 100 and / or the capacitor 200 may be mounted on a mounting surface, such as a circuit board 450.

[0145] As in Fig. 5, a package of an integrated circuit 560 may also be provided on a circuit board 550. The package of the integrated circuit 560 may be connected to the circuit board 550 using a ball grid array 562. The circuit board may further include a processor 564. The processor 564 may also be connected to the circuit board 560 using a ball grid array 566.

[0146] In general, the ball grid array 562 may be configured such that the pitch is 1.5 mm or less, such as 1.25 mm or less, such as 1 mm or less, such as 0.8 mm or less, such as 0.6 mm or less, and 0.4 mm or more, such as 0.5 mm or more, such as 0.6 mm or more.

[0147] Additionally, the package of the integrated circuit 560 may also be connected to the circuit board 550 using a capacitor as defined herein. In this regard, the internal electrode layers of the capacitor 100 / 200 / 300 may be positioned so that they are perpendicular to a horizontal plane of the circuit board 550 and the integrated circuit package 560. In other words, the internal electrode layers of the capacitor 100 / 200 / 300 may be positioned so that they are substantially non-parallel to the circuit board 550. For example, the capacitor 100 / 200 / 300 may be positioned between the integrated circuit package 560 and the circuit board 550 such that the capacitor 100 / 200 / 300 is sandwiched between the two components. In this regard, the capacitor 100 / 200 / 300 is directly connected to the integrated circuit package 560 and the circuit board 550.For example, the capacitor 100 / 200 / 300 may be connected (e.g., physically and / or electrically) to the circuit board 550 and / or to a circuit package 560 using any method well known in the art, such as general soldering techniques.

[0148] By using the capacitor in the above arrangement, the capacitor 100 / 200 / 300 can allow the removal of some of the original ball grid array 562. However, the capacitor 100 / 200 / 300 can still be surrounded by a ball grid array 562, as shown in Fig. 5 is shown.

[0149] Thus, as in Fig.5, the capacitor 100 / 200 / 300 of the present invention may be directly connected to an integrated circuit package 560 and a circuit board 550, such as a printed circuit board. This direct connection allows current 568 to flow through the capacitor, thus establishing a direct power-to-ground connection.

[0150] Furthermore, although not shown here, in one embodiment, the package of the integrated circuit itself may include the multilayer capacitor. In this regard, the capacitor may be embedded directly within the package. This embedding of the capacitor may enable a reduction in size, which may be beneficial for various electronic applications.

[0151] While the above provides only one example of a method for mounting the capacitor disclosed herein, it should be understood that other methods may also be used. For example, the capacitor may be mounted using a land grid array configuration. The capacitor may also be embedded in another substrate or component.

[0152] In the embodiments described above, the internal electrode layers are aligned in a substantially vertical configuration. This is, of course, by no means required, and other geometric configurations, such as a horizontal configuration, may also be used.

[0153] These and other modifications and variations of the present invention may be practiced by those skilled in the art without departing from the spirit and scope of the present invention. Furthermore, it should be understood that aspects of the various embodiments may be substituted for one another, in whole or in part. Furthermore, those skilled in the art will appreciate that the above description is merely exemplary and is not intended to limit the invention, which is particularly described in the appended claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 420,722

[0001] US 7,177,137

[0141]

Claims

[1] Multilayer capacitor comprising: a body having an upper surface, a lower surface opposite the upper surface, a pair of side surfaces opposite each other along a transverse direction, and a pair of end surfaces opposite each other along a longitudinal direction, the body also having side edges defining lateral boundaries of the upper and lower surfaces and comprising a first upper side edge, a second upper side edge, a first lower side edge, and a second lower side edge, each extending between the pair of end surfaces along the longitudinal direction.the first upper side edge and the second upper side edge are opposite each other along the transverse direction, and the first lower side edge and the second lower side edge are opposite each other along the transverse direction, the body contains alternating dielectric layers and internal electrode layers, the internal electrode layers comprising first internal electrode layers and second internal electrode layers, each internal electrode layer comprising:. a main body having an upper edge, a lower edge opposite the upper edge, and two side edges extending between the upper edge and the lower edge, at least one terminal tab extending from the upper edge of the main body of the internal electrode layer, and at least one terminal tab extending from the lower edge of the main body of the internal electrode layer, and external terminals, including a first external terminal arranged on the upper and / or lower surface and electrically connected to the first internal electrode layers, and a second external terminal arranged on the upper and / or lower surface and electrically connected to the second internal electrode layers, wherein the external terminals are arranged linearly on the upper and / or lower surface of the body and are spaced from the side edges of the body at such a distance that only dielectric material is present between the external terminals and the side edges of the body. [2] A multilayer capacitor according to claim 1, wherein the first external terminal is located adjacent to a first end face of the pair of end faces of the body, and the second external terminal is located adjacent to a second end face of the pair of end faces of the body, wherein the first external terminal and the second external terminal are spaced apart from each other in the longitudinal direction on the upper surface by an external end terminal spacing, wherein the body has a body length in the longitudinal direction and where the ratio of the body length to the external end connection distance is 1.1 or more. [3] A multilayer capacitor according to claim 2, wherein the ratio of the body length to the external end terminal pitch is in the range of 2 to 500. [4] A multilayer capacitor according to claim 2, wherein the ratio of the body length to the external end terminal pitch is in the range of 10 to 100. [5] A multilayer capacitor according to claim 1, wherein the first external terminal is located adjacent to a first end face of the pair of end faces of the body, and the second external terminal is located adjacent to a second end face of the pair of end faces of the body, wherein the first external terminal is formed on the upper surface, the lower surface and the first end surface from the upper surface to the lower surface, so that the first external terminal is located on the upper surface, the lower surface and the first end surface, and wherein the second external terminal is formed on the upper surface, the lower surface and the second end surface from the upper surface to the lower surface such that the second external terminal is located on the upper surface, the lower surface and the second end surface. [6] A multilayer capacitor according to claim 1, wherein the external terminals are arranged in at least two columns, the at least two columns being spaced apart from each other along the longitudinal direction. [7] A multilayer capacitor according to claim 6, wherein the number of columns of the external terminals corresponds to the number of terminal tabs extending from the top edge of the main body of a respective internal electrode layer. [8] A multilayer capacitor according to claim 1, wherein the body has end edges defining longitudinal boundaries of the upper and lower surfaces and comprising a first upper end edge, a second upper end edge, a first lower end edge and a second lower end edge each extending between the pair of side surfaces along the longitudinal direction, the first upper end edge and the second upper end edge are opposite to each other along the longitudinal direction, the first lower end edge and the second lower end edge are opposite to each other along the longitudinal direction, and wherein the external terminals are spaced from the end edges of the body such that only dielectric material is present between the external terminals and the end edges of the body. [9] A multilayer capacitor according to claim 1, wherein the external terminals comprise adjacent terminals spaced apart longitudinally on the upper surface by a pitch of adjacent external terminals, wherein the body has a body length in the longitudinal direction and where the ratio of the body length to the distance between adjacent external terminals is 1.1 or more. [10] A multilayer capacitor according to claim 9, wherein the ratio of the body length to the distance between adjacent external terminals is in the range of 2 to 500. [11] A multilayer capacitor according to claim 9, wherein the ratio of the body length to the distance between adjacent external terminals is in the range of 10 to 100. [12] A multilayer capacitor according to claim 2, wherein the external terminals comprise an adjacent terminal adjacent to the first external terminal on the same surface of the body, the first external terminal and the adjacent terminal being spaced apart longitudinally on the same surface by a pitch of adjacent external terminals, and the ratio of the pitch between external end terminals to the pitch between adjacent external terminals is 1.1 or more. [13] A multilayer capacitor according to claim 12, wherein the ratio of the distance between external end terminals to the distance between adjacent external terminals is in the range of 2 to 500. [14] A multilayer capacitor according to claim 12, wherein the ratio of the distance between external end terminals to the distance between adjacent external terminals is in the range of 10 to 100. [15] A multilayer capacitor according to claim 1, wherein a regular distance is defined between adjacent external terminals, wherein the body has a body length in the longitudinal direction and where the ratio of the body length to the regular spacing is 1.1 or more. [16] A multilayer capacitor according to claim 15, wherein the ratio of the body length to the regular pitch is in the range of 2 to 500. [17] A multilayer capacitor according to claim 15, wherein the ratio of the body length to the regular pitch is in the range of 10 to 100. [18] A multilayer capacitor according to claim 1, wherein the first external terminal is located on the upper surface of the body and the second external terminal is located on the upper surface of the body, and wherein the external terminals further comprise a third external terminal located on the lower surface and electrically connected to the first internal electrode layers, and a fourth external terminal located on the lower surface and electrically connected to the second internal electrode layers. [19] A multilayer capacitor according to claim 1, wherein the first internal electrode layer and the second internal electrode layer are interlocked in an opposite relationship, and a dielectric layer is disposed between each of the first internal electrode layer and the second internal electrode layer. [20] A multilayer capacitor according to claim 19, wherein the dielectric layers comprise a ceramic. [21] A multilayer capacitor according to claim 1, wherein each internal electrode layer comprises at least two terminal tabs, the at least two terminal tabs extend from the upper edge of the main body, the lower edge of the main body, or both the upper edge and the lower edge of the main body, the two terminal tabs comprising a first terminal tab and a second terminal tab. [22] The multilayer capacitor of claim 21, wherein the first terminal tab extends from the top edge and the second terminal tab extends from the bottom edge, and wherein at least one lateral edge of the first terminal tab is substantially aligned with at least one lateral edge of the second terminal tab. [23] A multilayer capacitor according to claim 21, wherein the first terminal tab extends from the upper edge and the second terminal tab extends from the lower edge, wherein the first connection tab and the second connection tab each comprise two lateral edges and wherein both lateral edges of the first terminal tab are substantially aligned with respective lateral edges of the second terminal tab. [24] A multilayer capacitor according to claim 1, wherein at least one lateral edge of the terminal tab at the upper edge is substantially aligned with at least one lateral edge of the terminal tab at the lower edge. [25] A multilayer capacitor according to claim 1, wherein both lateral edges of the terminal tab at the upper edge are substantially aligned with the respective lateral edges of the terminal tab at the lower edge. [26] The multilayer capacitor according to claim 1, wherein the at least one terminal tab extending from the upper edge of the main body of the internal electrode layer and the at least one terminal tab extending from the lower edge of the main body of the internal electrode layer include a side edge aligned with a side edge of the main body of the internal electrode layer. [27] A multilayer capacitor according to claim 1, wherein the internal electrode layers comprise a conductive metal. [28] A multilayer capacitor according to claim 1, wherein the external terminals comprise a plating layer. [29] A multilayer capacitor according to claim 1, wherein the external terminals comprise a layer deposited by electroless plating. [30] A multilayer capacitor according to claim 1, wherein the external terminals comprise an electroless plating layer and a plating layer. [31] A multilayer capacitor according to claim 1, wherein the external terminals comprise a first electroless plating layer, a second plating layer, and a third plating layer. [32] A multilayer capacitor according to claim 31, wherein the first electroless plating layer comprises copper, the second plating layer comprises nickel, and the third plating layer comprises tin. [33] A multilayer capacitor according to claim 1, wherein the capacitor comprises at least three sets of alternating dielectric layers and internal electrode layers. [34] A printed circuit board comprising the multilayer capacitor according to claim 1 located on the printed circuit board. [35] The circuit board of claim 34, wherein the board further comprises an integrated circuit package, and wherein the multilayer capacitor is located between the circuit board and the integrated circuit package in a vertical direction such that the circuit board, the multilayer capacitor, and the integrated circuit package are in a stacked arrangement. [36] The circuit board of claim 35, wherein the multilayer capacitor is directly connected to the circuit board and the integrated circuit package. [37] An integrated circuit package containing the multilayer capacitor according to claim 1.

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