Semiconductor device and method for manufacturing a semiconductor device

Abstract

A semiconductor device is provided that can be miniaturized or highly integrated. The semiconductor device includes first to third transistors and first to fourth insulating layers. The first transistor includes first to third conductive layers, a fifth insulating layer, and a first semiconductor layer. The first insulating layer, the third conductive layer, and the second insulating layer above the first conductive layer have a first opening. The fifth insulating layer is in contact with a sidewall of the first opening. The first semiconductor layer is in contact with a bottom of the first opening and a side surface of the fifth insulating layer. The second conductive layer is above and in contact with the first semiconductor layer. The second (third) transistor includes second, fourth, and fifth (sixth to eighth) conductive layers, a sixth (seventh) insulating layer, and a second (third) semiconductor layer.The third (fourth) insulating layer and the fourth (seventh) conductive layer above the second (sixth) conductive layer have a second (third) opening. The second (third) semiconductor layer is in contact with a bottom and a sidewall of the second (third) opening. The sixth (seventh) insulating layer is above and in contact with the second (third) semiconductor layer. The fifth (eighth) conductive layer is above and in contact with the sixth (seventh) insulating layer.

Description

Technical area

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Another embodiment of the present invention relates to a memory device and a method for manufacturing the memory device. One embodiment of the present invention relates to a transistor and a method for manufacturing the transistor. One embodiment of the present invention relates to a capacitor and a method for manufacturing the capacitor. Another embodiment of the present invention relates to an electronic device.

[0002] Note that an embodiment of the present invention is not limited to the above technical field. As an exemplary technical field of an embodiment of the present invention, a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch screen), an electronic device including any of these, an operating method thereof, or a method of manufacturing thereof may be given.

[0003] In this specification and the like, a semiconductor device refers to a device that utilizes semiconductor properties, and refers to a circuit including a semiconductor element (e.g., a transistor, a diode, or a photodiode), a device including the circuit, and the like. The semiconductor device also refers to devices that can operate by utilizing semiconductor properties. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is stored in a package are examples of the semiconductor device. In some cases, a memory device, a display device, a light-emitting device, a lighting device, and an electronic appliance are semiconductor devices per se, and they also include a semiconductor device. State of the art

[0004] In recent years, the development of semiconductor devices has progressed, and large-scale integration (LSI) circuits are being used in semiconductor devices. For example, central processing units (CPUs), memories, and the like are used in semiconductor devices. A CPU is an aggregate of semiconductor elements; the CPU includes a semiconductor integrated circuit (including at least one transistor and one memory) formed into a chip by processing a semiconductor wafer and provided with an electrode that serves as a connection terminal.

[0005] A semiconductor circuit (IC chip) of a CPU or memory is mounted on a circuit board, such as a printed circuit board, to be used as a component of various electronic devices.

[0006] A technique in which a transistor is formed using a semiconductor thin film formed over a substrate with an insulating surface has attracted attention. The transistor is used in a wide range of electronic devices, such as integrated circuits (ICs) and display devices. A silicon-based semiconductor material is widely known as a semiconductor thin film that can be applied to a transistor. Another material that has attracted attention is an oxide semiconductor.

[0007] It is known that a transistor containing an oxide semiconductor has a very low leakage current in a non-conductive state. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristic of the transistor containing an oxide semiconductor. Furthermore, Patent Document 2, for example, discloses a memory device that can retain stored contents for a long time by utilizing the low leakage current characteristic of the transistor containing an oxide semiconductor.

[0008] In recent years, the demand for a higher-density integrated circuit has increased with the reduction in size and weight of electronic devices. Furthermore, the productivity of a semiconductor device including an integrated circuit is to be improved. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique that enables a higher-density integrated circuit by overlapping a plurality of memory cells by stacking a first transistor including an oxide semiconductor film and a second transistor including an oxide semiconductor film.

[0009] Furthermore, a higher-density integrated circuit can be achieved by using vertical transistors. For example, Patent Document 4 discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode, with a gate insulating layer interposed therebetween. [Reference][Patent document] [Patent Document 1] Japanese Patent Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Laid-Open No. 2011-151383 [Patent Document 3] PCT International Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Laid-Open No. 2013-211537 [Non-patent document]

[0010] [Non-Patent Document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72 nm,” IEDM Tech. Dig., 2019, pp. 50-53 Summary of the inventionProblem to be solved by the invention

[0011] An object of an embodiment of the present invention is to provide a semiconductor device, a memory device, or a transistor which can be miniaturized or highly integrated. Another object of an embodiment of the present invention is to provide a highly reliable semiconductor device, a highly reliable memory device, or a highly reliable transistor. Another object of an embodiment of the present invention is to provide a semiconductor device or a memory device with high read accuracy. Another object of an embodiment of the present invention is to provide a transistor with high on-state current. Another object of an embodiment of the present invention is to provide a transistor with advantageous electrical characteristics.Another object of an embodiment of the present invention is to provide a semiconductor device or a memory device with low cost. Another object of an embodiment of the present invention is to provide a semiconductor device or a memory device with low power consumption. Another object of an embodiment of the present invention is to provide a semiconductor device or a memory device with high operating speed. Another object of an embodiment of the present invention is to provide a novel semiconductor device, a novel memory device, or a novel transistor.

[0012] An object of an embodiment of the present invention is to provide a method for manufacturing a semiconductor device, a memory device, or a transistor that can be miniaturized or highly integrated. Another object of an embodiment of the present invention is to provide a method for manufacturing a highly reliable semiconductor device, a highly reliable memory device, or a highly reliable transistor. Another object of an embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with high read accuracy. Another object of an embodiment of the present invention is to provide a method for manufacturing a transistor with high on-state current.Another object of an embodiment of the present invention is to provide a method for manufacturing a transistor with advantageous electrical properties. Another object of an embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with high yield. Another object of an embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with low power consumption. Another object of an embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with a high operating speed.Another object of an embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device, a novel memory device or a novel transistor.

[0013] It should be noted that the description of these objects does not preclude the existence of further objects. In one embodiment of the present invention, it is not necessarily required to fulfill all of the objects. Further objects may be derived from the explanation of the description, the drawings, and the claims. Means to solve the problem

[0014] One embodiment of the present invention is a semiconductor device comprising a first transistor, a second transistor, a third transistor, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring. A source and a drain of each of the first transistor, the second transistor, and the third transistor are provided at different heights with respect to a substrate surface. The second transistor is provided so as to overlap the first transistor. The third transistor is provided so as to overlap the second transistor. A gate of the first transistor and the first wiring are electrically connected to each other. A terminal of source and drain of the first transistor and a gate of the second transistor are electrically connected to each other.The other terminal of the source and drain of the first transistor and the second line are electrically connected to each other. One terminal of the source and drain of the second transistor and one terminal of the source and drain of the third transistor are electrically connected to each other. The other terminal of the source and drain of the second transistor and the third line are electrically connected to each other. A gate of the third transistor and the fourth line are electrically connected to each other. The other terminal of the source and drain of the third transistor and the fifth line are electrically connected to each other.

[0015] In the above, at least one of the first transistor, the second transistor and the third transistor is preferably a transistor comprising a metal oxide.

[0016] In the above, a node electrically connecting one of the source and drain of the first transistor and the gate of the second transistor is preferably included. The first transistor preferably has a function of writing data corresponding to a potential supplied from the second wiring to the node when a first potential is supplied from the first wiring, and a function of holding the data at the node when a second potential is supplied from the first wiring. The second transistor and the third transistor each preferably have a function of reading the data held at the node when a fifth potential is supplied to the fourth wiring in a state where a third potential is supplied to the third wiring and a fourth potential is supplied to the fifth wiring. The first potential is preferably a potential at which the first transistor is turned on.The second potential is preferably a potential at which the first transistor is turned off. The fourth potential is preferably higher than the third potential. The fifth potential is preferably a potential at which the third transistor is turned on.

[0017] Another embodiment of the present invention is a semiconductor device comprising a first transistor, a second transistor, a third transistor, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring. A source and a drain of each of the first transistor, the second transistor, and the third transistor are provided at different heights with respect to a substrate surface. The second transistor is provided so as to overlap the first transistor. The third transistor is provided so as to overlap the second transistor. The first transistor is provided such that, in a plan view, a gate encloses a semiconductor layer. The second transistor is provided such that, in a plan view, a semiconductor layer encloses a gate.The third transistor is provided such that, in a plan view, a semiconductor layer encloses a gate. The gate of the first transistor and the first wiring are electrically connected to each other. One terminal of the source and drain of the first transistor and the gate of the second transistor are electrically connected to each other. The other terminal of the source and drain of the first transistor and the second wiring are electrically connected to each other. One terminal of the source and drain of the second transistor and one terminal of the source and drain of the third transistor are electrically connected to each other. The other terminal of the source and drain of the second transistor and the third wiring are electrically connected to each other. The gate of the third transistor and the fourth wiring are electrically connected to each other. The other terminal of the source and drain of the third transistor and the fifth wiring are electrically connected to each other.

[0018] In the above, at least one of the first transistor, the second transistor and the third transistor is preferably a transistor comprising a metal oxide in a semiconductor layer.

[0019] In the above, a node electrically connecting one of the source and drain of the first transistor and the gate of the second transistor is preferably included. The first transistor preferably has a function of writing data corresponding to a potential supplied from the second wiring to the node when a first potential is supplied from the first wiring, and a function of holding the data at the node when a second potential is supplied from the first wiring. The second transistor and the third transistor each preferably have a function of reading the data held at the node when a fifth potential is supplied to the fourth wiring in a state where a third potential is supplied to the third wiring and a fourth potential is supplied to the fifth wiring. The first potential is preferably a potential at which the first transistor is turned on.The second potential is preferably a potential at which the first transistor is turned off. The fourth potential is preferably higher than the third potential. The fifth potential is preferably a potential at which the third transistor is turned on.

[0020] Another embodiment of the present invention is a semiconductor device comprising a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first transistor, the second transistor, and the third transistor are stacked in this order. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fifth insulating layer, and a first semiconductor layer. The first insulating layer, the third conductive layer, and the second insulating layer are stacked in this order above the first conductive layer. A first opening reaching the first conductive layer is provided in the first insulating layer, the third conductive layer, and the second insulating layer.The fifth insulating layer is provided in contact with a sidewall of the first opening. The first semiconductor layer is provided in contact with a top surface of the first conductive layer in the first opening, a side surface of the fifth insulating layer in the first opening, and a top surface of the second insulating layer. The second conductive layer is provided in contact with a top surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer. The second transistor includes the second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth insulating layer, and a second semiconductor layer. The third insulating layer and the fourth conductive layer are stacked in this order over the second conductive layer.A second opening reaching the second conductive layer is provided in the third insulating layer and the fourth conductive layer. The second semiconductor layer is provided in contact with a top surface of the second conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the fourth conductive layer in the second opening, and a top surface of the fourth conductive layer. The sixth insulating layer is provided in contact with a top surface of the second semiconductor layer, a side surface of the second semiconductor layer, the top surface of the fourth conductive layer, the side surface of the fourth conductive layer, and a top surface of the third insulating layer. The fifth conductive layer is provided over and in contact with the sixth insulating layer so as to fill the second opening.The third transistor includes a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a seventh insulating layer, and a third semiconductor layer. The sixth conductive layer is provided in contact with a top surface of the fifth conductive layer. The fourth insulating layer and the seventh conductive layer are stacked in this order above the sixth conductive layer. The third opening reaching the sixth conductive layer is provided in the fourth insulating layer and the seventh conductive layer. The third semiconductor layer is provided in contact with a top surface of the sixth conductive layer in the third opening, a side surface of the fourth insulating layer in the third opening, a side surface of the seventh conductive layer in the third opening, and a top surface of the seventh conductive layer.The seventh insulating layer is provided in contact with a top surface of the third semiconductor layer, a side surface of the third semiconductor layer, the top surface of the seventh conductive layer, the side surface of the seventh conductive layer, and a top surface of the fourth insulating layer. The eighth conductive layer is provided above and in contact with the seventh insulating layer such that it fills the third opening.

[0021] In the above, at least one of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer preferably comprises a metal oxide.

[0022] In the above, the second conductive layer preferably comprises a ninth conductive layer and a tenth conductive layer. The ninth conductive layer is preferably provided in contact with the upper surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer. The tenth conductive layer is preferably provided in contact with an upper surface of the ninth conductive layer such that it includes a region overlapping with the first conductive layer. The second semiconductor layer is preferably provided in contact with an upper surface of the tenth conductive layer.

[0023] In the above, the second conductive layer preferably comprises a ninth conductive layer, a tenth conductive layer, and an eleventh conductive layer. The ninth conductive layer is preferably provided in contact with the upper surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer. The tenth conductive layer is preferably provided in contact with an upper surface of the ninth conductive layer. The eleventh conductive layer is preferably provided in contact with an upper surface of the tenth conductive layer such that it includes a region overlapping with the first conductive layer. The second semiconductor layer is preferably provided in contact with an upper surface of the eleventh conductive layer.

[0024] In the above, a capacitor is preferably included between the first transistor and the second transistor. The first transistor, the second transistor, the capacitor, and the third transistor are preferably stacked in this order. The capacitor preferably includes the ninth conductive layer, the tenth conductive layer, and an eighth insulating layer. The eighth insulating layer preferably includes a region in contact with a side surface of the ninth conductive layer. The tenth conductive layer preferably covers at least a part of the side surface of the ninth conductive layer with the eighth insulating layer interposed therebetween. The ninth conductive layer is preferably provided in contact with the upper surface of the fifth conductive layer. The sixth conductive layer is preferably provided in contact with an upper surface of the ninth conductive layer.

[0025] Another embodiment of the present invention is a semiconductor device comprising a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first transistor, the second transistor, and the third transistor are stacked in this order. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fifth insulating layer, and a first semiconductor layer. The first insulating layer, the third conductive layer, and the second insulating layer are stacked in this order above the first conductive layer. A first opening reaching the first conductive layer is provided in the first insulating layer, the third conductive layer, and the second insulating layer.The fifth insulating layer is provided in contact with a sidewall of the first opening. The first semiconductor layer is provided in contact with a top surface of the first conductive layer in the first opening, a side surface of the fifth insulating layer in the first opening, and a top surface of the second insulating layer. The second conductive layer is provided in contact with a top surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer. The third conductive layer is provided such that, in a plan view, it encloses the first semiconductor layer with the fifth insulating layer therebetween. The second transistor includes the second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth insulating layer, and a second semiconductor layer.The third insulating layer and the fourth conductive layer are stacked in this order over the second conductive layer. A second opening reaching the second conductive layer is provided in the third insulating layer and the fourth conductive layer. The second semiconductor layer is provided so as to be in contact with a top surface of the second conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the fourth conductive layer in the second opening, and a top surface of the fourth conductive layer, and to enclose the fifth conductive layer in a plan view, with the sixth insulating layer interposed therebetween.The sixth insulating layer is provided in contact with a top surface of the second semiconductor layer, a side surface of the second semiconductor layer, the top surface of the fourth conductive layer, the side surface of the fourth conductive layer, and a top surface of the third insulating layer. The fifth conductive layer is provided over and in contact with the sixth insulating layer so as to fill the second opening. The third transistor includes a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a seventh insulating layer, and a third semiconductor layer. The sixth conductive layer is provided in contact with a top surface of the fifth conductive layer. The fourth insulating layer and the seventh conductive layer are stacked in this order over the sixth conductive layer.The third opening reaching the sixth conductive layer is provided in the fourth insulating layer and the seventh conductive layer. The third semiconductor layer is provided so as to be in contact with a top surface of the sixth conductive layer in the third opening, a side surface of the fourth insulating layer in the third opening, a side surface of the seventh conductive layer in the third opening, and a top surface of the seventh conductive layer, and so as to enclose the eighth conductive layer in a plan view with the seventh insulating layer therebetween. The seventh insulating layer is provided in contact with a top surface of the third semiconductor layer, a side surface of the third semiconductor layer, the top surface of the seventh conductive layer, the side surface of the seventh conductive layer, and a top surface of the fourth insulating layer.The eighth conductive layer is provided over and in contact with the seventh insulating layer such that it fills the third opening.

[0026] In the above, at least one of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer preferably comprises a metal oxide.

[0027] In the above, the second conductive layer preferably comprises a ninth conductive layer and a tenth conductive layer. The ninth conductive layer is preferably provided in contact with the upper surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer. The tenth conductive layer is preferably provided in contact with an upper surface of the ninth conductive layer such that it includes a region overlapping with the first conductive layer. The second semiconductor layer is preferably provided in contact with an upper surface of the tenth conductive layer.

[0028] In the above, the second conductive layer preferably comprises a ninth conductive layer, a tenth conductive layer, and an eleventh conductive layer. The ninth conductive layer is preferably provided in contact with the upper surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer. The tenth conductive layer is preferably provided in contact with an upper surface of the ninth conductive layer. The eleventh conductive layer is preferably provided in contact with an upper surface of the tenth conductive layer such that it includes a region overlapping with the first conductive layer. The second semiconductor layer is preferably provided in contact with an upper surface of the eleventh conductive layer.

[0029] In the above, a capacitor is preferably included between the first transistor and the second transistor. The first transistor, the second transistor, the capacitor, and the third transistor are preferably stacked in this order. The capacitor preferably includes the ninth conductive layer, the tenth conductive layer, and an eighth insulating layer. The eighth insulating layer preferably includes a region in contact with a side surface of the ninth conductive layer. The tenth conductive layer preferably covers at least a part of the side surface of the ninth conductive layer with the eighth insulating layer interposed therebetween. The ninth conductive layer is preferably provided in contact with the upper surface of the fifth conductive layer. The sixth conductive layer is preferably provided in contact with an upper surface of the ninth conductive layer.

[0030] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming a first conductive layer; forming a first insulating layer over the first conductive layer; forming a second conductive layer over the first insulating layer; forming a second insulating layer over the first insulating layer and the second conductive layer; processing the second conductive layer and the second insulating layer and forming a first opening reaching the first conductive layer; forming a first insulating film in contact with a top surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the first opening, a side surface of the second insulating layer in the first opening, and a top surface of the second insulating layer;Processing the first insulating film to expose the top surface of the first conductive layer in the first opening and the top surface of the second insulating layer, and forming a third insulating layer in contact with the side surface of the first insulating layer in the first opening, the side surface of the second conductive layer in the first opening, and the side surface of the second insulating layer in the first opening; Forming a first metal oxide film in contact with the top surface of the first conductive layer, a side surface of the third insulating layer, a top surface of the third insulating layer, and the top surface of the second insulating layer; Processing the first metal oxide film and forming a first semiconductor layer including a region overlapping with the first opening; Forming a third conductive layer in contact with a top surface of the first semiconductor layer;Forming a fourth insulating layer over the third conductive layer and the second insulating layer; forming a first conductive film over the fourth insulating layer; processing the first conductive film and the fourth insulating layer and forming a second opening reaching the third conductive layer; forming a second metal oxide film in contact with a top surface of the third conductive layer in the second opening, a side surface of the fourth insulating layer in the second opening, a side surface of the first conductive film in the second opening, and a top surface of the first conductive film; processing the second metal oxide film and forming a second semiconductor layer including a region overlapping with the second opening; processing the first conductive film and forming a fourth conductive layer including a region overlapping with the third conductive layer;Forming a fifth insulating layer over the second semiconductor layer, the fourth conductive layer, and the fourth insulating layer; forming a second conductive film over the fifth insulating layer; processing the second conductive film and forming a fifth conductive layer including a region overlapping with the second semiconductor layer; forming a sixth insulating layer over the fifth conductive layer and the fifth insulating layer; processing a top surface of the sixth insulating layer and a top surface of the fifth conductive layer to make their heights substantially equal with respect to a substrate surface; forming a sixth conductive layer in contact with the top surface of the fifth conductive layer; forming a seventh insulating layer over the fifth conductive layer and the sixth insulating layer; forming a third conductive film over the seventh insulating layer;Processing the third conductive film and the seventh insulating layer and forming a third opening reaching the sixth conductive layer; forming a third metal oxide film in contact with a top surface of the sixth conductive layer in the third opening, a side surface of the seventh insulating layer in the third opening, a side surface of the third conductive film in the third opening, and a top surface of the third conductive film; processing the third metal oxide film and forming a third semiconductor layer including a region overlapping with the third opening; processing the third conductive film and forming a seventh conductive layer including a region overlapping with the sixth conductive layer; forming an eighth insulating layer over the third semiconductor layer, the seventh conductive layer, and the seventh insulating layer;Forming a fourth conductive film over the eighth insulating layer; and processing the fourth conductive film and forming an eighth conductive layer including a region overlapping with the third semiconductor layer. Effect of the invention

[0031] With one embodiment of the present invention, a semiconductor device, a memory device, or a transistor can be provided which can be miniaturized or highly integrated. With one embodiment of the present invention, a highly reliable semiconductor device, a highly reliable memory device, or a highly reliable transistor can be provided. With one embodiment of the present invention, a semiconductor device or a memory device with high read accuracy can be provided. With one embodiment of the present invention, a transistor with high forward current can be provided. With one embodiment of the present invention, a transistor with advantageous electrical properties can be provided.An embodiment of the present invention can provide a low-cost semiconductor device or a memory device. An embodiment of the present invention can provide a low-power semiconductor device or a memory device. An embodiment of the present invention can provide a high-speed semiconductor device or a memory device. An embodiment of the present invention can provide a novel semiconductor device, a novel memory device, or a novel transistor.

[0032] One embodiment of the present invention can provide a method for manufacturing a semiconductor device, a memory device, or a transistor that can be miniaturized or highly integrated. One embodiment of the present invention can provide a method for manufacturing a highly reliable semiconductor device, a highly reliable memory device, or a highly reliable transistor. One embodiment of the present invention can provide a method for manufacturing a semiconductor device or a memory device with high read accuracy. One embodiment of the present invention can provide a method for manufacturing a transistor with a high forward current.One embodiment of the present invention can provide a method for manufacturing a transistor with advantageous electrical properties. One embodiment of the present invention can provide a method for manufacturing a semiconductor device or a memory device with high yield. One embodiment of the present invention can provide a method for manufacturing a semiconductor device or a memory device with low power consumption. One embodiment of the present invention can provide a method for manufacturing a semiconductor device or a memory device with a high operating speed. One embodiment of the present invention can provide a method for manufacturing a novel semiconductor device, a novel memory device, or a novel transistor.

[0033] It should be noted that the description of these effects does not preclude the existence of further effects. An embodiment of the present invention does not necessarily have to exhibit all of these effects. Further effects can be derived from the explanation of the description, the drawings, and the claims. Short description of the drawings Fig. 1A is a block diagram illustrating a structural example of a semiconductor device. Fig. 1B and Fig. 1C are circuit diagrams, each showing an example structure of a memory cell. Fig. 2A and Fig. 2B are circuit diagrams, each showing a structural example of a memory cell. Fig. 3A is a block diagram illustrating a structural example of a semiconductor device. Fig. 3B and Fig. 3C are circuit diagrams, each showing an example structure of a memory cell. Fig. 4A is a plan view illustrating a structural example of a semiconductor device. Fig. 4B and Fig. 4C are cross-sectional views illustrating a structural example of the semiconductor device. Fig. 5A is a plan view illustrating a structural example of a semiconductor device. Fig. 5B and Fig. 5C are cross-sectional views illustrating a structural example of the semiconductor device. Fig. 6A and Fig. 6B are cross-sectional views illustrating a structural example of a transistor. Fig. 7A is a plan view illustrating a structural example of a semiconductor device. Fig. 7B and Fig. 7C are cross-sectional views illustrating a structural example of the semiconductor device. Fig. 8A is a plan view illustrating a structural example of a semiconductor device. Fig. 8B and Fig. 8C are cross-sectional views illustrating a structural example of the semiconductor device. Fig. 9A is a plan view showing a structural example of a semiconductor device. Fig. 9B and Fig. 9C are cross-sectional views illustrating a structural example of the semiconductor device. Fig. 10A is a plan view illustrating a structural example of a semiconductor device. Fig. 10B and Fig. 10C are cross-sectional views illustrating a structural example of the semiconductor device. Fig. 11A is a plan view illustrating a structural example of a semiconductor device. Fig. 11B and Fig. 11C are cross-sectional views illustrating a structural example of the semiconductor device. Fig. 12A is a plan view illustrating a structural example of a semiconductor device. Fig. 12B and Fig. 12C are cross-sectional views illustrating a structural example of the semiconductor device. Fig. 13A to Fig. 13C are plan views each showing a structural example of a semiconductor device. Fig. 14A to Fig. 14C are plan views each showing a structural example of a semiconductor device. Fig. 15A to Fig. 15C are plan views each showing a structural example of a semiconductor device. Fig. 16A and Fig. 16B are cross-sectional views illustrating a structural example of a semiconductor device. Fig. 17A and Fig. 17B are cross-sectional views illustrating a structural example of a semiconductor device. Fig. 18A and Fig. 18B are cross-sectional views illustrating a structural example of a semiconductor device. Fig. 19A and Fig. 19B are cross-sectional views illustrating a structural example of a semiconductor device. Fig. 20A and Fig. 20B are cross-sectional views illustrating a structural example of a semiconductor device. Fig. 21A and Fig. 21B are cross-sectional views illustrating a structural example of a semiconductor device. Fig. 22A and Fig. 22B are cross-sectional views illustrating a structural example of a semiconductor device. Fig. 23A and Fig. 23B are cross-sectional views illustrating a structural example of a semiconductor device. Fig. 24A and Fig. 24B are cross-sectional views illustrating a structural example of a semiconductor device. Fig. 25A is a block diagram showing a structural example of a display device. Fig. 25B is a plan view showing a structure example of a pixel. Fig. Figure 25C is a circuit diagram showing a structure example of a pixel. Fig. 26A and Fig. 26B are plan views each showing a structural example of a semiconductor device. Fig. 27 is a cross-sectional view showing a structural example of a semiconductor device. Fig. 28 is a cross-sectional view showing a structural example of a semiconductor device. Fig. 29A and Fig. 29B are plan views each showing a structural example of a semiconductor device. Fig. 30A and Fig. 30B are plan views each showing a structural example of a semiconductor device. Fig. 31A and Fig. 31B are plan views each showing a structural example of a semiconductor device. Fig. 32A and Fig. 32B are plan views each showing a structural example of a semiconductor device. Fig. 33A and Fig. 33B are plan views each showing a structural example of a semiconductor device. Fig. 34A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 34B and Fig. 34C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 35A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 35B and Fig. 35C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 36A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 36B and Fig. 36C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 37A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 37B and Fig. 37C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 38A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 38B and Fig. 38C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 39A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 39B and Fig. 39C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 40A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 40B and Fig. 40C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 41A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 41B and Fig. 41C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 42A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 42B and Fig. 42C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 43A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 43B and Fig. 43C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 44A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 44B and Fig. 44C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 45A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 45B and Fig. 45C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 46A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 46B and Fig. 46C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 47A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 47B and Fig. 47C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 48A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 48B and Fig. 48C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 49A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 49B and Fig. 49C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 50A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 50B and Fig. 50C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 51A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 51B and Fig. 51C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 52A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 52B and Fig. 52C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 53A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 53B and Fig. 53C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 54A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 54B and Fig. 54C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 55A is a plan view illustrating an example of a method for manufacturing a semiconductor device. Fig. 55B and Fig. 55C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device. Fig. 56 is a perspective view showing a structural example of a semiconductor device. Fig. 57 is a cross-sectional view showing a structural example of a semiconductor device. Fig. 58 is a cross-sectional view showing a structural example of a semiconductor device. Fig. 59A and Fig. 59B are diagrams showing examples of electronic components. Fig. 60A and Fig. 60B are diagrams showing examples of electronic devices. Fig. 60C to Fig. 60E are diagrams that show an example of a large computer. Fig. 61 is a diagram showing an example of furnishing for the room. Fig. Figure 62 is a diagram showing an example of a storage system that can be used for a data center. Embodiments of the invention

[0034] Embodiments will be described in detail with reference to the drawings. It should be noted that the embodiments of the present invention are not limited to the following description, and it will be readily apparent to those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as limited to the description of the following embodiments.

[0035] Note that in the structures of the invention described below, the same sections or sections with similar functions are designated by the same reference numerals in different drawings, and the description thereof will not be repeated. The same hatching pattern is used for sections with similar functions, and in some cases, the sections are not designated by specific reference numerals.

[0036] The position, size, area, or the like of each structure shown in the drawings is not precisely illustrated in some cases for ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, area, or the like shown in the drawings. For example, in the actual manufacturing process, the size of a layer, a photoresist mask, or the like may be inadvertently reduced by a treatment such as etching, which is not illustrated in some cases for ease of understanding.

[0037] It should be noted that ordinal numbers such as "first" and "second" are used in this specification and the like for convenience and do not limit the number or order (e.g., the order of steps or the order of arrangement) of components. The ordinal number assigned to a component in one part of this specification may be different from the ordinal number assigned to the component in another part of this specification or the scope of the claims.

[0038] A transistor is a type of semiconductor device that enables amplification of current or voltage, switching to control conduction or non-conduction, and the like. A transistor in this description includes an insulated-gate field-effect transistor (IGFET) and a thin-film transistor (TFT).

[0039] In this specification and the like, a transistor is an element that has at least three terminals, namely a gate, a drain, and a source. The transistor includes a region where a channel is formed (also referred to as a channel formation region) between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and a current can flow through the channel formation region between the source and the drain. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.

[0040] For example, if a transistor with a different polarity is used or if the current flow direction is changed during circuit operation, the functions of a "source" and a "drain" are interchanged. Therefore, the terms "source" and "drain" may be used interchangeably in this description.

[0041] It should be noted that, for example, impurities in a semiconductor refer to elements that are different from the main components of the semiconductor. For example, an element whose concentration is lower than 0.1 atomic% is an impurity. When a semiconductor contains an impurity, it can cause, for example, an increase in the density of defect states or a decrease in the crystallinity of the semiconductor. In the case where the semiconductor is an oxide semiconductor, examples of an impurity that changes the properties of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals that are different from the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.It should be noted that water also serves as a contaminant in some cases. The ingress of a contaminant can, for example, cause oxygen vacancies (also known as V. O (called) in an oxide semiconductor.

[0042] It should be noted that in this specification and the like, oxynitride refers to a material that contains more oxygen than nitrogen. Nitride oxide refers to a material that contains more nitrogen than oxygen.

[0043] The contents of elements such as hydrogen, oxygen, carbon, and nitrogen in a film can be analyzed using methods such as secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of a target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more). In contrast, SIMS is suitable when the content of a target element is low (e.g., 0.5 atomic% or less or 1 atomic% or less). To compare element contents, analysis using a combination of SIMS and XPS is preferably used.

[0044] In this specification and the like, the terms "film" and "layer" may be interchanged depending on the circumstances. For example, the term "conductive layer" may be converted to the term "conductive film" in some cases. The term "conductive film" may be converted to the term "conductive layer" in some cases. For example, the term "insulating film" may be converted to the term "insulating layer" in some cases. The term "insulating layer" may be converted to the term "insulating film" in some cases. For example, the term "semiconductor film" may be converted to the term "semiconductor layer" in some cases.

[0045] In this specification and the like, the term "parallel" indicates that the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°. Therefore, the case where the angle is greater than or equal to -5° and less than or equal to 5° is also included. The term "substantially parallel" indicates that the angle formed between two straight lines is greater than or equal to -30° and less than or equal to 30°. The term "perpendicular" indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°. Therefore, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included.Furthermore, the term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.

[0046] In this specification and the like, the term "electrically connected" includes the case where components are connected to each other via an object having any electrical function. There is no particular limitation on an "object having any electrical function" as long as electrical signals can be sent and received between components connected via the object. Examples of the "object having any electrical function" include a switching element such as a transistor, a resistor, a coil, a capacitor, and an element with various functions, as well as an electrode and a wire.

[0047] Furthermore, a term "X and Y are connected" in this specification and the like means that the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are disclosed in this specification and the like. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship illustrated in drawings or texts, it is understood that a connection relationship not illustrated in drawings or texts is also disclosed in the drawings or texts. X and Y each represent an object (e.g., a device, an element, a circuit, a wire, an electrode, a terminal, a conductive film, or a layer).

[0048] For example, when X and Y are electrically connected, one or more elements that enable electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display device, a light-emitting device, and a load) may be connected between X and Y. Note that a switch has a function of being controlled to turn on or off. That is, the switch has a function of controlling whether or not a current flows by placing it in a conducting state (on state) or a non-conducting state (off state).

[0049] Note that in the case where both an element and a power supply line (e.g., a line from which a high power supply potential (VDD), a low power supply potential (VSS), a ground potential (GND), or a desired potential is supplied) are provided between X and Y, it is not defined that X and Y are electrically connected to each other. Note that in the case where only a power supply line is provided between X and Y, there is no other element between X and Y, and therefore, it is considered that X and Y are directly connected to each other. Therefore, in the case where only a power supply line is provided between X and Y, it can also be said that "X and Y are electrically connected to each other."In the case where both an element and a power supply line are provided between X and Y, it is assumed that X and a power supply line are electrically connected (via the element), and that Y and a power supply line are electrically connected; however, it is not defined that X and Y are electrically connected. Note that in the case where a gate and a source of a transistor are provided between X and Y, it is not defined that X and Y are electrically connected. Note that in the case where a gate and a drain of a transistor are provided between X and Y, it is not defined that X and Y are electrically connected. That is, in the case of a transistor, when a drain and a source of a transistor are provided between X and Y, it is defined that X and Y are electrically connected.Note that in the case where a capacitor is arranged between X and Y, it is defined in some cases and not defined in other cases that X and Y are electrically connected to each other. For example, in the case where a capacitor is arranged between X and Y in a configuration of a digital circuit or a logic circuit, it is not defined in some cases that X and Y are electrically connected to each other. On the other hand, for example, in the case where a capacitor is arranged between X and Y in a configuration of an analog circuit, it is defined in some cases that X and Y are electrically connected to each other.

[0050] For example, if X and Y are functionally connected, one or more circuits that enable a functional connection between X and Y (e.g., a logic circuit (e.g., an inverter, a NAND circuit, and a NOR circuit); a signal conversion circuit (e.g., a digital-to-analog conversion circuit, an analog-to-digital conversion circuit, and a gamma correction circuit); a potential level conversion circuit (e.g., a power supply circuit, such asa step-up circuit or a step-down circuit, and a level shift circuit for changing the potential level of a signal); a voltage source; a current source; a switching circuit; an amplifier circuit (for example, a circuit that can increase the signal amplitude, the amount of current, or the like, an operational amplifier, a differential amplifier circuit, a source follower circuit, and a buffer circuit); a signal generation circuit; a memory circuit; and a control circuit) may be connected between X and Y. It should be noted that even if, for example, another circuit is provided between X and Y, X and Y are functionally connected when a signal output from X is transmitted to Y.

[0051] For example, the expression "X, Y, a source (in some cases referred to as one of a first terminal and a second terminal) of a transistor, and a drain (in some cases referred to as the other of the first terminal and the second terminal) of the transistor are electrically connected to each other, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected to each other in this order" may be used. Alternatively, the expression "a source of a transistor is electrically connected to X, a drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected to each other in this order" may be used.Alternatively, the expression "X is electrically connected to Y via a source and a drain of a transistor, and X, the source of the transistor, the drain of the transistor, and Y are arranged in this connection order" may be used. When the order of connection in a circuit configuration is defined by an expression similar to these examples, a source and a drain of a transistor can be distinguished from each other to determine the technical scope. Note that these expressions are examples and are not limited to these expressions. Here, X and Y each represent an object (e.g., a device, an element, a circuit, a line, an electrode, a terminal, a conductive film, or a layer).

[0052] It should be noted that even when independent components are electrically connected in a circuit diagram, in some cases a component performs functions of multiple components. For example, when a portion of a lead also serves as an electrode, a conductive film performs both a lead function and an electrode function. Therefore, the category "electrical connection" in this specification includes a case where a conductive film performs functions of multiple components.

[0053] In this specification and the like, a "resistive element" may refer to, for example, a circuit element with a resistance value greater than 0 Ω or a wire with a resistance value greater than 0 Ω. Therefore, in this specification and the like, a "resistive element" includes a wire with a resistance value, a transistor in which a current flows between a source and a drain, a diode, and an inductor. The term "resistive element" may therefore be replaced with the term "resistor," "load," or "region with a resistance value" in some cases. Conversely, the term "resistor," "load," or "region with the resistance value" may be replaced with the term "resistive element" in some cases.The resistance value may preferably be, for example, greater than or equal to 1 mΩ and less than or equal to 10 Ω, more preferably greater than or equal to 5 mΩ and less than or equal to 5 Ω, even more preferably greater than or equal to 10 mΩ and less than or equal to 1 Ω. The resistance value may also be, for example, greater than or equal to 1 Ω and less than or equal to 1 × 10. 9 Ω.

[0054] In this specification and the like, a "capacitor element" may refer to, for example, a circuit element with an electrostatic capacitance greater than 0 F, a portion of a wiring with an electrostatic capacitance greater than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The term "capacitor element," "parasitic capacitance," or "gate capacitance" may be replaced with the term "capacitance" in some cases. Conversely, the term "capacitance" may be replaced with the term "capacitor element," "parasitic capacitance," or "gate capacitance" in some cases. In addition, the "capacitor" (including a "capacitor" with three or more terminals) includes an insulator and a pair of conductors between which the insulator is sandwiched.The term "a pair of conductors" of a "capacitor" can therefore be replaced with the term "a pair of electrodes," "a pair of conductive regions," "a pair of regions," or "a pair of terminals." The terms "one of a pair of terminals" and "the other of the pair of terminals" are sometimes referred to as "first terminal" and "second terminal," respectively. Note that the electrostatic capacitance can be, for example, higher than or equal to 0.05 fF and lower than or equal to 10 pF. For example, the electrostatic capacitance can be higher than or equal to 1 pF and lower than or equal to 10 µF.

[0055] In this specification and the like, a transistor includes three terminals, which are referred to as gate, source, and drain. The gate is a control terminal for controlling the conduction state of the transistor. Two terminals, which serve as the source and drain, are input / output terminals of the transistor. Depending on the conductivity type (n-channel type or p-channel type) of the transistor and the levels of the potentials applied to the three terminals of the transistor, one of the two input / output terminals serves as the source and the other serves as the drain. In this specification and the like, therefore, the terms "source" and "drain" may be substituted for each other in some cases. When describing a connection relationship of a transistor in this specification and the like, the terms "one terminal of the source and drain" (or "first electrode" and "second electrode") are used."first terminal") and "the other of the source and drain" (or "second electrode" and "second terminal", respectively). It should be noted that, depending on its structure, the transistor may have a backgate in addition to the above three terminals. In this case, in this specification and the like, one of the gate and backgate of the transistor is referred to as the first gate in some cases, and the other of the gate and backgate of the transistor is referred to as the second gate in some cases. Furthermore, the terms "gate" and "backgate" may be interchanged in the same transistor in some cases. When the transistor has three or more gates, these gates are referred to as the first gate, second gate, and third gate, for example, in this specification and the like in some cases.

[0056] In this specification and the like, for example, a transistor having a multi-gate structure in which two or more gates are provided can be used as a transistor. When the multi-gate structure is employed, channel formation regions are connected in series; accordingly, a plurality of transistors are connected in series. Therefore, the multi-gate structure makes it possible to reduce the amount of off-state current and increase the withstand voltage (reliability) of the transistor. Alternatively, when the multi-gate structure is employed, during operation in the saturated region, the current between the drain and the source hardly changes even when the voltage between the drain and the source changes, so that voltage-current characteristics with a flat slope can be obtained.By utilizing the voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance can be obtained. As a result, a differential circuit, a current mirror circuit, and the like with excellent characteristics can be obtained.

[0057] Even if a single circuit element is represented in a circuit diagram, the circuit element may include a plurality of circuit elements. For example, the case where a single resistor is represented in a circuit diagram includes the case where two or more resistors are electrically connected in series. For example, the case where a single capacitor is represented in a circuit diagram includes the case where two or more capacitors are electrically connected in parallel. For example, the case where a single transistor is represented in a circuit diagram includes the case where two or more transistors are electrically connected in series and their gates are electrically connected to each other.Similarly, for example, the case where a single switch is represented in a circuit diagram includes the case where the switch comprises two or more transistors electrically connected in series or parallel and their gates are electrically connected together.

[0058] In this specification and the like, a node may also be referred to as a terminal, line, electrode, conductive layer, conductor, or impurity region, depending on the circuit configuration and device structure. Furthermore, a terminal, line, or the like may also be referred to as a node.

[0059] In this specification and the like, "voltage" and "potential" may be interchanged. A "voltage" refers to a potential difference from a reference potential; for example, if the reference potential is a ground potential, "voltage" may be replaced with "potential." Note that the ground potential does not necessarily mean 0 V. In addition, a potential has a relative value, and a potential supplied to a wire, a potential applied to a circuit or the like, a potential output from a circuit or the like, and the like are changed when a reference potential is changed.

[0060] In this specification and the like, the terms "high potential" and "low potential" do not refer to specific potentials. For example, in the case where it is expressed that both of the two lines "serve as a line for supplying a high potential," the high potentials supplied by the lines do not necessarily have to be the same. Similarly, in the case where it is expressed that both of the two lines "serve as a line for supplying a low potential," the low potentials supplied by the lines do not necessarily have to be the same.

[0061] A "current" refers to a phenomenon of the movement of charges (electrical conduction); for example, the phrase "electrical conduction of a positively charged object occurs" can be rewritten as "electrical conduction of a negatively charged object occurs in the opposite direction." Therefore, in this specification and the like, unless otherwise specified, "current" refers to a phenomenon of the movement of electric charges (electrical conduction) due to the movement of charge carriers. Examples of charge carriers mentioned here include electrons, holes, anions, cations, and complex ions, with the charge carriers depending on the system in which the current flows (e.g., a semiconductor, a metal, an electrolyte solution, and a vacuum).The "current direction" in a wire or the like is the direction in which charge carriers that become positive electric charges move, and is represented by a positive amount of current. In other words, charge carriers that become negative electric charges move in a direction opposite to the current direction, and this direction is represented by a negative amount of current. Therefore, in this specification and the like, unless it is determined that the current is positive or negative (or unless the current direction is determined), the expression "a current flows from an element A to an element B" can be reformulated to "a current flows from an element B to an element A." The expression "a current is input to an element A" can be reformulated to "a current is output from an element A."

[0062] Unless otherwise stated, a reverse current in this specification and the like refers to a leakage current of a transistor between a source and a drain in a reverse state (also referred to as a non-conductive state or cut-off state). Unless otherwise stated, the reverse state refers to a state in which, for an n-channel transistor, a voltage V gs between a gate and a source is lower than a threshold voltage V th (for a p-channel transistor V gs is higher than V th ).

[0063] Note that in this specification and the like, a top surface shape of a component refers to the contour of the component in a plan view. A plan view means that the component is observed from a normal direction of a surface on which the component is formed or from a normal direction of a surface of a support (e.g., a substrate) on which the component is formed.

[0064] Note that in this specification and the like, a tapered shape refers to a shape in which at least a portion of a side surface of a structure is inclined with respect to a substrate surface or a formation surface. For example, a tapered shape refers to a shape having a region where the angle formed between the inclined side surface and the substrate surface or the formation surface (also referred to as a taper angle) is less than 90°. Note that the side surface of the structure, the substrate surface, and the formation surface are not necessarily completely flat and may have a substantially flat shape with a very small radius of curvature or a small unevenness.

[0065] In this specification and the like, when the expression "A is in contact with B" is used, at least a part of A is in contact with B. In other words, A includes, for example, an area in contact with B.

[0066] In this specification and the like, when the expression "A is positioned above B" is used, at least a part of A is positioned above B. In other words, A includes, for example, a region positioned above B.

[0067] In this specification and the like, when the expression “A covers B” is used, a part of A covers B. In other words, A includes, for example, an area that covers B.

[0068] In this specification and the like, when the expression “A overlaps with B” is used, a part of A overlaps with B. In other words, A includes, for example, an area that overlaps with B.

[0069] In this description and the like, terms for explaining the arrangement, such as "above," "below," "right," and "left," are used for convenience to describe the positional relationship between components based on drawings. The positional relationship between components is appropriately changed according to the direction in which each component is described. Therefore, the positional relationship is not limited to that described by a term used in this description and may be appropriately described using other terms depending on the circumstances.

[0070] In this specification and the like, a metal oxide broadly means an oxide of a metal. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as OS), and the like. For example, a metal oxide used in a semiconductor layer of a transistor is sometimes referred to as an oxide semiconductor. That is, an OS transistor may also be referred to as a transistor comprising a metal oxide or an oxide semiconductor. Note that a metal oxide containing nitrogen is sometimes referred to as a metal oxide. In addition, a nitrogen-containing metal oxide may also be referred to as a metal oxynitride. (Embodiment 1)

[0071] In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to drawings. In this embodiment, the semiconductor device of one embodiment of the present invention will be described using a memory device as a primary example.

[0072] One embodiment of the present invention relates to a memory device comprising a memory section in which memory cells are arranged in a matrix. A first transistor, a second transistor, and a third transistor are provided in each memory cell. In the memory device, the first transistor has a function of writing data to a memory cell. The second transistor and the third transistor each have a function of reading data held in a memory cell.

[0073] In the memory device of one embodiment of the present invention, two transistors, namely the second transistor and the third transistor connected in series with the second transistor, are used to read data held in a memory cell. When the memory device of one embodiment of the present invention includes a third transistor, data held in a memory cell can be read more stably than in the case where the memory device does not include the transistor. Therefore, a memory device with high read accuracy can be achieved.

[0074] Furthermore, the memory device of one embodiment of the present invention has a structure in which the first transistor, the second transistor, and the third transistor are stacked. Therefore, the area occupied by the memory cell in a plan view can be reduced. Therefore, the memory cells can be miniaturized and highly integrated, and a memory device capable of miniaturization and higher resolution can be provided.

[0075] Furthermore, in the memory device of one embodiment of the present invention, the first transistor, the second transistor, and the third transistor each have a structure in which the source electrode and the drain electrode are provided at different heights with respect to the substrate surface so as to overlap with each other, and a drain current flows in a height direction (longitudinal direction). Therefore, these transistors can be further miniaturized than transistors having a structure in which a source electrode and a drain electrode are provided on the same plane. When the memory device of one embodiment of the present invention includes the transistors having the above-described structure, the memory device can be further miniaturized and have higher resolution. <Strukturbeispiel 1 der Halbleitervorrichtung>

[0076] Fig. 1A is a block diagram illustrating a structural example of a semiconductor device 10. The semiconductor device 10 can be used as a memory device.

[0077] The semiconductor device 10 includes a memory section 20, a word line driver circuit 11, a bit line driver circuit 13, and a power supply circuit 15. The memory section 20 includes a plurality of memory cells 21 arranged in a matrix. Note that the power supply circuit 15 may be provided outside the semiconductor device 10.

[0078] The word line driver circuit 11 is electrically connected to the memory cells 21 via lines 31. The lines 31 extend, for example, in the row direction of the matrix. The lines 31 serve as word lines. Fig. 1A represents lines 31 as a line 31R and a line 31W.

[0079] The bit line driver circuit 13 is electrically connected to the memory cells 21 via lines 33. The lines 33 extend, for example, in the column direction of the matrix. The lines 33 serve as bit lines. Fig. 1A represents lines 33 as a line 33R and a line 33W.

[0080] In Fig. 1A, as shown in the drawing, the direction in which the wirings 31 serving as word lines extend is the X direction, and the direction in which the wirings 33 serving as bit lines extend is the Y direction. As described above, the wirings 31 extend in the row direction of the matrix, and the wirings 33 extend in the column direction of the matrix. Therefore, the X direction may be the row direction, and the Y direction may be the column direction. The X direction and the Y direction may intersect each other, and in particular, may be perpendicular to each other. Furthermore, the direction that intersects both the X direction and the Y direction, in particular, the direction perpendicular to both the X direction and the Y direction, may be the Z direction.It should be noted that in the following drawings, directions are shown from the X direction, the Y direction and the Z direction, and that the definitions of the directions are the same as those in . Fig. 1A be the same or different from that in Fig. 1A can be distinguished. In Fig. In Figure 1A, the X-direction, Y-direction, and Z-direction are indicated by arrows; the forward direction and reverse direction are not distinguished from each other unless otherwise specified. The same applies to the following drawings.

[0081] The power supply circuit 15 is electrically connected to the memory cells 21 via a line 35. Fig. Figure 1A shows an example in which line 35 extends in the column direction of the matrix. Line 35 serves as a power supply line.

[0082] In Fig. 1A, lines 31, lines 33, and lines 35 are represented by straight lines; however, a straight line does not necessarily represent one line and may represent a plurality of lines in some cases. In the following block diagrams, circuit diagrams, and the like, a plurality of lines may be represented by a straight line. With respect to lines other than lines 31, lines 33, and lines 35, a plurality of lines may be represented by a straight line.

[0083] The word line driver circuit 11 has a function of selecting the memory cells 21 to which data is to be written, row by row. The word line driver circuit 11 has a function of selecting the memory cells 21 from which data is to be read, specifically, the memory cells 21 from which data is to be output to the lines 33, row by row. The word line driver circuit 11 can select the memory cells 21 to which data is to be written or the memory cells 21 from which data is to be read by supplying signals to the lines 31. Specifically, the word line driver circuit 11 has a function of selecting the memory cells 21 to which data is to be written by supplying a signal to the line 31W.The word line driver circuit 11 has a function of selecting the memory cells 21 from which data is read, specifically, the memory cells 21 from which data is output to the line 33R, by supplying a signal to the line 31R. Here, the line 31W is also referred to as a write word line, and the line 31R is also referred to as a read word line. Furthermore, the signal supplied from the word line driver circuit 11 to the line 31W is also referred to as a write signal, and the signal supplied to the line 31R is also referred to as a read signal.

[0084] In the manner described above, the word line driver circuit 11 has a function of controlling the writing of data into the memory cells 21 by supplying the write signal to the line 31W. The word line driver circuit 11 has a function of controlling the reading of data from the memory cells 21 by supplying the read signal to the line 31R.

[0085] The bit line driver circuit 13 has a function of writing data to the memory cell 21 selected by the word line driver circuit 11 via the line 33. The bit line driver circuit 13 has a function of reading data held in the memory cell 21 by amplifying data output from the memory cell 21 to the line 33 and outputting the amplified data to, for example, the outside of the semiconductor device 10. Furthermore, the bit line driver circuit 13 has a function of precharging the line 33 before reading data from the memory cell 21.

[0086] Specifically, the bit line driver circuit 13 has a function of writing data into the memory cell 21 selected by the word line driver circuit 11 via the write signal. The bit line driver circuit 13 has a function of reading data held in the memory cell 21 by amplifying data output from the memory cell 21 to the write signal and outputting the amplified data to, for example, the outside of the semiconductor device 10. Furthermore, the bit line driver circuit 13 has a function of precharging the write signal before reading data from the memory cell 21. Here, the write signal line 33W is also referred to as a write bit line, and the read signal line 33R is also referred to as a read bit line.

[0087] In the manner described above, the bit line driver circuit 13 has a function of writing data to the memory cell 21 via the line 33W. Furthermore, the bit line driver circuit 13 has a function of reading the data via the line 33R.

[0088] The power supply circuit 15 has a function of supplying a power supply potential to the line 35, specifically, a function of supplying a constant potential to the line 35. The power supply circuit 15 has a function of, for example, generating a high potential or a low potential and supplying it to the line 35. Note that the power supply circuit 15 may have a function of supplying a power supply potential to the word line driver circuit 11 and / or the bit line driver circuit 13.

[0089] Fig. 1B is a circuit diagram illustrating a structural example of memory cell 21 according to one embodiment of the present invention. Memory cell 21 having this structure includes a transistor 41 and a transistor 42.

[0090] One terminal of the source and drain of transistor 41 is electrically connected to the wiring 33R. The other terminal of the source and drain of transistor 41 is electrically connected to the wiring 35. A gate of transistor 41 is electrically connected to one terminal of the source and drain of transistor 42. The other terminal of the source and drain of transistor 42 is electrically connected to the wiring 33W. A gate of transistor 42 is electrically connected to the wiring 31W. Here, a node N denotes a node at which the gate of transistor 41 and one terminal of the source and drain of transistor 42 are electrically connected to each other.

[0091] The transistor 42 has a function for writing data into the memory cell 21. The transistor 41 has a function for reading data held in the memory cell 21. It should be noted that the Fig. 1B does not include a capacitor for holding data. In the memory cell 21, data is written to the node N. For example, due to the low leakage current characteristic of the OS transistor, using an OS transistor as the transistor 42 allows data to be held at the node N for a longer time than in the case where a transistor containing silicon in a semiconductor layer (also referred to as an Si transistor) is used. Therefore, even without a capacitor (C), a memory cell can consist of only two transistors (Tr), so that the manufacturing process of the memory cell can be simplified. Note that the memory cell having the above structure can be called a 2Tr0C memory cell.

[0092] It should be noted that, as a memory cell with a simple structure, a DRAM (Dynamic Random Access Memory) is widely known, which is a 1Tr1C memory cell consisting of a transistor and a capacitor. However, due to the structure of DRAM, both data writing and data reading must be performed using the same transistor, and there is a problem that when latched data is read (when the transistor is turned on to read data), the data is lost by the transistor (a so-called destructive read).

[0093] In contrast, the Fig. The memory cell 21 shown in FIG. 1B has a structure in which a data write transistor (transistor 42) and a data read transistor (transistor 41) are provided separately. Therefore, during data read, the data write transistor (transistor 42) is not necessarily turned on, and non-destructive reading can be achieved.

[0094] Specifically, potentials of different levels are applied to wiring 33R and wiring 35, thereby creating a potential difference between the source and drain of transistor 41. At this time, the gate of transistor 41 is in a state where a potential of a level corresponding to the data written to node N is applied to the gate. Thus, according to the magnitude relationship between the threshold voltage of transistor 41 and the data written to node N (i.e., the potential applied to the gate of transistor 41), whether transistor 41 is turned on or off is determined.In the case where the memory cell 21 is a bivalent memory cell in which data having a value of either "0" or "1" is held, a current flows between the source and drain of the transistor 41 when the transistor 41 is turned on; therefore, the current is output to the wiring 33R, and it can be detected that data of "1" is written to the node N. On the other hand, no current flows between the source and drain of the transistor 41 when the transistor 41 is turned off; therefore, no current is output to the wiring 33R, and it can be detected that data of "0" is written to the node N.

[0095] However, in the case of the data reading method described above, a potential must be applied to each of the wiring 33R and the wiring 35 when reading data; therefore, each time data is read, the applied potential is applied to the node N via a parasitic capacitance (e.g., a capacitance component included in the transistor 41). Therefore, there is a problem that the size of data originally written in all of the memory cells 21 (including the memory cells 21 from which data is not to be read) connected to the wiring 33R and the wiring 35 to which the potential is applied changes.

[0096] Therefore, in the memory cell of an embodiment of the present invention, as shown in Fig. 1C, a transistor 43 is provided which is connected in series with the transistor 41. In particular, one terminal of the source and drain of the transistor 41 is electrically connected to one terminal of the source and drain of the transistor 43. The other terminal of the source and drain of the transistor 43 is electrically connected to the line 33R. A gate of the transistor 43 is electrically connected to the line 31R. For the other components, reference can be made to the description of the memory cell 21 in Fig. 1B.

[0097] In the Fig. In the memory cell 21 of one embodiment of the present invention shown in Figure 1C, transistor 42 has a function for writing data. Transistor 41 and transistor 43 each have a function for reading data held in memory cell 21.

[0098] The following describes an operating procedure of the Fig. 1C, although some portions are the same as those shown in the Fig. 1B shown memory cell 21.

[0099] Transistor 42 serves as a switch for writing data to memory cell 21. For example, if transistor 42 is an n-channel transistor, transistor 42 can be turned on by setting the potential of wiring 31W to a high potential (a potential at which the potential between the source and gate of transistor 42 is higher than or equal to the threshold voltage), and transistor 42 can be turned off by setting the potential of wiring 31W to a low potential (a potential at which the potential between the source and gate of transistor 42 is lower than the threshold voltage). Transistor 42 has a function of controlling the conduction / non-conduction state between wiring 31W and node N based on the potential of wiring 31W.When transistor 42 is turned on, data is written into memory cell 21 via wiring 33W, and when transistor 42 is turned off, the written data is held. Specifically, when transistor 42 is turned on, a charge corresponding to data is accumulated at node N, and when transistor 42 is turned off, the charge is held at node N. Note that in the above series of operations (when data is written and held in memory cell 21), a constant potential (a ground potential (GND) or a low potential) is always applied to wiring 35.

[0100] The description below assumes that each of transistor 41, transistor 42, and transistor 43 is an n-channel transistor; however, by appropriately inverting the level of the potential, for example, the following description may also apply to the case where any one, any two, or all of transistor 41, transistor 42, and transistor 43 are a p-channel transistor.

[0101] Transistor 41 and transistor 43 have a function of controlling the reading of data held in memory cell 21. A method for reading data held in memory cell 21 will be described below. In memory cell 21, binary data representing "0" or "1" is held as the potential of node N; "1" is represented by a potential higher than that of "0."

[0102] To read data held in memory cell 21, first, line 33R is precharged to a high potential. Furthermore, the potential of line 35 is set to a constant potential (GND or a low potential), as in the above-described data writing and data holding. Furthermore, the potential of line 31R is set to a high potential (i.e., transistor 43 is turned on), so that electrical connection is established between line 33R and one of the source and drain terminals of transistor 41.

[0103] At this time, a high potential is applied to one of the source and drain of transistor 41, and GND or a low potential is applied to the other of the source and drain of transistor 41. Furthermore, a potential of a level corresponding to the data held in memory cell 21 (i.e., the data written to node N) is applied to the gate of transistor 41. That is, whether transistor 41 is turned on or off is determined depending on the type of data.

[0104] Here, in the case where data held in the memory cell 21 is "0", a difference between the gate potential and the source potential of the transistor 41 is lower than the threshold voltage of the transistor 41. In the case where data held in the memory cell 21 is "1", the difference between the gate potential and the source potential of the transistor 41 is higher than the threshold voltage of the transistor 41. In this case, when data held in the memory cell 21 is "0", the transistor 41 is turned off and the transistor 43 is turned on, so that no current flows from the wiring 33R to the wiring 35. On the other hand, when data held in the memory cell 21 is "1", both the transistor 43 and the transistor 41 are turned on, so that a current flows from the wiring 33R to the wiring 35.Therefore, the bit line driver circuit 13 can read data held in the memory cell 21 from the current flowing through the wiring 33R or the potential of the wiring 33R. Note that, regardless of whether data held in the memory cell 21 is "0" or "1," the difference between the gate potential and the source potential of the transistor 41 may be higher than the threshold voltage of the transistor 41. In this case, too, the bit line driver circuit 13 can read data held in the memory cell 21, for example, by reading the amount of current flowing through the wiring 33R.

[0105] As described above, the Fig. 1C, in each of the data writing, holding, and reading operations, the potential of the line 35 is always fixed at a constant level (GND or a low potential). When reading data (when a high potential is applied to the line 33R), only the transistor 43 in the memory cell 21 from which data is to be read can be turned on via the line 31R. In contrast, in the memory cells 21 from which data is not to be read, the transistors 43 are turned off; therefore, it is possible to prevent a potential from the line 33R from being applied to the node N and to prevent the size of data held in the memory cell 21 from being changed. Therefore, data stored in the Fig. 1C shown memory cell 21 of an embodiment of the present invention can be read more stably than data stored in the memory cell 21 shown in Fig. 1B, and a memory device with high reading accuracy can be obtained.

[0106] Fig. 2A shows a modification example of the Fig. 1C, in which the line 31R is electrically connected to the other terminal of the source and drain of the transistor 41 and the line 35 is electrically connected to the gate of the transistor 43. Writing data and holding data at the Fig. 2A can be carried out by a method similar to that for the memory cell 21 shown in Fig. 1C. Reading data can be performed by following the description of line 35 in the Fig. 1C shown memory cell 21 to the line 31R in the Fig. 2A, the description of the line 31R in the embodiment shown in Fig. 1C shown memory cell 21 to the line 35 in the Fig. 2A and the functions of the power supply circuit 15 in the Fig. 1A and the functions of the word line driver circuit 11 are interchanged.

[0107] The Fig. 1C and Fig. The memory cells 21 shown in Figure 2A are each a 3Tr0C memory cell that does not include a capacitor and consists of three transistors. Therefore, for example, OS transistors are preferably used as transistor 41, transistor 42, and transistor 43. In particular, an OS transistor is preferably used as transistor 42, in which the magnitude of the off-state current affects the data retention period of the memory cell 21. Examples of a metal oxide included in the channel formation regions of the OS transistors include indium oxide, gallium oxide, and zinc oxide.

[0108] Transistors other than the OS transistors can be used as transistor 41 and transistor 43. For example, Si transistors containing silicon in their channel formation regions can be used as transistor 41 and transistor 43. For example, single-crystal silicon, amorphous silicon (in some cases referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon (including low-temperature polycrystalline silicon) can be used as the silicon. An Si transistor has a higher forward current and higher field-effect mobility than an OS transistor. Therefore, when Si transistors are used as transistor 41 and transistor 43, the memory cell 21 with high data read speed can be achieved.

[0109] Transistors with the same structure or different structures can be used for transistor 41 and transistor 43. For example, transistor 41 and transistor 43 may each be an OS transistor, or transistor 41 may be an Si transistor and transistor 43 may be an OS transistor. Alternatively, transistor 41 may be an OS transistor and transistor 43 may be an Si transistor.

[0110] Fig. 2B shows a modification example of the Fig. 1C and differs from the memory cell 21 shown in Fig. 1C in that the capacitor 51 is included.

[0111] In the Fig. In the memory cell 21 shown in Figure 2B, one electrode of the capacitor 51 is electrically connected to the other terminal of the source and drain of the transistor 42 and the gate of the transistor 41. The other electrode of the capacitor 51 is electrically connected to the line 35. Here, a node N denotes a node at which the gate of the transistor 41, the other terminal of the source and drain of the transistor 42, and one electrode of the capacitor 51 are electrically connected to each other. For the other components in the Fig. 2B can refer to the description of the memory cell 21 shown in Fig. 1C shown memory cell 21.

[0112] At the Fig. 2B, each of the operations for writing, holding, and reading data can be performed by a method similar to that for the memory cell 21 shown in Fig. 1C is similar to the memory cell 21 shown in Fig. 2B includes the capacitor 51, it can hold the data written to the node N more stable than the memory cell 21 shown in Fig. 1C shown memory cell 21. Therefore, data can be kept more stable for a long time than in the Fig. 1C, which does not include the capacitor 51.

[0113] Fig. 3A is a block diagram illustrating a structural example of the semiconductor device 10, which differs from the semiconductor device in Fig. 1A. The Fig. The semiconductor device 10 shown in Figure 3A differs from that shown in Fig. 1A in that it comprises a line 36.

[0114] The memory cells 21 arranged in the same row are electrically connected to the word line driver circuit 11 via the common line 36. The line 36 serves as a capacitor line.

[0115] For the other components in the Fig. 3A, reference may be made to the description of the semiconductor device 10 shown in Fig. 1A.

[0116] Fig. 3B is a circuit diagram showing a structural example of the memory cell 21 used in the Fig. 3A. The memory cell 21 with such a structure differs from that shown in Fig. 1B in that it comprises the capacitor 51 in addition to the line 36 described above.

[0117] In the Fig. In the memory cell 21 shown in Figure 3B, one electrode of the capacitor 51 is electrically connected to the other terminal of the source and drain of the transistor 42 and the gate of the transistor 41. The other electrode of the capacitor 51 is electrically connected to the line 36. Here, a node N denotes a node at which the gate of the transistor 41, the other terminal of the source and drain of the transistor 42, and one electrode of the capacitor 51 are electrically connected to each other. For the other components in the Fig. 3B can refer to the description of the memory cell 21 shown in Fig. 1C shown memory cell 21.

[0118] At the Fig. 3B, each of the writing, holding and reading of data can be performed by a method similar to that for the memory cell 21 shown in Fig. 1C. Note that in the above series of operations, a constant potential, ie, a ground potential (GND) or a low potential, is always applied to line 36, as to line 35.

[0119] Fig. 3C shows a modification example of the Fig. 3B and differs from the memory cell 21 shown in Fig. 3B in that the transistor 44 is included.

[0120] In the Fig. 3C, one terminal of the source and drain of the transistor 44 is electrically connected to the line 35. The other terminal of the source and drain of the transistor 44 is electrically connected to the other electrode of the capacitor 51. A gate of the transistor 44 is electrically connected to the gate of the transistor 41 and one electrode of the capacitor 51. For the other components in the Fig. 3C can refer to the description of the memory cell 21 shown in Fig. 3B shown memory cell 21.

[0121] At the Fig. 3C, each of the writing, holding and reading of data can be performed by a method similar to that for the memory cell 21 shown in Fig. 3B. It should be noted that in the above series of operations, a constant potential identical to that applied to line 35, ie, a ground potential (GND) or a low potential, is always applied to line 36.

[0122] The Fig. 2B and Fig. The memory cells 21 shown in Figure 3B are each a 3Tr1C memory cell consisting of three transistors and one capacitor. Fig. Memory cell 21 shown in Figure 3C is a 4Tr1C memory cell consisting of four transistors and one capacitor. OS transistors or Si transistors can be used as transistors included in these memory cells.

[0123] Regarding the Fig. 2B, Fig. 3B and Fig. 3C, a memory cell having a structure in which OS transistors are used as transistors is also referred to as (NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor Random Access Memory).

[0124] As described above, the off-state current of an OS transistor is considerably small. Therefore, by using an OS transistor as transistor 42, which is used in each of the Fig. 1C, Fig. 2A, Fig. 2B, Fig. 3B and Fig. 3C, the charge accumulated at node N is retained for a long period. Data written to memory cell 21 can be retained for a long period, and accordingly, the frequency of the update operation (rewriting data to memory cell 21) can be reduced. Therefore, the power consumption of semiconductor device 10 can be reduced.

[0125] Fig. 4A is a plan view illustrating a structural example of a part of the semiconductor device 10, which is the semiconductor device of one embodiment of the present invention. Fig. 4A includes the structural example of the Fig. 1C. To clarify the drawing, some components, such as an insulating layer, are shown in Fig. 4A omitted. Some components are also omitted in the following plan views. Fig. 4B is a cross-sectional view along the dashed line A1-A2 in Fig. 4A. Fig. Figure 4C is a cross-sectional view along the dotted line A3-A4 in Fig. 4A.

[0126] The semiconductor device of one embodiment of the present invention includes an insulating layer 101 over a substrate (not shown) and the memory cell 21 over the insulating layer 101. The memory cell 21 includes the transistor 43, the transistor 41 over the transistor 43, and the transistor 42 over the transistor 41.

[0127] The semiconductor device of one embodiment of the present invention includes an insulating layer 103c_1 over the insulating layer 101, an insulating layer 103c_2 over the insulating layer 103c_1, an insulating layer 107c over the transistor 43, the insulating layer 103c_1 and the insulating layer 103c_2, an insulating layer 103c_3 over the insulating layer 107c, the transistor 41 and an insulating layer 103a over the insulating layer 103c_3, an insulating layer 107a over the transistor 41 and the insulating layer 103a, an insulating layer 131 over the insulating layer 107a, the transistor 42 and an insulating layer 103b over the transistor 41 and the insulating layer 131 and an insulating layer 107b over the transistor 42 and the insulating layer 103b. Here, the insulating layer 101, the insulating layer 103c_1, the insulating layer 103c_2, the insulating layer 103a, the insulating layer 131 and the insulating layer 103b each serve as an insulating intermediate layer and are preferably planarized.It should be noted that the insulating layers serving as the insulating interlayers do not necessarily have to be planarized.

[0128] The transistor 43 includes a conductive layer 111c, a conductive layer 111a, a semiconductor layer 113c, an insulating layer 105c, and a conductive layer 115c.

[0129] The conductive layer 111c serves as one of a source electrode and a drain electrode of the transistor 43 and serves as a wiring 33R. The conductive layer 111a serves as the other of the source electrode and the drain electrode of the transistor 43. The insulating layer 105c serves as the gate insulating layer of the transistor 43. The conductive layer 115c serves as the gate electrode of the transistor 43 and serves as a wiring 31R. The conductive layer 111c serving as a wiring 33R includes a region extending in the Y direction. The conductive layer 115c serving as a wiring 31R includes a region extending in the X direction.

[0130] The conductive layer 111c is provided over the insulating layer 101, the insulating layer 103c_1 is provided over the insulating layer 101 and the conductive layer 111c, the conductive layer 115c is provided over the insulating layer 103c_1, and the insulating layer 103c_2 is provided over the insulating layer 103c_1 and the conductive layer 115c. The insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2 have an opening 121c that reaches the conductive layer 111c. Fig. 4A illustrates an example in which the shape of the opening 121c is circular in plan view. When the top surface shape of the opening 121c is circular, the processing accuracy in forming the opening 121c can be increased, and the opening 121c with a fine size can be formed. Note that the top surface shape of the opening 121c can be, for example, an ellipse or polygons such as a quadrangle.

[0131] The insulating layer 105c serving as a gate insulating layer of the transistor 43 is provided to include, in the opening 121c, a region in contact with a part of a top surface of the conductive layer 111c, a side surface of the insulating layer 103c_1, a side surface of the conductive layer 115c, and a side surface of the insulating layer 103c_2.

[0132] The semiconductor layer 113c is provided to cover the opening 121c with the insulating layer 105c therebetween, and includes a region located within the opening 121c. An upper end portion of the insulating layer 105c has a curved shape. The semiconductor layer 113c includes a region in contact with a top surface of the insulating layer 103c_2, a region in contact with the curved portion of the insulating layer 105c, a region in contact with a side surface of the insulating layer 105c, and a region in contact with the top surface of the conductive layer 111c. The semiconductor layer 113c has a shape along the top surface of the insulating layer 103c_2, the curved portion of the insulating layer 105c, the side surface of the insulating layer 105c, and the top surface of the conductive layer 111c. Consequently, the semiconductor layer 113c has a recessed portion in a position overlapping with the opening 121c.In the recessed portion, the layer 114 is provided so as to fill it. The layer 114 has a function of filling the recessed portion and planarizing the upper surface. Note that even if the recessed portion is provided, if the cover with an upper layer formed subsequently is not affected or the recessed portion itself is not formed, the layer 114 does not need to be provided.

[0133] Although the semiconductor layer 113c in Fig. 4B and Fig. 4C has a single-layer structure, an embodiment of the present invention is not limited thereto. The semiconductor layer 113c may have a multilayer structure composed of two or more layers.

[0134] The insulating layer 107c is provided to cover a side surface of a side end portion of the semiconductor layer 113c and the upper surface of the insulating layer 103c_2. The insulating layer 107c has a function of suppressing diffusion of impurities into the transistor 43, for example, a function of suppressing diffusion of impurities into the semiconductor layer 113c. The insulating layer 103c_3 is provided above the insulating layer 107c. The uppermost surfaces of the semiconductor layer 113c, the insulating layer 107c, and the insulating layer 103c_3 preferably have substantially the same height with respect to the substrate surface. Consequently, the formation surface of an upper layer to be formed subsequently (e.g., the conductive layer 111a) can be planarized, resulting in favorable coverage with the upper layer.It should be noted that in the case where the thickness of the insulating layer 107c is substantially equal to the thickness of the semiconductor layer 113c (that is, in the case where the height of the top surface of the insulating layer 107c is substantially equal to the height of the top surface of the semiconductor layer 113c), the insulating layer 103c_3 is not necessarily provided.

[0135] The conductive layer 111a, which serves as the other of the source electrode and the drain electrode of the transistor 43, is provided in contact with the uppermost surface of the semiconductor layer 113c, a top surface of the layer 114, the uppermost surface of the insulating layer 107c, and a top surface of the insulating layer 103c_3. The conductive layer 111a is provided to include a region overlapping with the conductive layer 111c, which serves as one of the source electrode and the drain electrode of the transistor 43.

[0136] An end portion of the conductive layer 111a is preferably substantially aligned with an end portion of the semiconductor layer 113c or is preferably located further outward than the end portion of the semiconductor layer 113c. Consequently, the contact area between the conductive layer 111a and the semiconductor layer 113c can be increased, so that the contact resistance between the conductive layer 111a and the semiconductor layer 113c can be reduced.

[0137] In transistor 43, the source electrode, drain electrode, and gate electrode are provided at different heights relative to the substrate surface so that they overlap with each other. The gate electrode is provided between the source electrode and the drain electrode. Therefore, in transistor 43, the channel longitudinal direction corresponds to the direction along the side surface of insulating layer 105c in a cross-sectional view, and a drain current flows in this direction.

[0138] In the case where the transistor 43 has the structure described above, the channel length of the transistor 43 can be controlled by adjusting the thickness of the layers located between the source electrode and the drain electrode in a cross-sectional view (the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2). Therefore, the channel length of the transistor 43 can be smaller than the resolution limit of the exposure device. The area occupied by the transistor in a plan view can be smaller than that occupied by a transistor having a structure in which a source electrode and a drain electrode are provided on the same plane.

[0139] In the transistor 43, in a plan view, the gate electrode (the conductive layer 115c) is provided so as to surround the opening 121c (the semiconductor layer 113c and the insulating layer 105c). Therefore, all regions of the semiconductor layer 113c in the opening 121c facing the conductive layer 115c with the insulating layer 105c interposed therebetween can serve as the channel formation region of the transistor 43. In this case, the channel width direction of the transistor 43 is a direction parallel to the XY plane, and the channel width of the transistor 43 corresponds to the outer peripheral length of the opening 121c in Fig. 4A.

[0140] The transistor 41 includes a conductive layer 111a, a conductive layer 112a, a semiconductor layer 113a, an insulating layer 105a, and a conductive layer 115a.

[0141] The conductive layer 111a serves as one of a source electrode and a drain electrode of the transistor 41. The conductive layer 112a serves as the other of the source electrode and the drain electrode of the transistor 41 and serves as the wiring 35. The insulating layer 105a serves as the gate insulating layer of the transistor 41. The conductive layer 115a serves as the gate electrode of the transistor 41. The conductive layer 112a serving as the wiring 35 includes a region extending in the Y direction.

[0142] It should be noted that, as described above, the conductive layer 111a also serves as the other of the source electrode and the drain electrode of the transistor 43. Consequently, in the Fig. 4A to Fig. 4C, the conductive layer 111a has both a function of the other of the source electrode and the drain electrode of the transistor 43 and a function of the one of the source electrode and the drain electrode of the transistor 41.

[0143] The conductive layer 111a is provided over the semiconductor layer 113c, the layer 114, the insulating layer 107c, and the insulating layer 103c_3, the insulating layer 103a is provided over the insulating layer 103c_3 and the conductive layer 111a, and the conductive layer 112a is provided over the insulating layer 103a. The conductive layer 111a and the conductive layer 112a include a region where they overlap with each other, with the insulating layer 103a therebetween. The insulating layer 103a and the conductive layer 112a have an opening 121a that reaches the conductive layer 111a. In the Fig. 4A and Fig. In the example shown in Fig. 4B, a side end portion of the conductive layer 111a is located further outward in the X direction than a side end portion of the conductive layer 112a that does not face the opening 121a. In other words, the side end portion of the conductive layer 112a that does not face the opening 121a overlaps with the conductive layer 111a, and the side end portion of the conductive layer 111a does not overlap with the conductive layer 112a. However, an embodiment of the present invention is not limited to this. For example, the side end portion of the conductive layer 111a may be located further inward than the side end portion of the conductive layer 112a that does not face the opening 121a.

[0144] Fig. 4A illustrates an example in which the shape of the opening 121a is circular in plan view. When the top surface shape of the opening 121a is circular, the processing accuracy in forming the opening 121a can be increased, and the opening 121a with a fine size can be formed. Note that the top surface shape of the opening 121a can be, for example, an ellipse or polygons such as a quadrangle.

[0145] The semiconductor layer 113a is provided to cover the opening 121a and include a region located within the opening 121a. The semiconductor layer 113a includes a region in contact with a top surface of the conductive layer 112a, a region in contact with a side surface of the conductive layer 112a, a region in contact with a side surface of the insulating layer 103a, and a region in contact with a top surface of the conductive layer 111a. The semiconductor layer 113a has a shape along the top surface of the conductive layer 112a, the side surface of the conductive layer 112a, the side surface of the insulating layer 103a, and the top surface of the conductive layer 111a. Consequently, the semiconductor layer 113a has a depressed portion in a position overlapping with the opening 121a.

[0146] The semiconductor layer 113a preferably covers a side end portion of the conductive layer 112a on the side of the opening 121a. For example, in Fig. 4B and Fig. 4C, a side end portion of the semiconductor layer 113a above the conductive layer 112a. In other words, the lower end portion of the semiconductor layer 113a is in contact with the upper side of the conductive layer 112a. In the Fig. 4A to Fig. 4C, the side end portion of the semiconductor layer 113a is located further inside than the side end portion of the conductive layer 112a that does not face the opening 121a; in other words, the entire semiconductor layer 113a overlaps with the conductive layer 112a or the opening 121a. Furthermore, in the example shown in Fig. 4A to Fig.4C, the side end portion of the semiconductor layer 113a is further inside than the side end portion of the conductive layer 111a; in other words, the entire semiconductor layer 113a overlaps with the conductive layer 111a.

[0147] In this specification and the like, an upper end portion refers to the uppermost portion of a side end portion, and a lower end portion refers to the lowermost portion of a side end portion. That is, the upper end portion and the lower end portion are each part of the side end portion.

[0148] Although the semiconductor layer 113a in Fig. 4B and Fig. 4C has a single-layer structure, an embodiment of the present invention is not limited thereto. The semiconductor layer 113a may have a multilayer structure composed of two or more layers.

[0149] The insulating layer 105a serving as the gate insulating layer of the transistor 41 is provided to cover the opening 121a and include a region located within the opening 121a. The insulating layer 105a is provided over the semiconductor layer 113a, the conductive layer 112a, and the insulating layer 103a. The insulating layer 105a includes a region in contact with a top surface of the semiconductor layer 113a, a region in contact with a side surface of the semiconductor layer 113a, a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the conductive layer 112a, and a region in contact with a top surface of the insulating layer 103a.The insulating layer 105a has a shape along the top surface of the semiconductor layer 113a, the side surface of the semiconductor layer 113a, the top surface of the conductive layer 112a, the side surface of the conductive layer 112a, and the top surface of the insulating layer 103a. Consequently, the insulating layer 105a has a recessed portion in a position overlapping with the opening 121a.

[0150] The conductive layer 115a serving as the gate electrode of the transistor 41 is provided over the insulating layer 105a and includes a region in contact with a top surface of the insulating layer 105a. The conductive layer 115a includes a region overlapping the semiconductor layer 113a with the insulating layer 105a interposed therebetween. Here, a structure is possible in which, within the opening 121a, the semiconductor layer 113a covers a side surface and a bottom surface of the conductive layer 115a with the insulating layer 105a interposed therebetween. For example, within the opening 121a, the insulating layer 105a includes a region in contact with the side surface of the semiconductor layer 113a, a region in contact with a top surface of the recessed portion of the semiconductor layer 113a, a region in contact with the side surface of the conductive layer 115a, and a region in contact with the bottom surface of the conductive layer 115a.

[0151] As described above, the Fig. 4B and Fig. 4C is a transistor in which the semiconductor layer, the gate insulating layer, and the gate electrode are provided within the opening formed in the interlayer insulating layer. In other words, the transistor 41 is a transistor in which, in a plan view, the semiconductor layer is provided so as to enclose the gate electrode with the gate insulating layer interposed therebetween. Therefore, in a cross-sectional view, the channel length direction of the transistor 41 can be a direction along the side surface of the insulating layer 103a in the opening 121a. Therefore, the channel length is not affected by the performance of an exposure device used to fabricate the transistor 41 and can be shorter than the resolution limit of the exposure device. Consequently, the transistor 41 can be miniaturized. Although Fig. For example, while FIG. 4A illustrates an example in which the entire opening 121a includes a region overlapping with the conductive layer 111a, the semiconductor layer 113a, and the conductive layer 115a, it is permissible for a part of the opening 121a not to overlap with at least one of the conductive layer 111a, the semiconductor layer 113a, and the conductive layer 115a.

[0152] Transistor 41 is a so-called top-gate transistor in which the gate electrode is located above the semiconductor layer 113a. Furthermore, since a bottom surface of the semiconductor layer 113a (a surface on the side of the insulating layer 101) is in contact with the source electrode and the drain electrode, transistor 41 can be referred to as a TGBC (Top-Gate-Bottom-Contact) transistor.

[0153] As in Fig. 4B and Fig. 4C and the like, a part of the insulating layer 105a is located outside the opening 121a, that is, above the conductive layer 112a and the insulating layer 103a. In this case, the insulating layer 105a preferably covers the side end portions of the semiconductor layer 113a. Accordingly, a short circuit between the conductive layer 115a and the semiconductor layer 113a can be prevented. The insulating layer 105a preferably covers the side end portions of the conductive layer 112a. This can prevent a short circuit between the conductive layer 115a and the conductive layer 112a.

[0154] Furthermore, as in Fig. 4B and Fig. 4C and the like, a part of the conductive layer 115a outside the opening 121a, ie, above the conductive layer 112a and the insulating layer 103a. It should be noted that Fig. 4B, Fig. 4C and the like illustrate an example in which a side end portion of the conductive layer 115a is located further inside than the side end portion of the semiconductor layer 113a; however, an embodiment of the present invention is not limited thereto. The side end portion of the conductive layer 115a may be located further outside than the side end portion of the semiconductor layer 113a.

[0155] The insulating layer 107a is provided in contact with the upper surface of the insulating layer 105a and the side surface of the conductive layer 115a. The insulating layer 131 is provided above the insulating layer 107a. A top surface of the conductive layer 115a, the uppermost surface of the insulating layer 107a, and a top surface of the insulating layer 131 have substantially the same height with respect to the substrate surface.

[0156] The insulating layer 107a has a function of suppressing impurity diffusion into the transistor 41, for example, a function of suppressing impurity diffusion into the semiconductor layer 113a. The insulating layer 131 serves as an insulating interlayer, as described above.

[0157] The transistor 42 includes a conductive layer 111b, a conductive layer 112b, a semiconductor layer 113b, an insulating layer 105b, and a conductive layer 115b.

[0158] The conductive layer 111b serves as one of a source electrode and a drain electrode of the transistor 42. The conductive layer 112b serves as the other of the source electrode and the drain electrode of the transistor 42 and serves as a wiring 33W. The insulating layer 105b serves as the gate insulating layer of the transistor 42. The conductive layer 115b serves as the gate electrode of the transistor 42 and serves as a wiring 31W. The conductive layer 112b serving as a wiring 33W includes a region extending in the Y direction. The conductive layer 115b serving as a wiring 31W includes a region extending in the X direction.

[0159] It should be noted that, as described above, the conductive layer 111b also serves as the other of the source electrode and the drain electrode of the transistor 41. Consequently, in the Fig. 4A to Fig. 4C, the conductive layer 111b has both a function of the other of the source electrode and the drain electrode of the transistor 41 and a function of the one of the source electrode and the drain electrode of the transistor 42.

[0160] The conductive layer 111b is provided over the conductive layer 115a, the insulating layer 107a, and the insulating layer 131. The conductive layer 111b includes at least a region in contact with the upper surface of the conductive layer 115a. The insulating layer 103b is provided over the insulating layer 131 and the conductive layer 111b. The conductive layer 112b is provided over the insulating layer 103b. The conductive layer 111b and the conductive layer 112b include a region where they overlap with each other, with the insulating layer 103b interposed therebetween.

[0161] The insulating layer 103b and the conductive layer 112b have an opening 121b that reaches the conductive layer 111b. Fig. 4A illustrates an example in which the shape of the opening 121b is circular in plan view. Note that the shape of the opening 121b may be similar to the shape that the opening 121a may have.

[0162] Transistor 42 may have a structure similar to the above-described structure of transistor 41. For the description of the structure of transistor 42, reference may be made to the description of the structure of transistor 41 by replacing transistor 41, insulating layer 103a, insulating layer 105a, conductive layer 111a, conductive layer 112a, semiconductor layer 113a, and conductive layer 115a with transistor 42, insulating layer 103b, insulating layer 105b, conductive layer 111b, conductive layer 112b, semiconductor layer 113b, and conductive layer 115b, respectively, and performing appropriate substitution of words or sentences as needed.

[0163] In this specification and the like, the insulating layer 103a, the insulating layer 103b, the insulating layer 103c_1, the insulating layer 103c_2, the insulating layer 103c_3, and the like are collectively referred to as insulating layer 103 in some cases. The insulating layer 105a, the insulating layer 105b, and the insulating layer 105c are collectively referred to as insulating layer 105 in some cases. The insulating layer 107a, the insulating layer 107b, and the insulating layer 107c are collectively referred to as insulating layer 107 in some cases. The conductive layer 111a, the conductive layer 111b, and the conductive layer 111c are collectively referred to as conductive layer 111 in some cases. The conductive layer 112a and the conductive layer 112b are collectively referred to as conductive layer 112 in some cases.The semiconductor layer 113a, the semiconductor layer 113b, and the semiconductor layer 113c are collectively referred to as semiconductor layer 113 in some cases. The conductive layer 115a, the conductive layer 115b, and the conductive layer 115c are collectively referred to as conductive layer 115 in some cases. The opening 121a, the opening 121b, and the opening 121c are collectively referred to as opening 121 in some cases.

[0164] The insulating layer 107b is provided over the conductive layer 115b and the insulating layer 105b. The insulating layer 107b may be provided to cover a top surface and a side surface of the conductive layer 115b. The insulating layer 107b has a function of suppressing impurities from diffusing into the transistor 42, for example, a function of suppressing impurities from diffusing into the semiconductor layer 113b.

[0165] As described above, in the semiconductor device of one embodiment of the present invention, transistor 43, transistor 41, and transistor 42 are stacked in this order. In transistor 43, the source electrode, drain electrode, and gate electrode are provided at different heights with respect to the substrate surface such that they include a region where they overlap with each other, and the gate insulating layer and the semiconductor layer are provided such that the channel length direction is formed along the height direction.In each of the transistor 41 and the transistor 42, the semiconductor layer, the gate insulating layer, and the gate electrode are provided within the opening formed in the interlayer insulating layer, one of the source electrode and the drain electrode is provided below the opening, and the other of the source electrode and the drain electrode is provided above the interlayer insulating layer. Consequently, the area occupied by the memory cell 21 in a plan view can be reduced. Therefore, the memory cells can be miniaturized and highly integrated. Accordingly, according to an embodiment of the present invention, a semiconductor device capable of miniaturization and higher resolution can be provided.

[0166] In the cross-sectional views in Fig. 4B and Fig. 4C, boundaries between layers may not be clearly perceived in some cases. For example, a boundary between two insulating layers that are in contact with each other may not be clearly perceived in some cases. Furthermore, a boundary between two conductive layers that are in contact with each other may not be clearly perceived in some cases. Furthermore, a boundary between two semiconductor layers that are in contact with each other may not be clearly perceived in some cases. <Strukturbeispiel 2 der Halbleitervorrichtung>

[0167] Fig. 5A to Fig. 5C illustrate a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from that in Fig. 4A to Fig. 4C differs. Fig. 5A is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 5B is a cross-sectional view taken along a dot-dash line A1-A2 in Fig. 5A, and Fig. 5C is a cross-sectional view along a dash-dotted line A3-A4 in Fig. 5A.

[0168] The Fig. 5A to Fig. The semiconductor device 10 shown in Figure 5C differs from that shown in Fig. 4A to Fig. 4C by the structure of the transistor 43.

[0169] The transistor 43, which is in the Fig. 5A to Fig. 5C includes the conductive layer 111c, the conductive layer 111a, the semiconductor layer 113c, the insulating layer 105c, and the conductive layer 115c.

[0170] The conductive layer 111c serves as one of a source electrode and a drain electrode of the transistor 43 and serves as a wiring 33R. The conductive layer 111a serves as the other of the source electrode and the drain electrode of the transistor 43. The insulating layer 105c serves as the gate insulating layer of the transistor 43. The conductive layer 115c serves as the gate electrode of the transistor 43 and serves as a wiring 31R. The conductive layer 111c serving as a wiring 33R includes a region extending in the Y direction. The conductive layer 115c serving as a wiring 31R includes a region extending in the X direction.

[0171] The conductive layer 111c is provided over the insulating layer 101, the insulating layer 105c is provided over the insulating layer 101 and the conductive layer 111c, the conductive layer 115c is provided over the insulating layer 105c, and the insulating layer 103c is provided over the insulating layer 105c and the conductive layer 115c. As shown in Fig. 5A to Fig. 5C, the semiconductor layer 113c is provided in a columnar shape above the conductive layer 111c. It should be noted that Fig. 5A illustrates an example in which the shape of the semiconductor layer 113c is circular in plan view; however, an embodiment of the present invention is not limited thereto. The top surface shape of the semiconductor layer 113c may be, for example, an ellipse or polygons such as a quadrangle.

[0172] The insulating layer 105c, which serves as the gate insulating layer of the transistor 43, includes a region in contact with a side surface of the semiconductor layer 113c, the side surface and bottom surface of the conductive layer 115c, the top and one side surface of the conductive layer 111c, and one side surface of the insulating layer 103c. The semiconductor layer 113c and the conductive layer 115c are provided facing each other in a cross-sectional view, with the insulating layer 105c interposed therebetween.

[0173] The conductive layer 115c, which serves as the gate electrode of the transistor 43, is provided to cover the columnar semiconductor layer 113c with the insulating layer 105c therebetween. With this structure, a gate electric field (an electric field from the conductive layer 115c) can be applied to the semiconductor layer 113c from all directions in the XY plane.

[0174] The insulating layer 103c is provided to include a region in contact with the side surface of the conductive layer 115c, a top surface of the conductive layer 115c, a top surface of the insulating layer 105c, and the side surface of the insulating layer 105c.

[0175] The top surface of the semiconductor layer 113c, the top surface of the insulating layer 105c, and a top surface of the insulating layer 103c have substantially the same height with respect to the substrate surface.

[0176] The conductive layer 111a, which serves as the other of the source electrode and the drain electrode of the transistor 43, is provided in contact with the upper surface of the semiconductor layer 113c, the uppermost surface of the insulating layer 105c, and the upper surface of the insulating layer 103c. The conductive layer 111a is provided to include a region overlapping with the conductive layer 111c, which serves as one of the source electrode and the drain electrode of the transistor 43.

[0177] An end portion of the conductive layer 111a is preferably substantially aligned with an end portion of the semiconductor layer 113c or is preferably located further outward than the end portion of the semiconductor layer 113c. Consequently, the contact area between the conductive layer 111a and the semiconductor layer 113c can be increased, so that the contact resistance between the conductive layer 111a and the semiconductor layer 113c can be reduced.

[0178] In the Fig. 5A to Fig. 5C, as shown in the transistor 43 in Fig. 4A to Fig. In the transistor 43 shown in Figure 4C, the source electrode, drain electrode, and gate electrode are provided at different heights relative to the substrate surface so that they overlap with each other. The gate electrode is provided between the source electrode and the drain electrode. Therefore, in the transistor 43, the channel longitudinal direction corresponds to the direction along the side surface of the insulating layer 105c in a cross-sectional view, and a drain current flows in this direction.

[0179] In the case where the transistor 43 has the structure described above, the channel length of the transistor 43 can be controlled by adjusting the thickness of the semiconductor layer 113c located between the source electrode and the drain electrode in a cross-sectional view. Therefore, the channel length of the transistor 43 can be smaller than the resolution limit of the exposure device. The area occupied by the transistor in a plan view can be smaller than that occupied by a transistor with a structure in which a source electrode and a drain electrode are provided on the same plane.

[0180] In the Fig. 5A to Fig. 5C, as described above, in a plan view, the gate electrode (the conductive layer 115c) is provided so as to enclose the semiconductor layer 113c. Therefore, all regions of the semiconductor layer 113c facing the conductive layer 115c with the insulating layer 105c interposed therebetween can serve as the channel formation region of the transistor 43. In this case, the channel width direction of the transistor 43 is a direction parallel to the XY plane, and the channel width of the transistor 43 corresponds to the outer peripheral length of the semiconductor layer 113c in Fig. 5A.

[0181] The Fig. 4A to Fig. The transistor 43 shown in Fig. 4C has a structure in which the semiconductor layer 113c is provided so as to cover the opening provided in the insulating layer, while the transistor 43 shown in Fig. 5A to Fig. 5C has a structure in which the semiconductor layer 113c is provided in a columnar shape. Therefore, the transistor 43 can be formed with the structure shown in Fig. 5A to Fig. 5C may be referred to as a FIN transistor. Thus, the transistor 43 included in the semiconductor device 10 of one embodiment of the present invention may have various structures.

[0182] For those in Fig. 5A to Fig. 5C, except for the differences described above (e.g., for the structures of transistor 41 and transistor 42), can be referred to the description of the semiconductor device 10 shown in Fig. 4A to Fig. 4C.

[0183] Fig. 6A is an enlarged view of the Fig. 4C and its surroundings. Fig. 6B is such a cross-sectional view along the XY plane of the Fig. 6A that it comprises the semiconductor layer 113 and the conductive layer 112. The Fig. 6A and Fig. The structure shown in Figure 6B can be applied not only to transistor 42 but also to transistor 41.

[0184] As in Fig. As shown in Fig. 6A, the semiconductor layer 113 includes a region 113i and a region 113na and a region 113nb provided with the region 113i therebetween.

[0185] The region 113na is a region in the semiconductor layer 113 that is in contact with the conductive layer 111. At least a portion of the region 113na serves as one of a source region and a drain region of the transistor. The region 113nb is a region in the semiconductor layer 113 that is in contact with the conductive layer 112. At least a portion of the region 113nb serves as the other of the source region and the drain region of the transistor. As shown in Fig. 6B, the conductive layer 112 is in contact with the entire circumference of the semiconductor layer 113. Therefore, the other of the source region and the drain region of the transistor can be formed along the entire circumference of a region in the semiconductor layer 113 that is formed in the same layer as the conductive layer 112.

[0186] Region 113i is a region between region 113na and region 113nb in semiconductor layer 113. At least a portion of region 113i serves as a channel formation region of the transistor. This means that the channel formation region of the transistor is located in a region between the conductive layer 111 and the conductive layer 112 in semiconductor layer 113. In other words, the channel formation region of the transistor is located in a region in contact with the insulating layer 103 or a region in the vicinity of the insulating layer 103 in semiconductor layer 113.

[0187] The channel length of the transistor is the distance between the source and drain regions. This means that the channel length of the transistor is determined by the thickness of the insulating layer 103 above the conductive layer 111. Fig. In Figure 6A, a channel length L of the transistor is represented by a solid double-headed arrow. In a cross-sectional view, the channel length L is a distance between an end portion of the region where the semiconductor layer 113 is in contact with the conductive layer 111 and an end portion of the region where the semiconductor layer 113 is in contact with the conductive layer 112. That is, the channel length L corresponds to the length of a side surface of the insulating layer 103 on the opening 121 side in the cross-sectional view.

[0188] In a planar transistor, for example, the channel length is determined by the exposure limit of photolithography; in the present invention, the channel length can be determined by the thickness of the insulating layer 103. Therefore, the channel length of the transistor can be less than or equal to the exposure limit of photolithography, which enables a fairly fine structure (e.g., greater than or equal to 1 nm and less than or equal to 60 nm, greater than or equal to 1 nm and less than or equal to 50 nm, greater than or equal to 1 nm and less than or equal to 40 nm, greater than or equal to 1 nm and less than or equal to 30 nm, greater than or equal to 1 nm and less than or equal to 20 nm, greater than or equal to 1 nm and less than or equal to 10 nm, or greater than or equal to 5 nm and less than or equal to 10 nm). Accordingly, the transistor can have higher on-state current and higher frequency characteristics.Accordingly, the read speed and write speed of the memory cell can be increased, thereby providing a semiconductor device with high operating speed.

[0189] Although the details are described below, an OS transistor has a higher resistance to a short-channel effect than a Si transistor. Furthermore, as described above, the transistor can be Fig. 6A and Fig. 6B, for example, can have a shorter channel length than a planar transistor. Therefore, if the transistor has the Fig. 6A and Fig. 6B, for example, a metal oxide is preferably used for the semiconductor layer 113. It should be noted that a material other than a metal oxide, such as silicon, may be used for the semiconductor layer 113.

[0190] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 121. Therefore, the area occupied by the transistor can be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This enables high integration of the semiconductor device; therefore, the storage capacity per unit area can be increased.

[0191] In addition, as in Fig. As shown in Figure 6B, the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are provided concentrically on the XY plane, which includes the channel formation region of the semiconductor layer 113. Therefore, the side surface of the conductive layer 115 provided at the center faces the side surface of the semiconductor layer 113, with the insulating layer 105 interposed therebetween. This means that the entire inner circumference of the semiconductor layer 113 in the plan view serves as the channel formation region. In this case, for example, the channel width of the transistor is determined by the length of the circumference of the semiconductor layer 113. In other words, the channel width of the transistor is determined by the maximum width of the opening 121 (the diameter when the opening 121 is circular in the plan view). Fig. 6A and Fig. 6B, a maximum width D of the opening 121 is represented by a dash-colon-double arrow. In Fig. In Figure 6B, a channel width W of the transistor is represented by a dashed double-headed arrow. By increasing the maximum width D of the opening 121, the channel width per unit area can be increased, and the forward current can be increased.

[0192] The maximum width D of the opening 121 is preferably, for example, greater than or equal to 5 nm and less than or equal to 100 nm, greater than or equal to 10 nm and less than or equal to 60 nm, greater than or equal to 20 nm and less than or equal to 50 nm, greater than or equal to 20 nm and less than or equal to 40 nm, or greater than or equal to 20 nm and less than or equal to 30 nm. In the case where the opening 121 is circular in the plan view, the maximum width D of the opening 121 may correspond to the diameter of the opening 121, and the channel width W may be “D × π”.

[0193] In the semiconductor device of one embodiment of the present invention, the channel length L of the transistor is preferably shorter than at least the channel width W of the transistor. The channel length L of the transistor in one embodiment of the present invention is greater than or equal to 0.1 times and less than or equal to 0.99 times, preferably greater than or equal to 0.5 times and less than or equal to 0.8 times the channel width W of the transistor. This structure enables a transistor with advantageous electrical properties and high reliability.

[0194] By concentrically providing the semiconductor layer 113, the insulating layer 105, and the conductive layer 115, the distance between the conductive layer 115 and the semiconductor layer 113 is substantially uniform. Therefore, a gate electric field can be applied substantially uniformly to the semiconductor layer 113.

[0195] The sidewall of opening 121 is preferably perpendicular to the top surface of conductive layer 111, for example. This structure enables miniaturization or high integration of the semiconductor device. Note that the sidewall of opening 121 may be tapered.

[0196] The components of the transistors contained in the memory cell are described below. [Components of the transistor]

[0197] As the semiconductor layer 113, a single layer or stacked layers of one of the metal oxides described below in [Metal Oxide] may be used. As the semiconductor layer 113, a single layer or stacked layers of one of the materials described below in [Other Semiconductor Materials], such as silicon, may be used.

[0198] In the case of using a metal oxide for the semiconductor layer 113, a metal oxide having an atomic ratio of In:M:Zn = 1:3:2 or close thereto, In:M:Zn = 1:3:4 or close thereto, In:M:Zn = 1:1:0.5 or close thereto, In:M:Zn = 1:1:1 or close thereto, In:M:Zn = 1:1:1.2 or close thereto, In:M:Zn = 1:1:2 or close thereto, or In:M:Zn = 4:2:3 or close thereto can be used for the semiconductor layer 113. Note that the proximity of an atomic ratio includes ±30% of an intended atomic ratio. Gallium is preferably used as the element M.

[0199] When the metal oxide is deposited by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, and the above atomic ratio may be an atomic ratio of a sputtering target used for the deposition of the metal oxide.

[0200] The composition analysis of the metal oxide used for the semiconductor layer 113 can be performed by energy-dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, any of these methods can be combined for analysis. Note that with respect to an element whose content is low, the actual content may differ from the content obtained by analysis due to the influence of the analysis accuracy.For example, in the case where the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0201] An atomic layer deposition (ALD) process can be suitably used to form a metal oxide.

[0202] Alternatively, a metal oxide can be formed by a sputtering process or a chemical vapor deposition (CVD) process.

[0203] It should be noted that when the metal oxide is formed by a sputtering process, the atomic ratio of the deposited metal oxide may differ from the atomic ratio of a sputtering target. In particular, the zinc content in the deposited metal oxide may be reduced to approximately 50% of that of the sputtering target.

[0204] The metal oxide used for the semiconductor layer 113 preferably has crystallinity. Examples of an oxide semiconductor having crystallinity include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a nanocrystalline oxide semiconductor (nc-OS), a polycrystalline oxide semiconductor, and a single-crystalline oxide semiconductor. For the semiconductor layer 113, CAAC-OS or nc-OS is preferably used, and CAAC-OS is particularly preferred.

[0205] The CAAC-OS preferably comprises a plurality of layered crystal regions, and a c-axis is preferably aligned in a normal direction of a surface on which the CAAC-OS is deposited. For example, the semiconductor layer 113 preferably comprises a layered crystal that is substantially parallel to the sidewall of the opening 121, particularly parallel to a side surface of the insulating layer 103. With this structure, the layered crystal of the semiconductor layer 113 is formed substantially parallel to the channel length direction of the transistor, so that the on-state current of the transistor can be increased.

[0206] CAAC-OS is a metal oxide that exhibits a dense structure with high crystallinity and a low amount of impurities and defects (e.g., oxygen vacancies). Specifically, after the formation of a metal oxide, a heat treatment is performed at a temperature at which the metal oxide does not become a polycrystal (e.g., higher than or equal to 400°C and lower than or equal to 600°C), whereby a CAAC-OS exhibiting a dense structure with higher crystallinity can be obtained. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0207] CAAC-OS is less likely to experience a reduction in electron mobility due to a crystal grain boundary because it is difficult to observe a distinct crystal grain boundary. Therefore, a metal oxide containing CAAC-OS is physically stable. Therefore, the metal oxide containing CAAC-OS is heat-resistant and has high reliability.

[0208] When an oxide with crystallinity, such as CAAC-OS, is used for the semiconductor layer 113, the extrusion of oxygen from the semiconductor layer 113 through the source or drain electrode can be suppressed. In this case, the extraction of oxygen from the semiconductor layer 113 can be suppressed even when heat treatment is performed; therefore, the transistor is stable to high temperatures during the manufacturing process (i.e., the heat budget).

[0209] The crystallinity of the semiconductor layer 113 can be analyzed, for example, using X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, any of these methods can be combined for analysis.

[0210] The thickness of the semiconductor layer 113 is preferably, for example, greater than or equal to 1 nm and less than or equal to 20 nm, greater than or equal to 3 nm and less than or equal to 15 nm, greater than or equal to 5 nm and less than or equal to 12 nm, or greater than or equal to 5 nm and less than or equal to 10 nm.

[0211] Although in Fig. 4B and Fig. 4C and Fig. 6A, the semiconductor layer 113 has a single-layer structure, the present invention is not limited thereto. The semiconductor layer 113 may have a multilayer structure composed of a plurality of oxide layers having different chemical compositions. For example, a structure in which a plurality of types of metal oxides among the metal oxides described above are appropriately stacked may be used.

[0212] For the insulating layer 105 serving as the gate insulating layer, a single layer or stacked layers of one of the insulators described below in [Insulator] can be used. For example, silicon oxide or silicon oxynitride can be used for the insulating layer 105. Silicon oxide or silicon oxynitride is preferred because of its thermal stability.

[0213] For the insulating layer 105, one of the high relative permittivity materials, ie, high-k materials described below in [Insulator], may be used. For example, hafnium oxide, aluminum oxide, or the like may be used.

[0214] The thickness of the insulating layer 105 is preferably greater than or equal to 0.5 nm and less than or equal to 15 nm, more preferably greater than or equal to 0.5 nm and less than or equal to 12 nm, even more preferably greater than or equal to 0.5 nm and less than or equal to 10 nm. Preferably, the insulating layer 105 at least partially comprises a region having the thickness described above.

[0215] The concentration of impurities such as water and hydrogen in the insulating layer 105 is preferably reduced. This can suppress the entry of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 113.

[0216] Although in Fig. 4B and Fig. 4C and Fig. 6A, the insulating layer 105 has a single-layer structure, the present invention is not limited thereto. The insulating layer 105 may have a multi-layer structure.

[0217] For the conductive layer 115 serving as the gate electrode, a single layer or stacked layers of any of the conductors described below in [Conductors] may be used. For example, a conductive material with high conductivity, such as tungsten, aluminum, or copper, may be used for the conductive layer 115.

[0218] A conductive material that is less likely to be oxidized, a conductive material having a function of suppressing oxygen diffusion, or the like, is preferably used for the conductive layer 115. Examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a reduction in the conductivity of the conductive layer 115. A semiconductor with high electrical conductivity, typically polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide, can be used for the conductive layer 115.

[0219] Although in Fig. 4B and Fig. 4C and Fig. 6A, the conductive layer 115 has a single-layer structure, the present invention is not limited thereto. The conductive layer 115 may have a multi-layer structure.

[0220] For the conductive layer 111, a single layer or stacked layers of any of the conductors described below in [Conductor] can be used. A conductive material that is less likely to be oxidized, a conductive material having a function of suppressing oxygen diffusion, or the like is preferably used for the conductive layer 111. For example, titanium nitride, tantalum nitride, or the like can be used. For example, a structure in which tantalum nitride is arranged over titanium nitride can be used. In this case, titanium nitride is in contact with the insulating layer 101, the insulating layer 103c, the insulating layer 131, and the like, and tantalum nitride is in contact with the semiconductor layer 113. With such a structure, the conductive layer 111 can be suppressed from being excessively oxidized by the semiconductor layer 113.By using an oxide insulator for the insulating layer 101, the insulating layer 103c, the insulating layer 131, and the like, the conductive layer 111 can be suppressed from being excessively oxidized by these insulating layers. Alternatively, the conductive layer 111 may have a structure in which tungsten is disposed over titanium nitride, for example.

[0221] Since the conductive layer 111 includes a region in contact with the semiconductor layer 113, one of the conductive materials containing oxygen described below in [Conductor] is preferably used for the conductive layer 111. When the conductive material containing oxygen is used for the conductive layer 111, the conductive layer 111 can maintain its conductivity even if it absorbs oxygen. As the conductive layer 111, for example, a single layer or stacked layers of indium tin oxide (also referred to as ITO), indium tin oxide with silicon added (also referred to as ITSO), indium zinc oxide (IZO (registered trademark)), or the like can be used.

[0222] Although in Fig. 4B and Fig. 4C and Fig. 6A, the top surface of the conductive layer 111 is flat, the present invention is not limited thereto. For example, the top surface of the conductive layer 111 may have a recessed portion that overlaps with the opening 121. If at least a part of the semiconductor layer 113, at least a part of the insulating layer 105, and at least a part of the conductive layer 115 are formed to fill the recessed portion, an electric field of the gate of the conductive layer 115 can be easily applied to a portion of the semiconductor layer 113 near the conductive layer 111.

[0223] For the conductive layer 112, a single layer or stacked layers of one of the conductors described below in [Conductors] may be used. For example, a conductive material with high conductivity, such as tungsten, aluminum, or copper, may be used for the conductive layer 112.

[0224] For the conductive layer 112, as in the conductive layer 111 and the conductive layer 115, a conductive material that is less likely to be oxidized, a conductive material with a function of suppressing oxygen diffusion, or the like is preferably used. For example, titanium nitride, tantalum nitride, or the like can be used. With such a structure, the conductive layer 112 can be suppressed from being excessively oxidized by the semiconductor layer 113. For the conductive layer 112, as in the conductive layer 115, a semiconductor with high electrical conductivity, typically polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide, can be used.

[0225] Alternatively, for example, a structure in which tungsten is disposed over titanium nitride may be used. When tungsten is disposed over titanium nitride in this manner, the conductivity of the conductive layer 112 can be improved.

[0226] For example, in the case where the conductive layer 112 has a multilayer structure of a first conductive layer and a second conductive layer, the first conductive layer may be formed using a conductive material with high conductivity, and the second conductive layer may be formed using a conductive material containing oxygen. By using the conductive material containing oxygen for the second conductive layer, in which the area of ​​the region in contact with the insulating layer 105 is larger than that of the first conductive layer, oxygen contained in the insulating layer 105 can be suppressed from diffusing into the first conductive layer of the conductive layer 112.For example, tungsten is preferably used as the first conductive layer of the conductive layer 112, and indium tin oxide added with silicon is preferably used as the second conductive layer of the conductive layer 112.

[0227] When the semiconductor layer 113 is in contact with the conductive layer 111, a metal compound or oxygen vacancies are formed in the semiconductor layer 113, and the resistance of the region 113na in the semiconductor layer 113 is reduced. Reducing the resistance of the semiconductor layer 113 in contact with the conductive layer 111 can reduce the contact resistance between the semiconductor layer 113 and the conductive layer 111. Similarly, when the semiconductor layer 113 is in contact with the conductive layer 112, the resistance of the region 113nb of the semiconductor layer 113 is reduced. Accordingly, the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced.

[0228] The insulating layer 101, the insulating layer 103, and the insulating layer 131 serving as interlayer insulating films each preferably have a low relative permittivity. When a low relative permittivity material is used for an interlayer insulating film, parasitic capacitance between lines can be reduced. For the insulating layer 101, the insulating layer 103, and the insulating layer 131, a single layer or stacked layers of any of the insulators each containing a low relative permittivity material described below in [Insulator] can be used. In particular, silicon oxide and silicon oxynitride, which are thermally stable, are preferred.

[0229] The concentration of impurities such as water and hydrogen in the insulating layer 101, the insulating layer 103, and the insulating layer 131 is preferably reduced. This can suppress the ingress of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 113.

[0230] The insulating layer 103 provided near the channel formation region of the semiconductor layer 113 preferably contains oxygen released by heating (hereinafter also referred to as excess oxygen in some cases). When a heat treatment is performed on the insulating layer 103 containing excess oxygen, oxygen is supplied from the insulating layer 103 to the channel formation region of the semiconductor layer 113, so that oxygen vacancies and defects that are oxygen vacancies into which hydrogen enters (hereinafter also referred to as V OH) in the semiconductor layer 113 can be reduced. Consequently, electrical characteristics of the transistor can be stabilized and reliability can be improved.

[0231] For the insulating layer 103, one of the insulators with a hydrogen trapping or fixing function described below in [Insulator] can be used. With this structure, hydrogen can be trapped or fixed in the semiconductor layer 113, thereby reducing the hydrogen concentration in the semiconductor layer 113. Magnesium oxide, aluminum oxide, or the like can be used for the insulating layer 103.

[0232] Although in Fig. 4B and Fig. 4C and Fig. 6A, the insulating layer 103 has a single-layer structure, the present invention is not limited thereto. The insulating layer 103 may have a multi-layer structure.

[0233] For the insulating layer 107, one of the insulators with a hydrogen barrier property described below in [Insulator] is preferably used. In this case, hydrogen can be suppressed from diffusing from the outside of the transistors into the semiconductor layer 113 via the insulating layer 105. A silicon nitride film and a silicon nitride oxide film can be suitably used for the insulating layer 107 because they release little impurities (e.g., water and hydrogen) and are less likely to transmit oxygen and hydrogen.

[0234] For the insulating layer 107, one of the insulators having a function of capturing or fixing hydrogen, which are described in [Insulator] below, is preferably used. With this structure, diffusion of hydrogen from the above insulating layer 107 into the semiconductor layer 113 can be suppressed, and hydrogen in the semiconductor layer 113 can be captured or fixed, thereby reducing the hydrogen concentration in the semiconductor layer 113. Magnesium oxide, alumina, hafnium oxide, or the like can be used for the insulating layer 107. Alternatively, for example, a multilayer film of alumina and silicon nitride over the alumina can be used for the insulating layer 107.

[0235] Although in Fig. 4B and Fig. 4C and Fig. While the insulating layer 107 is formed over the top surface of the transistor in the structure shown in FIG. 6A, the structure is not limited to this. For example, the insulating layer 107, or an insulating layer having a similar function or containing a similar material to the insulating layer 107, may be formed on the side surface and bottom surface of the transistor to surround the transistor. Alternatively, the insulating layer 107 may be formed on the top surface, side surface, and bottom surface of the transistor 43, the transistor 41, and the transistor 42 to surround the transistor 43, the transistor 41, and the transistor 42. This structure can suppress the ingress of impurities (e.g., water and hydrogen) into the transistor 43, the transistor 41, and the transistor 42. <Strukturbeispiel 3 der Halbleitervorrichtung>

[0236] Fig. 7A to Fig. 7C illustrate a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 7A is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. Figure 7B is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 7A, and Fig. Figure 7C is a cross-sectional view along the dotted line A3-A4 in Fig. 7A.

[0237] The Fig. 7A to Fig. The semiconductor device 10 shown in Figure 7C differs from that shown in Fig. 4A to Fig. 4C in that a conductive layer serving as the other of the source electrode and the drain electrode of the transistor 43 and a conductive layer serving as the one of the source electrode and the drain electrode of the transistor 41 are provided separately from each other, and the two conductive layers are connected to each other via a conductive layer serving as a terminal plug.

[0238] In the transistor 43, which is in the Fig. 7A to Fig. 7C, the conductive layer 112c serves as the other of the source electrode and the drain electrode. Any of the materials described above that can be used for the conductive layer 111 or the conductive layer 112 can be used for the conductive layer 112c.

[0239] The conductive layer 112c is provided in such a way that it is in contact with the upper surfaces of the semiconductor layer 113c, the layer 114, the insulating layer 107c, and the insulating layer 103c_3, and includes a region that overlaps with the conductive layer 111c. An insulating layer 103c_4 is provided in a region above the insulating layer 103c_3 that does not overlap with the conductive layer 112c. A top surface of the conductive layer 112c and a top surface of the insulating layer 103c_4 have substantially the same height relative to the substrate.

[0240] An insulating layer 132 is provided over the conductive layer 112c and the insulating layer 103c_4. An opening is provided in the insulating layer 132 in a region overlapping with the conductive layer 112c, and a conductive layer 118 is provided to fill the opening. It is preferable that a top surface of the conductive layer 118 and a top surface of the insulating layer 132 have substantially the same height with respect to the substrate. The top surface of the conductive layer 112c is in contact with a bottom surface of the conductive layer 118. The top surface of the conductive layer 118 is in contact with a bottom surface of the conductive layer 111a. The insulating layer 103c_4 and the insulating layer 132 each serve as an insulating interlayer.Any of the above-described materials that can be used for the insulating layer 101, the insulating layer 103, and the insulating layer 131 can be used for the insulating layer 103c_4 and the insulating layer 132. The conductive layer 118 serves as a terminal plug that electrically connects the conductive layer 112c, which serves as the other of the source electrode and the drain electrode of the transistor 43, and the conductive layer 111a, which serves as the one of the source electrode and the drain electrode of the transistor 41. For example, any of the above-described conductive materials with high conductivity that can be used for the conductive layer 115 can be used for the conductive layer 118.In order to prevent the conductive layer 118 from being oxidized by oxygen contained in the insulating layer 132 and the like, a structure may be adopted in which any of the above-described conductive materials that are less likely to be oxidized or have a function of suppressing oxygen diffusion and can be used for the conductive layer 111, the conductive layer 112, and the conductive layer 115 is provided in contact with a side surface of the insulating layer 132, and a conductive material having high conductivity is provided on the inside of the conductive material.

[0241] For those in Fig. 7A to Fig. 7C, except for the differences described above, can be referred to the description of the semiconductor device 10 shown in Fig. 4A to Fig. 4C. <Strukturbeispiel 4 der Halbleitervorrichtung>

[0242] Fig. 8A to Fig. 8C illustrate a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 8A is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 8B is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 8A, and Fig. Figure 8C is a cross-sectional view along the dotted line A3-A4 in Fig. 8A.

[0243] The Fig. 8A to Fig. The semiconductor device 10 shown in Figure 8C differs from that shown in Fig. 7A to Fig. 7C in that the conductive layer serving as the other of the source electrode and the drain electrode of the transistor 43 (the conductive layer 112c) and the conductive layer serving as the one of the source electrode and the drain electrode of the transistor 41 (the conductive layer 111a) are not directly connected to each other via any terminal plug (that is, the top surface of the conductive layer 112c is in contact with the bottom surface of the conductive layer 111a).

[0244] If the Fig. 8A to Fig. 8C has the structure described above, the manufacturing process can be made simpler than that of the semiconductor device 10 shown in Fig. 7A to Fig. 7C shown semiconductor device 10.

[0245] For those in Fig. 8A to Fig. 8C, except for the differences described above, can be referred to the description of the semiconductor device 10 shown in Fig. 4A to Fig. 4C. <Strukturbeispiel 5 der Halbleitervorrichtung>

[0246] Fig. 9A to Fig. 9C illustrate a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 9A is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 9B is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 9A, and Fig. 9C is a cross-sectional view along the dotted line A3-A4 in Fig. 9A.

[0247] The Fig. 9A to Fig. 9C differs from the semiconductor device 10 shown in Fig. 4A to Fig. 4C in that the conductive layer 111a serving as the other of the source electrode and the drain electrode of the transistor 43 and the one of the source electrode and the drain electrode of the transistor 41 is not included.

[0248] In the Fig. 9A to Fig. In the semiconductor device 10 shown in Fig. 9C, the bottom surface of the semiconductor layer 113a of the transistor 41 (the surface on the transistor 43 side) is in direct contact with a part of the top surface of the semiconductor layer 113c of the transistor 43 and the top surface of the layer 114.

[0249] If the Fig. 9A to Fig. 9C has the structure described above, the manufacturing process can be made simpler than that of the semiconductor device 10 shown in Fig. 4A to Fig. 4C shown semiconductor device 10.

[0250] For those in Fig. 9A to Fig. 9C, except for the differences described above, can be referred to the description of the semiconductor device 10 shown in Fig. 4A to Fig. 4C. <Strukturbeispiel 6 der Halbleitervorrichtung>

[0251] Fig. 10A to Fig. 10C illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 10A is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 10B is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 10A, and Fig. 10C is a cross-sectional view along the dotted line A3-A4 in Fig. 10A.

[0252] The Fig. 10A to Fig. The semiconductor device 10 shown in Figure 10C differs from that shown in Fig. 9A to Fig. 9C by providing a single opening 126 in the transistor 43 and the transistor 41 without separately providing the opening 121c included in the transistor 43 and the opening 121a included in the transistor 41.

[0253] In the Fig. 10A to Fig. In the semiconductor device 10 shown in FIG. 10C, the opening 126 reaching the conductive layer 111c is provided in the insulating layer 103c_1, the conductive layer 115c, the insulating layer 103a, and the conductive layer 112a. The insulating layer 105c is provided in contact with the side surface of the insulating layer 103c_1, the side surface of the conductive layer 115c, the side surface of the insulating layer 103a, and the side surface of the conductive layer 112a on the opening 126 side. The semiconductor layer 113a is provided so as to fill at least a part of the opening 126 with the insulating layer 105c interposed therebetween. The conductive layer 115a is provided so as to fill a depressed portion above the semiconductor layer 113a in the opening 126 with the insulating layer 105a interposed therebetween.

[0254] If the Fig. 10A to Fig. 10C has the structure described above, the manufacturing process can be made simpler than that of the semiconductor device 10 shown in Fig. 9A to Fig. 9C shown semiconductor device 10.

[0255] For those in Fig. 10A to Fig. 10C, except for the differences described above, can be referred to the description of the semiconductor device 10 shown in Fig. 4A to Fig. 4C. <Strukturbeispiel 7 der Halbleitervorrichtung>

[0256] Fig. 11A to Fig. 11C illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 11A is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 11B is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 11A, and Fig. 11C is a cross-sectional view along the dotted line A3-A4 in Fig. 11A.

[0257] The Fig. 11 A to Fig. The semiconductor device 10 shown in Figure 11C differs from that shown in Fig. 9A to Fig. 9C by forming the semiconductor layer 113a of the transistor 41 so as to fill a recessed portion above the semiconductor layer 113c of the transistor 43.

[0258] In the Fig. 11A to Fig. 11C, the semiconductor layer 113a of the transistor 41 is provided in a position in which the layer 114 is provided which is used in the transistor 43 of the semiconductor device 10 shown in Fig. 9A to Fig. 9C shown semiconductor device 10.

[0259] If the Fig. 11A to Fig. 11C has the structure described above, the manufacturing process can be made simpler than that of the semiconductor device 10 shown in Fig. 9A to Fig. 9C shown semiconductor device 10.

[0260] For those in Fig. 11A to Fig. 11C, except for the differences described above, can be referred to the description of the semiconductor device 10 shown in Fig. 4A to Fig. 4C. <Strukturbeispiel 8 der Halbleitervorrichtung>

[0261] Fig. 12A to Fig. 12C illustrate a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 12A is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 12B is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 12A, and Fig. 12C is a cross-sectional view along the dotted line A3-A4 in Fig. 12A.

[0262] The Fig. 12A to Fig. 12C is the same as the semiconductor device 10 shown in Fig. 10A to Fig. 10C in that the opening 126 reaching the conductive layer 111c is provided in the insulating layer 103c_1, the conductive layer 115c, the insulating layer 103a, and the conductive layer 112a. However, the opening 126 shown in Fig. 12A to Fig. 12C shown semiconductor device 10 of the in Fig. 10A to Fig. 10C in that the bottom surface of the conductive layer 115a of the transistor 41 is located below the conductive layer 115c of the transistor 43 (on the side of the conductive layer 111c).

[0263] In the Fig. 12A to Fig. In the semiconductor device 10 shown in FIG. 12C, the insulating layer 105c is provided in contact with the side surface of the insulating layer 103c_1, the side surface of the conductive layer 115c, the side surface of the insulating layer 103a, and the side surface of the conductive layer 112a on the opening 126 side. The semiconductor layer 113a is provided in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 105c, and the top surface of the conductive layer 111c. The insulating layer 105a is provided to cover the semiconductor layer 113a. Here, a recessed portion reflecting the shape of the opening 126 is formed above the semiconductor layer 113a and the insulating layer 105a. The conductive layer 115a is provided to fill the recessed portion.

[0264] If the Fig. 12A to Fig. 12C has the structure described above, a region located between the conductive layer 115a and the conductive layer 115c is formed in the semiconductor layer 113a. This region is a region to which both an electric field from the conductive layer 115a and an electric field from the conductive layer 115c are applied. Therefore, the structure shown in Fig. 12A to Fig. 12C may have a higher charge carrier controllability in the semiconductor layer 113a than that shown in Fig. 10A to Fig. Semiconductor device 10 shown in Figure 10C.

[0265] For those in Fig. 12A to Fig. 12C, except for the differences described above, can be referred to the description of the semiconductor device 10 shown in Fig. 4A to Fig. 4C.

[0266] The semiconductor device of one embodiment of the present invention may be as shown in Fig. 2B, Fig. 3B and Fig. 3C, a memory cell with a capacitor. A structural example of a semiconductor device with a capacitor, which is an embodiment of the present invention, will be described below. <Strukturbeispiel 9 der Halbleitervorrichtung>

[0267] Fig. 13A, Fig. 16A and Fig. 16B illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention. Fig. 13A is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 16A is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 13A, and Fig. 16B is a cross-sectional view taken along the dot-dash line A3-A4 in Fig. 13A.

[0268] The Fig. 13A, Fig. 16A and Fig. 16B comprises, in addition to the components of the semiconductor device 10 shown in Fig. 4A to Fig. 4C, the semiconductor device 10 includes a capacitor 51. The capacitor 51 is provided across the transistor 41 to overlap each other, and the transistor 42 is provided across the capacitor 51 to overlap each other.

[0269] The capacitor 51 includes a conductive layer 141, a conductive layer 143 and an insulating layer 135.

[0270] The conductive layer 143 serves as one electrode of the capacitor 51. The conductive layer 141 serves as the other electrode of the capacitor 51 and serves as the line 36. The insulating layer 135 serves as the dielectric layer of the capacitor 51. The conductive layer 141 serving as the line 36 includes a region extending in the X direction.

[0271] The conductive layer 141 includes an opening 123, and the insulating layer 135 and the conductive layer 143 are provided within the opening 123. Specifically, within the opening 123, the insulating layer 135 is provided to cover a side surface of the conductive layer 141, and the conductive layer 143 is provided further inside than the insulating layer 135. Consequently, the conductive layer 141 is provided to cover at least a portion of a side surface of the conductive layer 143, with the insulating layer 135 interposed therebetween. The insulating layer 135 includes, within the opening 123, for example, a region in contact with a side surface of the conductive layer 141 and a region in contact with the side surface of the conductive layer 143.

[0272] An insulating layer 133 is provided over the conductive layer 141. The conductive layer 141 and the insulating layer 133 may have the same shape in a plan view, and they both include the opening 123. For example, first, a conductive film that will become the conductive layer 141 and an insulating film that will become the insulating layer 133 are formed in this order, after which a pattern is formed by a photolithography method, and then the insulating film and the conductive film are processed by an etching method using the pattern, whereby the insulating layer 133 and the conductive layer 141 including the opening 123 can be formed.

[0273] Fig. 13A shows an example in which the shape of the opening 123 is quadrangular in a plan view. Although the shape of the opening 123 in the plan view of Fig. 13A is square, the shape of the opening 123 is not limited thereto and may be, for example, a rectangle, a rhombus, or a parallelogram in a plan view. Furthermore, the shape of the opening 123 in a plan view may be, for example, a triangle or a polygon with five or more corners. Fig. In the example illustrated in Figure 13A, the conductive layer 143 has a square top shape, like the opening 123; the conductive layer 143 may have a shape similar to any of the above-described top shapes that the opening 123 may have. Note that the top shape of the opening 123 may be different from the top shape of the conductive layer 143.

[0274] The insulating layer 135 is provided over the insulating layer 133. Specifically, the insulating layer 135 is provided to cover a top surface and a side surface of the insulating layer 133. The insulating layer 137 is provided over the insulating layer 135.

[0275] An opening 125 is provided in the insulating layer 107a, the insulating layer 131, the insulating layer 135, and the insulating layer 137. The opening 125 is provided to include an area overlapping with the opening 123. The conductive layer 143 is provided within the opening 125. By providing the conductive layer 143 within the opening 125, which reaches the conductive layer 115a, for example, the upper surface of the conductive layer 115a can be in contact with a lower surface of the conductive layer 143. Consequently, the conductive layer 115a serving as the gate electrode of the transistor 41 and the conductive layer 143 serving as one electrode of the capacitor 51 can be electrically connected to each other.

[0276] Here, if the insulating layer 133 is not provided over the conductive layer 141, a region where the thickness of the insulating layer 135 is small may be formed between the conductive layer 141 and the conductive layer 143 in the step of forming the opening 125. In other words, a region where the distance between the conductive layer 141 and the conductive layer 143 is short may be formed. In this case, for example, a short circuit may occur between the conductive layer 141 and the conductive layer 143. By providing the insulating layer 133 over the conductive layer 141, the formation of the region where the distance between the conductive layer 141 and the conductive layer 143 is short can be suppressed. Accordingly, the reliability of the memory cell 21 can be improved, and a highly reliable semiconductor device can be provided.Furthermore, a semiconductor device with high manufacturing yield and low cost can be provided. Note that the insulating layer 133 is not necessarily provided as long as, for example, a short circuit does not occur between the conductive layer 141 and the conductive layer 143. In this case, the manufacturing process of the semiconductor device can be simplified.

[0277] The top surface of the conductive layer 143 and a top surface of the insulating layer 137 have substantially the same height relative to the substrate surface. The conductive layer 111b, which serves as one of the source electrodes and the drain electrodes of the transistor 42, is provided over the conductive layer 143 such that it includes a region overlapping with the conductive layer 143.

[0278] The conductive layer 111b includes a region in contact with the conductive layer 143. For example, a bottom surface of the conductive layer 111b includes a region in contact with a top surface of the conductive layer 143. Therefore, the conductive layer 111b serving as one of the source electrode and the drain electrode of the transistor 42 and the conductive layer 143 serving as one electrode of the capacitor 51 can be electrically connected to each other. As described above, the conductive layer 143 is electrically connected to the conductive layer 115a serving as the gate electrode of the transistor 41. In this way, the gate electrode of the transistor 41, the one of the source electrode and the drain electrode of the transistor 42, and the one electrode of the capacitor 51 are electrically connected to each other.

[0279] The components of the capacitor contained in the memory cell are described below. [Components of the capacitor]

[0280] For the conductive layer 141 and the conductive layer 143, a single layer or stacked layers of any of the conductors described below in [Conductors] can be used. For example, a conductive material with high conductivity, such as tungsten, aluminum, or copper, can be used for the conductive layer 141 and the conductive layer 143. By using a conductive material with high conductivity in this way, the conductivity of the conductive layer 141 and the conductive layer 143 can be improved.

[0281] For the conductive layer 141 and the conductive layer 143, a single layer or stacked layers of the conductive material that is less likely to be oxidized, a conductive material having a function of suppressing oxygen diffusion, or the like is preferably used. For example, titanium nitride, indium tin oxide to which silicon is added, or the like can be used. Alternatively, for example, a structure in which titanium nitride is disposed over tungsten can be used. Alternatively, for example, a structure in which tungsten is disposed over first titanium nitride and second titanium nitride is disposed over the tungsten can be used. With such a structure, when an oxide insulator is used for the insulating layer 135, oxidation of the conductive layer 141 and the conductive layer 143 by the insulating layer 135 can be suppressed.By using an oxide insulator for the insulating layer 133, the conductive layer 141 can be suppressed from being oxidized by the insulating layer 133. A semiconductor with high electrical conductivity, typically polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide, can be used for the conductive layer 141 and the conductive layer 143.

[0282] For the insulating layer 135, one of the materials with high relative permittivity, that is, high-k materials, described below in [Insulator] can be used. Using such a high-k material for the insulating layer 135 allows the insulating layer 135 to be sufficiently thick to suppress leakage current and ensures a sufficiently high capacitance of the capacitor 51.

[0283] The insulating layer 135 preferably has a multilayer structure using an insulator comprising a high-k material. A multilayer structure comprising a high relative permittivity material (a high-k material) and a material having higher dielectric strength than the high-k material is preferably used. For example, an insulating film in which zirconia, alumina, and zirconia are arranged in this order can be used as the insulating layer 135. For example, an insulating film in which zirconia, alumina, zirconia, and alumina are stacked in this order can be used. As another example, an insulating film in which hafnium-zirconium oxide, alumina, hafnium-zirconium oxide, and alumina are stacked in this order can be used.The superposition of such an insulator with relatively high dielectric strength, such as aluminum oxide, can increase the dielectric strength and suppress the electrostatic breakdown of the capacitor 51.

[0284] Alternatively, a material capable of exhibiting ferroelectricity may be used for the insulating layer 135. Examples of the material capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrOx (X is a real number greater than 0). Examples of the material capable of exhibiting ferroelectricity also include a material in which an element J1 (here, the element J1 is one or more of zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to hafnium oxide. Here, the atomic ratio of hafnium to the element J1 can be appropriately adjusted; for example, the atomic ratio of hafnium to the element J1 is 1:1 or close to it.Examples of materials capable of exhibiting ferroelectricity also include materials in which a J2 element (here, J2 element is one or more of hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to zirconium oxide. The atomic ratio of zirconium to J2 element can be appropriately adjusted; for example, the atomic ratio of zirconium to J2 element is 1:1 or close to it. As materials capable of exhibiting ferroelectricity, piezoelectric ceramics having a perovskite structure, such as lead titanate (PbTiOx), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, can be used.

[0285] Examples of the material capable of exhibiting ferroelectricity also include a metal nitride containing an M1 element, an M2 element, and nitrogen. Here, the M1 element is one or more of aluminum, gallium, indium, and the like. The M2 element is one or more of boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. Note that the atomic ratio of the M1 element to the M2 element can be appropriately adjusted. A metal oxide containing the M1 element and nitrogen exhibits ferroelectricity in some cases even if the metal oxide does not contain the M2 element. Examples of the material capable of exhibiting ferroelectricity also include the above metal nitride to which an M3 element is added. Note that the M3 element is one or more of magnesium, calcium, strontium, zinc, cadmium, and the like.The atomic ratio between element M1, element M2 and element M3 can be adjusted appropriately.

[0286] Examples of the material that can exhibit ferroelectricity also include perovskite-type oxynitride, such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina-type structure.

[0287] Although metal oxides and metal nitrides are described above as examples, an embodiment of the present invention is not limited thereto. For example, a metal oxynitride in which nitrogen is added to one of the above metal oxides, a metal nitride oxide in which oxygen is added to one of the above metal nitrides, or the like can be used.

[0288] As a material capable of exhibiting ferroelectricity, for example, a mixture or compound containing a plurality of the materials listed above can be used. Alternatively, the insulating layer 135 may have a multilayer structure of a plurality of the materials listed above. Since the above-listed materials change their crystal structures (properties) as well as deposition conditions according to different processes, a material exhibiting ferroelectricity is referred to in this specification and the like not only as a ferroelectric, but also as a material capable of exhibiting ferroelectricity or a material exhibiting ferroelectricity.

[0289] A metal oxide containing hafnium and / or zirconium is preferred because the metal oxide can exhibit ferroelectricity even when processed into a thin film of a few nanometers. Here, the thickness of the insulating layer 135 can be less than or equal to 100 nm, preferably less than or equal to 50 nm, more preferably less than or equal to 20 nm, and even more preferably less than or equal to 10 nm (typically greater than or equal to 2 nm and less than or equal to 9 nm). For example, the thickness is preferably greater than or equal to 8 nm and less than or equal to 12 nm. Using the ferroelectric layer, which can have a small thickness, the capacitor 51 can be combined with a miniaturized semiconductor element, such as a transistor, to fabricate a semiconductor device.Note that in this specification and the like, the material capable of exhibiting ferroelectricity and processed into a layered form is sometimes referred to as a ferroelectric layer, metal oxide film, or metal nitride film. Furthermore, in this specification and the like, a device comprising such a ferroelectric layer, metal oxide film, or metal nitride film is sometimes referred to as a ferroelectric device.

[0290] A metal oxide containing hafnium and / or zirconium is preferred because the metal oxide can exhibit ferroelectricity even with a very small area. For example, a ferroelectric layer can exhibit ferroelectricity even with an area (occupied area) of less than or equal to 100 µm 2 , less than or equal to 10 µm 2 , less than or equal to 1 µm 2 or less than or equal to 0.1 µm2 in a plan view. Furthermore, even with an area of ​​less than or equal to 10000 nm 2 or less than or equal to 1000 nm 2 A ferroelectric layer can exhibit ferroelectricity in some cases. Using a ferroelectric layer with a small area can reduce the area occupied by the capacitor 51.

[0291] A ferroelectric material refers to an insulator having a property that causes internal polarization upon application of an external electric field and maintains the polarization even after the electric field is zeroed. Therefore, a non-volatile memory element can be formed using a capacitor comprising the material as a dielectric (hereinafter, such a capacitor is sometimes referred to as a ferroelectric capacitor). A non-volatile memory element comprising a ferroelectric capacitor is sometimes also referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one terminal of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor.Therefore, in the case of using a ferroelectric capacitor as the capacitor 51, the semiconductor device described in this embodiment serves as a ferroelectric memory.

[0292] It should be noted that ferroelectricity is exhibited by the dislocation of oxygen or nitrogen of a crystal contained in a ferroelectric layer due to an external electric field. Ferroelectricity is presumably exhibited depending on a crystal structure of a crystal contained in a ferroelectric layer. Therefore, in order for the insulating layer 135 to exhibit ferroelectricity, the insulating layer 135 must include a crystal. It is particularly preferable that the insulating layer 135 include a crystal having an orthorhombic crystal structure in order to exhibit ferroelectricity. A crystal contained in the insulating layer 135 may have one or more of crystal structures selected from cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal structures. Alternatively, the insulating layer 135 may have an amorphous structure.In this case, the insulating layer 135 may have a composite structure including an amorphous structure and a crystal structure.

[0293] The insulating layer 133 preferably has a low relative permittivity. In this case, parasitic capacitance between lines can be reduced. For the insulating layer 133, a single layer or stacked layers of any of the insulators, each containing a low relative permittivity material described below in [Insulator], can be used. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0294] Although in Fig. 16A and Fig. 16B, the insulating layer 133 has a single-layer structure, the present invention is not limited thereto. The insulating layer 133 may have a multi-layer structure. <Strukturbeispiel 10 der Halbleitervorrichtung>

[0295] Fig. 13B, Fig. 17A and Fig. 17B illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 13B is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 17A is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 13B, and Fig. 17B is a cross-sectional view taken along the dot-dash line A3-A4 in Fig. 13B.

[0296] The Fig. 13B, Fig. 17A and Fig. 17B has a structure in which the semiconductor device 10 shown in Fig. 7A to Fig. 7C and the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B shown semiconductor device 10 can be combined with each other.

[0297] In particular, the Fig. 13B, Fig. 17A and Fig. 17B has a structure in which the arrangement of the transistor 43, the transistor 41 and the transistor 42 shown in the Fig. 7A to Fig. 7C, the capacitor 51 shown in the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B, is provided between the transistor 41 and the transistor 42.

[0298] For those in Fig. 13B, Fig. 17A and Fig. 17B except for the points described above, reference may be made to the description of the semiconductor device 10 shown in Fig. 7A to Fig. 7C and to the description of the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B illustrated semiconductor device 10. <Strukturbeispiel 11 der Halbleitervorrichtung>

[0299] Fig. 13C, Fig. 18A and Fig. 18B illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 13C is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 18A is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 13C, and Fig. 18B is a cross-sectional view taken along the dot-dash line A3-A4 in Fig. 13C.

[0300] The Fig. 13C, Fig. 18A and Fig. 18B has a structure in which the semiconductor device 10 shown in Fig. 8A to Fig. 8C and the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B shown semiconductor device 10 can be combined with each other.

[0301] In particular, the Fig. 13C, Fig. 18A and Fig. 18B has a structure in which the arrangement of the transistor 43, the transistor 41 and the transistor 42 shown in the Fig. 8A to Fig. 8C, the capacitor 51 shown in the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B, is provided between the transistor 41 and the transistor 42.

[0302] For those in Fig. 13C, Fig. 18A and Fig. 18B except for the points described above, reference may be made to the description of the semiconductor device 10 shown in Fig. 8A to Fig. 8C and to the description of the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B illustrated semiconductor device 10. <Strukturbeispiel 12 der Halbleitervorrichtung>

[0303] Fig. 14A, Fig. 19A and Fig. 19B illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 14A is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 19A is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 14A, and Fig. 19B is a cross-sectional view taken along the dotted line A3-A4 in Fig. 14A.

[0304] The Fig. 14A, Fig. 19A and Fig. 19B has a structure in which the semiconductor device 10 shown in Fig. 9A to Fig. 9C and the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B shown semiconductor device 10 can be combined with each other.

[0305] In particular, the Fig. 14A, Fig. 19A and Fig. 19B has a structure in which the arrangement of the transistor 43, the transistor 41 and the transistor 42 shown in the Fig. 9A to Fig. 9C, the capacitor 51 shown in the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B, is provided between the transistor 41 and the transistor 42.

[0306] For those in Fig. 14A, Fig. 19A and Fig. 19B except for the points described above, reference may be made to the description of the semiconductor device 10 shown in Fig. 9A to Fig. 9C and to the description of the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B illustrated semiconductor device 10. <Strukturbeispiel 13 der Halbleitervorrichtung>

[0307] Fig. 14B, Fig. 20A and Fig. 20B illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 14B is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 20A is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 14B, and Fig. 20B is a cross-sectional view taken along the dot-dash line A3-A4 in Fig. 14B.

[0308] The Fig. 14B, Fig. 20A and Fig. 20B has a structure in which the semiconductor device 10 shown in Fig. 10A to Fig. 10C and the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B shown semiconductor device 10 can be combined with each other.

[0309] In particular, the Fig. 14B, Fig. 20A and Fig. 20B has a structure in which the arrangement of the transistor 43, the transistor 41 and the transistor 42 shown in the Fig. 10A to Fig. 10C, the capacitor 51 shown in the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B, is provided between the transistor 41 and the transistor 42.

[0310] For those in Fig. 14B, Fig. 20A and Fig. 20B except for the points described above, reference may be made to the description of the semiconductor device 10 shown in Fig. 10A to Fig. 10C and to the description of the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B illustrated semiconductor device 10. <Strukturbeispiel 14 der Halbleitervorrichtung>

[0311] Fig. 14C, Fig. 21A and Fig. 21B illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 14C is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 21A is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 14C, and Fig. 21B is a cross-sectional view taken along the dot-dash line A3-A4 in Fig. 14C.

[0312] The Fig. 14C, Fig. 21Aand Fig. 21B has a structure in which the semiconductor device 10 shown in Fig. 11A to Fig. 11C and the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B shown semiconductor device 10 can be combined with each other.

[0313] In particular, the Fig. 14C, Fig. 21A and Fig. 21B has a structure in which the arrangement of the transistor 43, the transistor 41 and the transistor 42 shown in the Fig. 11A to Fig. 11C, the capacitor 51 shown in the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B, is provided between the transistor 41 and the transistor 42.

[0314] For those in Fig. 14C, Fig. 21A and Fig. 21B except for the points described above, reference may be made to the description of the semiconductor device 10 shown in Fig. 11A to Fig. 11C and to the description of the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B illustrated semiconductor device 10. <Strukturbeispiel 15 der Halbleitervorrichtung>

[0315] Fig. 15A, Fig. 22A and Fig. 22B illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 15A is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 22A is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 15A, and Fig. 22B is a cross-sectional view taken along the dot-dash line A3-A4 in Fig. 15A.

[0316] The Fig. 15A, Fig. 22A and Fig. 22B has a structure in which the semiconductor device 10 shown in Fig. 12A to Fig. 12C and the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B shown semiconductor device 10 can be combined with each other.

[0317] In particular, the Fig. 15A, Fig. 22A and Fig. 22B has a structure in which the arrangement of the transistor 43, the transistor 41 and the transistor 42 shown in the Fig. 12A to Fig. 12C, the capacitor 51 shown in the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B, is provided between the transistor 41 and the transistor 42.

[0318] For those in Fig. 15A, Fig. 22A and Fig. 22B except for the points described above, reference may be made to the description of the semiconductor device 10 shown in Fig. 12A to Fig. 12C and to the description of the semiconductor device 10 shown in Fig. 13A, Fig. 16A and Fig. 16B illustrated semiconductor device 10. <Strukturbeispiel 16 der Halbleitervorrichtung>

[0319] Fig. 15B, Fig. 23A and Fig. 23B illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 15B is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 23A is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 15B, and Fig. 23B is a cross-sectional view taken along the dot-dash line A3-A4 in Fig. 15B.

[0320] The Fig. 15B, Fig. 23A and Fig. 23B includes the transistor 43, the transistor 41, and the transistor 42 (a 3Tr0C memory cell structure).

[0321] In the Fig. 15B, Fig. 23A and Fig. In the semiconductor device 10 shown in FIG. 23B, the insulating layer 103c_1, the conductive layer 115c, the insulating layer 103a, the conductive layer 112a, the insulating layer 131, and the conductive layer 141 are provided in this order over the insulating layer 101 and the conductive layer 111c, and an opening 120 reaching the conductive layer 111c is provided in these layers. The insulating layer 105c is provided in contact with the side surface of the insulating layer 103c_1, the side surface of the conductive layer 115c, and the side surface of the insulating layer 103a on the opening 120 side. The semiconductor layer 113a is provided in contact with a top surface of the conductive layer 141, the side surface of the conductive layer 141 in the opening 120, a side surface of the insulating layer 131, the side surface of the conductive layer 112a, the side surface of the insulating layer 105c, and the top surface of the conductive layer 111c.The insulating layer 105a is provided to cover the semiconductor layer 113a. Here, a recessed portion reflecting the shape of the opening 120 is formed over the semiconductor layer 113a and the insulating layer 105a. The conductive layer 115a is provided to fill the recessed portion.

[0322] At the Fig. 15B, Fig. 23A and Fig. In the semiconductor device 10 shown in Figure 23B, the semiconductor layer 113a serves as both the semiconductor layer of the transistor 43 and the semiconductor layer of the transistor 41. The insulating layer 105a serves as both the gate insulating layer of the transistor 43 and the gate insulating layer of the transistor 41. The conductive layer 115a serves as both the gate electrode of the transistor 43 and the gate electrode of the transistor 41. The conductive layer 112a serves as both the other of the source electrode and the drain electrode of the transistor 43 and one of the source electrode and the drain electrode of the transistor 41. The conductive layer 141 serves as the other of the source electrode and the drain electrode of the transistor 41.

[0323] In the Fig. 16A, Fig. 16B and the like, the conductive layer 141 serves as the other electrode of the capacitor 51. The Fig. 15B, Fig. 23A and Fig. However, the semiconductor device 10 shown in Fig. 23B does not include the capacitor 51. In the case of the memory cell structure without a capacitor, a conductive layer that can be used as the other electrode of a capacitor may be used as part of a conductive layer of a transistor.

[0324] In transistor 43, in addition to insulating layer 105a, insulating layer 105c also serves as a gate insulating layer. In addition to conductive layer 115a, conductive layer 115c also serves as a gate electrode. This means that transistor 43 includes two gate electrodes. Therefore, charge carrier controllability in semiconductor layer 113a can be increased compared to the structure with only one gate electrode.

[0325] As described above, many layers such as the semiconductor layer 113a, the insulating layer 105a, and the conductive layer 115a can be shared by the transistor 43 and the transistor 41, therefore, the manufacturing process of the semiconductor device can be simplified. <Strukturbeispiel 17 der Halbleitervorrichtung>

[0326] Fig. 15C, Fig. 24A and Fig. 24B illustrates a structural example of the semiconductor device 10 of an embodiment of the present invention, which is different from the structures described above. Fig. 15C is a plan view illustrating a structural example of a part of the semiconductor device 10. Fig. 24A is a cross-sectional view taken along the dashed line A1-A2 in Fig. 15C, and Fig. 24B is a cross-sectional view taken along the dot-dash line A3-A4 in Fig. 15C.

[0327] The Fig. 15C, Fig. 24A and Fig. 24B differs from the semiconductor device 10 shown in Fig. 16A and Fig. 16B, in that the conductive layer 112a serving as the other of the source electrode and the drain electrode of the transistor 41 and the conductive layer 141 having a function of the other electrode of the capacitor 51 are electrically connected to each other.

[0328] In the Fig. 15C, Fig. 24A and Fig. In the semiconductor device 10 shown in Fig. 24B, the top surface of the conductive layer 115a, the uppermost surface of the insulating layer 105a, the uppermost surface of the semiconductor layer 113a, the top surface of the conductive layer 112a and the uppermost surface of the insulating layer 107a included in the transistor 41, and the top surface of the insulating layer 131 have substantially the same height with respect to the substrate surface. On the other hand, the bottom surface of the conductive layer 143, the lowermost surface of the insulating layer 135, and a bottom surface of the conductive layer 141 included in the capacitor 51 have substantially the same height with respect to the substrate surface. The top surface of the conductive layer 112a and the bottom surface of the conductive layer 141 are provided to include a region where they are in contact with each other.

[0329] If the Fig. 15C, Fig. 24A and Fig. When the semiconductor device 10 shown in Fig. 24B has the above-described structure, potentials of the same level can be supplied to the conductive layer 112a and the conductive layer 141. As described above, the conductive layer 112a serves as wiring 35, and the conductive layer 141 serves as wiring 36. Therefore, when the semiconductor device 10 has the above-described structure, the number of wirings can be reduced, and the manufacturing process can be simplified.

[0330] For those in Fig. 15C, Fig. 24A and Fig. 24B, except for the differences described above, can be referred to the description of the semiconductor device 10 shown in Fig. 16A and Fig. 16B illustrated semiconductor device 10. <Strukturbeispiel einer Anzeigeeinrichtung>

[0331] An embodiment of the present invention can also be applied to a display device. Fig. 25A is a block diagram illustrating a structural example of a display device 70, which is the display device of one embodiment of the present invention. The display device 70 includes a display section 80, a scanning line driver circuit 71, a signal line driver circuit 73, a power supply circuit 75, and a reference potential generation circuit 77. The display section 80 includes a plurality of pixels 81 arranged in a matrix. Note that the power supply circuit 75 may be provided outside the display device 70.

[0332] The scanning line driver circuit 71 is electrically connected to the pixels 81 via the lines 31 (a line 31a, a line 31b, and a line 31c). The lines 31 extend, for example, in the row direction of the matrix.

[0333] The signal line driver circuit 73 is electrically connected to the pixels 81 via the lines 33. The lines 33 extend, for example, in the column direction of the matrix.

[0334] The power supply circuit 75 is electrically connected to the pixels 81 via lines 35. The lines 35 extend, for example, in the row direction of the matrix.

[0335] The reference potential generation circuit 77 is electrically connected to the pixels 81 via lines 38. The lines 38 extend, for example, in the column direction of the matrix.

[0336] Pixel 81 includes a display element (also referred to as a display device) capable of displaying an image on display portion 80. For example, a light-emitting element (also referred to as a light-emitting device) can be used as the display element, and in particular, an organic EL element can be used. A liquid crystal element (also referred to as a liquid crystal device) can also be used as the display element.

[0337] The scanning line driver circuit 71 has, for example, a function of selecting the pixel 81 to which image data is to be written, line by line. Specifically, the scanning line driver circuit 71 can select the pixel 81 to which image data is to be written by outputting a signal to the wiring 31. Here, the scanning line driver circuit 71 can select all the pixels 81 by, for example, outputting the signal to the wiring 31 in the first line, outputting the signal to the wiring 31 in the second line, and sequentially outputting the signals to the wiring 31 from the third line to the last line. Therefore, the signal output from the scanning line driver circuit 71 to the wiring 31 is a scanning signal, and the wiring 31 provided in the display device 70 can be referred to as a scanning line.

[0338] The signal line driver circuit 73 has a function of generating image data. The image data is supplied to the pixel 81 via the line 33. For example, image data can be written to all pixels 81 contained in a row selected by the scanning line driver circuit 71. Here, the image data can be represented as a signal (image signal). The line 33 provided in the display device 70 can be referred to as a signal line.

[0339] The power supply circuit 75 has a function of generating a power supply potential and supplying it to the wiring 35. The power supply circuit 75 has a function of generating, for example, a high power supply potential (hereinafter also referred to simply as "high potential" or "VDD") and supplying it to the wiring 35. The power supply circuit 75 may have a function of generating a low power supply potential (hereinafter also referred to simply as "low potential" or "VSS"). As described above, the wiring 35 serves as a power supply line.

[0340] The reference potential generation circuit 77 has a function of generating a reference potential and supplying it to the wiring 38. Since the potential of the wiring 38 is a reference potential, the wiring 38 can be referred to as a reference potential line. Note that the electrical characteristics of each pixel can be output to the reference potential generation circuit 77 outside the pixel via the wiring 38. That is, the reference potential generation circuit 77 can have a function of detecting electrical characteristics of each pixel. The deterioration, fluctuations, and the like of elements (e.g., transistors or light-emitting elements) in each pixel can be detected by reading the electrical characteristics of each pixel in the reference potential generation circuit 77.Furthermore, the deterioration and fluctuations in image quality can be corrected by feeding the read characteristics back to a video signal.

[0341] Fig. 25B is a plan view illustrating a structural example of pixel 81. Pixel 81 may include a plurality of subpixels 83. Fig. 25B illustrates an example in which the pixel 81 includes a subpixel 83R, a subpixel 83G, and a subpixel 83B as subpixel 83. Here, when the pixel 81 includes a light-emitting element as a display element, for example, a top surface shape of the Fig. 25B shows the top surface shape of a light-emitting region of the light-emitting element. Although in Fig. 25B, subpixel 83R, subpixel 83G, and subpixel 83B have the same or substantially the same aperture ratio (also referred to as a size or size of a light-emitting area), an embodiment of the present invention is not limited to this. The aperture ratio of each of subpixel 83R, subpixel 83G, and subpixel 83B can be appropriately determined. Subpixel 83R, subpixel 83G, and subpixel 83B may have different aperture ratios, or two or more of subpixels 83R, 83G, and 83B may have the same or substantially the same aperture ratio.

[0342] In the Fig. In the pixel 81 shown in Figure 25B, a stripe array is used as the arrangement method of the subpixels 83. Examples of the arrangement of the subpixels 83 include an S-stripe array, a matrix array, a delta array, a Bayer array, or a PenTile array.

[0343] Subpixels 83R, 83G, and 83B emit light of different colors. For example, subpixels 83R, 83G, and 83B may have three colors of red (R), green (G), and blue (B), or three colors of yellow (Y), cyan (C), and magenta (M). Furthermore, four or more subpixels 83 may be provided in pixel 81. For example, pixel 81 may include subpixels of four colors of R, G, B, and white (W). In display device 70, display section 80 may display a full-color image by including the plurality of subpixels 83 emitting light of different colors in pixel 81. For example, pixel 81 may include subpixels of R, G, B, and infrared (IR) light.

[0344] Note that a sensor may be provided in the display portion 80, for example, in the pixel 81. For example, the display portion 80 may have a fingerprint sensor function. For example, the display portion 80 may have an optical fingerprint sensor or an ultrasonic fingerprint sensor function.

[0345] Fig. 25C is a circuit diagram showing a structural example of the subpixel 83 used in the Fig. 25A. The pixel 81 shown in Fig. The subpixel 83 shown in Figure 25C includes a pixel circuit 90 and a light-emitting element 91.

[0346] The pixel circuit 90 includes the transistor 41, the transistor 42, the transistor 43, a transistor 53, the capacitor 51, and a capacitor 58. That is, the pixel circuit 90 is a 4Tr2C pixel circuit.

[0347] In the pixel circuit 90, one of the source and drain terminals of the transistor 42 is electrically connected to the wiring 33. The other of the source and drain terminals of the transistor 42 are electrically connected to one electrode of the capacitor 51 and the gate of the transistor 41. The gate of the transistor 42 is electrically connected to the wiring 31a. One of the source and drain terminals of the transistor 41 is electrically connected to one of the source and drain terminals of the transistor 43. The other of the source and drain terminals of the transistor 43 is electrically connected to the wiring 35. The gate of the transistor 43 is electrically connected to the wiring 31c. One electrode of the capacitor 58 is electrically connected to the other of the source and drain terminals of the transistor 41, one of the source and drain terminals of the transistor 53, the other electrode of the capacitor 51, and one electrode of the light-emitting element 91.The other electrode of capacitor 58 is electrically connected to line 35. The other terminal of the source and drain of transistor 53 is electrically connected to line 38. A gate of transistor 53 is electrically connected to line 31b. The other electrode of light-emitting element 91 is electrically connected to a line 37.

[0348] The transistor 43 has a function of a switch and has a function of controlling the conducting / non-conducting state between the wiring 35 and one of the source and drain of the transistor 41 based on the potential of the wiring 31c.

[0349] When transistor 43 is turned on, a current with a magnitude corresponding to the gate potential of transistor 41 flows, for example, from wiring 35 toward wiring 37. Consequently, light-emitting element 91 emits light with a luminance corresponding to the gate potential of transistor 41. On the other hand, when transistor 43 is turned off, current can be prevented from flowing through light-emitting element 91, which can allow light-emitting element 91 to not emit light.

[0350] OS transistors are preferably used as transistors 41, 42, and 43. For example, an OS transistor has higher field-effect mobility than a transistor made of amorphous silicon. Therefore, by using OS transistors as transistors 41 and 42, the display device 70 can be operated at high speed.

[0351] As described above, an OS transistor has a very low off-state current. Therefore, by using an OS transistor as transistor 42, the charge accumulated in capacitor 51 can be retained for a long period. Therefore, image data written to subpixel 83 can be retained for a long period, and accordingly, the frequency of the update operation (rewriting image data to subpixel 83) can be reduced. Therefore, the power consumption of display device 70 can be reduced.

[0352] To increase the emission luminance of the light-emitting element 91, it is necessary to increase the amount of current flowing through the light-emitting element 91. To increase the amount of current, it is necessary to increase the source-drain voltage of the transistor 41, which is a driving transistor. An OS transistor has a higher withstand voltage between a source and a drain than an Si transistor; thus, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the transistor 41, the amount of current flowing through the light-emitting element 91 can be increased, resulting in an increase in the emission luminance of the light-emitting element 91.

[0353] For example, an organic light-emitting diode (OLED) or a quantum-dot light-emitting diode (QLED) is preferably used as the light-emitting element 91. Examples of a light-emitting substance contained in the light-emitting element 91 include a substance exhibiting fluorescence (a fluorescent material), a substance exhibiting phosphorescence (a phosphorescent material), a substance exhibiting thermally activated delayed fluorescence (a thermally activated delayed fluorescence (TADF) material), and an inorganic compound (such as a quantum dot material). Alternatively, an LED (light-emitting diode) such as a micro-LED may be used as the light-emitting element 91. <Strukturbeispiel 18 der Halbleitervorrichtung>

[0354] A structural example of the plurality of memory cells 21 will be described below. Specifically, a structural example of the memory cells 21 in four rows and four columns will be described using plan views. Note that some reference numerals are omitted in the plan views in some cases.

[0355] Fig. 26A is a plan view showing a structural example in which the Fig. 4A shown memory cells 21 are arranged in a matrix. Fig. 26B is a plan view in which the transistor 42 and the transistor 43 are shown in Fig. 26A are omitted.

[0356] As in Fig. 26A and Fig. As shown in Fig. 26B, the conductive layer 111c serving as wiring 33R and the conductive layer 112a serving as wiring 35 each include a region extending in the Y direction and are shared by the memory cells 21 arranged in the Y direction. In other words, the memory cells 21 in the same column share the same conductive layer 111c and the same conductive layer 112a. Consequently, when reading data held in the memory cell 21, a current can be prevented from flowing from the plurality of wirings 33R serving as a read bit line to a wiring 35 serving as a power supply line. Accordingly, the amount of current flowing through the wiring 35 can be reduced. According to Ohm's law, the voltage drop ΔV of a wiring is a product of the wiring resistance R and the current I (ΔV = R × I).Therefore, by reducing the amount of current flowing through the line 35, a reduction in the potential supplied as the power supply potential can be achieved, particularly, for example, in the memory cell 21 having a long line pitch from that shown in . Fig. 1A. This can prevent, for example, the data held in the memory cell 21 from being read incorrectly. Therefore, a memory cell and a semiconductor device having high reading accuracy can be provided.

[0357] In the Fig. In the example shown in Fig. 26A, the conductive layer 115b serving as wiring 31W includes a region extending in the X direction and is shared by the memory cells 21 arranged in the X direction. That is, the memory cells 21 in the same row share the same conductive layer 115b. Furthermore, the conductive layer 112b serving as wiring 33W includes a region extending in the Y direction and is shared by the memory cells 21 arranged in the Y direction. That is, the memory cells 21 in the same column share the same conductive layer 112b.

[0358] Fig. 27 and Fig. 28 are cross-sectional views of the memory cells 21 shown in plan view in Fig. 26A and are arranged in four rows and four columns. Fig. 27 is a cross-sectional view along the XZ plane, and Fig. 28 is a cross-sectional view along the YZ plane. As shown in the plan view in Fig. 26A and the cross-sectional views in Fig. 27 and Fig. As shown in Figure 28, the semiconductor device of one embodiment of the present invention may have a structure in which the memory cells 21, each comprising three stacked transistors in each of which the source electrode and the drain electrode are provided at different heights with respect to the substrate surface, are arranged in the XY plane at high density. Therefore, the area occupied by each memory cell in a plan view can be reduced, and furthermore, a semiconductor device in which a plurality of memory cells are highly integrated can be achieved.

[0359] As described below in Fig. 57 and the like, the semiconductor device of one embodiment of the present invention may have a structure in which the memory cells 21 are stacked not only in the XY plane but also in the Z direction. With such a structure, the semiconductor layer device can be more highly integrated.

[0360] Fig. 29A and Fig. 29B represent a modification example of the Fig. 26A or Fig. 26B and illustrate an example in which the conductive layer 112a serving as the wiring 35 is shared by the memory cells 21 in two adjacent columns. When the memory cells 21 in a plurality of columns share the conductive layer 112a, the memory cells 21 can be arranged at a high density.

[0361] Fig. 30A and Fig. 30B represent a modification example of the Fig. 26A or Fig. 26B, and the conductive layer 112a serving as the line 35, which is the power supply line, includes a portion extending in the X direction and a portion extending in the Y direction. The conductive layer 112a includes the opening 121a in a region where the portion extending in the X direction and the portion extending in the Y direction intersect each other. With such a shape of the conductive layer 112a, the line resistance of the conductive layer 112a can be lower than, for example, that of the Fig. 26A and Fig. 26B. In contrast, in the structure shown in Fig. 30A and Fig. 30B, for example, the conductive layers 112a included in all memory cells 21 are electrically connected to each other. Therefore, when reading data held in the memory cell 21, a current flows, for example, from all lines 33R toward a conductive layer 112a. It should be noted that in the example shown in Fig. 30B, the conductive layer 112a comprises an opening 122 which is surrounded by four memory cells 21.

[0362] Fig. 31A and Fig. 31B represent a modification example of the Fig. 30A or Fig. 30B and illustrate an example in which the conductive layer 112a does not include the opening 122. In the structure shown in Fig. 31A and Fig. 31B, in the memory section in which the memory cells 21 are arranged in a matrix, the shape of the conductive layer 112a may be square, and the opening 121a may be provided in the square conductive layer 112a.

[0363] Fig. 32A and Fig. 32B represent a modification example of the Fig. 26A or Fig. 26B and illustrate an example in which the conductive layer 112a serving as the line 35 includes a region extending in the X direction and is shared by the memory cells 21 arranged in the X direction. That is, in the structure shown in Fig. 32A and Fig. 32B, the memory cells 21 in the same row share the same conductive layer 112a.

[0364] Fig. 33A and Fig. 33B represent a modification example of the Fig. 32A or Fig. 32B and illustrate an example in which the conductive layer 112a is shared by the memory cells 21 in two adjacent rows. When the memory cells 21 in a plurality of rows share the conductive layer 112a, the memory cells 21 can be arranged at a high density. <Materialien für eine Halbleitervorrichtung>

[0365] Materials that can be used for a semiconductor device are described below. [Substrate]

[0366] As the substrate over which the transistor 41, the transistor 42, the transistor 43, and the capacitor 51 are formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttrium-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. A semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, such as a silicon-on-insulator (SOI) substrate or the like, is used.Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Other examples include a substrate containing a metal nitride and a substrate containing a metal oxide. Other examples include an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator. Alternatively, any of these substrates over which an element is provided may be used. [Insulator]

[0367] Examples of an insulator include an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, and an insulating metal nitride oxide.

[0368] With further miniaturization and higher integration of a transistor, for example, a problem such as leakage current may arise due to a thinned gate insulating layer. If a high-k material is used for the insulator serving as the gate insulating layer, the voltage at the time of transistor operation can be reduced while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator serving as the gate insulating layer can be reduced. In contrast, if a low relative permittivity material is used for the insulator serving as the interlayer insulating layer, the parasitic capacitance formed between lines can be reduced. Therefore, a material is preferably selected depending on the function of an insulator.It should be noted that a material with low relative permittivity is a material with high dielectric strength.

[0369] Examples of a high relative permittivity material (a high-k material) include alumina, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0370] Examples of a material with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (e.g., nylon and aramid), polyimide, polycarbonate, and acrylic. Other examples of an inorganic insulating material with low relative permittivity include silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added. Another example is porous silicon oxide. Note that the silicon oxide listed above may contain nitrogen. Silicon oxide can be formed, for example, using organosilane such as tetraethoxysilane (TEOS).

[0371] A transistor containing a metal oxide can exhibit stable electrical properties when enclosed in an insulator having a function of suppressing the passage of impurities and oxygen. The insulator having a function of suppressing the passage of impurities and oxygen can, for example, have a single-layer structure or a multi-layer structure made of an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. As the insulator having a function of suppressing the passage of impurities and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such asAluminum nitride, silicon nitride oxide or silicon nitride can be used.

[0372] An insulator that is in contact with a semiconductor layer or provided near the semiconductor layer, such as a gate insulating layer, preferably includes an excess oxygen region. For example, if an insulator with an excess oxygen region is in contact with a semiconductor layer or provided near the semiconductor layer, the number of oxygen vacancies in the semiconductor layer can be reduced. Examples of an insulator in which an excess oxygen region is easily formed include silicon oxide, silicon oxynitride, and porous silicon oxide.

[0373] Examples of the insulator with an oxygen barrier property include an oxide containing aluminum and / or hafnium, an oxide containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of the oxide containing aluminum and / or hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate).

[0374] Examples of an insulator with a hydrogen barrier property include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride and silicon nitride oxide.

[0375] An insulator with a barrier property against oxygen and an insulator with a barrier property against hydrogen can each be regarded as an insulator with a barrier property against oxygen and / or hydrogen.

[0376] Examples of an insulator with a hydrogen capture or fixation function include an oxide containing magnesium and an oxide containing aluminum and / or hafnium. These oxides each preferably have an amorphous structure. In an oxide with an amorphous structure, an oxygen atom has a dangling bond, and in some cases, the oxide has a hydrogen capture or fixation function with the dangling bond. Although these metal oxides preferably have an amorphous structure, a crystal region may be partially formed.

[0377] It should be noted that in this specification and the like, an insulating barrier film refers to an insulating film that has a barrier property. A barrier property refers to a property that hardly allows diffusion of a target substance (also referred to as a property that hardly allows passage of a target substance, low permeability of a target substance, or function of suppressing diffusion of a target substance). It should be noted that a function of capturing or fixing (also referred to as gettering) a target substance can be reformulated as a barrier property. It should be noted that hydrogen described as a target substance may include at least one of a hydrogen atom, a hydrogen molecule, a water molecule, a substance that bonds to hydrogen, such as OH. -, and the like. Unless otherwise specified, an impurity described as a target substance refers to an impurity in a channel formation region or a semiconductor layer, and refers, for example, to at least one of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, or NO2), a copper atom, and the like. Oxygen described as a target substance refers, for example, to at least one of an oxygen atom, an oxygen molecule, and the like. Specifically, an oxygen barrier property refers to a property that hardly allows diffusion of at least one of an oxygen atom, an oxygen molecule, and the like. [Director]

[0378] For the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like. As the alloy containing any of the above metal elements, a nitride of the alloy or an oxide of the alloy can be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like.A semiconductor with high electrical conductivity, typically polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0379] A conductive material containing nitrogen, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing ruthenium, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum, a conductive material containing oxygen, such as ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, or a material containing a metal element such as titanium, tantalum, or ruthenium, is preferred because it is a conductive material that is not easily oxidized, a conductive material with a function of suppressing diffusion of oxygen, or a material that maintains conductivity even after absorbing oxygen.Examples of the conductive material containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide with silicon added, indium zinc oxide, indium zinc oxide containing tungsten oxide, and the like. In this specification and the like, a conductive material containing oxygen may be referred to as an oxide conductor.

[0380] Furthermore, a conductive material containing tungsten, copper or aluminum as the main component is preferred because it has high conductivity.

[0381] Conductors formed using any of the above materials can be stacked. For example, a multilayer structure combining a material containing the above metal element and an oxygen-containing conductive material may be used. Alternatively, a multilayer structure combining a material containing the above metal element and a nitrogen-containing conductive material may be used. Alternatively, a multilayer structure combining a material containing the above metal element, an oxygen-containing conductive material, and a nitrogen-containing conductive material may also be used.

[0382] In the case where a metal oxide is used for the channel formation region of the transistor, a multilayer structure in which a material containing the above metal element and an oxygen-containing conductive material are combined is preferably used for the conductor serving as the gate electrode. In this case, the oxygen-containing conductive material is preferably provided on the channel formation region side. When the oxygen-containing conductive material is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0383] In particular, a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed is preferably used for the conductor serving as the gate electrode. A conductive material containing the above metal element and nitrogen may be used. For example, a nitrogen-containing conductive material such as titanium nitride or tantalum nitride may be used. One or more of an indium tin oxide, an indium oxide containing tungsten oxide, an indium zinc oxide containing tungsten oxide, an indium oxide containing titanium oxide, an indium tin oxide containing titanium oxide, an indium zinc oxide, and an indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used.By using such a material, hydrogen contained in the metal oxide in which the channel is formed can be trapped in some cases. Alternatively, hydrogen entering from a surrounding insulator or the like can be trapped in some cases. [metal oxide]

[0384] In some cases, a metal oxide exhibits a lattice defect. Examples of lattice defects include point defects such as atomic vacancies and exotic atoms, linear defects such as dislocations, surface defects such as crystal grain boundaries, and bulk defects such as voids. Examples of factors that can cause a lattice defect include a variation in the proportion of constituent elements (an excess or deficiency of constituent atoms) and impurities.

[0385] When a metal oxide is used for a semiconductor layer of a transistor, a lattice defect in the metal oxide could cause carrier generation, trapping, or the like. Therefore, if a metal oxide with a large number of lattice defects is used for a semiconductor layer of a transistor, the electrical properties of the transistor could be unstable. Therefore, a metal oxide used for a semiconductor layer of a transistor preferably has a small number of lattice defects.

[0386] Electrical properties of a transistor in which a metal oxide is used for its semiconductor layer are particularly affected when oxygen vacancies (V O ) and impurities in the metal oxide present in a channel formation region, and its reliability may be deteriorated. In some cases, hydrogen forms around the oxygen vacancies VO H and generates an electron serving as a charge carrier. Therefore, when the metal oxide in the channel formation region contains oxygen vacancies, the transistor is likely to exhibit self-conducting properties (properties with which a channel exists even when no voltage is applied to a gate electrode and a current flows through the transistor). Therefore, the oxygen vacancies and impurities in the metal oxide in the channel formation region are preferably reduced as much as possible. In other words, it is preferable that the metal oxide in the channel formation region has a reduced charge carrier concentration and is i-type (intrinsic) or substantially i-type.

[0387] The type of lattice defect likely to be present in a metal oxide and the number of lattice defects present vary depending on the structure of the metal oxide, a method of forming the metal oxide, or the like.

[0388] Metal oxide structures are classified into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include a CAAC structure, a polycrystalline structure, an nc structure, an amorphous-like (a-like) structure, and an amorphous structure. An a-like structure is intermediate between an nc structure and an amorphous structure.

[0389] A metal oxide with an α-like structure and a metal oxide with an amorphous structure each contain a void or a low-density region. This means that a metal oxide with an α-like structure and a metal oxide with an amorphous structure each have lower crystallinity than a metal oxide with an nc structure and a metal oxide with a CAAC structure. Furthermore, a metal oxide with an α-like structure has a higher hydrogen concentration in the metal oxide than a metal oxide with an nc structure and a metal oxide with a CAAC structure. Therefore, a lattice defect is likely to be generated in a metal oxide with an α-like structure and a metal oxide with an amorphous structure.

[0390] Therefore, a metal oxide with high crystallinity is preferably used for a semiconductor layer of a transistor. For example, a metal oxide with a CAAC structure or a metal oxide with a single-crystal structure is preferably used. By using the metal oxide for a semiconductor layer of a transistor, the transistor can have advantageous electrical properties. Furthermore, the transistor can have high reliability.

[0391] For the channel formation region of a transistor, a metal oxide that increases the transistor's forward current is preferably used. To increase the transistor's forward current, the mobility of the metal oxide used for the transistor is preferably increased. To increase the mobility of the metal oxide, the transfer of charge carriers (electrons in the case of an n-channel transistor) must be promoted or stray factors that influence charge carrier transfer must be reduced. Note that charge carriers flow from the source to the drain via the channel formation region. Thus, the transistor's forward current can be increased by providing a channel formation region through which charge carriers can easily flow in the channel's longitudinal direction.

[0392] Here, a metal oxide with high crystallinity is preferably used for a metal oxide including a channel formation region. The crystal preferably has a crystal structure in which a plurality of layers (e.g., a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or a layered structure). Here, the c-axis direction of the crystal is the direction in which the plurality of layers are stacked. Examples of a metal oxide including the crystal include a single-crystal oxide semiconductor, a CAAC-OS, and the like.

[0393] The c-axis of the protruding crystal is preferably oriented in the normal direction with respect to the formation surface or film surface of the metal oxide. This allows the plurality of layers to be arranged parallel or substantially parallel to the formation surface or film surface of the metal oxide. In other words, the plurality of layers extend in the channel longitudinal direction.

[0394] For example, the above layered crystal structure comprising three layers is as follows. The first layer has a coordination geometry of atoms that includes an octahedral structure of oxygen in which a metal contained in the first layer is located at the center. The second layer has a coordination geometry of atoms that includes a trigonal bipyramidal or tetrahedral structure of oxygen in which a metal contained in the second layer is located at the center. The third layer has a coordination geometry of atoms that includes a trigonal bipyramidal or tetrahedral structure of oxygen in which a metal contained in the third layer is located at the center.

[0395] Examples of the crystal structure of the above crystal include a YbFe2O4 structure, a Yb2Fe3O7 structure, their deformed structures, and the like.

[0396] Preferably, each of the first to third layers consists of one or more metal elements having the same valence, and oxygen. The valence of the one or more metal elements contained in the first layer is preferably equal to the valence of the one or more metal elements contained in the second layer. The first layer and the second layer may contain the same metal element. The valence of the one or more metal elements contained in the first layer is preferably different from the valence of the one or more metal elements contained in the third layer.

[0397] The above structure can increase the crystallinity of the metal oxide, resulting in an increase in the mobility of the metal oxide. Therefore, by using the metal oxide for the channel formation region of the transistor, the forward current of the transistor is increased, leading to an improvement in the electrical properties of the transistor.

[0398] Examples of the metal oxide in one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide in one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three kinds selected from indium, the element M, and zinc. The element M is a metal element or a semi-metal element having a high binding energy to oxygen, such as a metal element or a semi-metal element whose binding energy to oxygen is higher than that of In. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, in one embodiment of the present invention, the metal oxide preferably comprises one or more of indium, gallium, and zinc. In this specification and the like, a metal element and a semi-metal element may be collectively referred to as a "metal element," and a "metal element" in this specification and the like may refer to a semi-metal element.

[0399] As a metal oxide in one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (also referred to as Ga-Zn oxide or GZO), aluminum zinc oxide (also referred to as Al-Zn oxide or AZO), indium aluminum zinc oxide (also referred to as In-Al-Zn oxide or IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (also called In-Ga-Zn oxide or IGZO), indium gallium tin zinc oxide (also called In-Ga-Sn-Zn oxide or IGZTO), or indium gallium aluminum zinc oxide (also called In-Ga-Al-Zn oxide, IGAZO, or IAGZO) may be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), or the like may be used.

[0400] By increasing the proportion of the number of indium atoms in the total number of atoms of all metal elements contained in the metal oxide, the field effect mobility of the transistor can be increased.

[0401] Instead of indium, the metal oxide may contain one or more types of metal elements with a large period number. Alternatively, in addition to indium, the metal oxide may contain one or more types of metal elements with a large period number. As the overlap of orbitals of metal elements becomes larger, the metal oxide tends to exhibit higher carrier conduction. Therefore, if a metal element with a large period number is included, the field-effect mobility of the transistor can be increased in some cases. Examples of the metal element with a large period number are the metal elements belonging to period 5 and those belonging to period 6. Specific examples of the metal element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium.It should be noted that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are referred to as light rare earth elements.

[0402] The metal oxide may contain one or more types selected from non-metal elements. A transistor containing the metal oxide containing a non-metal element can, in some cases, exhibit high field-effect mobility. Examples of the non-metal element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0403] By increasing the proportion of zinc atoms in the total number of atoms of all metal elements contained in the metal oxide, the metal oxide exhibits high crystallinity, so that the diffusion of impurities in the metal oxide can be suppressed. Consequently, changes in the electrical properties of the transistor are suppressed, and the transistor can exhibit high reliability.

[0404] By increasing the proportion of atoms of element M in the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Accordingly, the generation of charge carriers due to oxygen vacancies is prevented, which reduces the off-state current of the transistor. Furthermore, changes in the electrical properties of the transistor are suppressed, and the transistor can exhibit high reliability.

[0405] By increasing the proportion of the number of In atoms in the total number of atoms of all metal elements contained in the metal oxide, a high forward current and high frequency characteristics of the transistor can be obtained.

[0406] In this embodiment, In-Ga-Zn oxide is described as an example of the metal oxide in some cases.

[0407] To form a metal oxide with a layered crystal structure, it is preferable to form atomic layers for each layer. A metal oxide with a layered crystal structure is easily formed using an ALD process.

[0408] Examples of the ALD process include a thermal ALD process in which a precursor and a reactant react with each other only through thermal energy, and a plasma-enhanced ALD (PEALD) process in which a reactant excited by plasma is used.

[0409] In an ALD process, atomic layers can be formed for each layer, and the ALD process has various advantages, such as the formation of an extremely thin film, deposition on a component with a high aspect ratio, formation of a film with few defects such as pinholes, deposition with excellent coverage, and low-temperature deposition. A PEALD process using plasma is preferable because low-temperature deposition is possible in some cases. Note that some precursors used in the ALD process contain an element such as carbon or chlorine. Therefore, in some cases, a film formed by the ALD process contains a larger amount of an element such as carbon or chlorine than a film formed by another deposition method.It should be noted that these elements can be quantified by XPS or SIMS.

[0410] When an ALD method is used as a deposition method of a metal oxide, a deposition condition with a high substrate temperature and / or a treatment for removing an impurity can form a film with smaller amounts of carbon and chlorine than in the case where an ALD method without the condition and treatment is used.

[0411] For example, an impurity removal treatment is preferably performed intermittently during deposition of the metal oxide in an oxygen-containing atmosphere. Furthermore, an impurity removal treatment is preferably performed in an oxygen-containing atmosphere after deposition of the metal oxide. The impurities in the film can be removed by performing the impurity removal treatment during and / or after deposition of the metal oxide. This can suppress impurities (e.g., hydrogen, carbon, and nitrogen) contained in a raw material such as a precursor from remaining in the metal oxide. Consequently, the impurity concentration in the metal oxide can be reduced. Furthermore, the crystallinity of the metal oxide can be increased.

[0412] Examples of treatment for removing an impurity include plasma treatment, microwave treatment, and heat treatment.

[0413] When plasma treatment or microwave treatment is performed, the substrate temperature is preferably higher than or equal to room temperature (e.g., 25°C) and lower than or equal to 500°C, higher than or equal to 100°C and lower than or equal to 500°C, higher than or equal to 200°C and lower than or equal to 500°C, higher than or equal to 300°C and lower than or equal to 500°C, higher than or equal to 400°C and lower than or equal to 500°C, or higher than or equal to 400°C and lower than or equal to 450°C. The temperature of the heat treatment is preferably higher than or equal to 100 °C and lower than or equal to 450 °C, higher than or equal to 200 °C and lower than or equal to 450 °C, higher than or equal to 300 °C and lower than or equal to 450 °C, or higher than or equal to 400 °C and lower than or equal to 450 °C.

[0414] The temperature of the impurity removal treatment is particularly preferably set to be lower than or equal to the maximum temperature in the manufacturing process of a transistor or semiconductor device. In this case, the impurity content in the metal oxide can be reduced without reducing productivity. For example, if the maximum temperature in manufacturing the semiconductor device of one embodiment of the present invention is lower than or equal to 500°C, preferably lower than or equal to 450°C, the productivity of the semiconductor device can be improved.

[0415] Here, microwave treatment refers, for example, to a treatment using a device with a power source for generating high-density plasma using a microwave. Note that in this specification and the like, in some cases, a microwave refers to an electromagnetic wave with a frequency higher than or equal to 300 MHz and lower than or equal to 300 GHz.

[0416] The microwave treatment is preferably performed, for example, with a microwave treatment device in which a power source for generating high-density plasma using microwaves is used. Here, the frequency of the microwave treatment device is preferably set to higher than or equal to 300 MHz and lower than or equal to 300 GHz, more preferably higher than or equal to 2.4 GHz and lower than or equal to 2.5 GHz, and may be, for example, 2.45 GHz. High-density oxygen radicals can be generated with high-density plasma. The electric power of the power source applying microwaves to the microwave treatment device is preferably set to higher than or equal to 1000 W and lower than or equal to 10,000 W, more preferably higher than or equal to 2000 W and lower than or equal to 5000 W. A power source for applying RF to one side of the substrate may be included in the microwave treatment device.Furthermore, applying RF to the side of the substrate allows oxygen ions generated by the high-density plasma to be efficiently introduced into a film.

[0417] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably higher than or equal to 10 Pa and lower than or equal to 1000 Pa, more preferably higher than or equal to 300 Pa and lower than or equal to 700 Pa. The treatment temperature is preferably higher than or equal to room temperature (25 °C) and lower than or equal to 750 °C, more preferably higher than or equal to 300 °C and lower than or equal to 500 °C, and more preferably higher than or equal to 400 °C and lower than or equal to 450 °C.

[0418] After the microwave treatment or plasma treatment, a heat treatment can be performed successively without exposure to air. For example, the heat treatment temperature is preferably higher than or equal to 100°C and lower than or equal to 750°C, more preferably higher than or equal to 300°C and lower than or equal to 500°C, and even more preferably higher than or equal to 400°C and lower than or equal to 450°C.

[0419] The microwave treatment can be performed, for example, using an oxygen gas and an argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is higher than 0% and lower than or equal to 100%. The oxygen flow ratio (O2 / (O2+Ar)) is preferably higher than 0% and lower than or equal to 50%. The oxygen flow ratio (O2 / (O2+Ar)) is more preferably higher than or equal to 10% and lower than or equal to 40%. The oxygen flow ratio (O2 / (O2+Ar)) is even more preferably higher than or equal to 10% and lower than or equal to 30%.

[0420] The heat treatment is carried out in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, in the case where the heat treatment is carried out in a mixed atmosphere of a nitrogen gas and an oxygen gas, the proportion of the oxygen gas may preferably be about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in the following manner: A heat treatment is carried out in an atmosphere of a nitrogen gas or an inert gas, and then another heat treatment is carried out in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for released oxygen.The heat treatment may be carried out in an atmosphere of ultra-dry air (air in which the water content is 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less).

[0421] By performing the heat treatment in this way, an impurity contained in the metal oxide, such as hydrogen or carbon, can be removed. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. Furthermore, metal atoms and oxygen atoms are rearranged simultaneously with the removal of the impurity, which can improve crystallinity. Therefore, a metal oxide with a layered crystal structure and high crystallinity, particularly a metal oxide with a CAAC structure, can be formed.

[0422] Unlike a deposition method that deposits particles emitted from a target, an ALD method, for example, forms a film by a reaction on a surface of an object to be processed. Therefore, an ALD method is a deposition method that is less likely to be affected by the shape of an object to be processed and therefore enables favorable step coverage. In particular, for example, an ALD method can provide excellent step coverage and excellent thickness uniformity and can therefore be suitably used for covering a surface of an opening portion with a high aspect ratio. On the other hand, an ALD method has a relatively low deposition rate; therefore, in some cases, it is suitable to use an ALD method in combination with another deposition method with a high deposition rate, such as a high-resolution film.a sputtering process or a CVD process. For example, a process may be provided in which a sputtering process is used to deposit a first metal oxide, and an ALD process is used to deposit a second metal oxide over the first metal oxide. For example, if the first metal oxide has a crystal portion, crystal growth occurs in the second metal oxide using the crystal portion as a nucleus.

[0423] When using an ALD method, the composition of a film to be formed can be controlled by the amount of source gases introduced. For example, in an ALD method, a film with a specific composition can be formed by regulating the amount of source gases introduced, the frequency of introduction (also called pulse frequency), and the time required for one pulse (also called pulse time). Furthermore, for example, a film whose composition changes continuously can be formed by changing the source gas during deposition in an ALD method. In the case where a film is formed while changing the source gas, the deposition time can be reduced compared to the case where a film is formed using a plurality of deposition chambers because the time for transferring and regulating pressure is omitted.Therefore, the productivity of the semiconductor device can be improved in some cases. [Transistor comprising a metal oxide]

[0424] Next, we'll describe the case where a metal oxide (oxide semiconductor) is used for a transistor. Hereinafter, a transistor including a semiconductor layer made of an oxide semiconductor is sometimes referred to as an OS transistor, and a transistor including a semiconductor layer made of silicon is sometimes referred to as an Si transistor.

[0425] When the metal oxide (oxide semiconductor) of one embodiment of the present invention is used for a transistor, the transistor can exhibit high field-effect mobility. Furthermore, the transistor can exhibit high reliability. Furthermore, a miniaturized or highly integrated transistor can be achieved. For example, a transistor with a channel length of greater than or equal to 2 nm and less than or equal to 30 nm can be fabricated.

[0426] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of the transistor. For example, the carrier concentration in the channel formation region of an oxide semiconductor is less than or equal to 1 × 10 18 cm -3 , preferably less than or equal to 1 × 10 17 cm -3 , preferably less than or equal to 1 × 10 15 cm -3, more preferably less than or equal to 1 × 10 13 cm -3 , even more preferably lower than or equal to 1 × 10 11 cm -3 , even more preferably lower than 1 × 10 10 cm -3 and higher than or equal to 1 × 10 -9 cm -3 To reduce the carrier concentration in an oxide semiconductor film, it is preferable to reduce the impurity concentration in the oxide semiconductor film so that the density of defect states can be reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic state. Note that an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0427] A high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low density of defect states and, accordingly, in some cases, has a low density of trap states.

[0428] An electric charge trapped by the trap states in the oxide semiconductor takes a long time to dissipate and may behave like a fixed electric charge. A transistor whose channel formation region is formed in an oxide semiconductor with a high density of trap states may exhibit unstable electrical properties in some cases.

[0429] To maintain stable electrical properties of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in a film adjacent to the oxide semiconductor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in an oxide semiconductor refer to elements other than the main components of the oxide semiconductor, for example. For example, an element with a concentration of less than 0.1 atomic % is an impurity.

[0430] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), more preferably greater than or equal to 2 eV, even more preferably greater than or equal to 2.5 eV, and even more preferably greater than or equal to 3.0 eV. Using an oxide semiconductor with a larger band gap than silicon can reduce the off-state current (also referred to as Ioff) of the transistor.

[0431] With the miniaturization of a Si transistor, a short-channel effect (SCE) occurs. This makes miniaturizing a Si transistor difficult. One factor contributing to the short-channel effect is the narrow band gap of silicon. Meanwhile, an OS transistor comprises an oxide semiconductor, a semiconductor material with a wide band gap, and is therefore less likely to suffer from the short-channel effect. In other words, the short-channel effect hardly occurs or is absent in an OS transistor.

[0432] It should be noted that the short-channel effect refers to the deterioration of electrical characteristics that becomes apparent with miniaturization of a transistor (a reduction in channel length). Specific examples of the short-channel effect include a reduction in threshold voltage, an increase in the subthreshold swing value (sometimes referred to as the S value), an increase in leakage current, and the like. Here, the S value refers to the amount of change in the gate voltage in the subthreshold region when the drain voltage is kept constant and the drain current is changed by one order of magnitude.

[0433] The characteristic length is widely used as an index of resistance to short-channel effects. The characteristic length is an index of the bending of the potential in a channel formation region. As the characteristic length becomes shorter, the potential increases more abruptly, indicating high resistance to short-channel effects.

[0434] An OS transistor is an accumulation-type transistor, and a Si transistor is an inversion-type transistor. Therefore, an OS transistor has a shorter characteristic length between a source region and a channel formation region, as well as a shorter characteristic length between a drain region and the channel formation region, than a Si transistor. Consequently, an OS transistor has higher resistance to the short-channel effect than a Si transistor. This means that in cases where a transistor with a short channel length needs to be manufactured, an OS transistor is more suitable than a Si transistor.

[0435] Even in the case where the carrier concentration in the oxide semiconductor is reduced until the channel formation region becomes an i-type or substantially i-type region, the conduction band minimum of the channel formation region in a short-channel transistor decreases due to the conduction band lowering (CBL) effect; therefore, there is a possibility that a difference in the energy of the conduction band minimum between the channel formation region and the source region or the drain region is as small as 0.1 eV or more and 0.2 eV or less. Therefore, the OS transistor can be considered a structure of a junction-less transistor of the n-type. + / n - / n + -accumulation type or a structure of a non-junction transistor of n + / n - / n + -accumulation type, in which the channel formation area is an n - -area and the source and drain areas n + -areas are.

[0436] An OS transistor having the above structure enables a semiconductor device to have favorable electrical characteristics even when the semiconductor device is miniaturized or highly integrated. For example, favorable electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is greater than or equal to 1 nm and less than or equal to 20 nm, greater than or equal to 3 nm and less than or equal to 15 nm, greater than or equal to 5 nm and less than or equal to 10 nm, greater than or equal to 5 nm and less than or equal to 7 nm, or greater than or equal to 5 nm and less than or equal to 6 nm. Meanwhile, due to a short channel effect, in some cases, it is difficult for a Si transistor to have a gate length of less than or equal to 20 nm or less than or equal to 15 nm.Therefore, an OS transistor can be more suitable for use as a transistor with a short gate length than a Si transistor. Note that the gate length refers to the length of a gate electrode in a direction in which charge carriers move within a channel formation region during transistor operation.

[0437] Miniaturizing an OS transistor can improve the high-frequency characteristics of the transistor. In particular, the cutoff frequency of the transistor can be improved. For example, if the gate length of the OS transistor is within the above range, the cutoff frequency of the transistor can be higher than or equal to 50 GHz, preferably higher than or equal to 100 GHz, and more preferably higher than or equal to 150 GHz at room temperature.

[0438] As described above, an OS transistor has advantages over a Si transistor, such as a small off-state current and an ability to have a short channel length. [Impurity in the metal oxide]

[0439] This describes the influence of each impurity in the metal oxide (oxide semiconductor).

[0440] When silicon or carbon, which is a Group 14 element, is contained in an oxide semiconductor, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor, measured by SIMS, is less than or equal to 1 × 10 20 atoms / cm 3 , preferably less than or equal to 5 × 10 19 atoms / cm 3 , more preferably less than or equal to 3 × 10 19 atoms / cm 3 , even more preferably lower than or equal to 1 × 10 19atoms / cm 3 , even more preferably lower than or equal to 3 × 10 18 atoms / cm 3 , even more preferably lower than or equal to 1 × 10 18 atoms / cm 3 . The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is less than or equal to 1 × 10 20 atoms / cm 3 , preferably less than or equal to 5 × 10 19 atoms / cm 3 , preferably less than or equal to 3 × 10 19 atoms / cm 3 , more preferably less than or equal to 1 × 10 19 atoms / cm 3 , even more preferably lower than or equal to 3 × 10 18 atoms / cm 3 , even more preferably lower than or equal to 1 × 10 18 atoms / cm 3 .

[0441] Furthermore, when the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type due to the generation of electrons that serve as charge carriers and an increase in the charge carrier concentration. As a result, a transistor using a nitrogen-containing oxide semiconductor for the semiconductor layer tends to exhibit self-conducting properties. When nitrogen is contained in the oxide semiconductor, a trap state is formed in some cases. This could lead to unstable electrical properties of the transistor. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor, measured by SIMS, is less than or equal to 1 × 10 20 atoms / cm 3 , preferably less than or equal to 5 × 10 19 atoms / cm 3 , preferably less than or equal to 1 × 10 19 atoms / cm 3 , more preferably less than or equal to 5 × 10 18 atoms / cm 3, even more preferably lower than or equal to 1 × 10 18 atoms / cm 3 , even more preferably lower than or equal to 5 × 10 17 atoms / cm 3 .

[0442] Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water and thus, in some cases, generates an oxygen vacancy. As a result of hydrogen invading the oxygen vacancy, an electron serving as a charge carrier is generated in some cases. Furthermore, bonding of a portion of hydrogen with oxygen bonded to a metal atom generates an electron serving as a charge carrier. Therefore, a transistor containing a hydrogen-containing oxide semiconductor is likely to exhibit self-conducting behavior. For this reason, hydrogen in the channel formation region of the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor, measured by SIMS, is lower than 1 × 10 20 atoms / cm 3 , preferably lower than 5 × 10 19 atoms / cm 3, preferably lower than 1 × 10 19 atoms / cm 3 , more preferably lower than 5 × 10 18 atoms / cm 3 , even more preferably lower than 1 × 10 18 atoms / cm 3 .

[0443] When the oxide semiconductor contains alkali metal or alkaline earth metal, defect states are sometimes formed and charge carriers are generated. Therefore, a transistor containing an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to behave normally. Therefore, the concentration of alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor, measured by SIMS, is set to less than or equal to 1 × 10 18 atoms / cm 3 , preferably less than or equal to 2 × 10 18 atoms / cm 3 set.

[0444] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region in a transistor, the transistor can exhibit stable electrical characteristics. [other semiconductor materials]

[0445] The semiconductor layer 113 can be reformulated as a semiconductor layer including a channel formation region of a transistor. Semiconductor materials that can be used for the semiconductor layer are not limited to the above metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) can be used for the semiconductor layer. For example, a single-element semiconductor, a compound semiconductor, a layered material (also referred to as an atomic layered material or a two-dimensional material), or the like is preferably used as the semiconductor material.

[0446] In this specification and the like, the layered material is a group of materials having a layered crystal structure. In the layered crystal structure, layers formed by a covalent bond or an ionic bond are stacked one on top of the other with a bond such as van der Waals forces that is weaker than a covalent bond or an ionic bond. The layered material has high electrical conductivity in a monolayer, that is, high two-dimensional electrical conductivity. When a material serving as a semiconductor and having high two-dimensional electrical conductivity is used for a channel formation region, the transistor can have a high on-state current.

[0447] Examples of single-element semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used for the semiconductor layer include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0448] Examples of compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used as a semiconductor layer preferably has an amorphous structure. Boron nitride that can be used as a semiconductor layer preferably has a crystal with a cubic structure.

[0449] Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenide. Boron carbonitride, which serves as a layered material, contains carbon atoms, nitrogen atoms, and boron atoms arranged on a plane in a hexagonal lattice structure. Chalcogenide is a compound containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and chalcogenides of Group 13 elements.

[0450] For example, a transition metal chalcogenide serving as a semiconductor is preferably used as the semiconductor layer. Specific examples of the transition metal chalcogenide that can be used for the semiconductor layer include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (HfS2), hafnium selenide (HfSe2), zirconium sulfide (ZrS2), and zirconium selenide (ZrSe2). The use of the transition metal chalcogenide for the semiconductor layer makes it possible to provide a semiconductor device with a high forward current.

[0451] This embodiment can be combined with any of the other embodiments as needed. Where a plurality of structural examples are shown in one embodiment in this specification, the structural examples can be combined as needed. (Embodiment 2)

[0452] In this embodiment, an example of a method for manufacturing the semiconductor device of one embodiment of the present invention will be described with reference to drawings. <Beispiel für ein Verfahren zum Herstellen der Halbleitervorrichtung>

[0453] As a method for manufacturing the semiconductor device of one embodiment of the present invention, an example of a method for manufacturing the semiconductor device shown in Fig. 4A to Fig. 4C is described below.

[0454] A of each drawing is a plan view. Furthermore, B of each drawing is a cross-sectional view corresponding to a section indicated by a dashed line A1-A2 in A of each drawing. Furthermore, C of each drawing is a cross-sectional view corresponding to a section indicated by a dashed line A3-A4 in A of each drawing. Note that, for the sake of simplicity of the drawing, some components are not shown in the plan view of A of each drawing.

[0455] In the following steps, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor may be deposited by appropriately using a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0456] Examples of the sputtering method include an RF sputtering method in which a high-frequency power source is used as the sputtering power source, a DC sputtering method in which a DC power source is used, and a pulsed DC sputtering method in which a voltage is applied and changed in a pulsed manner. The RF sputtering method is mainly used in the case where an insulating film is formed, and the DC sputtering method is mainly used in the case where a conductive metal film is formed. A pulsed DC sputtering method is mainly used in the case where a compound such as an oxide, a nitride, or a carbide is deposited by a reactive sputtering method.

[0457] It should be noted that CVD processes can be divided into plasma-enhanced CVD (PECVD) processes that use plasma, thermal CVD (TCVD) processes that use heat, photo-CVD processes that use light, and the like. Furthermore, depending on the source gas, CVD processes can be divided into metal-organic CVD (MCVD) processes and metal-organic CVD (MOCVD).

[0458] A PECVD process can obtain a high-quality film at a relatively low temperature. A thermal CVD process is a deposition process that does not use plasma, and therefore enables film formation without plasma damage to a subject. For example, a wire, an electrode, an element (e.g., a transistor and a capacitor), and the like included in a semiconductor device may be charged by receiving charges from the plasma. In this case, the accumulated charges could damage the wire, electrode, element, or the like included in the semiconductor device. In contrast, in the case of a thermal CVD process that does not use plasma, no such plasma damage is caused, and therefore the yield of semiconductor devices can be increased.Furthermore, since no plasma damage is caused during film formation by a thermal CVD process, a film with few defects can be obtained.

[0459] As the ALD method, a thermal ALD method in which a precursor and a reactant react with each other only by thermal energy, a PEALD method in which a reactant excited by plasma is used, or the like can be used.

[0460] A CVD method and an ALD method are different from a sputtering method, which deposits particles emitted from a target or the like. Therefore, a CVD method and an ALD method are less likely to be affected by the shape of an object to be processed, and thus they enable favorable step coverage. In particular, for example, an ALD method can provide excellent step coverage and excellent thickness uniformity and can therefore be suitably used for covering a surface of an opening portion with a high aspect ratio. An ALD method has a relatively low deposition rate; therefore, in some cases, it is appropriate to use an ALD method in combination with another deposition method with a high deposition rate, such as a CVD method.

[0461] By a CVD process, a film with a specific composition can be formed by adjusting the flow rate ratio of the source gases. For example, a film whose composition changes continuously can be formed by changing the flow rate ratio of the source gases during deposition in a CVD process. In the case where a film is formed while changing the flow rate ratio of the source gases, the deposition time can be reduced compared to the case where a film is formed using a plurality of deposition chambers because the time for transferring or regulating pressure is omitted. Therefore, the productivity of the semiconductor device can be improved in some cases.

[0462] An ALD process that introduces a variety of different types of precursors simultaneously enables the formation of a film with the desired composition. By introducing a variety of different types of precursors, the number of precursor deposition cycles can be controlled, allowing the formation of a film with the desired composition.

[0463] First, a substrate (not shown) is prepared and the insulating layer 101 is formed over the substrate ( Fig. 34A to Fig. 34C). Any of the insulating materials described above can be appropriately used for the insulating layer 101. A deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method can be appropriately used to form the insulating layer 101.

[0464] Next, the conductive layer 111c is formed over the insulating layer 101 ( Fig. 34A to Fig. 34C). For example, the conductive layer 111c can be formed by forming and processing a conductive film that becomes the conductive layer 111c. For the conductive film that becomes the conductive layer 111c, any of the above-described conductive materials that can be used for the conductive layer 111 can be appropriately used.

[0465] The conductive film that will become the conductive layer 111c can be formed by appropriately using a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, as the conductive film that will become the conductive layer 111c, a multilayer film in which tungsten and titanium nitride are deposited in this order by a CVD method can be used. After the conductive film that will become the conductive layer 111c is formed, a pattern is formed by a lithography method, and the conductive film is processed by a dry etching method, a wet etching method, or the like using the pattern, whereby the conductive layer 111c can be formed. Here, the conductive film is preferably processed for microfabrication by a dry etching method.

[0466] In the lithography process, a photoresist is first exposed through a mask. Next, an exposed area is removed using a developing solution, or it is left behind, forming a photoresist mask. In this way, a pattern is formed.

[0467] A photoresist mask is formed, for example, by exposing the photoresist to light such as KrF excimer laser light, ArF excimer laser light, extreme ultraviolet (EUV) light, or the like. A liquid immersion technique may be used in which a portion between a substrate and a projection lens is filled with a liquid (e.g., water) to perform exposure. Note that when an electron beam or an ion beam is used, a photomask is not necessary. Note that when an electron beam or an ion beam is used, a mask is not necessary. To remove the photoresist mask, a dry etching treatment such as ashing or a wet etching treatment may be used. Alternatively, a wet etching treatment may be performed after a dry etching treatment, or a dry etching treatment may be performed after a wet etching treatment.

[0468] Next, an etching treatment is performed using the photoresist mask. This allows the conductive layer, semiconductor layer, insulating layer, and the like to be processed into desired shapes.

[0469] In the case where dry etching is performed as the above-described etching treatment, an etching gas containing halogen can be used as the etching gas, specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as the etching gas, a C4F6 gas, a C5F6 gas, a C4F8 gas, a CF4 gas, an SF6 gas, an NF3 gas, a CHF3 gas, a Cl2 gas, a BCl3 gas, a SiCl4 gas, a CCl4 gas, a BBr3 gas, or the like can be used alone or in combination. An oxygen gas, a carbon dioxide gas, a nitrogen gas, a helium gas, an argon gas, a hydrogen gas, a hydrocarbon gas, or the like can be added to the above etching gas as needed. The etching conditions can be appropriately adjusted depending on an object to be etched.

[0470] A capacitively coupled plasma (CCP) etching device comprising parallel plate electrodes can be used as the dry etching device. The capacitively coupled plasma etching device comprising the parallel plate electrodes can have a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, the capacitively coupled plasma etching device can have a structure in which different high-frequency voltages are applied to one of the parallel plate electrodes. Alternatively, the capacitively coupled plasma etching device can have a structure in which high-frequency voltages of the same frequency are applied to the parallel plate electrodes. Alternatively, the capacitively coupled plasma etching device can have a structure in which high-frequency voltages of different frequencies are applied to the parallel plate electrodes.Alternatively, a dry etching device comprising a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching device can be used as a dry etching device comprising a high-density plasma source.

[0471] Next, the insulating layer 103c_1 serving as an insulating interlayer is formed over the insulating layer 101 and the conductive layer 111c ( Fig. 35A to Fig. 35C). Any of the insulating materials described above can be appropriately used as the insulating layer 103c_1. The insulating layer 103c_1 can be formed by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, a silicon oxide film is formed as the insulating layer 103c_1 by a sputtering method. Note that preferably, the upper surface of the deposited insulating layer 103c_1 is planarized by a chemical mechanical polishing (CMP) treatment. The planarization treatment on the insulating layer 103c_1 allows the conductive layer 115c serving as a wiring to be advantageously formed in a later step.After aluminum oxide has been deposited over the insulating layer 103c_1, for example, by a sputtering process, a CMP treatment may be performed until the insulating layer 103c_1 is exposed. The CMP treatment may planarize and smooth the surface of the insulating layer 103c_1. When the CMP treatment is performed on the aluminum oxide disposed over the insulating layer 103c_1, the end point of the CMP treatment is easily visible.

[0472] Note that in some cases, CMP treatment is unnecessary. In such a case, the upper surface of the insulating layer 103c_1 has a convex shape. By not performing planarization treatment, manufacturing costs can be reduced and production yield can be increased.

[0473] Next, a conductive layer 115c is formed over the insulating layer 103c_1 ( Fig. 36A to Fig. 36C). For example, a conductive film that will become the conductive layer 115c is formed and processed, whereby the conductive layer 115c can be formed. For the conductive film that will become the conductive layer 115c, any of the above-described conductive materials that can be used for the conductive layer 115 can be appropriately used. The conductive film that will become the conductive layer 115c can be formed by appropriately using a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0474] After the conductive film that will become the conductive layer 115c is formed, a pattern is formed by a lithography method, and the conductive film is processed by a dry etching method, a wet etching method, or the like using the pattern, whereby the conductive layer 115c can be formed. Here, the conductive film is preferably processed by a dry etching method for microfabrication.

[0475] Next, the insulating layer 103c_2 serving as an insulating interlayer is formed over the insulating layer 103c_1 and the conductive layer 115c ( Fig. 37A to Fig. 37C). The insulating layer 103c_2 may be formed using the same material and the same formation method as those of the insulating layer 103c_1. The top surface of the deposited insulating layer 103c_2 is preferably planarized by a CMP treatment.

[0476] Here, since the total thickness of the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103_2 corresponds to the channel length of the transistor 43, the thicknesses of the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2 can be appropriately set depending on the design value of the channel length of the transistor 43.

[0477] Next, a part of the insulating layer 103c_2, a part of the conductive layer 115c, and a part of the insulating layer 103c_1 are processed to form the opening 121c reaching the conductive layer 111c ( Fig. 38A to Fig. 38C). The opening 121c can be formed, for example, by a lithography process and an etching process.

[0478] Here, the sidewall of the opening 121c is preferably perpendicular to the top surface of the conductive layer 111c, for example. This structure enables miniaturization or high integration of the semiconductor device. The sidewall of the opening 121c may be tapered. When the sidewall of the opening 121c is tapered, the coverage with a metal oxide film described below, which becomes the semiconductor layer 113c, or the like, is improved, so that, for example, the number of defects such as voids can be reduced.

[0479] The maximum width of the opening 121c (in the case where the opening 121c is circular in plan view, the diameter) is preferably small. For example, the maximum width of the opening 121c is preferably greater than or equal to 1 nm and less than or equal to 60 nm, greater than or equal to 1 nm and less than or equal to 50 nm, greater than or equal to 1 nm and less than or equal to 40 nm, greater than or equal to 1 nm and less than or equal to 30 nm, greater than or equal to 1 nm and less than or equal to 20 nm, or greater than or equal to 5 nm and less than or equal to 20 nm.

[0480] Since the opening 121c has a high aspect ratio, a part of the insulating layer 103c_2, a part of the conductive layer 115c, and a part of the insulating layer 103c_1 are preferably processed by anisotropic etching. Processing by a dry etching method is particularly preferred because it is suitable for microfabrication. The processing can be performed under different conditions. Note that in some cases, depending on the conditions under which a part of the insulating layer 103c_2, a part of the conductive layer 115c, and a part of the insulating layer 103c_1 are processed, the inclination of the side surface of the insulating layer 103c_2 in the opening 121c, the inclination of the side surface of the conductive layer 115c in the opening 121c, and the inclination of the side surface of the insulating layer 103c_1 in the opening 121c differ from each other.

[0481] Next, a heat treatment may be performed. The heat treatment is performed at a temperature higher than or equal to 250°C and lower than or equal to 650°C, preferably higher than or equal to 300°C and lower than or equal to 500°C, more preferably higher than or equal to 320°C and lower than or equal to 450°C. Note that the heat treatment is performed, for example, in a nitrogen gas atmosphere or an inert gas atmosphere. The heat treatment may be performed under reduced pressure. By the above-described heat treatment, impurities such as water contained in the insulating layer 103c_1, the insulating layer 103c_2, and the like can be reduced before the metal oxide film described below, which will become the semiconductor layer 113c, is deposited.

[0482] The gas used in the above-described heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above-described heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. When the heat treatment is performed using a highly purified gas, for example, the penetration of moisture into the insulating layer 103c_1 and the insulating layer 103c_2 can be prevented as much as possible.

[0483] Next, an insulating film 105C, which later becomes the insulating layer 105c, is formed in contact with the upper surface of the insulating layer 103c_2, the side surface of the insulating layer 103c_2, the side surface of the conductive layer 115c, the side surface of the insulating layer 103c_1, and the upper surface of the conductive layer 111c ( Fig. 39A to Fig. 39C). Any of the insulating materials described above can be appropriately used for the insulating film 105C. The insulating film 105C can be formed by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Here, the insulating film 105C is preferably formed in contact with the bottom and the sidewall of the opening 121c with a high aspect ratio. Therefore, the insulating film 105C is preferably formed by a deposition method with favorable coverage, and is more preferably formed by a CVD method, an ALD method, or the like. For example, silicon oxide is deposited as the insulating film 105C by an ALD method.

[0484] Note that in the case where the sidewall of the opening 121c has a tapered shape, the method for forming the insulating film 105C is not limited to a CVD method or an ALD method. For example, a sputtering method may be used.

[0485] Next, the insulating film 105C is processed to expose the top surface of the insulating layer 103c_2 and the top surface of the conductive layer 111c, thereby forming the insulating layer 105c that is in contact with the side surface of the insulating layer 103c_1, the side surface of the conductive layer 115c, and the side surface of the insulating layer 103c_2 ( Fig. 40A to Fig. 40C). The upper end portion of the insulating layer 105c has a curved shape.

[0486] Anisotropic etching is preferably used for processing the insulating film 105C. By using anisotropic etching for processing the insulating film 105C, only a portion of the insulating film 105C in contact with the bottom of the opening 121c, which is located in the opening 121c with a high aspect ratio, can be selectively removed. Therefore, the insulating layer 105c in contact with the sidewall of the opening 121c can be formed with high precision.

[0487] Next, the metal oxide film 113C, which will later become the semiconductor layer 113c, is formed in contact with the top surface of the conductive layer 111c, the side surface of the insulating layer 105c, the curved portion of the insulating layer 105c, and the top surface of the insulating layer 103c_2 ( Fig. 41A to Fig. 41C). For the metal oxide film 113C, any of the above-described metal oxides that can be used for the semiconductor layer 113 can be appropriately used. The metal oxide film 113C can be formed by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Here, the metal oxide film 113C is formed in the opening 121c with a high aspect ratio, preferably in contact with the side surface of the insulating layer 105c and the top surface of the conductive layer 111c. Therefore, the metal oxide film 113C is preferably formed by a deposition method with favorable coverage, and is more preferably formed by a CVD method or an ALD method. For example, an In-Ga-Zn oxide is deposited as the metal oxide film 113C by an ALD method.Alternatively, an In-Al-Zn oxide can be deposited as a metal oxide film 113C.

[0488] Note that in the case where the sidewall of the opening 121c has a tapered shape, the method for forming the metal oxide film 113C is not limited to a CVD method or an ALD method. For example, a sputtering method may be used.

[0489] In the case where the semiconductor layer 113c has a multilayer structure, the layers included in the semiconductor layer 113c may be formed by the same method or different methods from each other. For example, when the semiconductor layer 113c has a multilayer structure of two layers, the lower layer of the metal oxide film 113C may be formed by a sputtering method, and the upper layer of the metal oxide film 113C may be formed by an ALD method. A metal oxide film formed by a sputtering method is likely to have crystallinity. Therefore, if a metal oxide film having crystallinity is provided as the lower layer of the metal oxide film 113C, the crystallinity of the upper layer of the metal oxide film 113C can be increased.Even if a pinhole, a separation, or the like is formed in the lower layer of the metal oxide film 113C formed by a sputtering method, the upper layer of the metal oxide film 113C formed by an ALD method can fill a portion overlapping with the pinhole, the separation, or the like with a favorable coverage.

[0490] Here, the metal oxide film 113C is preferably formed in contact with the upper surface of the conductive layer 111a in the opening 121c, the side surface of the insulating layer 105c in the opening 121c, the curved portion of the insulating layer 105c, and the upper surface of the insulating layer 103c_2. When the metal oxide film is formed in contact with the conductive layer 111c, the conductive layer 111c serves as one of the source electrode and the drain electrode of the transistor 43.

[0491] Next, a heat treatment is preferably performed. The heat treatment can be performed in a temperature range where the metal oxide film 113C does not become polycrystals, that is, at a temperature higher than or equal to 250°C and lower than or equal to 650°C, preferably higher than or equal to 400°C and lower than or equal to 600°C. The details of the heat treatment can be referred to in the above description.

[0492] Here, the above-described heat treatment is preferably performed in the state where the insulating layer 103c_2 containing excess oxygen is in contact with the metal oxide film 113C. By p...

Claims

[1] A semiconductor device comprising a first transistor, a second transistor, a third transistor, a first line, a second line, a third line, a fourth line, and a fifth line, wherein a source and a drain of each of the first transistor, the second transistor and the third transistor are provided at different heights with respect to a substrate surface, wherein the second transistor is provided so as to overlap the first transistor, wherein the third transistor is provided so as to overlap the second transistor, wherein a gate of the first transistor and the first line are electrically connected to each other, wherein a terminal of source and drain of the first transistor and a gate of the second transistor are electrically connected to each other, wherein the other terminal of the source and drain of the first transistor and the second line are electrically connected to each other, wherein a terminal of the source and drain of the second transistor and a terminal of the source and drain of the third transistor are electrically connected to each other, wherein the other terminal of the source and drain of the second transistor and the third line are electrically connected to each other, wherein a gate of the third transistor and the fourth line are electrically connected to each other, and wherein the other terminal of the source and drain of the third transistor and the fifth line are electrically connected to each other. [2] The semiconductor device according to claim 1, wherein at least one of the first transistor, the second transistor and the third transistor is a transistor comprising a metal oxide. [3] A semiconductor device according to claim 1 or 2, wherein a node is included which electrically connects one terminal of the source and drain of the first transistor and the gate of the second transistor, wherein the first transistor has a function of writing data corresponding to a potential supplied from the second line into the node when a first potential is supplied from the first line, and a function of holding the data at the node when a second potential is supplied from the first line, wherein the second transistor and the third transistor each have a function of reading the data held at the node when a fifth potential is supplied to the fourth line in a state where a third potential is supplied to the third line and a fourth potential is supplied to the fifth line, where the first potential is a potential at which the first transistor is turned on, wherein the second potential is a potential at which the first transistor is turned off, where the fourth potential is higher than the third potential, and where the fifth potential is a potential at which the third transistor is turned on. [4] A semiconductor device comprising a first transistor, a second transistor, a third transistor, a first line, a second line, a third line, a fourth line, and a fifth line, wherein a source and a drain of each of the first transistor, the second transistor and the third transistor are provided at different heights with respect to a substrate surface, wherein the second transistor is provided so as to overlap the first transistor, wherein the third transistor is provided so as to overlap the second transistor, wherein the first transistor is provided such that in a plan view a gate encloses a semiconductor layer, wherein the second transistor is provided such that in a plan view a semiconductor layer encloses a gate, wherein the third transistor is provided such that in a plan view a semiconductor layer encloses a gate, wherein the gate of the first transistor and the first line are electrically connected to each other, wherein a terminal of the source and drain of the first transistor and the gate of the second transistor are electrically connected to each other, wherein the other terminal of the source and drain of the first transistor and the second line are electrically connected to each other, wherein a terminal of the source and drain of the second transistor and a terminal of the source and drain of the third transistor are electrically connected to each other, wherein the other terminal of the source and drain of the second transistor and the third line are electrically connected to each other, wherein the gate of the third transistor and the fourth line are electrically connected to each other, and wherein the other terminal of the source and drain of the third transistor and the fifth line are electrically connected to each other. [5] The semiconductor device according to claim 4, wherein at least one of the first transistor, the second transistor and the third transistor is a transistor comprising a metal oxide in a semiconductor layer. [6] A semiconductor device according to claim 4 or 5, wherein a node is included which electrically connects one terminal of the source and drain of the first transistor and the gate of the second transistor, wherein the first transistor has a function of writing data corresponding to a potential supplied from the second line into the node when a first potential is supplied from the first line, and a function of holding the data at the node when a second potential is supplied from the first line, wherein the second transistor and the third transistor each have a function of reading the data held at the node when a fifth potential is supplied to the fourth line in a state where a third potential is supplied to the third line and a fourth potential is supplied to the fifth line, where the first potential is a potential at which the first transistor is turned on, wherein the second potential is a potential at which the first transistor is turned off, where the fourth potential is higher than the third potential, and where the fifth potential is a potential at which the third transistor is turned on. [7] A semiconductor device comprising a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, wherein the first transistor, the second transistor and the third transistor are arranged one above the other in this order, wherein the first transistor comprises a first conductive layer, a second conductive layer, a third conductive layer, a fifth insulating layer and a first semiconductor layer, wherein the first insulating layer, the third conductive layer and the second insulating layer are arranged one above the other in this order over the first conductive layer, wherein a first opening reaching the first conductive layer is provided in the first insulating layer, the third conductive layer and the second insulating layer, wherein the fifth insulating layer is provided in contact with a side wall of the first opening, wherein the first semiconductor layer is provided in contact with a top surface of the first conductive layer in the first opening, a side surface of the fifth insulating layer in the first opening, and a top surface of the second insulating layer, wherein the second conductive layer is provided in contact with an upper surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer, wherein the second transistor comprises the second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth insulating layer and a second semiconductor layer, wherein the third insulating layer and the fourth conductive layer are arranged one above the other in this order over the second conductive layer, wherein a second opening reaching the second conductive layer is provided in the third insulating layer and the fourth conductive layer, wherein the second semiconductor layer is provided in contact with a top surface of the second conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the fourth conductive layer in the second opening, and a top surface of the fourth conductive layer, wherein the sixth insulating layer is provided in contact with a top surface of the second semiconductor layer, a side surface of the second semiconductor layer, the top surface of the fourth conductive layer, the side surface of the fourth conductive layer, and a top surface of the third insulating layer, wherein the fifth conductive layer is provided over and in contact with the sixth insulating layer such that it fills the second opening, wherein the third transistor comprises a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a seventh insulating layer and a third semiconductor layer, wherein the sixth conductive layer is provided in contact with an upper surface of the fifth conductive layer, wherein the fourth insulating layer and the seventh conductive layer are arranged one above the other in this order over the sixth conductive layer, wherein a third opening reaching the sixth conductive layer is provided in the fourth insulating layer and the seventh conductive layer, wherein the third semiconductor layer is provided in contact with a top surface of the sixth conductive layer in the third opening, a side surface of the fourth insulating layer in the third opening, a side surface of the seventh conductive layer in the third opening, and a top surface of the seventh conductive layer, wherein the seventh insulating layer is provided in contact with a top surface of the third semiconductor layer, a side surface of the third semiconductor layer, the top surface of the seventh conductive layer, the side surface of the seventh conductive layer and a top surface of the fourth insulating layer, and wherein the eighth conductive layer is provided over and in contact with the seventh insulating layer so as to fill the third opening. [8] The semiconductor device according to claim 7, wherein at least one of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer comprises a metal oxide. [9] A semiconductor device according to claim 7 or 8, wherein the second conductive layer comprises a ninth conductive layer and a tenth conductive layer, wherein the ninth conductive layer is provided in contact with the top surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer, wherein the tenth conductive layer is provided in contact with an upper surface of the ninth conductive layer such that it includes a region overlapping with the first conductive layer, and wherein the second semiconductor layer is provided in contact with an upper surface of the tenth conductive layer. [10] A semiconductor device according to claim 7 or 8, wherein the second conductive layer comprises a ninth conductive layer, a tenth conductive layer and an eleventh conductive layer, wherein the ninth conductive layer is provided in contact with the top surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer, wherein the tenth conductive layer is provided in contact with an upper surface of the ninth conductive layer, wherein the eleventh conductive layer is provided in contact with an upper surface of the tenth conductive layer such that it includes a region overlapping with the first conductive layer, and wherein the second semiconductor layer is provided in contact with an upper surface of the eleventh conductive layer. [11] A semiconductor device according to claim 7 or 8, wherein a capacitor is included between the first transistor and the second transistor, wherein the first transistor, the second transistor, the capacitor and the third transistor are arranged one above the other in this order, wherein the capacitor comprises the ninth conductive layer, the tenth conductive layer and an eighth insulating layer, wherein the eighth insulating layer comprises a region which is in contact with a side surface of the ninth conductive layer, wherein the tenth conductive layer covers at least a part of the side surface of the ninth conductive layer, with the eighth insulating layer therebetween, wherein the ninth conductive layer is provided in contact with the top surface of the fifth conductive layer, and wherein the sixth conductive layer is provided in contact with an upper surface of the ninth conductive layer. [12] A semiconductor device comprising a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, wherein the first transistor, the second transistor and the third transistor are arranged one above the other in this order, wherein the first transistor comprises a first conductive layer, a second conductive layer, a third conductive layer, a fifth insulating layer and a first semiconductor layer, wherein the first insulating layer, the third conductive layer and the second insulating layer are arranged one above the other in this order over the first conductive layer, wherein a first opening reaching the first conductive layer is provided in the first insulating layer, the third conductive layer and the second insulating layer, wherein the fifth insulating layer is provided in contact with a side wall of the first opening, wherein the first semiconductor layer is provided in contact with a top surface of the first conductive layer in the first opening, a side surface of the fifth insulating layer in the first opening, and a top surface of the second insulating layer, wherein the second conductive layer is provided in contact with an upper surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer, wherein the third conductive layer is provided so as to enclose the first semiconductor layer in a plan view, with the fifth insulating layer therebetween, wherein the second transistor comprises the second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth insulating layer and a second semiconductor layer, wherein the third insulating layer and the fourth conductive layer are arranged one above the other in this order over the second conductive layer, wherein a second opening reaching the second conductive layer is provided in the third insulating layer and the fourth conductive layer, wherein the second semiconductor layer is provided such that it is in contact with a top surface of the second conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the fourth conductive layer in the second opening, and a top surface of the fourth conductive layer, and that it encloses the fifth conductive layer in a plan view, with the sixth insulating layer therebetween, wherein the sixth insulating layer is provided in contact with a top surface of the second semiconductor layer, a side surface of the second semiconductor layer, the top surface of the fourth conductive layer, the side surface of the fourth conductive layer, and a top surface of the third insulating layer, wherein the fifth conductive layer is provided over and in contact with the sixth insulating layer such that it fills the second opening, wherein the third transistor comprises a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a seventh insulating layer and a third semiconductor layer, wherein the sixth conductive layer is provided in contact with an upper surface of the fifth conductive layer, wherein the fourth insulating layer and the seventh conductive layer are arranged one above the other in this order over the sixth conductive layer, wherein a third opening reaching the sixth conductive layer is provided in the fourth insulating layer and the seventh conductive layer, wherein the third semiconductor layer is provided such that it is in contact with a top surface of the sixth conductive layer in the third opening, a side surface of the fourth insulating layer in the third opening, a side surface of the seventh conductive layer in the third opening, and a top surface of the seventh conductive layer, and that it encloses the eighth conductive layer in a plan view, with the seventh insulating layer therebetween, wherein the seventh insulating layer is provided in contact with a top surface of the third semiconductor layer, a side surface of the third semiconductor layer, the top surface of the seventh conductive layer, the side surface of the seventh conductive layer and a top surface of the fourth insulating layer, and wherein the eighth conductive layer is provided over and in contact with the seventh insulating layer so as to fill the third opening. [13] The semiconductor device according to claim 12, wherein at least one of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer comprises a metal oxide. [14] A semiconductor device according to claim 12 or 13, wherein the second conductive layer comprises a ninth conductive layer and a tenth conductive layer, wherein the ninth conductive layer is provided in contact with the top surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer, wherein the tenth conductive layer is provided in contact with an upper surface of the ninth conductive layer such that it includes a region overlapping with the first conductive layer, and wherein the second semiconductor layer is provided in contact with an upper surface of the tenth conductive layer. [15] A semiconductor device according to claim 12 or 13, wherein the second conductive layer comprises a ninth conductive layer, a tenth conductive layer and an eleventh conductive layer, wherein the ninth conductive layer is provided in contact with the top surface of the first semiconductor layer such that it includes a region overlapping with the first conductive layer, wherein the tenth conductive layer is provided in contact with an upper surface of the ninth conductive layer, wherein the eleventh conductive layer is provided in contact with an upper surface of the tenth conductive layer such that it includes a region overlapping with the first conductive layer, and wherein the second semiconductor layer is provided in contact with an upper surface of the eleventh conductive layer. [16] A semiconductor device according to claim 12 or 13, wherein a capacitor is included between the first transistor and the second transistor, wherein the first transistor, the second transistor, the capacitor and the third transistor are arranged one above the other in this order, wherein the capacitor comprises the ninth conductive layer, the tenth conductive layer and an eighth insulating layer, wherein the eighth insulating layer comprises a region which is in contact with a side surface of the ninth conductive layer, wherein the tenth conductive layer covers at least a part of the side surface of the ninth conductive layer, with the eighth insulating layer therebetween, wherein the ninth conductive layer is provided in contact with the top surface of the fifth conductive layer, and wherein the sixth conductive layer is provided in contact with an upper surface of the ninth conductive layer. [17] A method of manufacturing a semiconductor device comprising the following steps: Forming a first conductive layer; Forming a first insulating layer over the first conductive layer; Forming a second conductive layer over the first insulating layer; Forming a second insulating layer over the first insulating layer and the second conductive layer; Processing the second conductive layer and the second insulating layer and forming a first opening reaching the first conductive layer, Forming a first insulating film in contact with a top surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the first opening, a side surface of the second insulating layer in the first opening, and a top surface of the second insulating layer; Processing the first insulating film to expose the top surface of the first conductive layer in the first opening and the top surface of the second insulating layer, and forming a third insulating layer in contact with the side surface of the first insulating layer in the first opening, the side surface of the second conductive layer in the first opening, and the side surface of the second insulating layer in the first opening; Forming a first metal oxide film in contact with the top surface of the first conductive layer, a side surface of the third insulating layer, a top surface of the third insulating layer, and the top surface of the second insulating layer; processing the first metal oxide film and forming a first semiconductor layer including a region overlapping with the first opening; Forming a third conductive layer in contact with a top surface of the first semiconductor layer; Forming a fourth insulating layer over the third conductive layer and the second insulating layer; Forming a first conductive film over the fourth insulating layer; processing the first conductive film and the fourth insulating layer and forming a second opening reaching the third conductive layer; Forming a second metal oxide film in contact with a top surface of the third conductive layer in the second opening, a side surface of the fourth insulating layer in the second opening, a side surface of the first conductive film in the second opening, and a top surface of the first conductive film; processing the second metal oxide film and forming a second semiconductor layer including a region overlapping with the second opening; processing the first conductive film and forming a fourth conductive layer including a region overlapping with the third conductive layer; Forming a fifth insulating layer over the second semiconductor layer, the fourth conductive layer and the fourth insulating layer; forming a second conductive film over the fifth insulating layer; processing the second conductive film and forming a fifth conductive layer including a region overlapping with the second semiconductor layer; Forming a sixth insulating layer over the fifth conductive layer and the fifth insulating layer; processing a top surface of the sixth insulating layer and a top surface of the fifth conductive layer to make their heights substantially equal with respect to a substrate surface; Forming a sixth conductive layer in contact with the top surface of the fifth conductive layer; Forming a seventh insulating layer over the fifth conductive layer and the sixth insulating layer; forming a third conductive film over the seventh insulating layer; processing the third conductive film and the seventh insulating layer and forming a third opening reaching the sixth conductive layer; Forming a third metal oxide film in contact with a top surface of the sixth conductive layer in the third opening, a side surface of the seventh insulating layer in the third opening, a side surface of the third conductive film in the third opening, and a top surface of the third conductive film; processing the third metal oxide film and forming a third semiconductor layer including a region overlapping with the third opening; processing the third conductive film and forming a seventh conductive layer including a region overlapping with the sixth conductive layer; Forming an eighth insulating layer over the third semiconductor layer, the seventh conductive layer and the seventh insulating layer; forming a fourth conductive film over the eighth insulating layer; and Processing the fourth conductive film and forming an eighth conductive layer including a region overlapping with the third semiconductor layer.

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