Metal-insulator-metal (MIM) capacitors with curved electrode

Abstract

A method of manufacturing a metal-insulator-metal (MIM) capacitor by etching a dielectric layer to form a via or contact hole, a well, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the well, and the trench, wherein the deposited conformal metal forms a via or contact in the via hole or contact hole; depositing a bottom electrode metal in the well to form a bottom electrode of a metal-to-metal (MIM) capacitor, removing the bottom electrode metal from the bottom electrode to form a cup-shaped top surface; depositing an insulator material on the bottom electrode to form an insulator layer of the MIM capacitor, and depositing a top electrode metal on the insulator layer to form a top electrode of the MIM capacitor.

Description

RELATED PATENT APPLICATIONS

[0001] This application claims priority to commonly owned U.S. Patent Application No. 63 / 426,256 filed November 17, 2022, the entire contents of which are hereby incorporated by reference for all purposes. TECHNICAL FIELD

[0002] The present disclosure relates to metal-insulator-metal (MIM) capacitors, e.g., MIM capacitors in analog / mixed-signal / RF CMOS circuits. BACKGROUND

[0003] A metal-insulator-metal (MIM) capacitor is a capacitor made up of a metal top electrode, a metal bottom electrode, and an insulator (dielectric) sandwiched between the two metal electrodes.

[0004] MIM capacitors are critical components in many electrical circuits, including many analog, mixed-signal, and high-frequency circuits using complementary metal oxide semiconductor (RF CMOS) devices. MIM capacitors generally provide better performance than alternatives such as POP (poly-oxide-poly) capacitors and MOM (metal-oxide-metal lateral flux) capacitors due to lower resistance, better matching, and / or better signal-to-noise ratio.

[0005] MIM capacitors are typically provided directly beneath the top metal layer, for example, by using the existing top-1 metal layer as the bottom electrode, constructing a top electrode from another metal (e.g., Ti / TiN, Ta / TaN, W), and connecting an overlying top metal layer to the top and bottom electrodes of the capacitor by appropriate vias.

[0006] Conventional MIM capacitors are constructed on an aluminum composite and include an insulator layer formed between an aluminum bottom electrode (top-1 metal layer) and a top electrode made of metal (e.g., Ti, TiN, or Al). The Al bottom electrode and the top electrode made of metal are each connected to a corresponding pad (top metal layer) via one or more vias, which are formed, for example, by filling a via with tungsten (W) or another suitable metal. The insulator layer can be, for example, a SiN layer with a thickness of approximately 500 Å.

[0007] Another conventional MIM capacitor is built on a copper (Cu) bottom electrode and includes an insulator layer formed between a Cu bottom electrode (top-1 metal layer) and a top electrode made of metal (e.g., Ta, TaN, or TiN). The Cu bottom electrode and the top metal electrode are each connected to a corresponding pad (top metal layer) via one or more vias, which are formed, for example, by filling a via with copper or another suitable metal. As with a capacitor built on Al interconnects, the insulator layer of a capacitor built on Cu interconnects can be a SiN layer, for example, having a thickness of about 500 Å. An insulator layer also serves as a dielectric diffusion barrier for the copper of the bottom electrode.

[0008] As used herein, a "via" refers to a conductive via formed by plugging or otherwise depositing a conductive material (e.g., tungsten) in a via hole with a small diameter or width, e.g., a diameter or width of less than 1 µm, and thus having a relatively large resistance, e.g., a resistance of at least 1 ohm per via hole. For example, conventional vias typically have a small diameter in the range of 0.1 µm to 0.5 µm and may have a resistance of, e.g., about 10 ohms / via hole, particularly for vias formed of tungsten or another high-resistance material. Therefore, conventional MIM capacitors often include multiple via holes (e.g., multiple vias between the top electrode and the top electrode pad and / or multiple vias between the bottom electrode and the bottom electrode pad) to reduce the overall resistance to some extent.In the context of an MIM capacitor, the term “via connection” refers to a via that extends from a capacitor electrode (top electrode or bottom electrode) to an overlying conductive pad.

[0009] MIM capacitors can also be constructed between a poly (e.g., polysilicide) layer and a metal layer. The poly layer can be connected to a pad in a metal layer through one or more contacts, each formed by filling a contact hole with a suitable material. As used herein, a "contact" refers to a conductive contact formed by plugging or otherwise depositing a conductive material (e.g., tungsten) in a contact hole that has a small diameter or width, e.g., a diameter or width of less than 1 µm, and thus has a relatively large resistance, e.g., a resistance of at least 1 ohm per contact.For example, conventional contacts typically have a small diameter in the range of 0.1 µm to 0.5 µm and can have a resistance of approximately 10 ohms / contact, particularly for contacts made of tungsten or another high-resistance material. Conventional MIM capacitors therefore often incorporate multiple contacts (e.g., multiple contacts between the poly / active layer forming a bottom electrode and a bottom electrode pad) to reduce the overall resistance to some extent. In the context of an MIM capacitor, the term "contact interconnect" refers to a contact extending from a polycapacitor electrode to an overlying conductive pad.

[0010] As stated above, MIM capacitors can offer better performance than other alternatives due to their lower resistance, better matching, and better signal-to-noise ratio. For example, MIM capacitors offer better performance than POP (Poly-Oxide-Poly) and MOM (Metal-Oxide-Metal Lateral Flux) capacitors. Furthermore, with MIM capacitors, the resistance of the top and bottom electrodes usually affects the performance of the MIM capacitor, especially when used in RF applications. Furthermore, MIM capacitors are typically expensive to manufacture, for example, compared to other specific types of capacitors. For example, compared to POP (Poly-Oxide-Poly) and MOM (Metal-Oxide-Metal Lateral Flux) capacitors, MIM capacitors require additional mask layers and many additional process steps.

[0011] A conventional MIM capacitor can be constructed with a top electrode, a bottom electrode, and an insulator (dielectric) between them, hence metal-insulator-metal (MIM). The MIM capacitor can be constructed between an Mx metal layer and an Mx+1 metal layer. The MIM capacitor includes an insulator layer formed between a bottom electrode (a portion of the Mx metal layer) and a top metal electrode. The bottom electrode and the top metal electrode are each connected to a corresponding contact and one or more vias. Pads can be etched or formed into the Mx+1 metal layer.

[0012] Typically, MIM capacitors are manufactured with an additional mask layer to define the top electrode and are therefore more expensive to manufacture than MOM and POP capacitors. If the bottom electrode is made of aluminum, it can be rough and have bumps or protrusions that cause a low and uncontrolled breakdown voltage. Conventional MIM capacitors can suffer from low and uncontrolled breakdown voltage due to bumps or protrusions located in the bottom electrode, especially with aluminum bottom plates. A bump is a protrusion large enough to significantly reduce the breakdown voltage of the MIM capacitor.

[0013] There is a need for MIM capacitors that can be manufactured more cost-effectively, especially without the additional mask layer, and that have improved breakdown voltage by having fewer hillocks. SUMMARY OF THE INVENTION

[0014] The invention includes a method for constructing an MIM capacitor in an MIM module that can be performed concurrently with the construction of an interconnect structure without the use of additional masks. One aspect of the method constructs an MIM capacitor without a mask by etching a trench into a dielectric layer such that a first chemical mechanical polishing (CMP) of the entire integrated circuit structure removes the metal of the bottom electrode adjacent to the trench to a depth sufficient to construct an MIM capacitor whose bottom electrode lies below the top surface of the dielectric layer. Since the bottom electrode of the MIM capacitor lies below the top surface of the dielectric layer, a second CMP polishes the dielectric layer material away from the rest of the chip without damaging the dielectric layer of the MIM capacitor.Aspects further include an MIM capacitor in an MIM module, the MIM capacitor having a cup-shaped bottom electrode.

[0015] One aspect provides a method comprising: etching a dielectric layer to form a via or contact hole, a well, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the well, and the trench, wherein the deposited conformal metal forms a via or contact in the via or contact hole; depositing a metal bottom electrode in the well to form a bottom electrode of a metal-to-metal (MIM) capacitor; removing a portion of the bottom electrode metal from the bottom electrode to form a cup-shaped top surface of the bottom electrode; depositing an insulator material on the bottom electrode to form an insulator layer of the MIM capacitor, and depositing a top electrode metal on the insulator layer to form a top electrode of the MIM capacitor.

[0016] According to one aspect, a device is provided comprising: a metal-insulator-metal (MIM) capacitor comprising: a bottom electrode comprising a bottom electrode metal and having a cup-shaped top surface; a top electrode comprising a top electrode metal and having a substantially convex bottom surface disposed opposite the cup-shaped top surface of the bottom electrode; and an insulator layer between the top electrode and the bottom electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The figures illustrate exemplary methods for constructing an MIM capacitor in an MIM module simultaneously with an interconnect structure without the use of additional masks, and exemplary MIM capacitors having cup-shaped bottom electrodes. Fig. Figure 1 shows a cross-section and a side view of a metal-insulator-metal (MIM) module having an MIM capacitor constructed with a curved top electrode, a curved bottom electrode, and a curved insulator (dielectric) therebetween. Fig. 2 shows a cross-section and a side view of an interconnect structure and an MIM module including an MIM capacitor, wherein the MIM capacitor has a cup-shaped surface. Fig. Figure 3A shows a cross-section and a side view of a wafer and an etched dielectric layer for building an MIM capacitor in an MIM module simultaneously with an interconnect structure. Fig. Figure 3B shows a top view of the wafer of Fig. 3A, where the trench is a continuous trench surrounding the tub. Fig. Figure 3C shows a top view of the wafer of Fig. 3A, where the trench may be segmented, for example four trenches in four directions surrounding the tub but not connected. Fig. 3D shows a cross-section and a side view of the wafer from Fig. 3A with a conformal metal layer deposited thereon for constructing an MIM capacitor in an MIM module simultaneously with an interconnect structure. Fig. Figure 3E shows a side cross-sectional view of the wafer from Fig. 3B, after bottom electrode metal has been deposited on the wafer. Fig. Figure 3F shows a cross-section and a side view of the connection structure and the MIM module from Fig. 3C after a first chemical mechanical polishing (CMP) of the wafer. Fig. Figure 3G shows a cross-section and side view of the interconnect structure and MIM module of Fig. 3D after applying an insulator and a metal top electrode. Fig. Figure 3H shows a cross-section and a side view of the connection structure and the MIM module from Fig. 3E after a second chemical mechanical polishing (CMP) of the wafer. Fig. Figure 3I shows a cross-sectional side view of the interconnect structure and MIM module of Fig. 3F, after an Mx+1 metal layer was deposited on the wafer. Fig. Figure 3J shows a cross-section and side view of the interconnect structure and MIM module of Fig. 3G, after the Mx+1 metal layer was patterned and etched. Fig. Figure 4 shows how the Preston equation can explain the metal removal rate of the bottom electrode. Fig. Figures 5A-5C show the effects of the Preston equation, where the removal rate can depend on the patterning density. Fig. Figure 6 shows a cross-section and side views of an MIM capacitor constructed between a silicided poly layer and an M1 metal layer. Fig. 7 shows a flowchart for a method for manufacturing an MIM capacitor. Fig. 8 shows a flowchart for a method of manufacturing an MIM capacitor. Fig. Figure 9 shows a side cross-sectional view of an MIM capacitor with curved surfaces.

[0018] The reference numerals for each illustrated element that appears in several different figures have the same meaning in all figures, and mention or discussion of an illustrated element in connection with a particular figure also applies to any other figure in which the same illustrated element is shown. DESCRIPTION

[0019] Aspects provide methods for constructing an MIM capacitor in an MIM module that can be performed simultaneously with the construction of an interconnect structure without the use of additional masks. MIM capacitors, for example, have cup-shaped bottom electrodes. It is not necessary to construct an interconnect structure simultaneously, and the method for constructing an MIM capacitor in an MIM module can be performed without simultaneously constructing an interconnect structure without exceeding the scope of the invention.

[0020] Fig. 1 shows a cross-section and side view of an MIM module 134 including an MIM capacitor 110. The MIM capacitor 110 may be constructed in a dielectric layer 140 between the Mx metal layer 128 and the Mx+1 metal layer 130. The dielectric layer 140 may include a well 144 and a trench 146. The well 144 is a recess in the dielectric layer 140 in which the MIM capacitor 110 may be constructed. The trench 146 is a recess in the dielectric layer 140 proximate the well 144 that facilitates the removal of material to form a curved electrode. The MIM capacitor 110 may be installed in the well 144 and include a bottom electrode 114, an insulating layer 112, and a top electrode 116. The bottom electrode 114 is located below the top surface 148 of the dielectric layer 140. The bottom electrode 114 and the top electrode 116 may be formed in the form of plates.A connection for the bottom electrode 156 may optionally be formed in the trench 146. The MIM capacitor 110 may be surrounded by trenches 146 (single or multiple trenches or dummy trenches) so that, in a polishing step, a portion of the bottom electrode material may be removed to create a slightly curved surface of the bottom electrode material in the dielectric layer 140 in which the MIM capacitor 110 is to be formed. Optionally, the trenches 146 may also serve as a connection for the bottom electrode 156. The bottom electrode 114 may be made of refractory metal and polished so that the surface is smooth and substantially free of bumps. For the purposes of this disclosure, "bump-free" means that the surface does not have bumps or protrusions large enough to significantly reduce the breakdown voltage of the MIM capacitor 110.Refractory metals are a class of metals that are highly resistant to heat and wear. In this disclosure, they are metals used in a semiconductor process (e.g., Ti, TiN, W, Ta, TaN, Co) whose melting point is well above 400°C. Because backend-of-the-line (BEOL) semiconductor processes are controlled to be below ~400°C, refractory metals cannot generate hillocks through thermal stress relief and can therefore provide capacitors with high and constant breakdown voltage. For example, tungsten or cobalt can be used without generating hillocks. A surface without hillocks can have a narrower breakdown voltage distribution because it has no outliers and can be the result of the use of refractory metals.Alternatively, with high radio frequency power, aluminum Al can be used during deposition (a so-called smooth metal), which has a large grain size and lower film roughness.

[0021] Fig. Figure 2 shows a cross-sectional and side view of an interconnect structure 232 and an MIM module 234 including an MIM capacitor 210. In this approach, an MIM capacitor 210 is built simultaneously with the interconnect structures 232, which does not require a mask added as part of the build process. The MIM capacitor 210 may be built in a dielectric layer 240 between the Mx metal layer 228 and the Mx+1 metal layer 230. The dielectric layer 240 may include a via hole 242, a well 244, and a trench 246. A well 244 is a recess in the dielectric layer 240 into which an MIM capacitor 210 may be incorporated, as described further below. A trench 246 is a recess in the dielectric layer 240 near a well 244 that facilitates the removal of material to form a curved electrode, as further described below.An MIM capacitor 210 may be constructed in the well 244 and include a bottom electrode 214, an insulator layer 212, and a top electrode 216. One or more vias 252 may be introduced into the via holes 242 of the interconnect structure 232. A connection of the bottom electrode 256 may optionally be formed in the trench 246. The capacitor 210 may be surrounded by trenches 246 (single or multiple trenches or dummy trenches) so that a portion of the bottom electrode material can be removed in a polishing step to allow the capacitor 210 to be formed in the well 244. The polishing step creates a slightly curved surface of the bottom electrode material in the dielectric layer 240 in which the capacitor 210 is to be formed. Optionally, the trenches 246 can also serve as a connection for the bottom electrode 256 in addition to using a via 252 (Via-x) made of tungsten W.The bottom electrode 214 may be made of refractory metal and polished so that the surface is smooth and substantially free of bumps. For the purposes of this disclosure, "bump-free" means that the surface does not have bumps or protrusions large enough to significantly reduce the breakdown voltage of the MIM capacitor 210.

[0022] Fig. 3A-3J illustrate an example method for forming an MIM capacitor according to one aspect. Each of the Fig. 3A-3J show cross-sectional views at two positions of an integrated circuit structure 300 under construction, namely a first position (labeled “Interconnect Structure” 332) where an upper metal level is formed that is connected to an Mx metal layer 328, e.g., a Cu MTOP layer, as shown in Fig. 3A, and a second position (labeled “MIM Module” 334) where an MIM capacitor 310 is constructed.

[0023] Fig. 3A shows side cross-sectional views of a wafer on which an MIM module 334 including an MIM capacitor may be fabricated. The Mx metal layer 328 may be, for example, any interconnect metal layer. The MIM module 334 may be fabricated at the same time as the interconnect structure 332. The MIM module 334 begins by applying a dielectric layer 340 to the Mx metal layer 328 of the wafer. Chemical mechanical planarization (CMP) may be performed. A photoresist layer (not shown) may be applied over the dielectric layer 340 and patterned to form via holes 342, a via layer 344, and a trench 346.

[0024] Etching may then occur through the openings in the photoresist layer to define the via hole(s) 342, the well 344, and the trench(es) 346 and expose the upper surface regions of the Mx metal layer 328. The via hole 342 is patterned into the dielectric layer 340 simultaneously with a well 344 (large-area well opening) and a trench 346 (a dummy structure surrounding the well 344 to reduce patterning density, as described further). The via holes 342 are small, typically in the range of 0.1µm-0.5µm, the well 344 is relatively large, e.g., in the range of 1µm-100µm, and the width of the trench 346 is between the diameter of the via hole 342 and the diameter or width of the well 344, e.g., in the range of 1µm-10µm. As shown in Fig. 3A, the tub 344 is surrounded by the trench 346. In Fig. 3A shows a single trench, but alternatively, multiple trenches of different widths can be used to achieve the desired pattern density variations. Dielectric layer 340 can be plasma etched to create the via hole(s) 342 in the interconnect structure 332, the well 344 in the MIM module 334, and the trench(es) 346 in a dummy structure around the well 344.

[0025] Fig. 3B shows a top view of the Fig. 3A, where trench 346 is a continuous trench around the perimeter of well 344. A portion of dielectric layer 340 extends completely around the perimeter of well 344 in which the MIM capacitor is built, with trench 346 extending completely around the perimeter of the portion of dielectric layer material 340. Fig. Figure 3C shows a top view of an alternative example of the Fig. 3A (as constructed), where trench 346 is a segmented trench comprising a series of separate trenches around the perimeter of well 344, for example, four trenches in four directions surrounding well 344 but not connected to each other, such that trench 346 extends partially around a perimeter of the portion of dielectric layer material 340 surrounding well 344.

[0026] Fig. Figure 3D shows the deposition of a conformal metal layer 360, for example, tungsten W, onto the wafer to fabricate an MIM capacitor. A titanium nitride TiN liner (not shown) or an adhesive layer may be deposited to a thickness of approximately 50Å–300Å, followed by the deposition of the conformal metal layer 360, for example, a tungsten W layer. The conformal metal layer 360 may be deposited by plasma-enhanced chemical vapor deposition (PECVD) so that it has a substantially uniform thickness on all exposed surfaces. The conformal metal layer 360, e.g., the tungsten W film, may have a relatively high tensile stress. The deposition thickness of the tungsten W layer can typically be limited to about 5000 Å and can have any suitable thickness to later define the insulator layer of the MIM capacitor to be formed, e.g., a thickness in the range of 200-1000 Å, e.g., 300-700 Å, e.g., 400-600 Å, or about 500 Å.If the conformal metal layer 360 is too thick, it may cause delamination or breakage of the wafer during subsequent chemical mechanical polishing (CMP) of the conformal metal layer 360. The via holes 342 in the dielectric layer 340 of the interconnect structure 332 may be completely filled with the conformal metal layer 360 to form via(s) 352, but the well 344 and trench 346 may be partially filled with the conformal metal layer 360.

[0027] Fig. Figure 3E shows how a bottom electrode is deposited on the wafer. A metal for the bottom electrode 370, e.g., titanium nitride (TIN) or titanium nitride (TIN) plus tungsten (W), can be deposited by physical vapor deposition (PVD) or a combination of PVD and chemical vapor deposition (CVD) processes. Titanium nitride (TIN) can exhibit compressive stresses (for films below 1 µm) and can be used to offset the tensile stresses of tungsten (W) for the conformal metal layer 360. Refractory metal (TiN, W, and others) does not produce hillocks when used for the bottom electrode, which also provides a higher, more uniform breakdown voltage.

[0028] Alternatively, aluminum Al with high radio frequency power can be used during deposition (a so-called smooth metal), which has a large grain size and lower film roughness. Fig. In the example illustrated in Figure 3E, the metal of the bottom electrode 370 covers the interconnect structure 332 and completely fills the trenches 346 of the MIM module 334. The metal of the bottom electrode 370 also substantially or at least almost completely fills the well 344 of the MIM module 334 to form a bottom electrode 314.

[0029] Fig. 3F shows cross-sectional side views of the interconnect structure 332 and the MIM module 334 after a first chemical mechanical polishing (CMP) of the wafer. CMP may be performed to remove the metal of the bottom electrode 370 and the conformal metal layer 360 outside the via(s) 352 of the interconnect structure 332. CMP may further remove a portion of the metal of the bottom electrode 370 and the conformal metal layer 360 from the well 344 and the trench(es) 346. The high downward force (HDF or high pressure) in combination with the patterns of the trenches 346 near the well 344 enables an intentional cupping of the MIM module 334, in particular the upper surface 318 of the metal of the bottom electrode 370 within the well 344 is cup-shaped, ie an upper surface 318 of the metal of the bottom electrode 370 has a convex function.To clarify: A convex function is a function where a line segment between any two points on the graph of the function lies above the graph between the two points. The polishing pressure can typically be 3-5 psi (pounds per square inch) or higher, and highly selective slurries (with a significantly higher polishing rate for metal than for dielectric materials) can be used for the initial CMP process. Due to the reduced patterning density provided by the trench 346 around the well 344 (the formation of the trench reduces the patterning density), CMP can penetrate into the metal of the bottom electrode 370 in the well 344 (essentially a depth D in a range of approximately 0.1 µm - 0.50 µm (i.e., 1000 angstroms - 5000 angstroms), e.g., of approximately 0.2 µm or 2000 A) and cupped into trench 346 (to a much lesser extent), creating a cupped (somewhat concave) top surface in the metal of bottom electrode 370, specifically bottom electrode 314. The top surface 318 of bottom electrode metal 370, which forms the bottom electrode of the MIM capacitor, thus lies below the top surface 348 of dielectric layer 340. The first CMP process can create a smooth, cupped top surface 318, providing a higher breakdown voltage MIM capacitor (as constructed). The first CMP process can remove a protrusion large enough to significantly reduce the breakdown voltage of the MIM capacitor. The polished, bowl-shaped top surface 318 of the bottom electrode 314 may be hillock-free, meaning that the surface does not have protrusions large enough to significantly reduce the breakdown voltage of the capacitor.

[0030] As in Fig. 3F, the curvature induced by CMP for polishing is microscopic and not significantly macroscopic. For example, polishing may be performed to a depth D between about 0.1 µm and about 0.5 µm, e.g., about 0.2 µm (2000 Å), in the vertical direction (depth D) over a horizontal scale (width W) between about 1 µm and about 100 µm, e.g., about 10 µm, representing a very slight deviation from a flat (planar) surface at an angle of about 2 degrees at the perimeter of the polish in the well 344 and the trench(es) 346. The cupped (somewhat concave) top surface 318 does not affect capacitance matching because all cupped top surfaces polished on a single wafer have approximately the same depth of recess. Capacitance matching is achieved when two capacitors have the same or very similar physical dimensions in order to maintain the same or very similar capacitance values.Capacitance matching can be an important characteristic for capacitors used in precision analog applications or in a SAR ADC (Successive Approximation Register Analog to Digital Converter). Variations in CMP polishing depth are more likely between two different wafer batches due to varying consumables such as polishing pads, polishing slurries, and other factors. Within a single wafer, especially within a chip (device), the variation in immersion depth can be very small, allowing capacitance matching to be maintained. Furthermore, the finished cup-shaped (slightly concave) top surface 318 of the bottom electrode 370, particularly the bottom electrode 314, can be polished to a smooth, bump-free surface.The polished bowl-shaped (slightly concave) top surface 318 may be hillock-free both at the time of manufacture and after subsequent thermal cycling, where the refectory metal is unlikely to produce hillocks due to stress relief by subsequent thermal processes.

[0031] As in Fig. As shown in Figure 4, the Preston equation can explain the use of a dummy trench pattern to create a curved bottom electrode metal 370 in the tub. The chemical mechanical polishing (CMP) removal rate can be proportional to the downward force and velocity. RR=Kp*P*V where RR = removal rate K p = Preston coefficient P = Applied pressure V = Linear velocity

[0032] The removal rate RR can increase with an increase in the downward pressure P and / or an increase in the linear velocity V.

[0033] Fig. Figures 5A-5C show the effects of the Preston equation, where the removal rate RR can depend on the local pattern density. By adjusting the local pattern density, the desired degree of comminution and erosion of the bottom electrode metal can be achieved. A difference in pattern density can lead to a difference in the polishing rate, so the sensitivity of the pattern density can be adjusted to achieve the desired polishing and erosion. Fig. Figure 5A shows a wafer with 10% patterning density (P actual = 10 * P applied ). The removal rate at 10% patterning density can be ten times the blanket removal rate because the actual applied pressure is ten times the applied pressure, as it is ultimately only applied to 10% of the wafer surface, although the total material removal may be similar. Fig. Figure 5B shows a wafer with 50% patterning density (P actual = 2 * P applied ). The removal rate at a structuring density of 50% can be twice the blanket removal rate, although the total amount of material removed may be similar. Fig. 5C shows a wafer without structure (P actual = P applied ), i.e. the wafer is already planarized.

[0034] Fig. 3G shows cross-sectional and side views of the interconnect structure 332 and the MIM module 334 after the deposition of an insulator layer 312 and a metal top electrode 380. The deposition of the insulator may be followed by the deposition of the metal top electrode. The insulator layer 312 may be a layer of silicon nitride (SiN) with a thickness of approximately 500 Å, deposited by PECVD (plasma-enhanced chemical vapor deposition) onto the finished cup-shaped (slightly concave) top surface 318 of the top electrode 370. Alternatively, the insulating layer 312 can also be made of silicon oxide or a high-k dielectric (κ > 7), such as Al2O3 (κ ~ 10), Ta2Os (κ ~ 25), HfO2 (κ ~ 22), ZrO2 (κ ~ 35), and others, and can be deposited by ALD (Atomic Layer Deposition) onto the finished cup-shaped (slightly concave) top surface 318 of the bottom electrode 370. The insulating layer 312 is thus similarly cup-shaped (slightly concave).The insulating layer 312 may have a substantially uniform thickness between the top electrode 316 and the bottom electrode 314. The top electrode metal 380 may be titanium nitride (TIN), titanium plus titanium nitride (Ti+TiN), titanium nitride plus tungsten (TIN+W), aluminum (Al), or other suitable metals deposited on the cup-shaped (slightly concave) insulator layer 312. Bumps in the top electrode metal are not necessarily significant for the breakdown voltage of the capacitor. By depositing both the insulator layer 312 and the top electrode metal 380, an MIM capacitor 310 may be constructed in the domed well 344. The MIM capacitor 310 may include a bottom electrode 314, an insulator layer 312, and a top electrode 316.

[0035] Fig. 3H shows cross-sectional side views of the interconnect structure 332 and the MIM module 334 after a second chemical mechanical polishing (CMP) of the wafer. The second CMP may be performed to remove the top electrode metal 380 and the insulator layer 312 outside the via(s) 352 of the interconnect structure 332 and outside the well 344 and trench(es) 346 of the MIM module 334. The second CMP process may planarize the surface of the wafer, including a top surface of the top electrode metal 380. A lower surface 317 of the top electrode metal 380, facing the insulator layer 312, is curved to mate with the upper surface of the cup-shaped (slightly concave) insulator layer 312, which in turn mates with the upper surface 318 of the bottom electrode 314, forming a curved top electrode metal 380 that forms a top electrode 316 in the well 344 of the MIM module 334.A difference between the first CMP procedure (see . Fig. 3F) and the second CMP procedure (see Fig. 3H) may primarily consist of the downward force (pressure) used. In the first CMP process, a high downward force (HDF, or high pressure) may be used along with dummy trench patterns around a tub to intentionally create a depression in the MIM module. The polishing pressure in the first CMP process may typically be 3-5 psi (pounds per square inch) or higher. The second CMP process may use low down force (LDF, or low pressure) to planarize the surface. The polishing pressure may be lower than the polishing pressure used for the first CMP process, e.g., 1-2 psi. The selectivity of the slurries used for the first CMP process and the second CMP process may also be different. In the first CMP process, a highly selective slurry may be used that polishes metals such as the conformal metal layer 360 and the bottom electrode metal 370 at a much higher rate than oxide.The second CMP process can use a low selectivity slurry that polishes metals such as the top electrode metal 380 at a similar rate to dielectrics (e.g., insulator layer 312 and oxide).

[0036] Fig. Figure 3I shows cross-sectional and side views of the interconnect structure 332 and the MIM module 334 after an Mx+1 metal layer 330 has been deposited on the wafer. This Mx+1 metal layer 330 can be formed as part of the CMOS interconnect structure.

[0037] Fig. 3J shows cross-sectional and side views of the interconnect structure 332 and the MIM module 334 after metal patterning and etching. The Mx+1 metal layer 330 may be patterned and etched. This may be part of the CMOS interconnect structure. To avoid short circuits, the top electrode metal layer 380 in the area between the well 344 and the trench(es) 346 may be etched through with a slight overetch. The MIM capacitor 310 is entirely constructed in the dielectric layer 340 between the Mx metal layer 328 and the Mx+1 metal layer 330. The MIM capacitor 310 includes a bottom electrode 314, an insulating layer 312, and a top electrode 316. The bottom electrode 314 is electrically connected to the Mx metal layer 328 via the bottom electrode metal 370 and the conformal metal layer 360 in the well 344.In the interconnect structure 332, a bottom electrode pad 322 is formed in the Mx+1 metal layer 330 and electrically connects to the Mx metal layer 328 through the via(s) 352. In one example, the Mx metal layer 328 of the interconnect structure 332 is formed contiguously with the Mx metal layer 328 of the MIM module 334. In the MIM module 334, a top electrode pad 320 in the Mx+1 metal layer 330 is electrically connected to the top electrode 316 via a portion of the top electrode metal layer 380. An optional bottom electrode connection pad 321 may also be formed in the Mx+1 metal layer 330 and electrically connected to the Mx metal layer 328 via a bottom electrode connection 356, which may be formed in a trench 346 through the conformal metal layer 360 and the bottom electrode metal 370. As shown in FIG. Fig. 3J, the MIM module 334 is complete and ready for the wafer to proceed with the construction of the CMOS interconnects.

[0038] As in Fig. 6, an MIM capacitor 610 can alternatively be constructed between a silicided poly layer and an M1 metal layer. In the case of polysilicide, the dielectric layer can be a polymetal dielectric (PMD) layer. The polysilicide layer 638 can be disposed on a poly layer 637. The MIM capacitor 610 can be constructed in a polymetal dielectric (PMD) layer 641 between a polysilicide layer 638 and an M1 metal layer 639. The MIM capacitor 610 includes a bottom electrode 614, an insulation layer 612, and a top electrode 616. The bottom electrode 614 is electrically connected to the polysilicide layer 638 via the bottom electrode metal 670 and the conformal metal layer 660 in the well 644.A bottom electrode pad 622 is formed in the M1 metal layer 639 and electrically connects to the polysilicide layer 638 via the contact(s) 653, in an example where the polysilicide layer 638 of the CMOS interconnect structure 636 is formed contiguously with the polysilicide layer 638 of the MIM module 634. A top electrode pad 620 in the M1 metal layer 639 is electrically connected to the top electrode 616 via the top electrode metal 680. An optional bottom electrode connection pad 621 may also be formed in the M1 metal layer 639 and electrically connected to the polysilicide layer 638 via a bottom electrode connection 656, which may be formed in a trench 646 through conformal metal 660 and bottom electrode metal 670. The bottom electrode 614 may be made of refractory metal and polished so that the surface is smooth and substantially free of hillocks.For the purposes of this disclosure, “hillock-free” means that the surface does not have hillocks or protrusions large enough to significantly reduce the breakdown voltage of the MIM capacitor 610.

[0039] The structure of the shell MIM capacitor can differ from other MIM structures. It can have a slightly curved insulator layer, and the bottom electrode surface can be smooth (polished) and free of bumps (refractory metals). Trenches (single or multiple) surrounding the well can be used to provide local patterning density, which facilitates polishing to create a curved bottom electrode surface and can optionally be bonded to the bottom electrode. Different patterning densities can provide different curved bottom electrode surfaces. The MIM capacitor can be constructed between two metal layers or between a silicided poly layer and an M1 metal layer.

[0040] Fig. Figure 7 shows a manufacturing method whereby an MIM capacitor can be manufactured simultaneously with interconnect structures without additional masks. Application 702 of a dielectric layer and etching of a via hole(s), a well, and a trench(s). The pattern of a trench(s) surrounding the well reduces the patterning density. See Fig. 3A-3C. Applying 704 conformal metal to form the via holes. A layer of tungsten W may be deposited by plasma-enhanced chemical vapor deposition (PECVD) and may be conformal, such that it is deposited with a substantially uniform thickness on all exposed surfaces. The via hole(s) may be completely filled with conformal metal of the conformal metal layer (e.g., tungsten W), but the well and trench(es) may be partially filled with conformal metal. See Fig. 3D. Applying bottom electrode metal 706 to form a bottom electrode. See Fig. 3E. Removal 708 of a portion of the bottom electrode metal to form a cup in the tub. The wafer is polished by chemical mechanical polishing (CMP) with high downward force (HDF or high pressure) and / or a highly selective slurry to remove the bottom electrode metal and the conformal metal outside the via hole, tub, and trench and to create a cup in the tub (to a greater extent) and in the trench (to a much lesser extent), resulting in a curved bottom electrode surface in the tub. See Fig. 3F. Applying 710 an insulator layer on the cup-shaped top surface 318, i.e., on the exposed surfaces, and coating the cup-shaped top surface 318 of the bottom electrode with metal 370. In one example, silicon nitride (SiN) is applied by PECVD (plasma enhanced chemical vapor deposition). Alternatively, silicon oxide or a high-k dielectric is applied by ALD (atomic layer deposition). See Fig. 3G. Applying 712 a top electrode metal to the insulator layer to overfill the shell, i.e., to completely cover the insulator layer and fill any depression caused by the removal 708. The top electrode may be made of titanium nitride (TIN), titanium plus titanium nitride (Ti+TiN), titanium nitride plus tungsten (TiN+W), aluminum (Al), or other suitable metals. See Fig. 3G, Removing 714 excess top electrode metal to form a top electrode in the shell. The wafer is polished by chemical mechanical polishing (CMP) with low down force (LDF) and / or a low selectivity slurry to planarize the surface and remove the top electrode metal and insulator outside the via hole, well, and trench. See Fig. 3H. Forming 716 a metal layer on the wafer by deposition, which may be part of the CMOS interconnect structure. See Fig. 3I. Structuring and etching 718 the metal layer through the top electrode metal layer in the area between the well and the trench, which may be part of the CMOS interconnect structure. See Fig. 3 years

[0041] Fig. 8 shows a method for building an MIM capacitor in an MIM module simultaneously with an interconnect structure without using an additional mask. Etching 802 a dielectric layer to form a via or contact hole, a well, and a trench in the dielectric layer. Depositing 804 conformal metal into the via or contact hole, the well, and the trench, wherein the deposited conformal metal forms a via or contact in the via hole or contact hole. Depositing 806 a bottom electrode metal in the well to form a bottom electrode of a metal-insulator-metal (MIM) capacitor. Removing 810 a portion of the bottom electrode metal from the bottom electrode to form a cup-shaped top surface. Depositing 812 an insulating material onto the bottom electrode to form an insulating layer of the MIM capacitor.Applying 814 a top electrode metal to the insulator layer to form a top electrode of the MIM capacitor.

[0042] Fig.Figure 9 shows a cross-section and side view of an MIM capacitor 910. The MIM capacitor 910 includes a bottom electrode 914, an insulating layer 912, and a top electrode 916. The bottom electrode 914 has a top cup-shaped surface 918. For the purposes of this disclosure, "cup-shaped surface" means a surface that is non-planar. The top electrode 916 has a substantially convex surface 917 opposite the cup-shaped surface 918 of the bottom electrode 914 and separated from the cup-shaped surface 918 of the bottom electrode 914 by the insulating layer 912, which is similarly shaped, ie, with a substantially convex surface opposite the cup-shaped surface 918 of the bottom electrode 914 and a substantially concave surface opposite the substantially convex surface 917 of the top electrode 916.

[0043] Aspects can be used in any wafer fab. The integration of the process described here can be compatible with the CMOS process flow of the manufacturing facilities.

[0044] Although examples have been described above, other variations and examples may be derived from this disclosure without departing from the spirit and scope of these disclosed examples. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 426,256

[0001]

Claims

[1] Method comprising: Etching a dielectric layer to form a via or contact hole, a well, and a trench in the dielectric layer; Depositing conformal metal in the via or contact hole, the well and the trench, wherein the deposited conformal metal forms a via or contact in the via or contact hole; Depositing a bottom electrode metal in the tub to form a bottom electrode of a metal-insulator-metal (MIM) capacitor; Removing a portion of the bottom electrode metal from the bottom electrode to form a cup-shaped top surface; Applying an insulator material to the bottom electrode to form an insulator layer of the MIM capacitor; and Applying a top electrode metal to the insulator layer to form a top electrode of the MIM capacitor. [2] The method of claim 1, wherein removing the portion of the bottom electrode metal from the bottom electrode comprises chemical mechanical polishing. [3] The method of claim 1 or 2, wherein removing the portion of the bottom electrode metal from the bottom electrode comprises chemical mechanical polishing with a downward force and a selectivity slurry sufficient to remove the portion of the bottom electrode metal from the tub. [4] The method of claim 1 or claim 3, wherein removing the portion of the bottom electrode metal from the bottom electrode of the MIM capacitor comprises removing a protrusion large enough to substantially reduce the breakdown voltage of the MIM capacitor. [5] The method of claim 1 or claim 2, wherein removing the portion of the bottom electrode metal from the bottom electrode comprises hollowing the bottom electrode to a depth of between about 0.1 µm and about 0.5 µm and a width of between about 1 µm and about 100 µm. [6] The method of claim 1 or claim 2, wherein removing the portion of the bottom electrode metal from the bottom electrode comprises removing the bottom electrode metal proximate the trench to a depth sufficient to fabricate an MIM capacitor having a bottom electrode below a top surface of the dielectric layer. [7] A method according to claim 1 or claim 2, wherein the via or contact is a via, and comprising: Applying the dielectric layer on a lower metal layer; Applying a top metal layer on the via and the top electrode; and Etching a pattern into the top metal layer to form a bottom electrode pad electrically connected to the bottom electrode through the via and to form a top electrode pad electrically connected to the top electrode. [8] A method according to claim 1 or claim 2, wherein the via or contact is a contact, and comprising: Applying the dielectric layer on a polysilicide layer; Applying a metal layer to the contact and the top electrode; and Etching a pattern into the metal layer to form a bottom electrode pad electrically connected to the bottom electrode through the contact and to form a top electrode pad electrically connected to the top electrode. [9] Device comprising: a metal-insulator-metal (MIM) capacitor having: a bottom electrode comprising a bottom electrode metal and having a cup-shaped top surface; a top electrode comprising a top electrode metal and having a substantially convex lower surface opposite the cup-shaped upper surface of the bottom electrode; and an insulator layer between the top electrode and the bottom electrode. [10] The device of claim 9, wherein the cup-shaped top surface of the bottom electrode has a depth between about 0.1 µm and about 0.5 µm and a width between about 1 µm and about 100 µm. [11] The device of claim 9 or claim 10, wherein the insulator layer has a substantially uniform thickness between the top electrode and the bottom electrode. [12] The device of claim 9 or claim 10, wherein the cup-shaped top surface of the bottom electrode does not have a protrusion large enough to substantially reduce the breakdown voltage of the MIM capacitor. [13] Apparatus according to claim 9 or claim 10, comprising: a trench comprising the bottom electrode metal; and a portion of the dielectric layer material, wherein the portion of the dielectric layer material lies between the trench and the MIM capacitor. [14] The device of claim 13, wherein the portion of the dielectric layer material extends partially around a perimeter of the MIM capacitor and wherein the trench extends partially around a perimeter of the portion of the dielectric layer material. [15] The device of claim 13, wherein the portion of the dielectric layer material extends completely around a perimeter of the MIM capacitor and wherein the trench extends completely around a perimeter of the portion of the dielectric layer material. [16] Apparatus according to claim 9 or claim 10, comprising: a lower metal layer electrically connected to the bottom electrode of the MIM capacitor; and an upper metal layer electrically connected to the top electrode of the MIM capacitor; a bottom electrode pad electrically connected to the bottom electrode by a via; and a top electrode pad that is electrically connected to the top electrode of the MIM capacitor. [17] Apparatus according to claim 9 or claim 10, comprising: a polysilicide layer electrically connected to the bottom electrode of the MIM capacitor and a metal layer electrically connected to the top electrode of the MIM capacitor; a ground electrode pad electrically connected to the ground electrode via a contact; and a top electrode pad that is electrically connected to the top electrode of the MIM capacitor. [18] Apparatus according to claim 9 or claim 10, comprising: a dielectric layer having a top surface, wherein a bottom electrode of the MIM capacitor lies below the top surface of the dielectric layer.

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