Stacked and unstacked transistors with double-sided connections

Abstract

A semiconductor structure is provided that includes a stacked transistor comprising at least one transistor stacked over another transistor and one non-stacked transistor integrated on a same wafer. Both the stacked transistor and the non-stacked transistor include front-side and back-side connections.

Description

BACKGROUND

[0001] The present application relates to semiconductor technology and, more particularly, to a semiconductor structure including a stacked transistor comprising at least one transistor stacked over another transistor and laterally adjacent to an unstacked transistor, wherein both the stacked transistor and the unstacked transistor include front and back connections.

[0002] A stacked transistor includes at least a first transistor stacked vertically above a second transistor. Stacking can enable smaller-scale devices and increase device density. Integrating a stacked transistor and a non-stacked transistor on a same wafer is attractive because the non-stacked transistor can provide a high-performance, low-density device (e.g., a logic device), whereas the stacked transistor can provide a low-performance, high-density device (e.g., a static random access memory (SRAM) device). The stacked transistor significantly reduces the area, and no design change to the non-stacked transistor is required. SUMMARY

[0003] A semiconductor structure is provided that includes a stacked transistor comprising at least one transistor stacked over another transistor and one unstacked transistor integrated on a same wafer. Both the stacked transistor and the unstacked transistor include front-side and back-side interconnects, further increasing the attractiveness of such an integrated device.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment of the present application, the semiconductor structure includes an unstacked transistor having a front side and a back side, and a stacked transistor laterally adjacent to the unstacked transistor and having a front side and a back side, wherein the stacked transistor includes two or more transistors stacked on top of each other. The semiconductor structure further includes a front-side interconnect located on the front side of both the unstacked transistor and the stacked transistor, and a back-side interconnect located on the back side of both the unstacked transistor and the stacked transistor. The structure of the present application combines a unit (e.g.A high-performance, low-density device (e.g., a logic device) with a low-performance, high-density device (e.g., an SRAM device) while simultaneously providing front-side and back-side interconnection. In this application, the term "front-side" refers to an area of ​​a wafer in which transistors (and other semiconductor devices) are formed, whereas the term "back-side" refers to an area of ​​a wafer opposite the area containing the transistors.

[0005] In embodiments of the present application, the front-side interconnect includes a multilayer front-side structure made of an interlayer dielectric (ILD) material in which front-side contact structures are embedded, and a front-side back-end-of-the-line (BEOL) structure located on the multilayer front-side structure made of an ILD material. The front-side contact structures enable electrical connection between the stacked transistor and the unstacked transistor with the front-side BEOL structure, and the front-side BEOL structure enables electrical connection to the remaining devices.

[0006] In embodiments of the present application, the semiconductor structure may further include a carrier wafer located on the front-side BEOL structure.

[0007] In embodiments of the present application, the front-side contact structures include a first front-side gate contact structure electrically connecting a gate structure of the unstacked transistor to the front-side BEOL structure, a second gate contact structure electrically connecting a gate structure of each of the transistors of the stacked transistor to the front-side BEOL structure, a first front-side source / drain contact structure electrically connecting a first source / drain region of the unstacked transistor to the front-side BEOL structure, and a second front-side source / drain contact structure electrically connecting a first source / drain region and a second source / drain region of a first transistor of the two or more transistors of the stacked transistor to the front-side BEOL structure.

[0008] In embodiments of the present application, the backside interconnect includes a first backside metal level including a plurality of first backside electrically conductive structures, and a second backside metal level located on the first backside metal level and including a plurality of second backside electrically conductive structures. The backside interconnect can supply current to the stacked transistor and the unstacked transistor without occupying any surface area on the frontside of the wafer for the same purpose (i.e., supplying current).

[0009] In embodiments of the present application, one of the first back-side electrically conductive structures of the plurality of first back-side electrically conductive structures is electrically connected to a second source / drain region of the unstacked transistor by a first back-side source / drain contact structure, and at least two other first back-side electrically conductive structures of the plurality of first back-side electrically conductive structures are electrically connected to a first source / drain region and a second source / drain region of a second transistor of the two or more transistors of the stacked transistor by second back-side source / drain contact structures.

[0010] In embodiments of the present application, one of the second backside electrically conductive structures is electrically connected to the first backside electrically conductive structure, which is electrically connected to the second source / drain region of the unstacked transistor through a first backside metal via.

[0011] In embodiments of the present application, another of the second backside electrically conductive structures is electrically connected to the first backside electrically conductive structures, which are electrically connected to the second source / drain region of one of the transistors of the stacked transistor by a second backside metal via.

[0012] In embodiments of the present application, the unstacked transistor is a nanosheet transistor. Nanosheet transistors are attractive because they provide smaller, high-density devices.

[0013] In embodiments of the present application, the two or more transistors of the stacked transistor are nanosheet transistors.

[0014] In embodiments of the present application, the structure may further include a dielectric structure separating each nanosheet transistor. The dielectric structure isolates the stacked transistors from each other.

[0015] In embodiments of the present application, the dielectric structure is continuous and includes a gate dielectric column, a middle dielectric insulation layer, a dielectric spacer, and a bottom dielectric insulation layer, wherein a first end of the middle dielectric insulation layer is connected to the gate dielectric column and a second end of the middle dielectric insulation layer is connected to the bottom dielectric insulation layer, the gate dielectric column is in contact with the front-side interconnect, and the bottom dielectric insulation layer is in contact with the back-side interconnect.

[0016] In embodiments of the present application, the middle dielectric insulating layer and the bottom dielectric insulating layer are oriented parallel to each semiconductor material nanosheet of each nanosheet transistor of the two or more transistors of the stacked transistor, and the dielectric gate trench pillar and the dielectric spacer are oriented perpendicular to each semiconductor material nanosheet of each nanosheet transistor of the two or more transistors of the stacked transistor.

[0017] In embodiments of the present application, the two or more transistors of the stacked transistor each have the same conductivity type.

[0018] In embodiments of the present application, the two or more transistors of the stacked transistor include an upper transistor having a first conductivity type and a lower transistor having a second conductivity type different from the first conductivity type.

[0019] In embodiments of the present application, the first conductivity type is an n-type and the second conductivity type is a p-type.

[0020] In embodiments of the present application, the first conductivity type is a p-type and the second conductivity type is an n-type.

[0021] In embodiments of the present application, the unstacked transistor and the stacked transistor have the same device height, and the unstacked transistor has a top surface and a bottom surface, wherein the top surface of the unstacked transistor is coplanar with a top surface of the stacked transistor, and the bottom surface of the unstacked transistor is coplanar with a bottom surface of the stacked transistor. This aspect of the present application means that the stacked transistor and the unstacked transistor are located on the same device level, thus allowing front-side and back-side connections to be easily formed.

[0022] In embodiments of the present application, the unstacked transistor includes vertically stacked semiconductor nanosheets, and each of the transistors of the stacked transistor includes vertically stacked semiconductor nanosheets, wherein a total number of vertically stacked semiconductor nanosheets of the unstacked transistor is equal to or greater than a total number of vertically stacked semiconductor nanosheets of the two or more transistors of the stacked transistor.

[0023] In embodiments of the present application, the unstacked transistor is a logic device and the two or more transistors of the stacked transistor are SRAM devices. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view illustrating a device layout including a region of an unstacked transistor device and a laterally adjacent region of a stacked transistor device used in the present application, each device region including a plurality of gate structures oriented parallel to each other and perpendicular to an active area region. Fig. 2A to 2B are cross-sectional views through Y1-Y1 and Y2-Y2, respectively, shown in Fig. 1, an exemplary structure that may be used in the present application, the exemplary structure including a layer of a sacrificial placeholder material located on a substrate and a first material stack of alternating layers of a first sacrificial semiconductor material and layers of a first semiconductor channel material. Fig. 3A to 3B are cross-sectional views of the respective Fig. 2A to 2B, after forming a hard mask over the first material stack in the region of the non-stacked transistor unit and recessing the first material stack in the region of the stacked transistor unit to provide a first material stack with reduced height in the region of the stacked transistor unit. Fig. 4A to 4B are cross-sectional views of the respective Fig. 3A to 3B, after forming a layer of a first sacrificial semiconductor material and another layer of a sacrificial placeholder material on the first material stack with reduced height in the region of the stacked transistor device and forming a second material stack of alternating layers of a second sacrificial semiconductor material and layers of a second semiconductor channel material. Fig. 5A to 5B are cross-sectional views of the respective Fig. 4A to 4B, after removing the hard mask over the first material stack in the region of the unstacked transistor unit, patterning the first material stack and the layer of sacrificial placeholder material in the region of the unstacked transistor unit to provide a first patterned material stack, patterning the second material stack, the further layer of sacrificial placeholder material, the layer of first sacrificial semiconductor material, and the first reduced-height material stack in the region of the stacked transistor unit to provide a second patterned material stack, and forming a shallow trench isolation pattern in the substrate and on the footprint of both the first and second patterned material stacks. Fig. 6A to 6E are cross-sectional views of the Fig. 5A to 5B after forming a sacrificial spacer on one side of the second patterned material stack and forming a layer of a sacrificial gate material and a layer of a sacrificial hard mask in both the region of the unstacked transistor unit and the region of the stacked transistor unit; it should be noted that Fig. 6A one in Fig. 1 shows the section Y1-Y1, Fig. 6B one in Fig. 1 shows the section X1-X1, Fig. 6C one in Fig. 1 shows section Y2-Y2, Fig. 6D one in Fig. 1 shows the section Y2'-Y2' and Fig. 6E one in Fig. 1 shows section X2-X2. Fig. 7A to 7E are cross-sectional views of the respective Fig. 6A to 6E after patterning the layer of a sacrificial hard mask and the layer of a sacrificial gate material to provide hard mask covered sacrificial gate structures in both the region of the unstacked transistor device and the region of the stacked transistor device. Fig. 8A to 8E are cross-sectional views of the respective Fig. 7A to 7E after removing the remaining layer of sacrificial placeholder material from the first patterned material stack and the sacrificial spacer and the remaining layers of sacrificial placeholder material from the second patterned material stack. Fig. 9A to 9E are cross-sectional views of the respective Fig. 8A to 8E illustrates an exemplary structure after processing a nanosheet device, comprising simultaneously forming a dielectric gate spacer along sidewalls of the hard mask-covered sacrificial gate structures in both the region of the unstacked transistor device and the region of the stacked device, a lower dielectric insulating layer in a first gap previously occupied by the layer of sacrificial placeholder material in the region of the unstacked transistor device, another lower dielectric insulating layer in a first gap previously occupied by the layer of sacrificial placeholder material in the region of the stacked transistor device, a middle dielectric insulating layer in a second gap previously occupied by the further layer of sacrificial placeholder material,in the region of the stacked transistor device and a gate spacer for the stacked device in a third gap previously occupied by the sacrificial spacer, converting the first patterned material stack into a first nanosheet-containing stack and the second patterned material stack into a second nanosheet-containing stack, recessing each nanosheet of a sacrificial semiconductor material present in the first and second nanosheet-containing stacks, forming an inner spacer laterally adjacent to each recessed nanosheet of a semiconductor material, and forming source / drain regions and front-side layers of a first ILD material in each of the device regions. Fig. 10A to 10E are cross-sectional views of the respective Fig. 9A to 9E after gate processing including removing the sacrificial gate structure to expose the nanosheet-containing material stacks in the respective device region, removing the recessed nanosheets of sacrificial semiconductor material from the exposed nanosheet-containing stack, forming a gate structure, and forming a gate dielectric pillar cutting into the gate structure in the stacked transistor device region. Fig. 11A to 11E are cross-sectional views of the respective Fig. 10A to 10E after forming a front-side interconnect including front-side contact structures, a front-side BEOL structure, and a carrier wafer. Fig. 12A to 12E are cross-sectional views of the respective Fig. 11A to 11E after flipping the wafer 180° to physically expose a backside of the substrate; in these drawings, the substrate includes a layer of a first semiconductor material, an etch stop layer, and a layer of a second semiconductor material. Fig. 13A to 13E are cross-sectional views of the respective Fig. 12A to 12E after removing the physically exposed layer of a first semiconductor material of the substrate to physically expose the etch stop layer of the substrate. Fig. 14A to 14E are cross-sectional views of the respective Fig. 13A to 13E after removing the physically exposed etch stop layer of the substrate to physically expose the layer of a second semiconductor material of the substrate. Fig. 15A to 15E are cross-sectional views of the respective Fig. 14A to 14E after removing the physically exposed layer of a second semiconductor material from the substrate. Fig. 16A to 16E are cross-sectional views of the respective Fig. 15A to 15E after forming a backside interconnect including a first backside metal level including a plurality of first backside electrically conductive structures and a second backside metal level located on the first backside metal level and including a plurality of second backside electrically conductive structures. Fig. 17 illustrates a semiconductor structure according to the present application including a region of an unstacked transistor device including a full-height nanosheet logic nFET and a full-height nanosheet logic pFET, and a region of a stacked transistor device including reduced-height stacked nanosheet SRAM FETs. DETAILED DESCRIPTION

[0024] The present application will now be described in more detail with reference to the following discussion and the drawings accompanying this application. It should be noted that the drawings of this application are provided for illustrative purposes only and, as such, are not drawn to scale. It should also be noted that like reference numerals refer to like and corresponding elements.

[0025] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of various embodiments of the present application. However, it will be apparent to one skilled in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order not to obscure the present application.

[0026] It is understood that when an element such as a layer, region, or substrate is referred to as being "on" or "over" another element, it may be directly on top of the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly above" another element, no intervening elements are present. It is also understood that when an element is referred to as being "below" or "under" another element, it may be directly below or under the other element, or intervening elements may be present. Conversely, when an element is referred to as being "directly below" or "directly beneath" another element, no intervening elements are present.

[0027] With reference first to Fig. 1 illustrates a device layout including a region 100 of an unstacked transistor device and a laterally adjacent region 102 of a stacked transistor device used in the present application. Each device region includes a plurality of gate structures, GS, oriented parallel to each other and perpendicular to an active area region, AA. The region 100 of the unstacked transistor device includes a cut X1-X1 extending in a longitudinal direction of the active area region, AA, and through the active area region, AA, and a Y1-Y1 extending in a longitudinal direction of the gate structures and through one of the gate structures, GS.The region 102 of the stacked transistor unit includes a cut X2-X2 running in a longitudinal direction of the active area, AA, and through the active area, AA, a Y2-Y2 running in a longitudinal direction of the gate structures and through one of the gate structures, GS, and a cut Y2'-Y1 located between two adjacent gate structures, GS, and in a source / drain region.

[0028] With reference to Fig. 2A to 2B illustrate an exemplary structure that may be used in the present application; Fig. 2A shows the area 100 of the unstacked unit and by the Fig. 1 shown section Y1-Y1, whereas Fig. 2B the area 102 of the stacked unit and by the Fig. 1 shows the section Y2-Y2. It should be noted that the section shown in Fig. 2A and Fig. 2B is a one-piece structure and is located on the same substrate (or wafer). It should be noted that the illustrated structure Fig. 2A and Fig. 2B includes a layer 12L of a sacrificial placeholder material located on a substrate 10 and a first material stack MS1 of alternating layers 14L of a first sacrificial semiconductor material and layers 16L of a first semiconductor channel material.

[0029] The substrate 10 may include a semiconductor substrate containing at least one semiconductor material having semiconductor properties. Examples of semiconductor materials that may be used in the present application to provide the substrate 10 include, but are not limited to, silicon (Si), a silicon-germanium (SiGe) alloy, a silicon-germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors. In some embodiments of the present application, the substrate 10 may be a solid semiconductor substrate, i.e., a substrate made entirely of at least one semiconductor material. In other embodiments of the present application, the substrate 10 may be a semiconductor-on-insulator (SOI) substrate, i.e.,, be a substrate containing a lower semiconductor material layer, a buried insulator layer and an upper semiconductor material layer.

[0030] In some embodiments and as described below in Fig. 12A to 12E, the substrate 10 may include a layer 10A of a first semiconductor material, an etch stop layer 10B, and a layer 10C of a second semiconductor material. The layer 10A of a first semiconductor material of the substrate 10 is made of a first semiconductor material. The layer 10C of a second semiconductor material of the substrate 10 is made of a second semiconductor material. The second semiconductor material providing the layer 10C of a second semiconductor material may be the same in composition as or different in composition from the first semiconductor material providing the layer 10A of a first semiconductor material. In some embodiments of the present application, the etch stop layer 10B of the substrate 10 may be made of a dielectric material such as silicon dioxide and / or boron nitride.In other embodiments of the present application, the etch stop layer 10B of the substrate 10 is composed of a third semiconductor material that differs in composition from the semiconductor material that provides both the layer 10A of a first semiconductor material and the layer 10C of a second semiconductor material. In one example, the layer 10A is composed of a first semiconductor material made of silicon, the etch stop layer 10B is composed of silicon dioxide, and the layer 10C is composed of a second semiconductor material made of silicon. In another example, the layer 10A is composed of a first semiconductor material made of silicon, the etch stop layer 10B is composed of silicon germanium, and the layer 10C is composed of a second semiconductor material made of silicon.

[0031] The sacrificial placeholder material layer 12L is comprised of a fourth semiconductor material that differs in composition from a topmost semiconductor material portion of the substrate 10, as well as from the semiconductor materials that provide the first sacrificial semiconductor material layers 14L and the first semiconductor channel material layers 16L. In one example, the sacrificial placeholder material layer 12L is comprised of a silicon-germanium alloy having a germanium content of 40 atomic percent to 75 atomic percent. Typically, the placeholder material layer 12L has a thickness of 5 nm to 20 nm.

[0032] As mentioned above, the first material stack, MS1, includes alternating layers 14L of a first sacrificial semiconductor material and layers 16L of a first semiconductor channel material. In some embodiments, and as shown in Fig. 2A to 2B, an equal number of layers 14L of a first sacrificial semiconductor material and layers 16L of a first semiconductor channel material are present. That is, the first material stack, MS1, may include an 'n' number of layers 16L of a first semiconductor channel material and an 'n' number of layers 14L of a first sacrificial semiconductor material, where n is an integer starting at one. As an example, the first material stack, MS1, includes three layers 14L of a first sacrificial semiconductor material and three layers 16L of a first semiconductor channel material.Each first sacrificial semiconductor material layer 14L is comprised of a fifth semiconductor material, whereas each first semiconductor channel material layer 16L is comprised of a sixth semiconductor material that differs in composition from the fifth semiconductor material; note that the fifth and sixth semiconductor materials both differ in composition from the fourth semiconductor material.

[0033] In some embodiments, the sixth semiconductor material providing each layer 16L of first semiconductor channel material is capable of providing high channel mobility for n-type FET devices. In other embodiments, the sixth semiconductor material providing each layer 16L of first semiconductor channel material is capable of providing high channel mobility for p-type FET devices. The fifth semiconductor material providing each layer 14L of first sacrificial semiconductor material and the sixth semiconductor material providing each layer 16L of first semiconductor channel material may include any of the semiconductor materials mentioned above for the substrate 10.In one example, each layer 14L of a first sacrificial semiconductor material is comprised of a silicon-germanium alloy having a germanium content of 20 atomic percent to 40 atomic percent (note that each layer 14L of a first sacrificial semiconductor material differs in composition from the aforementioned layer 12L of a sacrificial placeholder material), and the sixth semiconductor material provided by each layer 16L of a first semiconductor channel material is comprised of silicon.Other combinations of semiconductor materials are possible, provided that the fifth semiconductor material providing each layer 14L of a first sacrificial semiconductor material differs in composition from the sixth semiconductor material providing each layer 16L of a first semiconductor channel material, and the semiconductor materials providing both the layers 14L of a first sacrificial semiconductor material and the layers 16L of a first semiconductor channel material differ in composition from the semiconductor material providing the layer 12L of a sacrificial placeholder material.

[0034] Each layer 14L of a first sacrificial semiconductor material may have a first thickness, and each layer 16L of a first semiconductor channel material may have a second thickness. In the present application, a first thickness may be equal to, greater than, or less than the second thickness.

[0035] The Fig. The exemplary structure illustrated in Figures 2A-2B may be formed by first depositing the layer 12L of sacrificial placeholder material on the substrate 10 and then secondly depositing the first material stack, MS1, on the layer 12L of sacrificial placeholder material. The second deposition includes forming alternating continuous layers of the fifth semiconductor material and the sixth semiconductor material mentioned above. The first and second deposition may include chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or epitaxial growth.The terms "epitaxial growth" or "epitaxial growth" mean the growth of a semiconductor material on a growth surface of another semiconductor material, in which the semiconductor material being grown has the same crystalline properties as the growth surface of the other semiconductor material. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled, and the system parameters are set so that the depositing atoms impact the growth surface of the other semiconductor substrate with sufficient energy to move on the growth surface and align themselves with the crystal arrangement of the atoms of the growth surface. Examples of various apparatus for epitaxial growth processes that can be used in the present application include, for example,Rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature for epitaxial deposition is typically in the range of 550 °C to 900 °C. Although a higher temperature typically leads to faster deposition, the faster deposition can result in crystal defects and cracking in thin films.

[0036] With reference to Fig. 3A to 3B, the respective Fig. 2A to 2B after forming a hard mask 18 over the first material stack MS1 in the (in Fig. 3A) region 100 of the non-stacked transistor unit and a deepening of the first material stack MS1 in the (in Fig. 3B) to provide a first material stack MS1' of reduced height in the stacked transistor unit region 102.

[0037] The hard mask 18 is made of a hard mask material such as silicon dioxide, silicon nitride, or silicon oxynitride. The hard mask 18 may be formed by deposition of a hard mask material followed by lithographic patterning. The deposition of the hard mask material may include, for example, CVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD). Lithographic patterning includes lithography and etching. Lithography includes forming a photoresist material on a material or material stack that needs to be patterned, exposing the photoresist material to a radiation pattern, and developing the exposed photoresist material. The etching may include dry etching (i.e., reactive ion etching (RIE), ion beam etching (IBE) or plasma etching) and / or chemical wet etching.

[0038] Deepening the first material stack, MS1, in the stacked transistor unit region 102 may include a recess etch process. The recess etch process removes at least some, but not all, of the first semiconductor channel material layers 16L and the first sacrificial semiconductor material layers 14L. In some embodiments, the recess etch process stops on a surface of one of the underlying semiconductor channel material layers 16L within the first material stack, MS1. In one example, and as shown in Fig. 3B, two layers 16L of a first semiconductor channel material and two layers 14L of a first sacrificial semiconductor material are removed, such that only a single layer 16L of a first semiconductor channel material and a single layer 14L of a first sacrificial semiconductor material remain in the region 102 of the stacked transistor device.

[0039] With reference to Fig. 4A to 4B, the respective Fig. 3A to 3B illustrates the exemplary structure illustrated after forming a layer 14L of a first sacrificial semiconductor material and another layer 12L of a sacrificial placeholder material on the first material stack, MS1', with reduced height in the stacked transistor device region 102, and forming a second material stack, MS2, from alternating layers 15L of a second sacrificial semiconductor material and layers 17L of a second semiconductor channel material. In some embodiments, where the recess etch stops on one of the layers 14L of a first sacrificial semiconductor material, the formation of this additional layer of a first sacrificial semiconductor material on the first material stack, MS1', with reduced height may be omitted.The first sacrificial semiconductor material layer 14L, the further sacrificial placeholder material layer 12L, and the second material stack, MS2, may be formed using any of the above-mentioned deposition processes. The first sacrificial semiconductor material layer 14L and the further sacrificial placeholder material layer 12L formed on the first reduced-height material stack, MS1', in the stacked transistor device region 102 may include semiconductor materials as mentioned above for the sacrificial placeholder material layer 12L and the first sacrificial semiconductor material layer 14L, which may be used to form the second material stack shown in FIG. Fig. 2A to 2B were used.

[0040] In the second material stack, MS2, of alternating layers 15L of a second sacrificial semiconductor material and layers 17L of a second semiconductor channel material, there is an equal number of layers 15L of a second sacrificial semiconductor material and layers 17L of a second semiconductor channel material. That is, the second material stack, MS2, may include an 'm' number of layers 17L of a second semiconductor channel material and an 'm' number of layers 15L of a second sacrificial semiconductor material, where m is an integer starting at one. As an example, the second material stack MS2 includes a layer 15L of a second sacrificial semiconductor material and a layer 17L of a second semiconductor channel material.Each second sacrificial semiconductor material layer 15L is composed of the aforementioned fifth semiconductor material, whereas each second semiconductor channel material layer 17L is composed of a seventh semiconductor material that differs in composition from the fifth semiconductor material. In the present application, the seventh semiconductor material may be the same in composition as the sixth semiconductor material or may differ in composition from it. The seventh semiconductor material differs in composition from the fourth semiconductor material that has each of the above-mentioned fifth semiconductor material. Fig. 4B, layers 12L of a sacrificial placeholder material. The seventh semiconductor material can be selected to provide p-type or n-type transistors with increased channel mobility.

[0041] In embodiments of the present application, the number of layers 14L of a first sacrificial semiconductor material in the first material stack, MS1, in the region 100 of the unstacked transistor unit may be equal to or greater than the total number of layers 14L of a first sacrificial semiconductor material and layers 17 of a second semiconductor channel material present in the first material stack, MS1', with reduced height and in the second material stack, MS2, in the region 102 of the unstacked transistor unit. Note that in the present application, a top surface of the first material stack, MS1, in the region 100 of the unstacked transistor unit is coplanar with a top surface of the semiconductor material stack, MS2, in the region 102 of the stacked transistor unit.

[0042] With reference to Fig. 5A to 5B, the respective Fig. 4A to 4B illustrates the exemplary structure illustrated after removing the hard mask 18 over the first material stack, MS1, in the region 100 of the unstacked transistor unit, patterning the first material stack, MS1, and the layer 12L of sacrificial placeholder material in the region 100 of the unstacked transistor unit to provide a first patterned material stack, PS1, patterning the second material stack, MS2, the further layer 12L of sacrificial placeholder material, the layer 14L of first sacrificial semiconductor material, and the first material stack, MS1', with reduced height in the region 102 of the stacked transistor unit to provide a second patterned material stack, PS2, and forming a shallow trench isolation structure 20 in the substrate 10 and on the footprint of both the first and second patterned material stacks, PS1 and PS2.

[0043] The hard mask 18 may be removed using a material removal process such as planarization (e.g., chemical mechanical polishing (CMP)) or etching. Patterning in each of the device regions is typically performed using lithographic patterning simultaneously, as defined above. In embodiments, patterning of one of the device regions may be performed before patterning the other device region. The number of patterned material stacks in each device region may vary, provided that a first patterned material stack, PS1, and a second patterned material stack, PS2, are formed in the respective device region. In the present application, the first patterned material stack, PS1, present in the region 100 of the unstacked transistor device (see Fig. 5A) a remaining (i.e., non-etched) portion of the layer 12L of a sacrificial placeholder material and a remaining (i.e., non-etched) portion of the first material stack, MS1. In the present application, the second patterned material stack, PS2, present in the region 102 of the stacked transistor device (see Fig. 5B), a remaining (i.e., non-etched) portion of the layer 12L of a sacrificial placeholder material, a remaining (i.e., non-etched) portion of the first material stack, MS1', with reduced height, a remaining (i.e., non-etched) portion of both the layer 12L of a first sacrificial semiconductor material and the further layer 12L of a sacrificial placeholder material, and a remaining (i.e., non-etched) portion of the second material stack, MS2.

[0044] The shallow trench isolation structure 20 is comprised of any trench dielectric material, such as silicon oxide. In some embodiments, a dielectric trench liner, comprised of SiN, for example, may be present along a sidewall and a bottom wall of the trench dielectric material. The shallow trench isolation structure 20 may have a top surface coplanar with a top surface of the non-etched portion of the substrate 10. The shallow trench isolation structure 20 may be formed by first forming (by lithography and etching) a trench in an upper portion of the substrate 10, depositing the optional trench dielectric liner material and the trench dielectric material in the trench, and then performing an etch-back process.

[0045] With reference to Fig. 6A to 6E will be the Fig. 5A to 5B after forming a sacrificial spacer 26 on one side of the second patterned material stack, PS2, and forming a layer 22L of sacrificial gate material and a layer 24L of sacrificial hard mask in both the region 100 of the unstacked transistor device and the region 102 of the stacked transistor device.

[0046] The sacrificial spacer element 26 may be made of the fourth semiconductor material mentioned above with respect to the layer 12L of a sacrificial placeholder material, or of a metal oxide such as TiO xTypically, the sacrificial spacer 26 is composed of a fourth semiconductor material that matches the composition used to provide the sacrificial placeholder material layer 12L; this supports a one-step removal of the sacrificial placeholder material layers 12L and the sacrificial spacer 26. The sacrificial spacer 26 may be formed by deposition followed by a spacer etch; block mask technology may be used to protect the unstacked transistor device region 100 during the formation of the sacrificial spacer 26. The sacrificial spacer 26 has a top surface that is substantially (within ± 10%) coplanar with a top surface of the further sacrificial placeholder material layer 12L present in the second patterned material stack, PS2.

[0047] After the formation of the sacrificial spacer 26, the sacrificial gate material layer 22L and the sacrificial hard mask layer 24L are formed. The sacrificial gate material layer 22L includes at least one sacrificial gate material. In some embodiments, the sacrificial gate material layer 22L may further include a sacrificial gate dielectric material. The optional sacrificial gate dielectric material may be comprised of a dielectric material such as silicon dioxide. The sacrificial gate material may include, but is not limited to, polysilicon, amorphous silicon, amorphous silicon germanium, or amorphous germanium. The sacrificial hard mask layer 24L is comprised of one of the hard mask materials mentioned above for the hard mask 18.

[0048] Sacrificial gate material layer 22L and sacrificial hard mask layer 24L may be formed using a deposition process such as CVD, PECVD, PVD, or ALD. In the present application, sacrificial gate material layer 22L is deposited prior to deposition of sacrificial hard mask layer 24L. In some embodiments, the formation of sacrificial hard mask layer 24L may be omitted.

[0049] With reference to Fig. 7A to 7E, the respective Fig. 6A to 6E illustrates the exemplary structure shown after patterning the sacrificial hardmask layer 24L and the sacrificial gate material layer 22L to provide hardmask-covered sacrificial gate structures in both the unstacked transistor device region 100 and the stacked transistor device region 102. The number of hardmask-covered sacrificial gate structures may vary in each device region, provided that at least one hardmask-covered sacrificial gate structure is formed in each of the device regions. Each hardmask-covered sacrificial gate structure includes a remaining (i.e., unetched) portion of the sacrificial gate material layer 22L (hereinafter, sacrificial gate structure 22) and a remaining (i.e., unetched) portion of the sacrificial hardmask layer 24L (hereinafter, sacrificial gate mask 24). Patterning includes lithography and etching.It should be noted that the sacrificial gate mask 24 typically has a sidewall that is vertically aligned with a sidewall of the sacrificial gate structure 22. As shown in FIG. Fig. 7A, the sacrificial gate structure covered with a hard mask is located in the region 100 of the unstacked transistor device on top of and along opposite sidewalls of the first patterned material stack, PS1. As shown in Fig. As illustrated in Figure 7C, the hard mask covered sacrificial gate structure in the stacked transistor device region 102 is located on top of and along opposite sidewalls of the second patterned material stack, PS2.

[0050] With reference to Fig. 8A to 8E is the respective Fig. 7A to 7E illustrates the exemplary structure after removing the remaining layer 12L of sacrificial placeholder material from the first patterned material stack, PS1, and the [ ] from the second patterned material stack, PS2, and further removing the sacrificial spacer 26. The removal of the remaining layers 12L of sacrificial placeholder material and the sacrificial spacer 26 may be performed simultaneously using one or more wet chemical etching processes.Removing the remaining layer 12L of sacrificial placeholder material from the first patterned material stack, PS1, forms a first gap, G1, in the first patterned material stack, PS1, and removing the sacrificial spacer 26 and the remaining layers 12L of sacrificial placeholder material from the second patterned material stack, PS2, forms a first gap, G1, a second gap, G2, and a third gap, G3, in the second patterned material stack, PS2. Note that G1, G2, and G3 are interconnected, as shown in FIG. Fig. 8C. Furthermore, it should be noted that the remaining first and second material stacks, PS1 and PS2, are not free-floating, since the sacrificial gate structures covered with a patterned hard mask serve as an anchor element.

[0051] With reference to Fig. 9A to 9E will be the Fig. 8A to 8E illustrates the exemplary structure shown after processing a nanosheet device. Processing a nanosheet device may include simultaneously forming a dielectric gate spacer 30 along sidewalls of the hard masked sacrificial gate structures in both the unstacked transistor device region 100 and the stacked device region 102, a bottom dielectric isolation layer 28 in each first gap, G1, a middle dielectric isolation layer 32 in the second gap, G2, and a stacked device gate spacer 31 in the third gap, G3.The gate spacer dielectric 30, each lower dielectric insulating layer 28, the middle dielectric insulating layer 32, and the gate spacer 31 for the stacked unit are all made of the same dielectric spacer material, such as silicon dioxide, SiN, SiBCN, SiOCN, or SiOC. The gate spacer dielectric 30, each lower dielectric insulating layer 28, the middle dielectric insulating layer 32, and the gate spacer 31 for the stacked unit can be formed by a deposition process such as CVD, PECVD, or ALD.

[0052] After forming the gate dielectric spacer 30, each lower dielectric insulation layer 28, the middle dielectric insulation layer 32, and the gate spacer 31 for the stacked unit, the first patterned material stack, PS1, is converted into a first nanosheet-containing stack, NS1, and the second patterned material stack, PS2, is converted into a second nanosheet-containing stack, NS2. This conversion includes etching using at least each combination of the gate dielectric spacer 32 / sacrificial gate structure 22 as an etch mask. The etching may include, for example, a reactive ion etch. The term "nanosheet-containing stack" indicates that various material layers present in the stack are nanosheets.In the first nanosheet-containing stack, NS1, each remaining layer 14L of a first sacrificial semiconductor material may be referred to as a first sacrificial semiconductor material nanosheet 14 and each remaining layer 16L of a first semiconductor channel material may be referred to as a first semiconductor channel material nanosheet 16.In the second nanosheet-containing stack, NS2, each remaining layer 14L of a first sacrificial semiconductor material may be referred to as nanosheet 14 of a first sacrificial semiconductor material, each remaining layer 16L of a first semiconductor channel material may be referred to as nanosheet 16 of a first semiconductor channel material, each remaining layer 15L of a second sacrificial semiconductor material may be referred to as nanosheet 15 of a second sacrificial semiconductor material, and each remaining second semiconductor channel material 17L may be referred to as nanosheet 17 of a second semiconductor channel material.

[0053] Next, each nanosheet of sacrificial semiconductor material present in the first and second nanosheet-containing stacks, NS1 and NS2, is recessed using a recess etch process. The recess etch process is a lateral etch process selective for removing a portion of each nanosheet of sacrificial semiconductor material. Note that the recessed nanosheets of sacrificial semiconductor material have a width less than a width of each of the nanosheets of semiconductor channel material present in the first and second nanosheet-containing stacks, NS1 and NS2.

[0054] Next, an inner spacer 34 is formed laterally adjacent to each recessed nanosheet from a semiconductor material present in the first and second nanosheet-containing stacks, NS1 and NS2. Each inner spacer 34 is made of one of the dielectric spacer materials mentioned above for forming the gate dielectric spacer 30, each lower dielectric insulation layer 28, the middle dielectric insulation layer 32, and the gate spacer 31 for the stacked unit.The dielectric spacer material providing each inner spacer 34 may be the same or different in composition from the dielectric material providing the gate dielectric spacer 30, each lower dielectric insulation layer 28, the middle dielectric insulation layer 32, and the gate spacer 31 for the stacked unit. The inner spacer 34 is formed by deposition and etching.

[0055] Subsequently, source / drain regions and front-side layers of a first ILD material are formed in each of the device regions. Note that source / drain regions 36 of the unstacked device are formed in the region 100 of the unstacked transistor device (see Fig. 9B) extending outwardly from a sidewall of each nanosheet 16 of a first semiconductor channel material of the first nanosheet-containing stack, NS1, and a layer 38 of a first ILD material is formed on the source / drain regions 36 of the unstacked device. Underlying source / drain regions 40 are formed in the region 102 of the stacked transistor device (see Fig. 9E) extending outwardly from a sidewall of each nanosheet 16 of a first semiconductor channel material of the second nanosheet-containing stack, NS2, and top source / drain regions 42 are formed in the region 102 of the stacked transistor unit (see Fig. 9E) extending outwardly from a sidewall of each nanosheet 17 of a second semiconductor channel material of the second nanosheet-containing stack, NS2. The top source / drain regions 42 are separated from the bottom source / drain regions 40 by a dielectric material layer 41. Next, another layer 43 of a first ILD material is formed on top of and adjacent to the respective top source / drain regions 42. The first ILD material layer 38 and the another layer 43 of a first ILD material are both front-side layers of an ILD material.

[0056] In the present application, the formation of the source / drain regions and the front-side layer of a first ILD material within the region 100 of the non-stacked transistor unit may occur before or after the formation of the source / drain regions and the front-side layer of a first ILD material in the region 102 of the stacked transistor unit. The separate processing may be achieved using a block mask technology.

[0057] Each of the source / drain regions, including the unstacked device source / drain regions 36, the bottom source / drain regions 40, and the top source / drain regions 42, is comprised of a semiconductor material and a dopant. As used herein, a "source / drain" region may be a source region or a drain region depending on the subsequent wiring and the application of voltages during transistor operation. The semiconductor material providing each of the source / drain regions, including the unstacked device source / drain regions 36, the bottom source / drain regions 40, and the top source / drain regions 42, is comprised of one of the semiconductor materials mentioned above for the substrate 10.The semiconductor material providing the source / drain regions can be compositionally identical or different from any nanosheet of semiconductor channel material with which the source / drain region contacts. However, the semiconductor material providing each source / drain region differs in composition from any recessed nanosheet of sacrificial semiconductor material. The dopant present in the source / drain regions can be either a p-type dopant or an n-type dopant. The term "p-" refers to the addition of impurities into an intrinsic semiconductor, creating a deficiency of valence electrons. For a silicon-containing semiconductor material, examples of p-type dopants include, but are not limited to, boron, aluminum, gallium, phosphorus, and indium."n-" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. For a silicon-based semiconductor material, examples of n-type impurities include, but are not limited to, antimony, arsenic, and phosphorus. In one example, the source / drain regions may each have a dopant concentration of 4×10-6. 20 atoms / cm 3 up to 3×10 21 atoms / cm 3In some embodiments, the dopant within the upper source / drain regions 42 has the same conductivity type as the dopant within the lower source / drain regions 40. In other embodiments, the dopant within the upper source / drain regions 42 has a different conductivity type than the dopant within the lower source / drain regions 40. Consequently, and in the stacked transistor unit region 102, a transistor of the same conductivity type or different conductivity types may be formed. That is, in the stacked transistor unit region 102, two vertically stacked nFETs may be formed, or two vertically stacked pFETs may be formed, or an nFET stacked over a pFET may be formed, or a pFET stacked over an nFET may be formed.In the area of ​​the unstacked transistor unit, transistors of different conductivity types can also be formed.

[0058] The dielectric material layer 41, the layer 38 of a first ILD material present in the region 100 of the unstacked transistor unit, and the further layer 43 of a first ILD material formed in the region 102 of the stacked transistor unit may be formed using a deposition process (CVD, PECVD, ALD, or spin-on coating), followed by a recess etch (in the case of the formation of the dielectric material layer 41) and / or a planarization process (in the case of the ILD material layers 38, 43).The dielectric material layer 41, the first ILD material layer 38 present in the region 100 of the unstacked transistor device, and the further first ILD material layer 43 present in the region 102 of the stacked transistor device each consist of a dielectric material, including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof.The term "low-k," as used throughout this application, refers to a dielectric material having a dielectric constant of less than 4.0 (all dielectric constants mentioned herein are relative to a vacuum unless otherwise noted). The dielectric material providing the dielectric material layer 41 may be the same or different in composition than the dielectric material providing the further layer 43 of a first ILD material. The dielectric material providing the layer 38 of a first ILD material may be the same or different in composition than the dielectric material providing the further layer 43 of a first ILD material.In the drawings, a dotted line is shown to indicate that a material interface may exist between these different dielectric materials.

[0059] As illustrated, the planarization process following the deposition process that provides the layers of a first ILD material in the respective device regions removes the sacrificial gate cap 24 and a top portion of each dielectric gate spacer 30.

[0060] With reference to Fig. 10A to 10E is the respective Fig. 9A to 9E illustrates the exemplary structure after gate processing, which includes removing the sacrificial gate structure 22 to expose the nanosheet-containing material stacks (i.e., NS1 or NS2) in the respective device region, removing the recessed nanosheets (14 or 14 / 15) of a sacrificial semiconductor material from the exposed nanosheet-containing stack, forming a gate structure (44, 45), and forming a dielectric gate cut pillar 46 that cuts into the gate structure 45 in the region 102 of the stacked transistor device. In the present application, the gate structure 44 is formed in the region 100 of the unstacked transistor device, whereas the gate structure 45 is formed in the region 102 of the stacked transistor device. In Fig. 10C, T1 denotes a first (or lower) transistor of a stacked transistor unit and T2 denotes a second (or upper) transistor of the stacked transistor unit.

[0061] In the present application, the gate processing in the region 100 of the unstacked device may be performed simultaneously with, before, or after the gate processing in the region 102 of the stacked device. Gate processing at different times may be achieved using block mask technology. Each sacrificial gate structure 22 may be removed by an etching process, such as reactive ion etching. Next, each recessed nanosheet (14, 15) of sacrificial semiconductor material may be removed using at least one material removal process that is selective in removing the nanosheets (14, 15) of sacrificial semiconductor material.

[0062] Gate structures 44, 45 are then formed. The gate structures 44, 45 include a gate dielectric material and a gate electrode, both of which are not shown separately, but which are intended to be located within a region defined by the gate structures 44, 45. As is known to those skilled in the art, the gate dielectric material directly contacts one or more physically exposed surfaces of each nanosheet of semiconductor channel material, and the gate electrode is formed on the gate dielectric material. The gate dielectric material has a dielectric constant of 4.0 or higher. Illustrative examples of gate dielectric materials include silicon dioxide, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiO xN y ), tantalum oxide (TaO x ), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and / or lead zinc niobide (Pb(Zn,Nb)O), but are not limited to these. The gate dielectric material may further contain dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg).

[0063] The gate electrode may include a work function metal (WFM) and optionally a conductive metal. The WFM may be used to set a threshold voltage of the transistor to a desired value. In some embodiments, the WFM may be selected to cause an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" means a shift of the effective work function of the work function metal-containing material to a conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV. Examples of materials that can cause an n-threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof.In other embodiments, the WFM can be selected to cause a p-threshold voltage shift. In one embodiment, the work function of the work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, "threshold voltage" is the lowest achievable gate voltage that turns on a semiconductor device, e.g., a transistor, by rendering the device channel conductive. As used herein, "p-threshold voltage shift" means a shift of the effective work function of the work function metal-containing material to a valence band of silicon in the silicon-containing material. Examples of such materials that can cause a p-threshold voltage shift include, but are not limited to, titanium nitride and tantalum carbide, hafnium carbide, and combinations thereof.The optional conductive metal may include, but is not limited to, aluminum (Al), tungsten (W), or cobalt (Co). In embodiments of the present application, the gate structure 44 may be the same or different in composition as the gate structure 45. The gate structure 44, 45 may be formed by depositing the gate dielectric material and a gate electrode material, followed by a planarization process. It should be noted that the gate structure 44 has the same height as the gate structure 45 and that the gate structure 44 has a bottom surface coplanar with a bottom surface of the gate structure 45, and that the top surface of the gate structure 44 is coplanar with a top surface of the gate structure 45.

[0064] A gate dielectric pillar 46 may be formed by forming an opening in the gate structure 45 and then filling (including deposition and planarization) this opening with one of the dielectric materials mentioned above for providing the gate dielectric spacer 30, each lower dielectric insulating layer 28, the middle dielectric insulating layer 32, and the gate spacer 31 for the stacked unit. Typically, the gate dielectric pillar 46 is composed of a dielectric material the same in composition as that used to provide the gate dielectric spacer 30, each lower dielectric insulating layer 28, the middle dielectric insulating layer 32, and the gate spacer 31 for the stacked unit.In the stacked transistor unit region 102, the gate dielectric column 46, the middle dielectric isolation layer 32, the stacked unit gate spacer 31, and the bottom dielectric isolation layer 28 together provide a continuous dielectric structure. Within this continuous dielectric structure, a first end of the middle dielectric isolation layer 32 is connected to the gate dielectric column 46, and a second end of the middle dielectric isolation layer 32 is connected to the bottom dielectric isolation layer 28 through the stacked unit gate spacer 31.In the present application, the middle dielectric insulating layer 32 and the bottom dielectric insulating layer 28 are oriented parallel to each semiconductor nanosheet 16, 17, and the gate dielectric pillar 46 and gate spacer 31 for the stacked unit are oriented perpendicular to each semiconductor nanosheet 16, 17. In the drawings, a dotted line is shown in this dielectric structure to highlight each element that provides this structure.

[0065] These steps form an unstacked transistor (including the gate structure 44 enclosing the vertically stacked first semiconductor nanosheets 16 and source / drain regions 36 located on either side of the gate structure 44) in the unstacked device region 100, and a first transistor (including the gate structure 45 enclosing the nanosheets 14 of a first semiconductor channel material and bottom source / drain regions 40) and a second transistor (including the gate structure 45 enclosing the nanosheet 17 of a second semiconductor channel material and top source / drain regions 42) in the stacked transistor device region 102, with the second transistor stacked over the first transistor.

[0066] With reference to Fig. 11A to 11E, the respective Fig. 10A to 10E illustrates an exemplary structure after forming a front-side interconnect including front-side contact structures 50, 51, 52, 53, a front-side BEOL structure 54, and a carrier wafer 56. Each front-side contact structure 50, 51, 52, 53 is located in a front-side layer 48 of a second ILD material.

[0067] In the present application, the front-side second ILD material layer 48 is first formed using one of the deposition processes mentioned above for forming the ILD material layers 38, 43. The front-side second ILD material layer 48 may include one of the dielectric materials mentioned above for the ILD material layers 38, 43. The dielectric material providing the front-side second ILD material layer 48 may be the same or different in composition from the dielectric material providing the first ILD material layer 38 and / or the further first ILD material layer 43. The various front-side ILD material layers may provide a multi-layer front-side ILD material structure.

[0068] Subsequently, front-side contact structures 50, 51, 52, 53 are formed using a metallization process that includes forming front-side contact openings in the at least one front-side layer of an ILD material and then filling (including deposition and planarization) each front-side contact opening with at least one contact conductor material. The contact conductor material may, for example, include a silicide liner such as Ni, Pt, NiPt, an adhesion metal liner such as TiN, and conductive metals such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or an alloy thereof. The front-side contact structures 50, 51, 53 may further include one or more contact liners (not shown). In one or more embodiments, the contact liner (not shown) may include a diffusion barrier material.Example diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, an alloy of these, or a stack of these, such as Ti / TiN and Ti / WC. In one or more embodiments where a contact liner is present, the contact liner (not shown) may include a silicide liner such as Ti, Ni, NiPt, etc., and a diffusion barrier material as defined above. In the present application, the front-side contact structure 50 contacts the gate structure 44 of the unstacked transistor and electrically connects the gate structure 44 to the front-side BEOL structure 54. The front-side contact structure 50 may therefore be referred to as a gate contact structure located in the unstacked device region 100.The front-side contact structure 51 contacts one of the source / drain regions 36 of the unstacked transistor and electrically connects this source / drain region to the front-side BEOL structure 54. The front-side contact structure 51 can therefore be referred to as a source / drain contact structure located in the region 100 of the unstacked device. The front-side contact structures 52 contact the gate structure 45 of the first and second transistors and connect these two gate structures 45 to the front-side BEOL structure 54. The front-side contact structures 52 can therefore be referred to as a gate contact structure located in the region 102 of the stacked device. The front-side contact structures 53 come into contact with the top source / drain regions 42 of the second transistor and electrically connect these source / drain regions to the front-side BEOL structure 54.The front contact structures 53 can therefore be referred to as top source / drain contact structures located in the region 102 of the stacked unit.

[0069] The front-side BEOL structure 54 may have one or more layers of a dielectric interconnect material embedded therein (including one of the dielectric materials mentioned above for the front-side first ILD material layers 38, 48) containing one or more interconnect regions (wherein the interconnect regions may include any electrically conductive metal or metal alloy). The front-side BEOL structure 54 may be formed using any interconnect processing technique. In some embodiments, the interconnect regions are Cu interconnect regions. The carrier wafer 56 may include one of the semiconductor materials mentioned above for the first semiconductor material layer 10. After the front-side BEOL structure 54 is formed, the carrier wafer 56 is bonded to the front-side BEOL structure 54.

[0070] With reference to Fig. 12A to 12E, the respective Fig. 11A through 11E illustrates the exemplary structure shown after flipping the wafer 180° to physically expose a backside of the substrate 10; in these drawings, the substrate 10 includes a layer 10A of a first semiconductor material, an etch stop layer 10B, and a layer 11C of a second semiconductor material. In this way, flipping may physically expose the first semiconductor layer 10C of the substrate 10. This flipping step enables backside processing of the exemplary structure. Backside processing occurs on a side of a wafer opposite the side on which the transistors have been formed. Flipping the structure may be performed manually or using a mechanical means such as a robotic arm.

[0071] With reference to Fig. 13A to 13E, the respective Fig. 12A through 12E illustrate the exemplary structure shown after removing the physically exposed layer 10A of a first semiconductor material from the substrate 10 to physically expose the etch stop layer 10B of the substrate 10. Removing the layer 10A of a first semiconductor material from the substrate 10 may be performed using a material removal process that is selective in removing the first semiconductor material that provides the layer 10A of a first semiconductor material.

[0072] With reference to Fig. 14A to 14E, the respective Fig. 13A to 13E illustrates the exemplary structure shown after removing the physically exposed etch stop layer 10B from the substrate 10 to physically expose the second semiconductor material layer 10C of the substrate 10. Removing the etch stop layer 10B includes a material removal process that is selective in removing the etch stop layer 10B.

[0073] With reference to Fig. 15A to 15E, the respective Fig. 14A to 14E illustrates the exemplary structure after removing the physically exposed layer 10C of a second semiconductor material from the substrate 10. It should be noted that in some embodiments where the substrate 10 is entirely made of a semiconductor material, a material removal process may be used instead of the one shown in Fig. 13A to 15E. Physically exposing the second semiconductor material layer 10C of the substrate 10 may be performed using a material removal process that is selective in removing this layer from the structure.

[0074] With reference to Fig. 16A to 16E, the respective Fig. 15A to 15E illustrate an exemplary structure after forming a backside interconnect, including a first backside metal level, M1, including a plurality of first backside electrically conductive structures 60, and a second backside metal level, M2, located on the first backside metal level, M1, and including a plurality of second backside electrically conductive structures 62. A via level including via structures 61 is located between the first and second metal levels; in the present application, the via structures 61 may be used to electrically connect the first metal level to the second metal level. Note that the via structure 61 may electrically connect one of the second backside electrically conductive structures 62 to one of the first backside electrically conductive structures 60.

[0075] In the present application, one of the first backside electrically conductive structures 60 is electrically connected by a first backside source / drain contact structure 59A to another source / drain region 36 of the transistor in the region 100 of the unstacked transistor unit, and at least two other first backside electrically conductive structures 60 are electrically connected by a second backside source / drain contact structure 59B to underlying source / drain regions (i.e., the source / drain regions 40) of a lower transistor in the region 102 of the stacked transistor unit.

[0076] Each of the first backside source / drain contact structure 59A, the second backside source / drain contact structure 59B, the plurality of first backside electrically conductive structures 60, the via structures 61, and the plurality of second backside electrically conductive structures 62 is embedded in a multilayer backside structure 58 made of an ILD material. The multilayer backside structure 58 made of an ILD material includes a plurality of dielectric materials (including one of the dielectric materials mentioned above for the various frontside layers of an ILD material).

[0077] Each of the first backside source / drain contact structure 59A, the second backside source / drain contact structures 59B, the plurality of first backside electrically conductive structures 60, the via structures 61, and the plurality of second backside electrically conductive structures 62 may be formed by a metallization process as described above, and each of the second backside source / drain contact structures 59B, the plurality of first backside electrically conductive structures 60, the via structures 61, and the plurality of second backside electrically conductive structures 62 is made of at least one contact conductor material (and any of the optional materials) mentioned above for the frontside contact structures 50, 51, 52, 53.

[0078] The various embodiments of the present application as described above provide a structure as shown in Fig. 17, which combines a high-performance, low-density unit (e.g., a logic unit) with a low-performance, high-density unit (e.g., an SRAM unit). It should be noted that Fig. 17 illustrates a semiconductor structure according to the present application including a region 100 of an unstacked transistor device containing a full-height nanosheet logic nFET and a full-height nanosheet logic pFET, and a region 102 of a stacked transistor device containing stacked reduced-height nanosheet SRAM FETs. For clarity, the front-side and back-side connections are shown in Fig.17 not shown. The full-height nanosheet logic nFET includes nFET nanosheets 70 of a semiconductor channel material and an nFET gate structure, GS1, and the full-height nanosheet logic pFET includes pFET nanosheets 71 of a semiconductor channel material and a pFET gate structure, GS2. The reduced-height stacked nanosheet SRAM FETs include a pair of stacked nFETs including nFET nanosheets 70 of a semiconductor channel material and nFET gate structures, GS1, and a stacked pFET including pFET nanosheets 71 of a semiconductor channel material and pFET gate structures, GS2. The nFET and pFET nanosheets 70, 71 comprise a semiconductor channel material as mentioned above, and the nFET gate structures, GS1, and the pFET gate structures, GS2, comprise a dielectric gate material and a gate electrode as mentioned above.

[0079] While this application has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the above and other changes in form and detail may be made without departing from the spirit and scope of this application. Therefore, this application is not intended to be limited to the precise forms and details described and illustrated, but is intended to be within the scope of the appended claims.

Claims

[1] Semiconductor structure that has: a non-stacked transistor having a front side and a back side; a stacked transistor laterally adjacent to the unstacked transistor and having a front side and a back side, the stacked transistor comprising two or more transistors stacked on top of one another; a front-side connection located on the front side of both the unstacked transistor and the stacked transistor; and a back connection located on the back of both the unstacked transistor and the stacked transistor. [2] The semiconductor structure of claim 1, wherein the front-side interconnect comprises a multi-layer front-side structure of an interlayer dielectric material, ILD material, in which front-side contact structures are embedded, and a front-side back-end-of-the-line structure, BEOL structure, located on the multi-layer front-side structure of an ILD material. [3] A semiconductor structure according to claim 2, further comprising: a carrier wafer located on the front-side BEOL structure. [4] Semiconductor structure according to claim 2, wherein the front-side contact structures a first front-side gate contact structure electrically connecting a gate structure of the unstacked transistor to the front-side BEOL structure, a second gate contact structure electrically connecting a gate structure of each of the transistors of the stacked transistor to the front-side BEOL structure, a first front-side source / drain contact structure electrically connecting a first source / drain region of the unstacked transistor to the front-side BEOL structure, and a second front-side source / drain contact structure electrically connecting a first source / drain region and a second source / drain region of a first transistor of the two or more transistors of the stacked transistor to the front-side BEOL structure. [5] The semiconductor structure of claim 4, wherein the backside interconnect comprises a first backside metal level having a plurality of first backside electrically conductive structures and a second backside metal level located on the first backside metal level and having a plurality of second backside electrically conductive structures. [6] Semiconductor structure according to claim 5, wherein one of the first rear-side electrically conductive structures of the plurality of first rear-side electrically conductive structures is electrically connected to a second source / drain region of the unstacked transistor by a first rear-side source / drain contact structure, and at least two other first rear-side electrically conductive structures of the plurality of first rear-side electrically conductive structures are electrically connected to a first source / drain region and a second source / drain region of a second transistor of the two or more transistors of the stacked transistor by second rear-side source / drain contact structures. [7] The semiconductor structure of claim 6, wherein one of the second backside electrically conductive structures is electrically connected to the first backside electrically conductive structure, which is electrically connected to the second source / drain region of the unstacked transistor by a first backside metal via. [8] The semiconductor structure of claim 6, wherein another of the second backside electrically conductive structures is electrically connected to the first backside electrically conductive structures, which are electrically connected to the second source / drain region of one of the transistors of the stacked transistor by a second backside metal via. [9] The semiconductor structure of claim 1, wherein the unstacked transistor is a nanosheet transistor. [10] The semiconductor structure of claim 9, wherein the two or more transistors of the stacked transistor are nanosheet transistors. [11] A semiconductor structure according to claim 10, further comprising: a dielectric structure separating each nanosheet transistor. [12] Semiconductor structure according to claim 11, wherein the dielectric structure is continuous and comprises a dielectric gate kerf column, a middle dielectric insulation layer, a gate spacer for the stacked unit, and a lower dielectric insulation layer, wherein a first end of the middle dielectric insulation layer is connected to the gate dielectric pillar and a second end of the middle dielectric insulation layer is connected to the lower dielectric insulation layer through the gate spacer for the stacked unit and the dielectric gate cut column is in contact with the front connection and the lower dielectric insulation layer is in contact with the rear connection. [13] Semiconductor structure according to claim 12, wherein the middle dielectric insulation layer and the lower dielectric insulation layer are oriented parallel to each semiconductor material nanosheet of each nanosheet transistor of the two or more transistors of the stacked transistor, and the dielectric gate cut column and the gate spacer for the stacked unit are oriented perpendicular to each semiconductor material nanosheet of each nanosheet transistor of the two or more transistors of the stacked transistor. [14] The semiconductor structure of claim 1, wherein the two or more transistors of the stacked transistor each have a same conductivity type. [15] The semiconductor structure of claim 1, wherein the two or more transistors of the stacked transistor comprise an upper transistor having a first conductivity type and a lower transistor having a second conductivity type different from the first conductivity type. [16] The semiconductor structure of claim 15, wherein the first conductivity type is an n-type and the second conductivity type is a p-type. [17] The semiconductor structure of claim 15, wherein the first conductivity type is a p-type and the second conductivity type is an n-type. [18] The semiconductor structure of claim 1, wherein the unstacked transistor and the stacked transistor have a same unit height and the unstacked transistor has a top surface and a bottom surface, the top surface of the unstacked transistor being coplanar with a top surface of the stacked transistor and the bottom surface of the unstacked transistor being coplanar with a bottom surface of the stacked transistor. [19] The semiconductor structure of claim 1, wherein the unstacked transistor includes vertically stacked semiconductor nanosheets and each of the transistors of the stacked transistor includes vertically stacked semiconductor nanosheets, wherein a total number of vertically stacked semiconductor nanosheets of the unstacked transistor is equal to or greater than a total number of vertically stacked semiconductor nanosheets of the two or more transistors of the stacked transistor. [20] The semiconductor structure of claim 1, wherein the unstacked transistor is a logic device and the two or more transistors of the stacked transistor are static random access memory (SRAM) devices.

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