Semiconductor equipment and method for manufacturing a semiconductor equipment

Abstract

A semiconductor device (100) of the insulated gate type with a trench structure suppresses the degradation of the reliability of a semiconductor device. The semiconductor device has a source electrode (11) electrically connected to source regions adjacent to a trench (6) in a first region, and a gate line (18) located on the upper surface of a gate electrode (8) situated in a trench in a second region. The radius of curvature (Re) of the gate insulating layer located on the upper corner region of the trench in the second region is larger than the radius of curvature (Rc) of the gate insulating layer located on the upper corner region of the trench in the first region.

Description

Technical field

[0001] The invention disclosed in the description of the present application relates to semiconductor technology. State of the art

[0002] Insulated gate semiconductor devices, such as metal oxide semiconductor field-effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs), are widely used as switching elements in power electronics equipment, with the switching elements controlling the power supply to loads such as motors.

[0003] Some insulated-gate semiconductor devices have a trench structure, in which the gate electrodes are embedded in a semiconductor layer. These trench-structured insulated-gate devices can improve the channel width and density in an active region compared to planar-type insulated-gate devices, where the gate electrodes are located on the surface of a semiconductor layer. Consequently, the electrical resistance per unit area is low in the on-state of these semiconductor devices.

[0004] Up to now, in semiconductor devices with an insulated gate and a trench structure, a terminal area formed in the vicinity of the active region, a gate electrode, and a gate insulating layer formed within each trench, which acts as an opening, as well as near the upper corner of the trench on the active region side, are affected. In this case, when the semiconductor devices are switched on by applying a gate voltage, the electric field concentrates on the lower surface of the trench and near the upper corner of the trench, causing degradation of the gate insulating layer's insulation in these areas. As a result, the reliability of the semiconductor devices can deteriorate.

[0005] To solve this problem, a method is known in which a field relief area with conductivity is arranged on the lower surface of a trench, so that the electric field is reduced that is applied to a gate insulating layer arranged on the lower surface of the trench (see e.g. patent document 1).

[0006] A method is also known in which a structure has a deep narrow trench in the active area and a shallow wide trench in the terminal area, and gate electrodes formed in the trenches in the active area and in the terminal area are flattened by a subsequent chemical-mechanical polishing (CMP) process or by a combination of a subsequent CMP and etching processes, so that the upper corners of the trenches are not covered by the gate electrodes (see, for example, patent document 2). State-of-the-art documents, patent documents Patent Document 1: Japanese Unexamined Patent Application Publication (Translation of the PCT Application) JP 2001 - 511 315 A Patent Document 2: Japanese Unexamined Patent Application Publication (Translation of the PCT Application) JP 2006 - 520 091 A Summary Problem to be solved with the invention

[0007] To define the potentials of the gate electrodes, it is necessary to provide gate contacts (contact holes) on the gate electrodes, arranged in gate grooves within a cell array. Since the gate grooves in the cell array are formed with minimal processing dimensions, there are concerns about misintegration with contact masks. Consequently, in some cases, gate contacts can be placed on the top surface of the polysilicon, arranged in wide grooves in the terminal area, thus avoiding the need for gate contacts to be located within cells.

[0008] Even in this case, it is not possible to avoid the situation where the upper corner region of the trench is covered with polysilicon. This leads to a concentration of an electric field on the area of ​​the upper corner region of the trench that is covered with polysilicon, and it degrades the reliability of the semiconductor devices due to insulation degradation of the gate insulating layer.

[0009] However, the method in which a field relief zone is placed on the lower surface of a trench may not be able to suppress insulation degradation near the upper corner of the trench. Furthermore, the method, which uses a cmP process, is difficult to apply in practical situations because it requires significantly reducing influences such as warping or distortion of a semiconductor substrate, unevenness on the substrate surface, in-plane thickness uniformity of a layer formed on the semiconductor substrate, or unevenness on the layer caused by particles or other factors.

[0010] Furthermore, if the gate insulating layer and the gate electrode are continuously deposited by forming a wide trench in the terminal area, the gate electrode can be exposed over a large area in a subsequent etching process. As a result of the etching, its thickness may decrease or even disappear. This can destabilize the operation of insulated-gate semiconductor devices (the reliability of the semiconductor device may deteriorate). There are also cases where it is not possible to suppress insulation degradation near the upper corner of the trench.

[0011] The invention disclosed in the description of the present application was conceived in view of the problems described above, and it is an invention for suppressing the deterioration of the reliability of an insulated gate-type semiconductor device with a trench structure. Ways to solve the problem

[0012] A semiconductor device according to a first aspect of the invention, disclosed in the description of the present application, comprises the following: a drift layer of a first conductivity type, a base region of a second conductivity type arranged in a surface layer of the drift layer, a plurality of source regions of the first conductivity type arranged in a surface layer of the base region, at least one trench extending from an upper surface of the drift layer through the base region into the third layer, a protective layer of the second conductivity type arranged in the drift layer located below the trench, a gate insulating layer arranged along the interior of the trench, including an upper corner region of the trench, a gate electrode arranged at least in the trench and surrounded by the gate insulating layer, and a source electrode.The system consists of a source electrode, electrically connected to the source regions adjacent to the trench, and a gate lead located on an upper surface of the gate electrode running within the trench. Among the regions subdivided in the trench in plan view, the region where the source electrode is located is defined as the first region, and the region where the gate lead is located is defined as the second region. The gate insulating layer located on the upper corner region of the trench in the second region has a larger radius of curvature than the gate insulating layer located on the upper corner region of the trench in the first region. Effects of the invention

[0013] According to at least the first aspect of the invention disclosed in the description of the present application, it is possible to suppress the concentration of an electric field, even when a gate voltage is applied, and thereby to suppress destruction of the gate insulating layer.

[0014] The object, features, aspects and advantages relating to the invention disclosed in the description of the present application will become even clearer from the following detailed description and the accompanying drawings. Brief description of the drawings Fig. Figure 1 is a top view schematically showing an example of a configuration of a semiconductor device according to an embodiment of the invention. Fig. Figure 2 is a sectional view showing part of the configuration of the semiconductor device according to the embodiment. Fig. Figure 3 is a sectional view showing part of the configuration of the semiconductor device according to the embodiment. Fig. Figure 4 is a top view showing part of the configuration of the semiconductor device according to the embodiment. Fig. Figure 5 is a section view showing an example of a configuration of a cell range in the drawing. Fig. Figure 6 is a sectional view showing an example of a configuration of a gate contact area in the active area 20, which is located in Fig. 3 is shown. Fig. Figure 7 is a diagram showing an example of a method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 8 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 9 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 10 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 11 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 12 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 13 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 14 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 15 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 16 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 17 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 18 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 19 is a top view schematically showing another example of the configuration of the semiconductor device according to the embodiment. Fig. Figure 20 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 21 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 22 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 23 is a top view which schematically shows another example of the configuration of the semiconductor device according to the embodiment. Fig. Figure 24 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 25 is a diagram showing an example of the method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 26 is a sectional view that schematically shows another example of the configuration of the semiconductor device according to the embodiment. Fig. Figure 27 is a sectional view that schematically shows another example of the configuration of the semiconductor device according to the embodiment. Fig. Figure 28 is a sectional view that schematically shows another example of the configuration of the semiconductor device according to the embodiment. Fig. Figure 29 is a sectional view that schematically shows another example of the configuration of the semiconductor device according to the embodiment. Fig. Figure 30 is a sectional view that schematically shows another example of the configuration of the semiconductor device according to the embodiment. Description of embodiments

[0015] The following descriptions illustrate embodiments with reference to the accompanying drawings. While detailed features and the like are also described in the following description to explain the technology, they serve only for illustrative purposes, and not all of them are absolutely essential features necessary for implementing the embodiments.

[0016] The drawings are presented schematically, and for the sake of simplicity, configurations may be omitted or simplified as appropriate. The relationships in size and position between configurations or similar elements shown in various drawings are not always accurate and may be modified as necessary. To facilitate understanding of the embodiments, cross-hatching may be used in drawings that differ from sectional views, such as top views.

[0017] In the following description, identical elements with the same reference numerals in the drawings are assumed to have the same names and functions. Therefore, in some cases, the detailed description of such elements can be omitted to avoid redundancy.

[0018] With regard to the description given in the description of the present invention, the following applies: Phrases such as "have", "contain" or "have" are not mutually exclusive expressions that eliminate the possibility of the presence of other elements, unless otherwise specified.

[0019] In the description given in the description of the present invention, the following applies: ordinal numbers, such as "first" or "second", may occasionally be used, but they are used only for the purpose of simplifying the understanding of the contents of the embodiments and are not intended to be restrictions on any sequence or order indicated by these ordinal numbers in the embodiments.

[0020] Regarding the description given in the description of the present invention, the following applies: terms such as "top", "bottom", "left", "right", "side", "bottom", "front" and "back", which may denote specific positions or directions, may be used in some cases, but these terms are used merely for the purpose of simplification to facilitate understanding of the content of the embodiments, and they do not refer to the positions or directions in the actual implementation of the embodiments.

[0021] In the description given in the description of the present invention, the following applies: phrases such as "the upper surface of..." or "the lower surface of..." do not only refer to the upper or lower surface of the target element itself, but also to a state in which any other element may be formed in / on the upper or lower surface of the target element. This means, for example, that the phrase "B is arranged on the upper surface of A" does not eliminate the possibility that another element C is present between A and B. First embodiment

[0022] A semiconductor device according to an embodiment of the invention and a method for manufacturing the semiconductor device are described below. To simplify the description, details of the semiconductor layers and electrodes may be omitted in each of the drawings. Semiconductor facility configuration

[0023] Fig. Figure 1 is a top view schematically showing an example of a configuration of a semiconductor device 100 according to the present embodiment. As in the example in Fig. As shown in Figure 1, the semiconductor device 100 has an active area 20 and a connection area 30.

[0024] The active area 20 has a plurality of gate trenches 6, which are aligned in plan view. The connection area 30 has a connection trench 16 and a gate conduit 18, which overlaps the connection trench 16 in plan view. The connection area 30 also has a gate trench 26, which is formed in an inner area.

[0025] The active region 20 is located in a central area of ​​the semiconductor device 100. The active region 20 is a region where current passes through the semiconductor device 100 by applying a voltage to the gate grooves 6, which are formed in strips within the active region 20.

[0026] In the switched-on state of the semiconductor device 100, a positive voltage is applied to the gate grooves 6, so that electrons are evoked at the interface between a gate insulating layer and a semiconductor layer, and so that the flow of current is enabled.

[0027] The connection area 30 is formed in the vicinity of the active area 20 in plan view. The connection area 30 comprises the following: the connection trench 16, a gate insulating layer 7, gate electrodes 8, the gate conductor 18, and a protective ring arranged for the purpose of reducing an electric field. The connection trench 16 is a trench located within the connection area 30.

[0028] Although in the present embodiment the first conductivity type is described as n-type and the second conductivity type as p-type, the first conductivity type and the second conductivity type can also be the p-type and the n-type respectively in the semiconductor device.

[0029] While the semiconductor device is described as a MOSFET in the present embodiment, it can also be an IGBT. While the present embodiment describes a drift layer contained within the semiconductor layer made of silicon carbide (SiC), the drift layer can also be a wide-bandgap semiconductor, such as gallium nitride (GaN) or diamond, which have a wider bandgap than silicon.

[0030] In Fig. Figure 1 of the semiconductor layer of the semiconductor device 100 has gate trenches 6 formed in the active region 20, and gate trench 26 and connection trench 16 formed in the connection region 30. In plan view, connection trench 16 surrounds gate trenches 6 and gate trench 26 and is spaced apart from gate trenches 6 and gate trench 26.

[0031] As in the example in Fig. As shown in Figure 1, the gate trenches 6 are formed in strips in the top view. Each area subdivided by the gate trenches 6 in the active area 20 has a plurality of cells (cell area), and the cells function as MOSFETs.

[0032] Fig. 2 and Fig. Figure 3 are sectional views showing part of the configuration of the semiconductor device according to the present embodiment. Fig. Figure 4 is a top view showing part of the semiconductor device configuration according to the present embodiment. The configurations shown in Fig. 2, Fig. 3 and Fig. The numbers shown in 4 correspond to an area of ​​1000, defined by a broken line in Fig. 1 is surrounded. The cut that is in Fig. Figure 2 corresponds to the section A-A', which is shown in Fig. 4 is shown. Similarly, the cut shown in Fig. 3 is shown, the section B-B', which is in Fig. 4 is shown.

[0033] As in the examples in Fig. 2 and Fig. Figure 3 shows that the semiconductor device 100, which functions as a MOSFET, comprises an n-type silicon carbide semiconductor substrate 1 and a semiconductor layer 2 formed by epitaxial growth on the upper surface of the silicon carbide semiconductor substrate 1. The semiconductor device 100 also includes a drain electrode 12 formed on the lower surface of the silicon carbide semiconductor substrate 1.

[0034] The semiconductor layer 2 in the active region 20 comprises the following: a drift layer 3 formed from an n-type silicon carbide semiconductor, a p-type base region 4 arranged in a surface layer of the drift layer 3, n-type source regions 5 selectively formed in a surface layer of the base region 4, gate trenches 6 passing through the source regions 5 and the base region 4 such that their lower surfaces are located within the drift layer 3, and a p-type diffusion protection layer 9 arranged under the lower surfaces of the gate trenches 6.

[0035] Meanwhile, the semiconductor layer 2 in the terminal region 30 comprises the following: the drift layer 3, which is formed from an n-type silicon carbide semiconductor, the p-type base region 4, which is located in the surface layer of the drift layer 3, the gate trench 26 and the terminal trench 16, which are configured such that their lower surfaces are located deeper than the base region 4 within the n-type drift layer 3, the p-type diffusion protection layer 9, which is located below the lower surface of the gate trench 26, and a p-type terminal protection layer 19, which is located below the lower surface of the terminal trench 16.

[0036] In the case where the semiconductor device 100 is an IGBT, the conductivity type of the silicon carbide semiconductor substrate 1 can be the p-type.

[0037] Here, the drift layer 3 can have a defect concentration of n-type, for example, higher than or equal to 1 × 10 14cm -3 and less than or equal to 1 × 10 17 cm -3 have a thickness of, for example, greater than or equal to 5 µm and less than or equal to 200 µm.

[0038] Base area 4 can contain a p-type impurity concentration of, for example, higher than or equal to 1 × 10 17 cm -3 and less than or equal to 1 × 10 20 cm -3 exhibit.

[0039] The source regions 5 can have an n-type defect concentration higher than or equal to the p-type defect concentration of the base region 4 and lower than or equal to 1 × 10 21 cm -3 have.

[0040] The diffusion protection layer 9 and the connection protection layer 19 can withstand p-type defect concentrations of, for example, higher than or equal to 1 × 10 17 cm -3and less than or equal to 1 × 10 19 cm -3 Preferably, the p-type impurity concentration of the diffusion protection layer 9 can be the same as the p-type impurity concentration of the connection protection layer 19, or it can be higher than or equal to the p-type impurity concentration of the connection protection layer 19.

[0041] As in the examples in Fig. 2 and Fig. As shown in Figure 3, the gate insulating layer 7 is formed on the side and lower surfaces of the gate grooves 6, and the gate electrodes 8, which are formed from polysilicon, are embedded in the gate grooves 6 via the gate insulating layer 7. Fig. 3, however, are the gate insulating layer 7 and the gate electrodes 8, which are arranged in the gate grooves 6, which overlap the gate line 18 in the top view, such that they run on the upper surface of the semiconductor layer 2 (the upper surface of the semiconductor layer 2 in which the base region 4 or the source regions 5 are formed).

[0042] Similarly, the gate insulating layer 7, which has the same thickness as the gate insulating layer 7 formed in the gate grooves 6, is formed on the side and lower surfaces of the gate groove 26, and the gate electrode 8, formed of polysilicon, is embedded in the gate groove 26 via the gate insulating layer 7. The gate electrode 8, which is arranged in the gate groove 26, is thus formed on the upper surface of the semiconductor layer 2. The gate conductor 18 is formed across the upper surfaces of the gate electrodes 8, which are arranged in the gate grooves 6.

[0043] The polysilicon, which is oriented towards the upper surface of semiconductor layer 2, features gate electrodes 8 formed via contact holes (gate contacts 34). The gate electrodes 8 extend to a bond pad for wire bonding a connection during chip assembly.

[0044] As in the examples in Fig. 2, Fig. 3 and Fig. As shown in Figure 4, the gate trench 26, which has no electrical function, is formed in a border area between the connection area 30 and the active area 20.

[0045] In connection area 30, the connection trench 16 is wider than the gate trenches 6 and the gate trench 26, and the gate insulating layer 7, with the same thickness as the gate insulating layer 7 formed in the gate trenches 6, is formed on the side and lower surfaces of the connection trench 16. Furthermore, an intermediate insulating layer 13 (oxide layer) is formed on part of the interior of the connection trench 16, and the gate electrode 8 is formed on the other part of the interior of the connection trench 16.

[0046] Gate electrodes 8 are also formed in the gate grooves 6 within the cell area. Polysilicon (gate electrode 8) is also deposited in the gate groove 26, which is located in the boundary region between the terminal area 30 and the active area 20.

[0047] The interlayer insulating layer 13 is configured to cover the upper surface of the semiconductor layer 2, including the gate electrodes 8. The gate conductor 18 is then in contact with the gate electrodes 8, which are exposed by the gate contacts 34, which serve as openings formed in the interlayer insulating layer 13. The gate contacts 34 include those that expose the gate electrodes 8 located in the terminal groove 16 in the terminal area 30, and those that expose the gate electrodes 8 extending from the gate grooves 6 to the upper surface of the semiconductor layer 2 in the active area 20.

[0048] Furthermore, a source electrode 11 is in contact with the upper surfaces of the base region 4 and the source regions 5 via an ohmic electrode 32, wherein the upper surfaces of the base region 4 and the source regions 5 are exposed by source contacts 31, which serve as openings formed in the interlayer insulating layer 13.

[0049] An oxide layer (the intermediate insulating layer 13) is formed in the connecting trench 16 in the connecting area 30, whereas polysilicon is formed in the gate trench 6 and in the gate trench 26. That is, different materials are formed in the connecting trench 16 and in the gate trenches 6 and 26.

[0050] Furthermore, the connection trench 16 in connection area 30 is processed in large dimensions, whereas the gate trenches 6 or gate trench 26 in the cell area are formed with a minimal processing line width or structure width. As a result of this difference in structure, the coefficients of thermal expansion of the materials vary depending on the thermal history in the wafer process. This causes residual stresses, resulting in differences in electrical characteristics between the elements, which in turn affects the reliability of the semiconductor device.

[0051] In each cell located in the active region 20, the voltages increase as they approach the outer peripheral regions of the gate trenches. This effect increases the failure rate of the gate insulating layer 7 as it approaches the outer peripheral regions of the gate trenches. Consequently, a malfunction of the elements is suppressed by electrically isolating the outermost peripheral cells from the remaining cells and bringing the gate potential into a potential-free or floating state.

[0052] Fig. Figure 5 is a section view that shows an example of the cell range configuration in Fig. 2 shows. As in the example in Fig. As shown in Figure 5, the upper corner area of ​​each gate trench 6 has a rounded shape.

[0053] Fig. Figure 6 is a sectional view showing an example of a configuration of the gate contact area in the active area 20, which is located in Fig. 3 is shown. As in the example in Fig. As shown in Figure 6, the upper corner area of ​​each gate trench 6 has a rounded shape.

[0054] As in Fig. As shown in Figure 5, the upper corner region of the semiconductor layer 2 in the cell region, where the gate electrode 8 is embedded in the gate groove 6, has a shape whose curvature is given by the radius of curvature Rc. Consequently, the gate insulating layer 7, which is formed in this region, also has a shape with a curvature given by the radius of curvature Rc.

[0055] As in Fig. As shown in Figure 6, the upper corner region of the semiconductor layer 2 in the gate contact area, which contains the gate electrode 8 extending from the gate groove 6 to the upper surface of the semiconductor layer 2, has a shape with a curvature expressed by the radius of curvature Re. Consequently, the gate insulating layer 7 formed in this region also has a shape with a curvature specified by the radius of curvature Re.

[0056] A comparison of the radii of curvature of the gate trenches 6, located directly beneath the gate insulating layers 7 described above, shows that Re > Rc, meaning that the shape of the gate contact area is gentler than the shape of the cell area. For example, the small radius of curvature Rc in the cell area can be greater than 0 µm and less than or equal to 0.1 µm. Similarly, the radius of curvature Re in the gate contact area can be greater than or equal to 0.1 µm and less than or equal to 2 µm. In particular, excellent characteristics are observed when the radius of curvature Re in the gate contact area is greater than or equal to 0.5 µm and less than or equal to 2 µm.

[0057] In the gate contact area, the gate insulating layer 7 and the gate electrode 8 are formed at the upper corners of the gate grooves 6. Since the radius of curvature Re is larger than the radius of curvature Rc, it is possible to suppress the application of a high electric field to the gate insulating layer 7, which is formed at the upper corner regions of the gate grooves 6 when the MOSFET is switched on.

[0058] For example, if the gate insulating layer 7 has a thickness of 50 nm and a gate voltage of 20 V is applied, an electric field of 4 MV / cm is applied to the sidewall regions of the gate grooves 6. In this case, in the gate contact region, where the gate insulating layer 7 is shaped to have a curvature with radius Re, it is possible to suppress the application of a high electric field to the gate insulating layer 7, which would form at the upper corner regions of the gate grooves 6, and thus prevent damage to the insulating layer.

[0059] From the perspective of the reliability of the gate insulating layer 7, it is desirable to design the radius of curvature Re such that the increment of an electric field applied to the gate insulating layer 7 near the gate trenches 6 with radius of curvature Re is suppressed to 5% or less.

[0060] Although it is assumed that the gate contact area, which is in Fig. As shown in Figure 6, in the active area 20, a configuration is also possible in which the upper corner area of ​​the connection trench 16 has a rounded shape in the gate contact area of ​​the connection area 30 (in the area where the gate line 18 and the gate electrodes 8 are connected to each other via the gate contacts 34).

[0061] In the present embodiment, the following applies: In the case where an ohmic electrode is arranged between the source electrode and the semiconductor layer, the source electrode and the ohmic electrode together may be referred to as the source electrodes, without distinction. Similarly, the following applies: In the case where an ohmic electrode is arranged between the gate bond pad, which serves as a metal electrode, and the gate electrodes formed from a semiconductor or the like, the gate bond pad and the ohmic electrode together may be referred to as the gate bond pads, without distinction.

[0062] This means that the source electrode and the gate bond pad according to the present embodiment are not limited to being formed from a single metal, and they may comprise material suitable for bonding to the semiconductor layer at the interface with the semiconductor layer. The resistive electrode is not limited to metal, and it may be silicide or a composite of a metal and a semiconductor. The resistive electrode may also comprise multiple metal layers or a conductor, such as a semiconductor. Method for manufacturing the semiconductor device

[0063] Next, a method for manufacturing the semiconductor device 100 according to the present embodiment is described.

[0064] Fig. Figures 7 to 18 are diagrams showing an example of the method for manufacturing the semiconductor device according to the present embodiment.

[0065] Fig. Figures 7 to 11 show an example of the steps until the diffusion protection layer 9 is formed on the lower surfaces of the gate trenches 6 and the connection protection layer 19 is formed on the lower surface of the connection trench 16. Fig. 7 to 10 correspond to the AA' cut in Fig. 11.

[0066] Fig. Figures 12 to 15 show an example of the steps taken until the gate electrodes 8 are formed after the diffusion protection layer 9 and the terminal protection layer 19 have been formed. Fig. 12 and Fig. 13 correspond to the AA' cut in Fig. 15. Fig. 14 corresponds to the section B-B', which is in Fig. 15 is shown.

[0067] Fig. Figures 16 to 18 show an example of the steps taken until the semiconductor device 100 is complete after the gate electrodes 8 have been formed.

[0068] As in the example in Fig. As shown in Figure 7, the silicon carbide semiconductor substrate 1 of n-type is first prepared with a 4H polytype, and the semiconductor layer 2 of n-type is formed epitaxially on the upper surface of the semiconductor substrate 1 by chemical vapor deposition (CVD).

[0069] At this time, the n-type semiconductor layer 2 can have an n-type defect concentration of, for example, higher than or equal to 1 × 10 14 cm -3 and less than or equal to 1 × 10 17 cm -3 and have a thickness of, for example, greater than or equal to 5 µm and less than or equal to 200 µm.

[0070] As in the example in Fig. As shown in Figure 7, aluminum (Al) ions, acting as p-type defects, are implanted into the surface layer of the epitaxially grown semiconductor layer 2, forming the base region 4. The depth of the Al ion implantation is controlled so that it does not exceed the thickness of the semiconductor layer 2 and can be set, for example, to greater than or equal to 0.3 µm and less than or equal to 3 µm. The defect concentration of implanted Al ions is controlled to be higher than the n-type defect concentration of the epitaxially grown semiconductor layer 2, and the p-type defect concentration of the base region 4 can be set, for example, to greater than or equal to 1 × 10⁻⁶. 17 cm -3 and less than or equal to 1 × 10 20 cm -3The result is that a region of the semiconductor layer 2, which differs from the base region 4 and is located deeper than the depth of the Al ion implantation, forms the drift layer 3 of the n-type.

[0071] It should be noted that the basal region 4 can be formed by epitaxial growth of a p-type semiconductor, and in this case, the basal region 4 can have the same p-type defect concentration and thickness as the basal region 4 formed by ion implantation.

[0072] As in the example in Fig. As shown in Figure 7, nitrogen (N) ions, acting as n-type impurities, are selectively implanted into the surface layer of the base region 4, forming the source regions 5. The source regions 5 are arranged in a pattern corresponding to the layout of the gate electrodes 8, which are to be formed in a subsequent step. The depth of the N-ion implantation is predetermined to be less than the thickness of the base region 4. The impurity concentration of the implanted N-ions is predetermined to be higher than or equal to the p-type impurity concentration of the base region 4 and lower than or equal to 1 × 10⁻⁶. 21 cm -3 is.

[0073] It should be noted that the order of the step to implant Al ions to form the base region 4 and the step to implant N ions to form the source region 5 can be changed. Alternatively, after an n-type semiconductor layer is formed by implanting N ions across the entire surface layer of the base region 4, parts that are to remain as the source regions 5 can be masked, and Al ions can be re-implanted into unmasked regions (regions distinct from the source regions 5), so that these unmasked regions again become the p-type base region 4.At this time, the following applies: In order to reduce the contact resistance with the source electrode, the impurity concentration of Al ions that are re-implanted can be specified to be higher than the impurity concentration of Al in the area of ​​the base region 4 that is adjacent to the drift layer 3.

[0074] As in the example in Fig. As shown in Figure 8, a silicon oxide layer 41 is then formed on the upper surface of the semiconductor layer 2, and an etch mask 42 is also formed on the upper surface of the silicon oxide layer 41. The silicon oxide layer 41 can be formed by depositing a thickness of, for example, greater than or equal to 1 µm and less than or equal to 2 µm, and then the etch mask 42 is formed on the upper surface of the silicon oxide layer 41. The etch mask 42 has a pattern formed by photolithography and has openings corresponding to areas where the gate trenches 6, gate trench 26, and connection trench 16 are to be formed.

[0075] The silicon oxide layer 41 is then patterned by reactive ion etching (RIE) using the etching mask 42 as a mask. That is, the pattern of the etching mask 42 is transferred to the silicon oxide layer 41, and the silicon oxide layer 41 is used as an etching mask for the semiconductor layer 2.

[0076] As in the example in Fig. As shown in Figure 9, the gate trenches 6 and gate trench 26, which penetrate the source regions 5 and the base region 4, and the connection trench 16, which penetrates the base region 4, are formed in the semiconductor layer 2 by RIE, using the patterned silicon oxide layer 41 as a mask.

[0077] The depths of the gate trenches 6, gate trench 26 and connection trench 16 are greater than or equal to the depth of the base region 4 formed in the semiconductor layer 2 by ion implantation, and can be in the range of, for example, greater than or equal to 1.0 µm and less than or equal to 6.0 µm.

[0078] Gate trenches 6, gate trench 26, and connecting trench 16 are formed using the silicon oxide layer 41 as a mask. After forming gate trenches 6, gate trench 26, and connecting trench 16—as in the example in Fig. As shown in Figure 10, an implantation mask 43 with openings having the same pattern as that of the silicon oxide layer 41 is formed, and the p-type diffusion protection layer 9 is formed by Al ion implantation on the undersides of the gate trenches 6 and the gate trench 26. Similarly, the p-type connection protection layer 19 is formed by Al ion implantation at the bottom of the connection trench 16. Preferably, the defect concentration of the implanted Al ions can be, for example, higher than or equal to 1 × 10⁻⁶. 17 cm -3 and less than or equal to 1 × 10 19 cm -3The depth of ion implantation can be, for example, greater than or equal to 0.1 µm and less than or equal to 2.0 µm. The impurity concentration of the implanted Al ions can be determined by an electric field applied to the gate insulating layer 7 when the same voltage as the standby voltage of the semiconductor device 100 is applied between the drain electrode 12 and the source electrode 11 of the semiconductor device 100.

[0079] If the etching conditions and the thickness of the silicon dioxide layer 41 are controlled such that the silicon dioxide layer 41 remains even after it has been used as a mask to form the gate trenches 6 and the connection trenches 16, the remaining silicon dioxide layer 41 described above can be used as a mask instead of the implantation mask 43, thus forming the diffusion protection layer 9 and the connection protection layer 19. This simplifies the manufacturing process and reduces manufacturing costs.

[0080] If Al ions are implanted at an oblique angle to the gate groove openings 6, specifically in the case where the diffusion protection layer 9 is formed, it is possible to form a p-type semiconductor layer within the drift layer 3, which is in contact with the side faces of the gate grooves 6. This p-type semiconductor layer can then be used to connect the p-type diffusion protection layer 9 and the p-type base region 4. This establishes an electrical connection between the diffusion protection layer 9 and the source electrode 11.

[0081] After the formation of the diffusion protection layer 9 and the connection protection layer 19, the implantation mask 43, which is used for ion implantation, is removed, and a tempering process is performed to activate the implanted defects using a heat treatment device. The tempering process can be carried out by heating defects to a temperature higher than or equal to 1300 °C and lower than or equal to 1900 °C for 30 seconds or more and one hour or less in a vacuum or in an inert gas atmosphere, such as an argon (Ar) atmosphere.

[0082] As in the example in Fig. As shown in Figure 12, the implantation mask 43 is then removed, and the upper surface of the semiconductor layer 2 is oxidized, specifically in section AA' and in section B-B', which are shown in Fig. Figure 15 shows that the oxide layer formed on the upper surface of semiconductor layer 2 can have a thickness on the order of, for example, greater than or equal to 5 nm and less than or equal to 100 nm. The oxide layer is then removed by hydrofluoric acid-based wet etching. This step rounds off the upper corner region of each groove (with a radius of curvature Rc).

[0083] Then an oxide layer 41A is deposited, as in the example in Fig. 13 shown, and only the areas of the oxide layer 41A, which correspond to the areas where the gate contacts are to be formed in the active region 20, are shown in the example in Fig. Open on the 14th.

[0084] As in the example in Fig. 14 is shown in the section B-B', which is in Fig. As shown in Figure 15, the oxide layer 41A is etched such that part of the semiconductor layer 2 is exposed, and the upper corner regions of the gate grooves 6 in the exposed semiconductor layer 2 are rounded (with radius of curvature Re). The section BB' in Fig. Figure 15 shows that an area spanning a plurality of gate trenches 6 is exposed from the oxide layer 41A.

[0085] The rounded shape can be formed by chemical dry etching (CDE: isotropic etching) or by any other etching process (e.g., heat treatment in a hydrogen atmosphere). The oxide layer 41A is then removed.

[0086] In the area where the upper corners of the trenches are rounded (with a radius of curvature Rc), specifically by the step that is in Fig. As shown in Figure 12, the upper corner regions of the gate trenches 6 are further rounded with a larger radius of curvature as a result of the CDE or heat treatment carried out in a hydrogen atmosphere, specifically in the step described in Fig. 14 is shown.

[0087] As described above, the radius of curvature Re of the gate insulating layer 7, which is arranged at the upper corner regions of the gate trenches 6 (or the connecting trench 16), in the area where the gate conductor 18 is located on the upper surface, is larger than the radius of curvature Rc of the gate insulating layer 7, which is arranged at the upper corner regions of the gate trenches 6, in the area where the source electrodes 11 are electrically connected to the adjacent source regions 5. With this configuration, even if a gate voltage is applied to the gate insulating layer 7, which has a rounded shape with a large radius of curvature (the radius of curvature Re), the concentration of an electric field is effectively suppressed due to the large radius of curvature, and the application of a high electric field is prevented. Consequently, it is possible to prevent damage to the gate insulating layer 7.

[0088] Next, the gate electrode 8 will be formed. Fig. 16 corresponds to the section A-A', which is in Fig. 18 is shown. Fig. 17 corresponds to the section B-B', which is in Fig. 18 is shown.

[0089] As in the example in Fig. As shown in Figure 16, the gate insulating layer 7 and the gate electrode 8 are formed in the gate trenches 6, the gate trench 26, and the connecting trench 16. More precisely: The polysilicon forming the gate electrodes 8 is deposited after the deposition of the gate insulating layer 7. The deposited polysilicon is then back-etched, using a resist as a mask. Consequently, the polysilicon is back-etched in an area without a resist, whereas the polysilicon remains in the gate trenches 6, the gate trench 26, and the connecting trench 16.

[0090] As in the example in Fig. As shown in Figure 17, the areas covered with the aforementioned resist are regions where the upper corner regions of the gate grooves 6 are rounded (with radius of curvature Re), and the polysilicon also remains on a mesa region (the upper surface of the semiconductor layer 2) without being etched back. Since the upper corner regions of the gate grooves 6 are highly rounded (with radius of curvature Re), there is no need to locally increase the thickness of the gate insulating layer 7 to suppress the concentration of an electric field at the upper corner regions of the gate grooves 6. Consequently, it is possible to fabricate the structure capable of suppressing the concentration of an electric field at the upper corner regions of the gate grooves 6 and suppressing an increase in manufacturing costs, without increasing the number of fabrication steps, using a single gate insulating layer formation process.

[0091] The intermediate insulating layer 13 is then formed to cover the gate electrodes 8 by means of low-pressure CVD on the upper surface of the semiconductor layer 2. The intermediate insulating layer 13 is then patterned to form contact holes (gate contacts 34) that reach the source regions 5 and the base region 4, specifically in the active region 20 and the terminal region 30. Additionally, contact holes (source contacts 31) are formed that reach the gate electrodes 8 in the active region. Finally, a resistive electrode 25 is formed in the gate contacts 34 (see Fig. 6) The ohmic electrode 32 is also formed in the source contacts 31. Each of the ohmic electrodes can be a silicide layer formed by first depositing a metal layer, primarily composed of nickel (Ni), on the top surface of the semiconductor layer 2 or on the top surfaces of the gate electrodes 8, and then causing Ni to react with a semiconductor by means of heat treatment carried out at a temperature of, for example, higher than or equal to 600 °C and lower than or equal to 1100 °C.

[0092] Then an Al alloy or the like is deposited on the upper surface of the interlayer insulating layer 13 and in the gate contacts 34 and the source contacts 31 and provided with a pattern so that the gate line 18 is formed via the gate contacts 34 and the source electrode 11 is formed via the source contacts 31.

[0093] The drain electrode 12 is then formed by depositing an Al alloy or the like onto the surface of the silicon carbide semiconductor substrate 1, on the side opposite the side where the semiconductor layer 2 is formed. The semiconductor device 100 is formed by the steps described above. Functions and effects of the semiconductor device

[0094] Next, the functions and effects of the semiconductor device 100 according to the present embodiment will be described.

[0095] The semiconductor device 100 according to the present embodiment, which is in Fig. As shown in Figures 2 to 5, a channel is to be formed in the base region 4, which is opposite the gate electrodes 8 via the gate insulating layer 7, and controls the on and off states of the semiconductor device 100 by controlling a voltage applied between the gate electrodes 8 and the source electrodes 11.

[0096] When a voltage high enough to switch on the semiconductor device 100 is applied between the gate electrodes 8 and the source electrode 11, a voltage higher than or equal to a threshold value is applied to the gate electrodes 8. As a result, a channel is formed in the base region 4 opposite the gate electrodes 8 via the gate insulating layer 7, and a path for allowing electrons, which act as charge carriers, to pass through is formed between the n-type source regions 5 and the n-type drift layer 3.

[0097] Then, the electrons flowing from the source regions 5 into the drift layer 3 are caused to reach the drain electrode 12 via the drift layer 3 and the silicon carbide semiconductor substrate 1 by an electric field generated by the voltage applied between the drain electrode 12 and the source electrode 11. As a result, a current flows from the drain electrode 12 to the source electrode 11 when a voltage higher than or equal to the threshold of the gate electrodes 8 is applied. This state corresponds to the on-state of the semiconductor device 100.

[0098] Conversely, if a voltage lower than the threshold is applied between the gate electrodes 8 and the source electrode 11, no channel is formed in the base region 4 opposite the gate electrodes 8 via the gate insulating layer 7. In this case, the presence of the p-type base region 4 between the n-type source regions 5 and the n-type drift layer 3 prevents current from flowing from the drain electrode 12 to the source electrode 11. This state corresponds to the off state of the semiconductor device 100.

[0099] When the semiconductor device 100 is switched off, a high voltage, supplied by an external electrical circuit, is applied between the drain electrode 12 and the source electrode 11. In the off state of the semiconductor device 100, a depletion layer grows from the diffusion protection layer 9 and the terminal protection layer 19 into the drift layer 3. This prevents the electric field generated by the voltage applied between the drain electrode 12 and the source electrode 11 from concentrating on the gate insulating layer 7 at the bottom surfaces of the gate grooves 6, and thus suppresses damage to the gate insulating layer 7 at the bottom surfaces of the gate grooves 6, even when a high electric field is applied to the gate insulating layer 7.

[0100] On the other hand, when the semiconductor device 100 is switched on, a voltage supplied by an external electrical circuit is applied between the gate electrodes 8 and the source electrode 11. As a result of the voltage being applied, an electric field is applied to the gate insulating layer 7. Since the upper corner regions of the gate grooves 6 in the semiconductor layer 2 have a rounded shape with radius of curvature Re, the gate insulating layer 7 also has a rounded shape with radius of curvature Re. This prevents the electric field generated by the voltage applied between the drain electrode 12 and the source electrode 11 from concentrating on the gate insulating layer 7 at the upper corner regions of the gate grooves 6, and this suppresses damage to the gate insulating layer 7, even when a high electric field is applied to it.

[0101] When the semiconductor device 100 is switched on, current flows from the drain electrode 12 towards the source electrode 11, with a voltage applied by an external electrical circuit. Consequently, the voltage between the drain electrode 12 and the source electrode 11 becomes a switch-on voltage, determined by the switch-on resistance of the semiconductor device 100 and the current flowing from the drain electrode 12 towards the source electrode 11. The switch-on voltage is much lower than the voltage present between the drain electrode 12 and the source electrode 11 in the switch-off state. Therefore, the depletion layer, which in the switch-off state expanded from the diffusion protection layer 9 and the terminal protection layer 19 into the drift layer 3, shrinks in the switch-off state towards the diffusion protection layer 9 and the terminal protection layer 19 in the same direction as in the switch-on state.

[0102] This means that when the semiconductor device 100 repeatedly switches between the on state and the off state, the depletion layer, which extends from the diffusion protection layer 9 and the terminal protection layer 19 to the drift layer 3, grows and shrinks according to the switching.

[0103] Although the semiconductor device 100 functions while repeatedly switching between the on and off states, voltage stresses act on the gate insulating layer 7, and the degradation even accelerates during the repeated switching between the on and off states. Since the upper corner regions of the gate grooves 6 in the semiconductor layer 2 have a rounded shape with radius of curvature Re, the gate insulating layer 7, which is located at this region, also has a rounded shape with radius of curvature Re. This prevents the electric field, which is present between the drain electrode 12 and the source electrode 11, from concentrating on the gate insulating layer 7, which is formed at the upper corner region of the semiconductor layer 2.Therefore, it is possible to suppress the acceleration of the deterioration of the gate insulating layer 7 and thereby suppress the destruction of the gate insulating layer 7.

[0104] In the present embodiment, the following applies: As in Fig. As shown in Figure 4, the non-functional gate trench 26 is located in the boundary region between the terminal region 30 and the active region 20. The terminal region 30 and the active region 20 differ in their laminated structure and processing dimensions along the silicon carbide semiconductor substrate 1. This can cause residual voltages in the aforementioned boundary region, affect the electrical characteristics, and lead to the destruction of the gate insulating layer 7. The gate insulating layer 7 also exhibits a higher failure rate as it approaches the outermost peripheral region. Therefore, element destruction can be prevented by electrically isolating the outermost peripheral cells (corresponding to the gate trench 26) from the remaining cells, forming the terminal region 30, and by converting the gate potential to a potential-free or neutral state.The floating state is achieved without electrically connecting the gate electrodes 8 to the source electrode 11 and the gate line 18.

[0105] Gate Trench 26, which is in Fig. The four gates shown will have a higher efficiency percentage when their number is increased. That is, the quality of the semiconductor device 100 is increased by forming a plurality of gate grooves 26. Second embodiment

[0106] A semiconductor device according to the present embodiment and the method for manufacturing the semiconductor device are described. In the following description, elements identical to those described in the embodiment above are assigned the same reference numerals, and their detailed description is omitted where appropriate. Semiconductor facility configuration

[0107] Fig. Figure 19 is a top view schematically showing an example of a configuration of a semiconductor device 101 according to the present embodiment. As in the example in Fig. As shown in Figure 19, the semiconductor device 101 has an active area 20 and a connection area 30.

[0108] The active area 20 comprises the following: a plurality of gate grooves 6 oriented in the top view, gate electrodes 8 formed in the gate grooves 6, and a gate line 18 connected to the gate electrodes 8 via gate contacts 34. The gate contacts 34 are located directly below the gate line 18 and directly above the gate electrodes 8.

[0109] The gate electrodes 8 are connected to a gate bond pad 58, which is located in the outer peripheral region of a chip. The gate bond pad 58 and the gate electrodes 8 are metal layers, such as aluminum, and they are formed by the same process.

[0110] A source electrode 11 is arranged on the upper surface of the source regions 5, which are formed in the surface layer of a semiconductor layer 2. The source electrode 11 is electrically connected to the source regions 5 via contact holes (source contacts 31). The source electrode 11 extends to a source bond pad 59.

[0111] The connection area 30 has a connection trench 16 and a gate line 18, which are located within the connection trench 16 in some areas. A metal conductor 120 is formed on the upper surface of the gate line 18 via a gate contact 34. The metal conductor 120 is formed by the same process as the gate electrodes 8 and the source electrode 11. Since the metal conductor 120 and the gate line 18 are connected in parallel, the electrical resistance is low. The semiconductor device 101 is configured as described above. Method for manufacturing the semiconductor device

[0112] Next, a method for manufacturing the semiconductor device 101 according to the present embodiment is described.

[0113] Fig. Figures 20 to 22 are diagrams showing an example of the method for manufacturing the semiconductor device according to the present embodiment.

[0114] The structure that is in Fig. Figure 20 shows a top view of the structure, which is in Fig. Figure 10 shows that the gate ditches 6 are located in active area 20, and the outermost gate ditches 26 and the connecting ditch 16 are located in connecting area 30.

[0115] The structure that is in Fig. Figure 21 shows a top view of the structure, which is in Fig. Figure 16 shows the top view. The gate line 18 is installed on the gate trenches 6 in the active area 20. The gate line 18 is also installed on the gate trench 26 in the connecting area 30. The gate line 18 is furthermore installed on some sections of the connecting trench 16.

[0116] The gate line 18 is formed by depositing polysilicon on the gate trenches 6 and etching back the polysilicon on some areas using a mask formed from a resist or the like.

[0117] Areas 108 and 109, which are marked with broken lines in Fig. The areas indicated in Figure 21 are where the aforementioned mask is arranged such that polysilicon remains on the upper surface of semiconductor layer 2 without being etched back. The polysilicon remaining in these areas not only covers the interior of the gate grooves 6, but also the upper corner regions of the gate grooves 6, and it also remains on the mesa region (the upper surface of semiconductor layer 2). The upper corner regions of the gate grooves 6 have a large radius of curvature Re and suppress the concentration of an electric field. Consequently, it is possible to suppress the destruction of the gate insulating layer 7.

[0118] In Fig. 21 is the gate electrode 8, which is formed in the gate groove 26 in the connection area 30, separated in the top view from the gate electrodes 8 which are formed in the gate grooves 6, which are arranged in strips, in the central area of ​​the active area 20. As in Fig. As shown in Figures 16 to 18, the gate line 18 is formed by back-etching the deposited polysilicon.

[0119] In the etching process, polysilicon remains in a sidewall form on the sidewall regions of the trenches in the area where there is a trench level difference (area where the upper surface is at different levels due to the presence of the trenches). In such a structure, which encloses the remaining polysilicon that has an electrical connection, an electric field is also applied to the gate insulating layer 7 on the underside of the polysilicon remaining in a sidewall form, and destruction of the gate insulating layer 7 occurs. In the structure that is in Fig. In contrast, as shown in Figure 21, the potential of the polysilicon remaining in a sidewall form is potential-free or floating, and no electrical connection is established with the gate electrodes. Therefore, it is possible to suppress damage to the gate insulating layer 7.

[0120] Fig. Figure 22 is a top view showing an example of the structure when first the intermediate insulating layer 13 and then the source contacts 31 and the gate contacts 34 are formed, after the step described in Fig. 21 is shown.

[0121] In Fig. 22 The gate contacts 34 are formed on the upper surfaces of the gate electrodes 8 in regions 108 and 109. In the structure shown in Fig. As shown in Figure 22, the gate contacts 34 and the gate line 18 can be formed at positions that overlap the gate grooves 6, which are arranged in strips in the top view. Consequently, there is no need to provide a separate area for forming the gate contacts 34. This reduces the chip area and increases the degree of design flexibility.

[0122] As in Fig. As shown in Figure 19, aluminum is then deposited and patterned by etching using a resist mask. The gate conductor 18 is then formed in area 108 and connected to the gate bond pad 58. In areas 109, the aluminum is patterned to form the metal conductor 120, which extends to the upper surface of the gate electrode 8 located in connection area 30. The metal conductor 120 is then electrically connected to the gate electrodes 8 via the contact holes (the gate contacts 34). The gate electrodes 8 in connection area 30 extend to a location directly below the gate bond pad 58 and are electrically connected to the gate electrodes 8 within the gate bond pad 58 via the gate contacts 34.

[0123] The gate electrodes 8, arranged in a cell array in the gate grooves 6, are electrically connected to each other via the gate contacts 34, which are located in the gate bond pad 58 and in the central area of ​​the active region 20. They are also electrically connected to the gate electrodes 8 and the aluminum layer (the metal conductor 120) formed in the terminal area 30, and to the remaining gate electrodes 8 in the active region 20. This reduces the resistance of the gate electrodes 8 in the gate grooves 6 located in the active region 20 and achieves excellent electrical characteristics (switching characteristics and turn-on characteristics).

[0124] The upper corner regions of the gate trenches 6 in region 108, located in the central area of ​​the active region 20 where the gate contact 34 is formed, are designed with a large radius of curvature Re. Consequently, it is possible to suppress the concentration of an electric field at the upper corner regions of the gate trenches 6 even when a gate voltage is applied during the element processes, and thereby to suppress the destruction of the gate insulating layer 7. Third embodiment

[0125] A semiconductor device according to the present embodiment and a method for manufacturing the semiconductor device are described. In the following description, elements identical to those described in the embodiments above are assigned the same reference numerals, and their detailed description is omitted where appropriate. Semiconductor facility configuration

[0126] Fig. Figure 23 is a top view schematically showing an example of a configuration of a semiconductor device 102 according to the present embodiment. As in the example in Fig. As shown in Figure 23, the semiconductor device 102 has an active area 20 and a connection area 30.

[0127] The active area 20 comprises the following: a plurality of gate grooves 6 oriented in the top view, gate electrodes 8 formed in the gate grooves 6, and a gate conductor 18 connected to the gate electrodes 8 via gate contacts 34. The gate contacts 34 are located directly below the gate conductor 18 and in the upper layers of the gate electrodes 8.

[0128] The gate electrodes 8 are connected to the gate bond pad 58, which is located in the outer peripheral region of a chip. The gate bond pad 58 and the gate trace 18 are metal layers made of aluminum or the like and are formed by the same process.

[0129] A source electrode 11 is arranged on the upper surfaces of the source regions 5, which are formed in the surface layer of the semiconductor layer 2. The source electrode 11 is electrically connected to the source regions 5 via contact holes (source contacts 31). The source electrode 11 extends to the source bond pad 59.

[0130] The connection area 30 has a connection trench 16 and gate electrodes 8, which are arranged in some areas within the connection trench 16. A metal conductor 122 is formed on the upper surfaces of the gate electrodes 8 via gate contacts 34. The metal conductor 122 is formed by the same process as the gate conductor 18 and the source electrode 11. Since the metal conductor 122 and the gate electrodes 8 are connected in parallel, the gate resistance is low. The semiconductor device 102 is configured as described above. Method for manufacturing the semiconductor device

[0131] Next, a method for manufacturing the semiconductor device 102 according to the present embodiment is described.

[0132] Fig. Figures 24 to 25 are diagrams showing an example of the method for manufacturing the semiconductor device according to the present embodiment.

[0133] The structure that is in Fig. Figure 24 shows a top view of the structure, which is in Fig. Figure 16 shows that the gate electrodes 8 are formed in the gate trenches 6 in the active area 20. The gate electrode 8 is also formed in the gate trench 26 in the connection area 30. The gate electrodes 8 are also formed in some areas of the connection trench 16.

[0134] The gate lines 8 are formed by depositing polysilicon in the gate trenches 6 and then etching back the polysilicon in some areas using a mask formed from a resist or the like.

[0135] Areas 108 and 109, which are marked with broken lines in Fig. The areas indicated in Figure 24 are regions where the polysilicon remains on the upper surface of semiconductor layer 2 without being etched back, due to the presence of the aforementioned mask. The polysilicon remaining in these regions not only covers the interior of the gate grooves 6, but also the upper corner regions of the gate grooves 6, and it also remains on the mesa region (the upper surface of semiconductor layer 2). The upper corner regions of the gate grooves 6 have a large radius of curvature Re and prevent the concentration of an electric field. This suppresses the destruction of the gate insulating layer 7.

[0136] The outermost peripheral end regions of the active region 20 (the parts corresponding to regions 109), which are in Fig. The gate electrodes 8, which are aligned in strips, are shown in Figure 24 and establish an electrical connection via the gate contacts 34. Consequently, it is possible to reduce the gate resistance of the narrow and long gate grooves 6.

[0137] Fig. Figure 25 is a top view showing an example of the structure when first the intermediate insulating layer 13 and then the source contact 31 and the gate contact 34 are formed, after the step described in Fig. 24 is shown.

[0138] In Fig. 25 the gate contacts 34 are formed on the upper surfaces of the gate electrodes 8 in the areas 108 and 109.

[0139] As in Fig. As shown in Figure 23, aluminum is then deposited and patterned by etching using a resist mask. The gate electrodes 8 are then formed in region 108 and connected to the gate bond pad 58 via the gate conductor 18. In region 109, the aluminum is patterned to form the metal conductor 122 (the gate conductor 18), which extends to the upper surfaces of the gate electrodes 8 located in connection region 30. The metal conductor 122 is electrically connected to the gate electrodes 8 via the contact holes (the gate contacts 34). The gate conductor 18 in connection region 30 runs directly beneath the gate bond pad 58 and is electrically connected to the gate electrodes 8 via the gate contacts 34 within the gate bond pad 58.

[0140] The gate electrodes 8, arranged in the gate grooves 6 in a cell array, are electrically connected to each other via the gate contacts 34, which are located in the gate bond pad 58 and in the central region of the active region 20. The gate electrodes 8, arranged in the gate grooves 6 in the cell array, are also electrically connected to the other gate conductor 18 in the active region 20 via the aluminum layer (the electrode region 121) and the gate contacts 34, which are formed in the end region of the active region 20. This reduces the resistance of the gate conductor 18 in the gate grooves 6 arranged in the active region 20 and achieves excellent electrical characteristics (switching characteristics and turn-on characteristics).

[0141] The upper corner regions of the gate trenches 6 in region 108, located in the central region of the active region 20 where the gate contact 34 is formed, and the upper corner regions of the gate trenches 6 in regions 109, located in the end regions of the active region 20, are both formed with a large radius of curvature Re. Consequently, it is possible to suppress the concentration of an electric field at the upper corner regions of the gate trenches 6 even when a gate voltage is applied during the element processes, and thereby to suppress the destruction of the gate insulating layer 7. Fourth embodiment

[0142] A semiconductor device according to the present embodiment and a method for manufacturing the semiconductor device are described. In the following description, elements identical to those described in the embodiments above are assigned the same reference numerals, and their detailed description is omitted where appropriate. Semiconductor facility configuration

[0143] Fig. Figures 26 to 30 are diagrams that schematically illustrate an example of a semiconductor device 103 according to the present embodiment. As in the example in Fig. As shown in Figures 26 to 30, the semiconductor device 103 has an active area 20 and a connection area 30.

[0144] The active area 20 comprises the following: a plurality of gate grooves 6 oriented in the top view, gate electrodes 8 formed in the gate grooves 6, and a gate conductor 18 connected to the gate electrodes 8 via gate contacts 34. The gate contacts 34 are located directly below the gate conductor 18 and on the upper layers of the gate electrodes 8.

[0145] The gate electrodes 8 are connected to a gate bond pad 58, which is located in the outer peripheral region of a chip. The gate bond pad 58 and the gate trace 18 are metal layers made of aluminum or the like and are formed by the same process.

[0146] A source electrode 11 is arranged on the upper surfaces of the source regions 5, which are formed in the surface layer of a semiconductor layer 2. The source electrode 11 is electrically connected to the source regions 5 via contact holes (source contacts 31). The source electrode 11 extends to the source bond pad 59.

[0147] The connection area 30 has a connection trench 16 and gate electrodes 8, which are arranged in some areas within the connection trench 16. A metal conductor 122 is formed on the upper surfaces of the gate electrodes 8 via gate contacts 34. The metal conductor 122 is formed by the same process as the gate electrodes 8 and the source electrode 11. Since the metal conductor 122 and the gate electrodes 8 are connected in parallel, the gate resistance is low. The semiconductor device 103 is configured as described above. Method for manufacturing the semiconductor device

[0148] Next, the method for manufacturing the semiconductor device 103 according to the present embodiment will be described.

[0149] The structure that is in Fig. Figure 26 shows a structure at a stage after the completion of the steps from the Fig. 7 to 9.

[0150] As in the example in Fig. As shown in Figure 26, after the formation of gate trenches 6, gate trench 26, and connecting trench 16, defects are implanted into the lower surfaces of these trenches. More precisely, Al ions are implanted into the undersides of gate trenches 6 and gate trench 26, thus forming a p-type diffusion protection layer 39. Similarly, Al ions are implanted into the bottom of connecting trench 16, thus forming a p-type connection protection layer 49. The defect concentration of the implanted Al ions can be, for example, higher than or equal to 1 × 10⁻⁶. 16cm -3 and less than or equal to 1 × 10 18 cm -3 the depth of ion implantation can be, for example, greater than or equal to 0.1 µm and less than or equal to 2.0 µm.

[0151] As in the example in Fig. As shown in Figure 27, a resist mask 51 is then formed on the gate trench 26 and the gate trenches 6, which are located in the boundary region between the active region 20 and the connection region 30. Then, Al ions are additionally implanted into the exposed areas of the p-type diffusion protection layer 39 and the connection protection layer 49. It is preferred that the impurity concentration of Al is, for example, higher than or equal to 1 × 10⁻⁶. 16 cm -3 and less than or equal to 1 × 10 18 cm -3is, and the depth of ion implantation can be, for example, greater than or equal to 0.1 µm and less than or equal to 2.0 µm.

[0152] As a result of the above two ion implantation processes, the diffusion protection layer 39, located in gate trench 26 and gate trenches 6 in the boundary region between active area 20 and connection area 30, has a lower defect concentration than the diffusion protection layer 9 located in gate trenches 6 that underwent two ion implantation processes (trenches formed in areas other than the boundary region). Similarly, the diffusion protection layer 39 has a lower defect concentration than the connection protection layer 19 located in connection trench 16, which underwent two ion implantation processes.

[0153] The resist is then removed, and a tempering process is performed to activate the defects implanted by ion implantation using a heat treatment device. Tempering can be carried out by heating the defects to a temperature higher than or equal to 1300 °C and lower than or equal to 1900 °C for 30 minutes or more, or one hour or less, in a vacuum or in an inert gas atmosphere such as an argon (Ar) atmosphere.

[0154] Then a gate insulating layer 97 is deposited, as in the example in Fig. Figure 28 shows that a resist mask 52 is then formed on the gate trench 26 and the gate trenches 6, which are located in the boundary region between the active region 20 and the connection region 30. The gate insulating layer 97, which is located in areas not covered by the resist mask 52, is removed by wet processing, for example, using hydrofluoric acid. Here, the gate insulating layer 97 can have a thickness of, for example, greater than or equal to 20 nm and less than or equal to 150 nm.

[0155] A gate insulating layer is then deposited across the entire surface, as in the example in Fig. Figure 29 shows the gate insulating layer, which is further formed by the second deposition, can have a diameter of, for example, greater than or equal to 20 nm and less than or equal to 150 nm.

[0156] As a result of the above double deposition process, the gate insulating layer 87 is thicker in some areas than the gate insulating layer 7 in the remaining areas.

[0157] Polysilicon is then deposited to form the gate electrodes 8. The deposited polysilicon is then etched back using a resist as a mask. From this point onward, an intermediate insulating layer 13, source contacts 31, gate contacts 34, a resistive electrode 32, a source electrode 11, and gate leads 18 are formed by the same process as described in the first embodiment, thus completing the MOSFET (see Fig. 30).

[0158] In the areas of the active region 20, where the gate contacts 34 are formed, polysilicon also remains on the mesa region (the upper surface of the semiconductor layer 2), and this region has a rounded shape with a large radius of curvature (radius of curvature Re). As in the case described in the first embodiment, it is therefore possible to suppress the concentration of an electric field on the upper corner regions of the gate grooves 6 and thereby suppress the destruction of the gate insulating layer 7.

[0159] During the configuration, which is in Fig.Since the connection trench 16, located in the connection area 30, is machined to a large extent, the gate trenches 6, located in the cell area, or the gate trench 26 are formed with a minimal processing line width or feature width. As a result of this difference, the material-dependent coefficient of thermal expansion fluctuates according to the thermal history of the wafer process. This causes residual stresses, leads to differences in the electrical characteristics of the elements, and affects the reliability of the semiconductor device.

[0160] The cells located in the active area 20 are subjected to higher stresses as they approach the outermost peripheral areas of the gate trenches. As a result of this influence, the failure rate of the gate insulation layer 7 increases as it approaches the outermost peripheral areas of the gate trenches.

[0161] Consequently, it is effective to bring the gate potential into a potential-free or floating state by electrically isolating the outermost peripheral cells from the remaining cells, but this prevents the above area from functioning as a MOSFET.

[0162] In light of this, in the present embodiment, the thickness of the gate insulating layer 87, which is arranged in the cells located in the peripheral region (the boundary region between the active region 20 and the terminal region 30), is increased, or the impurity concentration of the diffusion protection layer 39 of these cells is designed to be lower than the impurity concentration of the diffusion protection layer 9 in the remaining cells in the active region 20. This suppresses the concentration of an electric field applied to the gate insulating layer 87 when the semiconductor device is switched on by applying a gate electrode. As a result, it is possible to suppress damage to the gate insulating layer and improve the reliability of the semiconductor device. Effects achieved by the embodiments described above

[0163] Examples of the effects achieved by the embodiments described above are shown below. Although the following description discusses these effects based on specific configurations, examples of which are described in the embodiments above, the specific configurations can be replaced by any other specific configuration, as described as an example in the description of the present invention, within the scope in which similar effects are achieved. This means that—although for the sake of simplicity only one of the identifiable specific configurations can be described below in the name of all specific configurations—this specific configuration can be replaced by any other specific configuration identifiable with the specific configuration.

[0164] This exchange can take place across multiple embodiments. That is, similar effects can be achieved through a combination of examples described in different embodiments.

[0165] According to the embodiments described above, the semiconductor device comprises the following: the first conductivity type (n-type) drift layer 3, the second conductivity type (p-type) base region 4 arranged in the surface layer of the drift layer 3, the plurality of n-type source regions 5 arranged in the surface layer of the base region 4, at least one trench (e.g., the gate trench 6, the gate trench 26, or the terminal trench 16) extending from the upper surface of the drift layer 3 into the interior of the drift layer 3 via the base region 4, and the p-type protective layer (e.g.,the diffusion protection layer 9, the diffusion protection layer 39 or the connection protection layer 19), which is arranged in the drift layer 3 below the trench, the gate insulation layer 7, which is arranged along the inside of the trench, including the upper corner area of ​​the trench, and the gate electrodes 8, which are arranged at least in the trench and are surrounded by the gate insulation layer 7.

[0166] Here, the areas subdivided in the trench in the top view are defined as the first and second areas. The semiconductor device further comprises the source electrode 11, which is electrically connected to the source areas 5 located adjacent to the trench in the first area (the gate trench 6), and the gate lead 18, which is located on the upper surface of the gate electrode 8, which is located in the trench in the second area (the gate trench 6 or the terminal trench 16). The radius of curvature Re of the gate insulating layer 7, which is located on the upper corner area of ​​the trench in the second area (the gate trench 6 or the terminal trench 16), is larger than the radius of curvature Rc of the gate insulating layer 7, which is located on the upper corner area of ​​the trench in the first area (the gate trench 6).

[0167] With this configuration, the following applies: Even if a gate voltage is applied to the gate insulating layer 7, which has a rounded shape with a large radius of curvature (the radius of curvature Re), the concentration of an electric field is effectively suppressed due to the large radius of curvature, and the application of a high electric field is suppressed. Consequently, it is possible to prevent damage to the gate insulating layer 7.

[0168] It should be noted that similar effects are achieved even if any other configuration described as an example in the description of the present invention is appropriately added to the configuration described above, i.e., even if any other configuration not referred to in the configuration described above but described in the description of the present invention is appropriately added to the configuration described above.

[0169] According to the embodiments described above, the gate conductor 18 is arranged on the upper surfaces of the gate electrodes 8, extending to the upper surfaces of the source regions 5. This configuration suppresses damage to the gate insulating layer and improves the reliability of the semiconductor device.

[0170] According to the embodiments described above, the gate line 18 is connected via the plurality of contact holes (the gate contacts 34) to the upper surfaces of the gate electrodes 8, which extend to the upper surfaces of the source regions 5. This configuration suppresses damage to the gate insulating layer and improves the reliability of the semiconductor device.

[0171] According to the embodiments described above, the gate insulating layer 7 arranged in the trenches in the first region and the gate insulating layer 7 arranged in the trenches in the second region have the same thickness. With this configuration, it is possible to form the gate insulating layer 7 in a plurality of trenches through a single process.

[0172] According to the embodiments described above, a plurality of trenches are present. At least one gate trench 6 is then arranged in the active area 20, and at least one gate trench 26 is arranged in the terminal area 30. The gate electrode 8, which is arranged in the gate trench 26 in the terminal area 30, is not electrically connected to the source electrode 11 and the gate line 18. With this configuration, element damage is suppressed by bringing the potential of the gate electrode 8 in the gate trench 26 into a potential-free or floating state.

[0173] According to the embodiments described above, a plurality of grooves are present. The gate grooves 6 are aligned in strips in the top view. The gate conductor 18 extends across the upper surfaces of the gate electrodes 8, which are arranged in the gate grooves 6. This configuration suppresses damage to the gate insulating layer and improves the reliability of the semiconductor device.

[0174] According to the embodiments described above, a plurality of trenches are present. At least one gate trench 6 is arranged in the active area 20, and at least one connection trench 16 is arranged in the connection area 30. The connection trench 16 located in the connection area 30 is wider than the gate trenches 6 (or gate trench 26) located in the active area 20. This configuration creates a structure in which polysilicon does not remain on the side wall of the connection trench 16. Consequently, it is possible to suppress the destruction of the gate insulating layer, compared to a structure in which an electric field is applied to the gate insulating layer 7, which serves as a lower layer, via polysilicon remaining on the side wall of the connection trench.

[0175] According to the embodiments described above, a plurality of trenches are present. At least one gate trench 6 is located in the active region 20, which is surrounded by the terminal region 30 in plan view. The gate insulating layer 87, located in the trenches at the boundary between the active region 20 and the terminal region 30 (gate trench 6 and gate trench 26), has a greater thickness than the gate insulating layer 7 located in the trenches in the active region 20 and the terminal region 30, which is distinct from the boundary region (gate trench 6 and terminal trench 16). This configuration suppresses the concentration of an electric field applied to the gate insulating layer 87 when the semiconductor device is switched on by applying a gate voltage. As a result, it is possible to suppress damage to the gate insulating layer and improve the reliability of the semiconductor device.

[0176] According to the embodiments described above, a plurality of trenches are present. At least one gate trench 6 is then arranged in the active region 20, which is surrounded in plan view by the terminal region 30. The protective layer arranged beneath the gate trenches 6 and the gate trench 26 in the boundary region between the active region 20 and the terminal region 30 (the diffusion protection layer 39) has a lower impurity concentration than the protective layer arranged beneath the trenches (the gate trenches 6 and the terminal trench 16) in the active region 20 and in the terminal region 30, which is distinct from the boundary region (the diffusion protection layer 9 or the terminal protection layer 19). This configuration suppresses the concentration of an electric field applied to the gate insulating layer 87 when the semiconductor device is switched on by applying a gate voltage.As a result, it is possible to suppress destruction of the gate insulating layer and improve the reliability of the semiconductor device.

[0177] According to the embodiments described above, in the method for manufacturing the semiconductor device, the p-type base region 4 is arranged in the surface layer of the n-type drift layer 3. Then, the plurality of n-type source regions 5 are arranged in the surface layer of the base region 4. Finally, at least one trench is provided, extending from the upper surface of the drift layer 3 to a location within the drift layer 3 via the base region 4 (e.g., the gate trench 6, the gate trench 26, or the connection trench 16).

[0178] The p-type protective layer (e.g., diffusion protective layer 9, diffusion protective layer 39, or connection protective layer 19) is then placed in drift layer 3 beneath the trench. The areas subdivided in the trench in plan view are defined as the first and second regions. In the first and second regions, the upper corner region of the trench (gate trench 6) is etched. In the second region, the upper corner region of the trench (gate trench 6 or connection trench 16) is etched. The gate insulating layer 7 is then placed along the interior of the trench, including the upper corner region. Finally, the gate electrode 8 is placed in the trench surrounded by the gate insulating layer 7. Then the source electrode 11 is arranged so that it is electrically connected to the source areas 5 that are adjacent to the trench in the first area (the gate trench 6).The gate conductor 18 is then positioned on the upper surface of the gate electrode 8, which is located in the trench in the second area (the gate trench 6 or the connection trench 16). The radius of curvature Re of the gate insulating layer 7, which is located on the upper corner of the trench in the second area (the gate trench 6 or the connection trench 16), is larger than the radius of curvature Rc of the gate insulating layer 7, which is located on the upper corner of the trench in the first area (the gate trench 6).

[0179] With this configuration, the following applies: Even if a gate voltage is applied to the gate insulating layer 7, which has a rounded shape with a large radius of curvature (the radius of curvature Re), it is possible to effectively suppress the concentration of an electric field due to the large radius of curvature, and thus prevent the application of a high electric field. Consequently, damage to the gate insulating layer 7 is suppressed.

[0180] It should be noted that the order of each processing step can be changed unless specifically restricted otherwise.

[0181] It should be noted that similar effects are achieved even if any other configuration described as an example in the description of the present invention is suitably added to the configuration described above, i.e., even if any other configuration not referred to in the configuration described above but described in the description of the present application is suitably added. Variations of the embodiments described above

[0182] The embodiments described above may, in some cases, describe features such as the quality, material, size, and shape of each element, the relationship of the relative positions of the elements, and the conditions for implementing the present invention. However, all these features are merely examples and are not limited to them.

[0183] Accordingly, it is assumed that an unlimited number of variations and equivalents not described as examples fall within the scope of the invention disclosed in the description of the present application. For example, it is assumed that the scope of the invention includes cases in which at least one element is modified, added, or omitted, and in which at least one element is extracted from at least one embodiment and combined with an element described in another embodiment.

[0184] In cases where features such as the name of a material are described without specific description in at least one of the embodiments described above, it is assumed that the material includes some other additive, such as an alloy, unless a contradiction arises. Reference symbol list 3 Drift layer 4 Basic area 5 Source area 6 Gate Trench 7 Gate insulating layer 8 Gate electrode 11 Source electrode 16 Connection trench 18 Gate line 20 active area 26 Gate Trench 30 Connection area 34 Gate contact 87 Gate insulating layer 97 Gate insulating layer 100 semiconductor equipment 101 Semiconductor Equipment 102 Semiconductor equipment 103 Semiconductor equipment Area 108 Area 109 1000 area. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2001 - 511 315 A

[0006] JP 2006 - 520 091 A

[0006]

Claims

[1] Semiconductor device comprising: a drift layer of a first conductivity type; a base region of a second conductivity type, which is located in a surface layer of the drift layer; a plurality of source regions of the first conductivity type, arranged in a surface layer of the base region; at least one trench running from an upper surface of the drift layer through the base area into the third layer; a protective layer of the second conductivity type, which is arranged in the drift layer located under the trench; a gate insulation layer arranged along the inside of the trench, including an upper corner area of ​​the trench; a gate electrode that is at least arranged in the trench and surrounded by the gate insulating layer; a source electrode that is electrically connected to the source areas adjacent to the trench; and a gate conductor located on an upper surface of the gate electrode, running in the trench, wherein, among the areas subdivided in the trench in plan view, an area where the source electrode is located is defined as a first area, and an area where the gate line is located is defined as a second area, and The gate insulation layer located on the upper corner of the trench in the second area has a larger radius of curvature than the gate insulation layer located on the upper corner of the trench in the first area. [2] Semiconductor device according to claim 1, wherein the gate line is arranged on the upper surface of the gate electrode, extending to the upper surfaces of the source regions. [3] Semiconductor device according to claim 2, wherein the gate line is connected to the upper surface of the gate electrode via a plurality of contact holes extending to the upper surfaces of the source regions. [4] Semiconductor device according to any one of claims 1 to 3, wherein the gate insulating layer arranged in the trench in the first region and the gate insulating layer arranged in the trench in the second region have the same thickness. [5] Semiconductor device according to any one of claims 1 to 4, where the ditch has a plurality of ditches, at least one of the trenches in each is arranged by an active area and a connecting area that surrounds the active area in plan view, and The gate electrode, which is located in the trench in the connection area, is not electrically connected to the source electrode and the gate lead. [6] Semiconductor device according to any one of claims 1 to 5, where the ditch has a plurality of ditches, the majority of ditches are aligned in strips in plan view, and wherein the gate conductor is arranged across the upper surface of the gate electrode, which is located in each of the plurality of trenches. [7] Semiconductor device according to any one of claims 1 to 6, wherein the trench has a plurality of trenches, at least one of the trenches being arranged in each of an active area and a connecting area surrounding the active area in plan view, wherein the trenches arranged in the active area and in the connecting area are spaced apart from each other, and The trench in the connecting area is wider than the trench in the active area. [8] Semiconductor device according to any one of claims 1 to 7, wherein the trench has a plurality of trenches, at least one of the trenches is located in an active area which is surrounded by a connecting area in plan view, and The gate insulation layer located in the trench situated in a boundary area between the active area and the connection area has a greater thickness than the gate insulation layer located in the trench situated in the active area and in the connection area outside the boundary area. [9] Semiconductor device according to any one of claims 1 to 8, where the ditch has a plurality of ditches, at least one of the trenches is located in an active area surrounded by a connecting area in plan view, and The protective layer located under the trench, which is situated in a border area between the active area and the connection area, has a lower concentration of faults than the protective layer located under the trench, which is situated in the active area and in the connection area outside the border area. [10] Method for manufacturing a semiconductor device, the method comprising: Arranging a base region of a second conductivity type in a surface layer of a drift layer of a first conductivity type; Arranging a plurality of source regions of the first conductivity type in a surface layer of the base region; Arranging at least one trench that runs from an upper surface of the drift layer through the base area into the interior of the drift layer; Arranging a protective layer of the second conductivity type in the drift layer located under the trench; Defining areas in the trench that are subdivided in plan view as a first area and a second area; Etching of an upper corner area of ​​the trench in the first area and in the second area, Etching of the upper corner area of ​​the trench in the second area; Arrange a gate insulation layer along the inside of the trench, including the upper corner area of ​​the trench; Arranging a gate electrode in the trench surrounded by the gate insulating layer; Arranging a source electrode that is electrically connected to the source areas adjacent to the trench in the first area; and Arranging a gate line on an upper surface of the gate electrode, which runs in the trench in the second area, wherein the gate insulation layer located on the upper corner area of ​​the trench in the second area has a larger radius of curvature than the gate insulation layer located on the upper corner area of ​​the trench in the first area.

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