POWER CONVERSION DEVICE

Abstract

An inverter circuit is a three-level inverter circuit. The inverter circuit comprises: a P busbar (71) connected to a high-potential terminal of a battery, an N busbar (72) connected to a low-potential terminal of the battery, and an M busbar (73) with a potential between the P busbar (71) and the N busbar (72). The inverter circuit also includes: a PM capacitor (30) connected to the P busbar and the N busbar, an MN capacitor (40) connected to the N busbar and the M busbar, and a semiconductor device (20) connected to the M busbar.The M busbar is a part between (i) the second power module (20) and (ii) the PM capacitor and the MN capacitor, is arranged between the P busbar and the N busbar and has a base section (73a) opposite the P busbar and the N busbar.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] The present application is based on Japanese patent application number 2023-005267, which was filed on January 17, 2023, and whose entire contents are hereby incorporated by reference. TECHNICAL AREA

[0002] The present disclosure relates to an electrical power conversion device. STATE OF THE ART

[0003] As an example of a conventional multi-level inverter, a three-level inverter is disclosed in patent document 1. The three-level inverter comprises a cooling fin base, a first switching element, a first diode, a second switching element, a fourth switching element, a second diode, a third switching element, and a connecting plate. Furthermore, the three-level inverter is provided with the first switching element, the first diode, the second switching element, the fourth switching element, the second diode, and the third switching element, which are arranged on both sides of the cooling fin base, with their rear surfaces facing each other. In the three-level inverter, the switching elements and the diodes are each connected by the connecting plate, which is oriented such that it faces the three surfaces of the cooling fin base. DOCUMENT ACCORDING TO THE STATE OF THE TECHNOLOGY PATENT DOCUMENT

[0004] Patent document 1: JP H10 - 201 249 A SUMMARY OF THE INVENTION

[0005] In the three-level inverter, the center-tap wiring is divided into two parts, with the cooling fin base positioned between them. Therefore, a problem arises with this three-level inverter: the inductance between the high-potential and low-potential wiring becomes significant. Furthermore, improvements to the power conversion device are required in the aspects described above and others not mentioned previously.

[0006] It is an objective of the present disclosure to provide a power conversion device that has a reduced inductance.

[0007] A power conversion device according to one embodiment of the present disclosure is capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels through an output wiring. The power conversion device comprises: a high-potential wiring connected to a positive electrode of a power source; a low-potential wiring connected to a negative electrode of the power source; at least one center-tap wiring having a potential between the high-potential wiring and the low-potential wiring; a first power module connected to the high-potential wiring, the low-potential wiring, and the output wiring; and a first capacitor having a high-potential electrode connected to the high-potential wiring and a first center-tap electrode connected to the center-tap wiring.a second capacitor having a low-potential electrode connected to the low-potential wiring and a second mid-potential electrode connected to the mid-potential wiring; and a second power module connected to the mid-potential wiring and the output wiring. In the power conversion device, at least one mid-potential wiring section is located between (i) the second power module and (ii) the first capacitor and the second capacitor, is arranged between the high-potential wiring and the low-potential wiring, and has a counter section opposite the high-potential wiring and the low-potential wiring.

[0008] In the power conversion device disclosed above, the center-tap wiring is arranged between the high-potential and low-potential wiring and has a counterpart section opposite both the high-potential and low-potential wiring. Therefore, the power conversion device can cancel a magnetic field at a position between the high-potential wiring and the counterpart section of the center-tap wiring, and also at a position between the counterpart section of the center-tap wiring and the low-potential wiring. Thus, the power conversion device can effectively reduce inductance.

[0009] The various embodiments disclosed in the description employ different technical solutions to solve their respective tasks. Reference numerals in parentheses, as described in the claims and in this section, illustrate corresponding relationships with parts of embodiments described later and are not intended to limit the technical scope. The tasks, features, and advantages disclosed in the description become clear by reference to the detailed description below and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a circuit diagram illustrating a schematic configuration of an inverter circuit according to a first embodiment. Fig. Figure 2 shows a cross-sectional view illustrating a schematic configuration of the inverter circuit. Fig. Figure 3 shows a cross-sectional view along a line III-III in Fig. 2 is taken, Fig. 4 shows a top view from the direction of arrow IV in Fig. 2 is seen, Fig. Figure 5 shows a perspective view illustrating a schematic configuration of the inverter circuit. Fig. Figure 6 shows a cross-sectional view illustrating a schematic configuration of a capacitor device according to a second embodiment. Fig. Figure 7 shows a cross-sectional view illustrating a schematic configuration of a capacitor device according to a third embodiment. Fig. Figure 8 shows a cross-sectional view illustrating a schematic configuration of a capacitor device according to a fourth embodiment. Fig. Figure 9 shows a top view illustrating a schematic configuration of a capacitor device according to a fifth embodiment, Fig. Figure 10 shows a cross-sectional view extending along a line XX from Fig. 9 is taken, Fig. Figure 11 shows a cross-sectional view extending along a line XI-XI in Fig. 9 is taken, Fig. Figure 12 shows a top view illustrating a schematic configuration of a capacitor device according to a sixth embodiment. Fig. Figure 13 shows a circuit diagram illustrating a schematic configuration of an inverter circuit according to a seventh embodiment. Fig. Figure 14 shows a cross-sectional view illustrating a schematic configuration of an inverter circuit. Fig. Figure 15 shows a perspective view illustrating an arrangement of a capacitor device. Fig. Figure 16 shows a perspective view illustrating an arrangement of a capacitor device according to an eighth embodiment. Fig. Figure 17 shows a cross-sectional view illustrating a schematic configuration of an inverter circuit according to a ninth embodiment. Fig. Figure 18 shows a cross-sectional view illustrating a schematic configuration of an inverter circuit according to a tenth embodiment, Fig. Figure 19 shows a cross-sectional view illustrating a schematic configuration of an inverter circuit according to an eleventh embodiment, and Fig. Figure 20 shows a cross-sectional view illustrating a schematic configuration of an inverter circuit according to a twelfth embodiment. Examples of how to implement the invention

[0010] Several embodiments for realizing the present disclosure are described below with reference to the drawings. In each embodiment, sections corresponding to those described in the preceding embodiments are designated by the same reference numerals, and in some cases redundant descriptions are omitted. In each embodiment, if only part of the configuration is explained, the previously explained other embodiment applies to the other part of such embodiment. (First embodiment)

[0011] An inverter circuit 100 according to a first embodiment is described with reference to Fig. Sections 1 to 5 describe the inverter circuit 100. It is configured to divide an input DC voltage into a multitude of values ​​and output voltages at a multitude of levels. The inverter circuit 100 is a so-called multi-level inverter. While a two-level inverter can output voltages of +E, -E, 0, and two other levels as zero, assuming the voltage of a battery is 200 E, a multi-level inverter can output voltages of three or more levels. In the present embodiment, a three-level inverter circuit 100 is used as an example.

[0012] The inverter circuit 100 can be mounted on a moving object such as a vehicle or an aircraft. As shown in Fig. As shown in Figure 1, the inverter circuit 100 is electrically connected to the battery 200 and a motor 300. The motor 300 is a three-phase motor with a U-phase coil 301, a V-phase coil 302, and a W-phase coil 303. The motor 300 could, for example, be a motor-generator or the like. The inverter circuit 100 converts direct current power output by the battery 200 into three-phase alternating current power and supplies the three-phase alternating current power to the motor 300. The inverter circuit 100 corresponds to a power conversion device. <Schaltungskonfiguration der Wechselrichterschaltung 100>

[0013] The circuit configuration of the inverter circuit 100 is based on Fig. 1 described. The inverter circuit 100 has switching elements 11 to 16, a U-phase center section 21, a V-phase center section 22, a W-phase center section 23, a capacitor device 60 and the like. In Fig. Figure 1 illustrates a PM capacitor 30 and an MN capacitor 40 contained in the capacitor device 60.

[0014] The switching elements 11 to 16 can be MOSFETs, IGBTs, or the like. Furthermore, the switching elements 11 to 16 can be made primarily of a wide-bandgap semiconductor such as silicon (Si) or silicon carbide (SiC). The gates of the switching elements 11 to 16 are connected to an electronic control device (not shown). The switching elements 11 to 16 are controlled and driven by the electronic control device.

[0015] The switching elements 11 to 16 have a U-phase upper branch element 11, a U-phase lower branch element 12, a V-phase upper branch element 13, a V-phase lower branch element 14, a W-phase upper branch element 15 and a W-phase lower branch element 16.

[0016] The U-phase upper branch element 11 and the U-phase lower branch element 12 are connected in series between a high-potential terminal (P) and a low-potential terminal (N) of the battery 200. A source terminal of the U-phase upper branch element 11 and a drain terminal of the U-phase lower branch element 12 are connected to the U-phase coil 301. The U-phase upper branch element 11 and the U-phase lower branch element 12 can be collectively referred to as a U-phase branch.

[0017] The V-phase upper branch element 13 and the V-phase lower branch element 14 are connected in series between the high-potential terminal and the low-potential terminal of battery 200. The source terminal of the V-phase upper branch element 13 and the drain terminal of the V-phase lower branch element 14 are connected to the V-phase coil 302. The V-phase upper branch element 13 and the V-phase lower branch element 14 can be collectively referred to as a V-phase branch.

[0018] The W-phase upper branch element 15 and the W-phase lower branch element 16 are connected in series between the high-potential terminal and the low-potential terminal of battery 200. The source terminal of the W-phase upper branch element 15 and the drain terminal of the W-phase lower branch element 16 are connected to the W-phase coil 303. The W-phase upper branch element 15 and the W-phase lower branch element 16 can be collectively referred to as a W-phase branch.

[0019] In this way, each branch is connected in series between a P-busbar 71 and an N-busbar 72, which are described later. With regard to the structure of the switching elements 11 to 16, the battery 200, which is described later, corresponds to a power source. The high-potential terminal corresponds to a positive electrode. The low-potential terminal corresponds to a negative electrode.

[0020] The U-phase center section 21, the V-phase center section 22, and the W-phase center section 23 are connected to a midpoint (neutral point) M between a high potential and a low potential and to each branch. Each of the center sections 21 to 23 has two switching elements. The switching elements can be the same as the switching elements 11 to 16 described above. The gate electrodes of the switching elements are connected to the electronic control device. The switching elements are driven and controlled by the electronic control device. The midpoint M can be defined as a section of an intermediate potential between the high potential and the low potential. Furthermore, the midpoint M is a section between the PM capacitor 30 and the MN capacitor 40.

[0021] The U-phase center section 21 comprises a first U-phase center element 21a and a second U-phase center element 21b as switching elements. A drain terminal of the first U-phase center element 21a is connected to the center point M, and a source terminal of the first U-phase center element 21a is connected to the source terminal of the second U-phase center element 21b. The drain terminal of the second U-phase center element 21b is connected to the source terminal of the U-phase upper branch element 11 and the drain terminal of the U-phase lower branch element 12.

[0022] The V-phase center section 22 comprises a first V-phase center element 22a and a second V-phase center element 22b as switching elements. The drain terminal of the first V-phase center element 22a is connected to the center point M, and the source terminal of the first V-phase center element 22a is connected to the source terminal of the second V-phase center element 22b. The drain terminal of the second V-phase center element 22b is connected to the source terminal of the V-phase upper branch element 13 and the drain terminal of the V-phase lower branch element 14.

[0023] The W-phase center section 23 comprises a first W-phase center element 23a and a second W-phase center element 23b as switching elements. The drain terminal of the first W-phase center element 23a is connected to the center point M, and the source terminal of the first W-phase center element 23a is connected to the source terminal of the second W-phase center element 23b. The drain terminal of the second W-phase center element 23b is connected to the source terminal of the W-phase upper branch element 15 and the drain terminal of the W-phase lower branch element 16. The structures of the U-phase center section 21, the V-phase center section 22, and the W-phase center section 23 are described later.

[0024] The capacitor device 60 comprises the PM capacitor 30 and the MN capacitor 40 as smoothing capacitors. The PM capacitor 30 is connected between the high-potential terminal and the midpoint M. The MN capacitor 40 is connected between the midpoint M and the low-potential terminal. Therefore, the PM capacitor 30 and the MN capacitor 40 are connected in series.

[0025] The PM capacitor 30 and the MN capacitor 40 are primarily provided for voltage stabilization and current ripple absorption. In other words, the PM capacitor 30 and the MN capacitor 40 are designed to suppress permissible voltage fluctuations at the midpoint M and to reduce the current ripple flowing out of the inverter circuit 100. The PM capacitor 30 corresponds to a first capacitor. The MN capacitor 40 corresponds to a second capacitor.

[0026] The present disclosure is also applicable to an inverter circuit 100 of the diode-terminal type (T-type). The present disclosure is also applicable to inverter circuits 100 that have N levels or more (for example, N = 4). In such a case, the intermediate potential is N - 2. <Struktur der Wechselrichterschaltung 100>

[0027] The structure of the inverter circuit 100 is shown below with reference to Fig. Sections 2 to 5 are described. In the inverter circuit 100, the capacitor device 60 and a structural body in which semiconductor devices 10 and 20 and a cooler 90 are integrally assembled are arranged side by side. In the drawing, the orientation of the capacitor device 60 and the structural body is indicated by an arrow AD.

[0028] Furthermore, it shows how it is in Fig. As shown in Figures 2 to 5 and the like, the inverter circuit 100 connects the busbars 71 to 74, which connect the capacitors 30 to 50 to the semiconductor devices 10 and 20, respectively. The busbars 71 to 74 are conductive elements whose main component is copper or the like. The busbars 71 to 74 are flat, plate-shaped elements. Each of the busbars 71 to 74 is formed from a single flat, plate-shaped element. It can also be said that each of the busbars 71 to 74 is formed, for example, by bending a single metal plate.

[0029] The P-busbar 71 is connected to the high-potential terminal. The terminal connected to the high-potential terminal is therefore connected to the P-busbar 71. The P-busbar 71 corresponds to a high-potential wiring configuration.

[0030] As it is in Fig. 2 and Fig. As shown in Figure 4, the P-busbar 71 has a base section 71a, a switch connection section 71b connected to the base section 71a, and a capacitor connection section 71c connected to the base section 71a. The base section 71a is a base section connected to both the switch connection section 71b and the capacitor connection section 71c. The switch connection section 71b is connected to a P-terminal 1 of the semiconductor device 10, which will be described later. The capacitor connection section 71c is connected to a first PM terminal 31 of the PM capacitor 30, which will be described later.

[0031] The N busbar 72 is connected to the low-potential terminal. The terminal connected to the low-potential terminal is connected to the N busbar 72. The N busbar 72 corresponds to a low-potential wiring configuration.

[0032] As it is in Fig. 2 and Fig. As shown in Figure 4, the N busbar 72 has a base section 72a, a switch connection section 72b connected to the base section 72a, and a capacitor connection section 72c connected to the base section 72a. The base section 72a is a base section connected to both the switch connection section 72b and the capacitor connection section 72c. The switch-side connection section 72b is connected to an N terminal 2 of the semiconductor device 10. The capacitor connection section 72c is connected to a second MN terminal 42 of the MN capacitor 40, which is described later.

[0033] Furthermore, it shows how it is in Fig. As shown in Figure 5, the N-busbar 72 has an extension section 72d. The extension section 72d is a section that is connected to the base section 72a and extends to the O-busbar 74. The extension section 72d is arranged such that it is opposite the O-busbar 74. Fig. For the sake of simplicity, section 72d has been omitted from diagram 4. The N-busbar 72 does not need to include section 72d.

[0034] The M-bus 73 configures the center point M. The M-bus 73 has a potential between the P-bus 71 and the N-bus 72. The M-bus 73 is connected to the PM capacitor 30 and the MN capacitor 40. A terminal connected to the center point M is thus connected to the M-bus 73. The M-bus 73 corresponds to a center point wiring configuration. According to the present embodiment, a configuration with a (single) M-bus 73 is used. However, the present disclosure is not limited to such a configuration. The configuration can include at least one M-bus 73. The number of M-bus 73s varies depending on the number of output levels of the inverter circuit 100.

[0035] As it is in Fig. 2 and Fig. As shown in Figure 4, the M-busbar 73 has a base section 73a, a switch connection section 73b connected to the base section 73a, and a capacitor connection section 73c connected to the base section 73a. The base section 73a is a base section connected to the switch connection section 73b and the capacitor connection section 73c. ​​The switch connection section 73b is connected to an M-terminal 4 of the semiconductor device 20, which is described later.

[0036] The capacitor connection section 73c is connected to the second PM terminal 32 of the PM capacitor 30 and the first MN terminal 41 of the MN capacitor 40. This means that one surface of the capacitor connection section 73c is connected to the second PM terminal 32, and the opposite surface of the capacitor connection section 73c is connected to the first MN terminal 41. The capacitor connection section 73c is connected to both the PM capacitor 30 and the MN capacitor 40. In this way, according to the present embodiment, the M-busbar 73, which is equipped with only one (single) capacitor connection section 73c, is used as an example. The positional relationship between the busbars 71 to 73 is described in detail later.

[0037] The O-bus 74 is an output wiring connection that is connected to an O-terminal 3 of the semiconductor device 10. The inverter circuit 100 has the O-bus 74 connected to each of the U-phase coil 301, the V-phase coil 302, and the W-phase coil 303. The O-bus 74 corresponds to an output wiring connection.

[0038] According to the present embodiment, an insulating element 80 is provided, as an example, to electrically isolate the components from one another. The insulating element 80 is provided between the P busbar 71 and the M busbar 73, as well as between each of the busbars 71 and 73 and the PM capacitor 30. Furthermore, the insulating element 80 is provided between the M busbar 73 and the N busbar 72, as well as between each of the busbars 72 and 73 and the MN capacitor 40. However, if electrical isolation is possible, there is no need to provide the insulating element 80.

[0039] The semiconductor devices 10 and 20 are, for example, covered with an electrically insulating potting resin in a state in which two bare-chip switching elements are connected to each other. Furthermore, as described in Fig. 2, Fig. As shown in Figure 4, etc., the tips of terminals 1 to 5 of the semiconductor devices 10 and 20 are covered with potting resin. The inverter circuit 100 has a plurality of semiconductor devices 10 and a plurality of semiconductor devices 20. The semiconductor devices 10 and 20 are arranged side by side and attached to the cooler 90. Fig. In figure 4, the cooler 90 is omitted for the sake of simplicity.

[0040] The inverter circuit 100 has three semiconductor devices 10, each forming a branch. The U-phase branch semiconductor device 10 has the U-phase upper branch element 11 and the U-phase sub-branch element 12. The V-phase branch semiconductor device 10 has the V-phase upper branch element 13 and the V-phase sub-branch element 14. The W-phase branch semiconductor device 10 has the W-phase upper branch element 15 and the W-phase sub-branch element 16. The semiconductor device 10 also has the P-terminal 1, the N-terminal 2, the O-terminal 3, and the signal terminal 5. The semiconductor device 10 can also be referred to as a branch device. The semiconductor device 10 corresponds to a first power module.

[0041] The inverter circuit 100 has three semiconductor devices 20 that form the middle sections 21 to 23. The semiconductor device 20 of the U-phase middle section 21 has the first U-phase middle element 21a and the second U-phase middle element 21b. The semiconductor device 20 of the V-phase middle section 22 has the first V-phase middle element 22a and the second V-phase middle element 22b. The semiconductor device 20 of the W-phase middle section 23 has the first W-phase middle element 23a and the second W-phase middle element 23b. The semiconductor device 20 also has the O-terminal 3, the M-terminal 4, and the signal terminal 5.

[0042] The semiconductor device 20 can also be referred to as a central device. The semiconductor device 20 corresponds to a second power module.

[0043] As it is in Fig. As shown in Figure 4, P terminal 1 is connected to P busbar 71. N terminal 2 is connected to N busbar 72. O terminal 3 is connected to O busbar 74. M terminal 4 is connected to M busbar 73. As shown in Fig. As shown in Figure 2, the signal terminal 5 is connected to a printed circuit board 110. The printed circuit board 110 is a board (circuit board) on which conductive wiring is provided on an insulating base material such as resin or the like. The printed circuit board 110 is connected to an electronic control device.

[0044] The cooler 90 is configured to circulate a coolant such as water to cool the semiconductor devices 10 and 20. The cooler 90 surrounds the semiconductor devices 10 and 20 in a sandwich-like manner between the sections through which the coolant flows.

[0045] Therefore, the switch connection sections 71b to 73b, which are connection sections connected to terminals 1 to 4, of the busbars 71 to 74 are arranged close to the cooler 90. Furthermore, as described above, the busbars 71 to 74 are connected to terminals 1 to 4 of the semiconductor devices 10 and 20, which are cooled by the cooler 90. Therefore, the busbars 71 to 74 are cooled by the cooler 90 together with the semiconductor devices 10 and 20. It can also be said that one end of the busbars 71 to 73 is connected to the structural body, and the other end of the busbars 71 to 73 is connected to the capacitor device 60.

[0046] As it is in Fig. 2 and Fig. As shown in Figure 3, the capacitor device 60 comprises capacitors 30 and 40, a capacitor housing 61, and a potting resin 63. The capacitors 30 and 40 are housed in the capacitor housing 61, which has an opening 62 formed in part of it. The capacitor housing 61 is filled with the potting resin 63 in such a way that the capacitors 30 and 40 are contained within it. That is to say, the capacitor housing 61 contains the capacitors 30 and 40 and the potting resin 63, which are enclosed in a single space. The capacitors 30 and 40 are potted with the potting resin 63.

[0047] Furthermore, sections of the P busbar 71, the N busbar 72, and the M busbar 73 are arranged within the capacitor housing 61 for connection to the capacitors 30 and 40. The sections of the P busbar 71, the N busbar 72, and the M busbar 73 arranged in the capacitor housing 61 are potted with the potting resin 63. Furthermore, as shown in Fig. Figure 3 shows the P busbar 71, the N busbar 72 and the M busbar 73 from the opening 62.

[0048] In this way, the capacitor assembly 60 comprises the two capacitors 30 and 40 held in one piece. The capacitor assembly 60 can also be referred to as the capacitor structure body. Furthermore, the capacitors 30 and 40 can be configured with a single capacitor element or with a plurality of capacitor elements. The capacitor element here is a film capacitor.

[0049] As it is in Fig. As shown in Figure 2, the PM capacitor 30 has a first PM terminal 31 and a second PM terminal 32. The first PM terminal 31 is connected to the P busbar 71. The second PM terminal 32 is connected to the M busbar 73. The PM capacitor 30 corresponds to a first capacitor. The first PM terminal 31 corresponds to a high-potential electrode. The second PM terminal 32 corresponds to a first center-tap electrode.

[0050] The MN capacitor 40 has a first MN terminal 41 and a second MN terminal 42. The first MN terminal 41 is connected to the M busbar 73. The second MN terminal 42 is connected to the N busbar 72. The MN capacitor 40 corresponds to a second capacitor. The first MN terminal 41 corresponds to a second center-trigger electrode. The second MN terminal 42 corresponds to a low-potential electrode.

[0051] Furthermore, as is stated in Fig. 2 and Fig. Figure 5 shows the PM capacitor 30 and the MN capacitor 40 in a stacked arrangement along a direction that intersects an arrangement direction AD. According to the present embodiment, as an example, the PM capacitor 30 and the MN capacitor 40 are in a stacked arrangement along a direction that is perpendicular to the arrangement direction AD.

[0052] More precisely, the PM capacitor 30 and the MN capacitor 40 are stacked such that the second PM terminal 32 of the PM capacitor 30 and the first MN terminal 41 of the MN capacitor 40 are opposite each other. In other words, the second PM terminal 32 and the first MN terminal 41 are arranged so that they are opposite each other.

[0053] The capacitor connection section 73c, which is part of the M-bus 73, is arranged between the PM capacitor 30 and the MN capacitor 40. The capacitor connection section 73c is sandwiched between the PM capacitor 30 and the MN capacitor 40. The capacitor connection section 73c is connected to the second PM terminal 32 and the first MN terminal 41. In other words, the second PM terminal 32 and the first MN terminal 41 are connected to the same M-bus 73. The capacitor connection section 73c corresponds to a connection section.

[0054] Therefore, as it is in Fig. 2, indicated by a dashed line interrupted by two dots, the M-busbar 73 connects the capacitor connection section 73c, which runs parallel to the PM capacitor 30 and the MN capacitor 40. In other words, the capacitor connection section 73c is arranged such that it is opposite the PM capacitor 30 and the MN capacitor 40. Furthermore, the capacitor connection section 73c is connected to the PM capacitor 30 and the MN capacitor 40. Therefore, it can be said that the capacitor connection section 73c and the PM capacitor 30, as well as the capacitor connection section 73c and the MN capacitor 40, are arranged in positions such that their magnetic fields can cancel each other out. In this way, it is made possible for the inverter circuit 100 to reduce the inductance between the second PM terminal 32 and the first MN terminal 41.

[0055] Therefore, inverter circuit 100 exhibits a smaller extent along the arrangement direction AD than a configuration in which the PM capacitors 30 and the MN capacitors 40 are arranged along the arrangement direction AD. It can also be said that inverter circuit 10 exhibits a smaller extent in a direction perpendicular to the stacking direction of the PM capacitor 30 and the MN capacitor 40. Furthermore, it can be said that the PM capacitor 30 and the MN capacitor 40 are stacked in a thickness direction of both capacitors 30 and 40. In short, it can be said that the PM capacitor 30 and the MN capacitor 40 are in a stacked arrangement.

[0056] The thickness direction is perpendicular to the connection surfaces of terminals 31 and 32 with busbars 71 and 73. The thickness direction is also perpendicular to the connection surfaces of terminals 41 and 42 with busbars 72 and 73. <Positionsbeziehung der Sammelschienen 71 bis 73>

[0057] As it is in Fig. 2, Fig. 3 and Fig. As shown in Figure 5, the base section 73a of the M-busbar 73 is arranged between (a) the semiconductor device 20 and (b) the capacitors 30 and 40. A portion of the base section 73a is arranged between the P-busbar 71 and the N-busbar 72 and faces both the P-busbar 71 and the N-busbar 72. Furthermore, the base section 73a has a section that faces the base section 71a of the P-busbar 71 and the base section 72a of the N-busbar 72. A portion of the base section 73a is provided outside the potting resin 63 such that it faces the base sections 71a and 72a. A further portion of the base section 73a is also provided within the potting resin 63 such that it faces the base sections 71a and 72a.

[0058] It can also be said that part of the base section 73a runs parallel to part of the P busbar 71 and part of the N busbar 72. It can also be said that the base section 73a is stacked together with the base sections 71a and 72a, with the insulating element 80 positioned between them. The base section 73a is stacked at a short distance from (facing) the base sections 71a and 72a. This short distance is such that the magnetic field can be canceled out. Part of the base section 73a can be considered to be a counterpart (opposite section). The portion of the base section 73a that corresponds to the counterpart can be considered a section facing the base sections 71a and 72a at a short distance. <wirkungen>

[0059] As indicated by the dashed line interrupted by two dots in Fig. As shown in Figure 2, the inverter circuit 100 has the M-busbar 73 arranged between the P-busbar 71 and the N-busbar 72 and has the base section 73a opposite the P-busbar 71 and the N-busbar 72. Therefore, the inverter circuit 100 can cancel the magnetic field (a) between the P-busbar 71 and the base section 73a of the M-busbar 73 and (b) between the base section 73a and the N-busbar 72. Therefore, the inverter circuit 100 can reduce the inductance. In other words, the inverter circuit 100 can reduce the inductance (a) between the P-busbar 71 and the M-busbar 73 and (b) between the M-busbar 73 and the N-busbar 72. Furthermore, the inverter circuit 100 can reduce inductance, thereby suppressing surge voltage. Therefore, the inverter circuit 100 can reduce losses.

[0060] It should be noted that the other embodiments are similar in that part of the base section 73a is arranged between and opposite the P busbar 71 and the N busbar 72. Therefore, according to the other embodiments, the inductance can be reduced, similar to the present embodiment.

[0061] One embodiment of the present disclosure has been described above. However, the present disclosure is not limited to the embodiment described above. Various modifications can be made without deviating from the scope and concept of the present disclosure. Embodiments two through twelve are described below as other embodiments of the present disclosure. The embodiment described above and embodiments two through twelve can be implemented independently or in suitable combinations. The present disclosure is not limited to the combinations described in the embodiments but can be implemented in various combinations.

[0062] The following embodiments mainly describe differences compared to the embodiment described above. The second through sixth embodiments differ from the first embodiment mainly in (a) the positional relationship between the PM capacitor 30 and the MN capacitor 40, and (b) the configurations of the busbars 71 to 73. The seventh embodiment differs from the first embodiment mainly in that a PN capacitor 50 is provided. (Second example)

[0063] An inverter circuit 100 according to a second embodiment is described below with reference to Fig. 6 described. Fig. Figure 6 shows partial illustrations of busbars 71 to 73. The same applies to the third to sixth embodiments described later.

[0064] A PM capacitor 30 and an MN capacitor 40 are stacked in a direction perpendicular to an arrangement direction AD. Furthermore, the PM capacitor 30 and the MN capacitor 40 are arranged such that their side walls face each other. The side wall of the PM capacitor 30 is a surface continuous with a first PM terminal 31 and a second PM terminal 32. The side wall of the MN capacitor 40 is a surface continuous with a first MN terminal 41 and a second MN terminal 42.

[0065] The second PM terminal 32 and the first MN terminal 41 are arranged along an imaginary plane perpendicular to the arrangement direction AD. Likewise, the first PM terminal 31 and the second MN terminal 42 are arranged along another imaginary plane perpendicular to the arrangement direction AD. The second PM terminal 32 and the first MN terminal 41 are located closer to the bottom of a capacitor housing 61 than the first PM terminal 31 and the second MN terminal 42. The bottom of the capacitor housing 61 is a position facing the opening 62.

[0066] The P-busbar 71 is bent from one end of a base section 71a to provide a capacitor connection section 71c. The capacitor connection section 71c is connected to the first PM terminal 31. The capacitor connection section 71c and the first PM terminal 31 are joined by welding or the like.

[0067] An N-type busbar 72 is bent from one end of a base section 72a to provide a capacitor connection section 72c. The capacitor connection section 72c is connected to the second MN terminal 42. The capacitor connection section 72c and the second MN terminal 42 are joined by welding or the like.

[0068] An M-busbar 73 has a base section 73a oriented along the AD direction of assembly. The M-busbar 73 has a capacitor connection section 73c located at one end of the base section 73a. The M-busbar 73 is provided with the capacitor connection section 73c connected to the second PM terminal 32 and the capacitor connection section 73c connected to the first MN terminal 41. In other words, the M-busbar 73 has two capacitor connection sections 73c. ​​The two capacitor connection sections 73c are oriented perpendicular to the AD direction of assembly. The capacitor connection section 73c is welded to the second PM terminal 32 and the first MN terminal 41.

[0069] The base section 73a is designed to project from a position between the two capacitor connection sections 73c. ​​The base section 73a has a portion that is sandwiched between the PM capacitor 30 and the MN capacitor 40. In other words, part of the base section 73a is located between the side wall of the PM capacitor 30 and the side wall of the MN capacitor 40. The base section 73a is not in contact with these side walls.

[0070] In inverter circuit 100, terminals 31, 32 of PM capacitor 30 and terminals 41, 42 of MN capacitor 40 are not arranged so that they face each other. Therefore, inverter circuit 100 can easily connect terminals 31, 32, 41 and 42 to the capacitor connection sections 71c to 73c. (Third embodiment)

[0071] An inverter circuit 100 according to a third embodiment is described below with reference to Fig. As described in Figure 7, a PM capacitor 30 and an MN capacitor 40 are arranged side by side along an arrangement direction AD. Furthermore, the PM capacitor 30 and the MN capacitor 40 are arranged such that their side walls face each other. A second PM terminal 32 and a second MN terminal 42 are arranged along the arrangement direction AD. Likewise, a first PM terminal 31 and a first MN terminal 41 are arranged along the arrangement direction AD. In other words, the second PM terminal 32 and the second MN terminal 42 are arranged on the same imaginary plane along the arrangement direction AD. The first PM terminal 31 and the first MN terminal 41 are arranged on the same imaginary plane along the arrangement direction AD. The two imaginary planes are located at different positions in a direction perpendicular to the arrangement direction AD.The MN capacitor 40 is located closer to the underside of a capacitor housing 61 than the PM capacitor 30.

[0072] An M-busbar 73 is provided with one capacitor connection section 73c connected to the second PM terminal 32 and another capacitor connection section 73c connected to the first MN terminal 41. In other words, the M-busbar 73 is provided with two capacitor connection sections 73c. ​​One capacitor connection section 73c is provided with the M-busbar 73 via a curved section relative to the other capacitor connection section 73c. ​​The M-busbar 73 has a section (connection section) that connects the two capacitor connection sections 73c. ​​The connection section is located between the PM capacitor 30 and the MN capacitor 40. It should be noted that the two capacitor connection sections 73c are different sections of a single metal plate.Therefore, it can be said that the connecting section is an intermediate section between the two capacitor connecting sections 73c.

[0073] As indicated by the dashed line interrupted by two dots in Fig. As shown in Figure 7, the inverter circuit 100 can be arranged such that the base section 72a and the capacitor connection section 73c face each other at the PM capacitor 30. Therefore, the inverter circuit 100 can further reduce the inductance between the N busbar 72 and the M busbar 73.

[0074] Furthermore, in the inverter circuit 100, the PM capacitors 30 and the MN capacitors 40 are arranged along the arrangement direction AD. Therefore, the inverter circuit 100 can be implemented with a low height in a direction perpendicular to the arrangement direction AD. (Fourth example)

[0075] An inverter circuit 100 according to a fourth embodiment is described below with reference to Fig. Figure 8 describes the following: A PM capacitor 30 and an MN capacitor 40 are stacked in a direction perpendicular to an arrangement direction AD. Furthermore, the PM capacitor 30 and the MN capacitor 40 are stacked such that a first PM terminal 31 and a first MN terminal 41 face each other.

[0076] An M-busbar 73 is provided with a capacitor connection section 73c, which is connected to a second PM terminal 32, and a capacitor connection section 73c, which is connected to the first MN terminal 41. The second M-busbar 73 has a section (connection section) that connects the two capacitor connection sections 73c. ​​The capacitor connection section 73c, which is connected to the first MN terminal 41, is arranged in a region where the PM capacitor 30 and the MN capacitor 40 face each other. Furthermore, the connection section and a base section 72a are arranged between the capacitors 30, 40 and the underside of a capacitor housing 61.

[0077] In the inverter circuit 100, a capacitor connection section 71c and the capacitor connection section 73c can be arranged such that they face each other at a position between the capacitors 30 and 40, as indicated by a dashed line interrupted by two dots in Fig. 8 is specified. Therefore, the inverter circuit 100 can further reduce the inductance between the P busbar 71 and the M busbar 73.

[0078] Furthermore, in the inverter circuit 100, the base section 72a of an N-busbar 72 and the connecting section of the M-busbar 73 can be arranged such that they face each other at a position between the capacitors 30, 40 and the underside of the capacitor housing 61. Therefore, the inverter circuit 100 can further reduce the inductance between the N-busbar 72 and the M-busbar 73. It should be noted that the inverter circuit 100 can achieve the same effects even if the PM capacitor 30 and the MN capacitor 40 are stacked such that the second PN terminal 32 and the second MN terminal 42 face each other. (Fifth example)

[0079] An inverter circuit 100 according to a fifth embodiment is described with reference to Fig. Described in sections 9 to 11. Fig. For the sake of simplicity, a capacitor housing 61 and a potting resin 63 have been omitted from Figure 9.

[0080] As it is in Fig. As shown in Figure 9, a PM capacitor 30 and an MN capacitor 40 are arranged side by side in a direction perpendicular to an arrangement direction AD. Furthermore, the PM capacitor 30 and the MN capacitor 40 are arranged such that their side walls face each other. A second PM terminal 32 and a second MN terminal 42 are arranged along the perpendicular direction. Likewise, the first PM terminal 31 and a first MN terminal 41 are arranged along the perpendicular direction. The PM capacitor 30 and the MN capacitor 40 are arranged at the same position in the depth direction of the capacitor housing 61.

[0081] As it is in Fig. 10 and Fig. As shown in Figure 11, an M-busbar 73 is provided with a capacitor connection section 73c connected to the second PM terminal 32 and a capacitor connection section 73c connected to the first MN terminal 41. The M-busbar 73 has a section (a connection section) that connects the two capacitor connection sections 73c. ​​The connection section is arranged along an orientation of the PM capacitor 30 and the MN capacitor 40. The inverter circuit 100 can be made smaller than that according to the first embodiment. (Sixth embodiment example)

[0082] An inverter circuit 100 according to a sixth embodiment is described with reference to Fig. 12. According to the present embodiment, a four-level inverter circuit 100 is used. The inverter circuit 100 has an MM capacitor 40a in addition to a PM capacitor 30 and an MN capacitor 40. The MM capacitor 40a is connected in series with the PM capacitor 30 and the MN capacitor 40. The MM capacitor 40a has a first MM terminal 41a and a second MM terminal 42a. The first MM terminal 41a is arranged such that it faces a second PM terminal 32. The second MM terminal 42 is arranged such that it faces the first MN terminal 41.

[0083] The inverter circuit 100 has two M-busbars 73. One of the M-busbars 73 has a capacitor connection section 73c, which is connected to the second PM terminal 32 and the first MM terminal 41a. The other M-busbar 73 has a capacitor connection section 73c, which is connected to the first MN terminal 41 and the second MM terminal 42a.

[0084] Base sections 73a of the two M-busbars 73 are arranged between a semiconductor device 20 and the capacitors 30 and 40. Part of the base section 73a is arranged between a P-busbar 71 and an N-busbar 72, and is opposite the P-busbar 71 and the N-busbar 72. Therefore, it can be said that the two M-busbars 73 each have a counterpart section. The inverter circuit 100 can also be applied to a multi-level inverter that has four or more levels. (Seventh embodiment)

[0085] A structure of an inverter circuit 100a according to a seventh embodiment is shown below with reference to Fig. described in sections 13 to 15. Inverter circuit 100a differs from inverter circuit 100 in that a PN capacitor 50 is provided. Fig. Busbars 71 to 73, an insulating element 80, and similar components are omitted. The same applies to Fig. 16, which will be described later.

[0086] As it is in Fig. 13 and Fig. As shown in Figure 14, a PN capacitor 50 is connected between a P busbar 71 and an N busbar 72 in inverter circuit 100a. The PN capacitor 50 is connected to a high-potential and a low-potential terminal. Therefore, the PN capacitor 50 is connected in parallel with a PM capacitor 30 and an MN capacitor 40. The PN capacitor 50 is designed for current ripple absorption. In other words, the PN capacitor 50 is designed to reduce current ripple flowing out of inverter circuit 100a. The PN capacitor 50 is equivalent to a third capacitor.

[0087] In inverter circuit 100a, the capacitance of the capacitor required to suppress permissible voltage fluctuations at a midpoint M is small, whereas the capacitance required to reduce current ripple flowing outwards is large. Therefore, inverter circuit 100a is equipped with a PN capacitor 50. The PN capacitor 50 is connected in parallel with the PM capacitor 30 and the MN capacitor 40, as described above. Therefore, inverter circuit 100a can reduce the total capacitance of the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50. Thus, in inverter circuit 100a, the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50 can be made to have smaller values.

[0088] As it is in Fig. As shown in Figure 14, a capacitor device 60 comprises the PN capacitor 50 in addition to the PM capacitor 30, the MN capacitor 40, a capacitor housing 61, and a potting resin 63. The PN capacitor 50 is housed in the capacitor housing 61 together with the PM capacitor 30 and the MN capacitor 40. The PN capacitor 60 is potted with the potting resin 63. Furthermore, as shown in Figure 14, the capacitor housing 61 is also enclosed in the capacitor housing 61. Fig. 14 and Fig. As shown in Figure 15, the PN capacitor 50 is arranged in an arrangement direction AD in relation to the PM capacitor 30 and the MN capacitor 40.

[0089] The PN capacitor 50 has a first PN terminal 51 and a second PN terminal 52. The first PN terminal 51 is connected to the P busbar 71. The second PN terminal 52 is connected to the N busbar 72.

[0090] The PM capacitor 30 and the MN capacitor 40 are positioned closer to a cooler 90 than the PN capacitor 50. According to the present embodiment, the cooler 90, the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50 are arranged in this order along the arrangement direction AD. Therefore, the PM capacitor 30 and the MN capacitor 40 are more easily cooled by the cooler 90 than the PN capacitor 50. It can be said that in the inverter circuit 100a, the PM capacitor 30 and the MN capacitor 40 receive more cooling power than the PN capacitor 50.

[0091] Furthermore, in the P-bus 71, the length from a connection section with a structural body to a connection section with the PM capacitor 30 is shorter than the length from a connection section with the structural body to a connection section with the PN capacitor 50. Therefore, the PM capacitor 30, which is cooled by the P-bus 71, which is cooled by the cooler 90, can be cooled more easily than the PN capacitor 50.

[0092] In contrast, in the N-busbar 72, the length from a connection section with the structural body to a connection section with the MN capacitor 40 is shorter than the length from a connection section with the structural body to a connection section with the PN capacitor 50. Therefore, the MN capacitor 40, which is cooled by the N-busbar 72, which is cooled by the cooler 90, can be cooled more easily than the PN capacitor 50.

[0093] In contrast, the ripple current caused by heat generation is greater in the PM capacitor 30 and the MN capacitor 40 than in the PN capacitor 50. Therefore, according to the present disclosure, the PM capacitor 30 and the MN capacitor 40 are located closer to the heat sink 90 than the PN capacitor 50. Therefore, the inverter circuit 100a can suppress the heat generated in the PM capacitor 30 and the MN capacitor 40. Therefore, the inverter circuit 100a can increase the permissible current of the PM capacitor 30 and the MN capacitor 40. In other words, the inverter circuit 100a can have an increased permissible current compared to a configuration in which the PN capacitor 50 is positioned closer to the cooler 90 than the PM capacitor 30 and the MN capacitor 40.The positional relationship between the cooler 90 and each of the capacitors 30 to 50, as described above, can also be applied to other embodiments.

[0094] The P busbar 71 and the N busbar 72 can exhibit higher thermal conductivity in sections connected to the PM capacitor 30 and the MN capacitor 40 than in sections connected to the PN capacitor 50. For example, the section connected to the PN capacitor 50 is primarily made of copper. In contrast, the sections connected to the PM capacitor 30 and the MN capacitor 40 are primarily made of silver. This also allows the permissible current of the PM capacitor 30 and the MN capacitor 40 to be increased in inverter circuit 100a.

[0095] The following exemplary embodiments mainly describe the differences compared to the seventh exemplary embodiment. (Eighth example)

[0096] An inverter circuit 100a according to an eighth embodiment is described with reference to Fig. 16 described. The present embodiment differs from the seventh embodiment in the positional relationship between a PM capacitor 30 and an MN capacitor 40.

[0097] The PM capacitor 30 and the MN capacitor 40 are arranged in parallel. The PM capacitor 30 and the MN capacitor 40 are arranged such that a first PM terminal 31 and a first MN terminal 41 are on the same imaginary plane. The PM capacitor 30 and the MN capacitor 40 are arranged such that a second PM terminal 32 and a second MN terminal 42 are on the same imaginary plane.

[0098] Therefore, the inverter circuit 100a can be smaller in a direction perpendicular to the capacitor arrangement direction of the PM capacitor 30 and the MN capacitor 40 than in a configuration where both capacitors 30 and 40 are arranged in a stacked manner. Furthermore, in the inverter circuit 100a, similar to the first embodiment, the size of each of the capacitors 30 to 50 can be reduced. It should be noted that the PM capacitor 50 is arranged in parallel to both the PM capacitor 30 and the MN capacitor 40. A first PM terminal 51 is arranged in the same imaginary plane as the first PM terminal 31 and the first MN terminal 41. A second PM terminal 52 is arranged in the same imaginary plane as the second PM terminal 32 and the second MN terminal 42. (Ninth example)

[0099] An inverter circuit 100a according to a ninth embodiment is described with reference to Fig. 17. The present embodiment differs from the first embodiment with respect to the positional relationship between a PM capacitor 30 and an MN capacitor 40. The PM capacitor 30 and the MN capacitor 40 are arranged in a displaced manner along an arrangement direction AD. In the inverter circuit 100a, similar to the seventh embodiment, the value of each of the capacitors 30 to 50 can be reduced. (Tenth example)

[0100] An inverter circuit 100a according to a tenth embodiment is described with reference to Fig. 18 described. According to the present embodiment, mainly sections are described that differ from the eighth embodiment. The present embodiment differs from the eighth embodiment in the positional relationship of a PN capacitor 50 with respect to a PM capacitor 30 and an MN capacitor 40.

[0101] The PN capacitor 50 is arranged in parallel to the PM capacitor 30 and the MN capacitor 40. In other words, the PM capacitor 30, the MN capacitor 40 and the PN capacitor 50 are arranged in a straight line.

[0102] Therefore, the inverter circuit 100a can have a smaller dimension in a direction perpendicular to an arrangement direction of the capacitors 30 to 50 than a configuration in which the capacitors 30 to 50 are arranged in a stacked manner. Furthermore, in the inverter circuit 100a, similar to the seventh embodiment, the dimension of each of the capacitors 30 to 50 can be reduced. (Eleventh example)

[0103] An inverter circuit 100a according to an eleventh embodiment is described with reference to Fig. 19 described. The present embodiment differs from the seventh embodiment in the positional relationship of a PN capacitor 50 with respect to a PM capacitor 30 and an MN capacitor 40.

[0104] The PN capacitor 50 is arranged in a stacked manner together with the PM capacitor 30 and the MN capacitor 40. Furthermore, the capacitors 30 to 50 are arranged such that their terminals do not face each other. A first PN terminal 51 is arranged in parallel with a first PM terminal 31 and a first MN terminal 41 with respect to the same imaginary plane. A second PN terminal 52 is arranged in parallel with a second PM terminal 32 and a second MN terminal 42 with respect to the same imaginary plane. The inverter circuit 100a can have a smaller extent in a direction perpendicular to the capacitor arrangement direction of the capacitors 30 to 50 than a configuration in which the capacitors 30 to 50 are arranged in parallel. Furthermore, in the inverter circuit 100a, similar to the seventh embodiment, the extent of each of the capacitors 30 to 50 can be reduced. (Twelfth example)

[0105] An inverter circuit 100aa according to a twelfth embodiment is described with reference to Fig. 20 described. The present embodiment differs from the seventh embodiment in the configurations of a P-bus 71 and an N-bus 72.

[0106] The P busbar 71 has a PM busbar section 71m connected to a PM capacitor 30 and a PN busbar section 71p connected to a PN capacitor 50. The N busbar 72 has an MN busbar section 72m connected to an MN capacitor 40 and a PN busbar section 72p connected to a PN capacitor 50. The PM busbar section 71m has a larger cross-sectional area than the PN busbar section 71p. The MN busbar section 72m has a larger cross-sectional area than the PN busbar section 72p.

[0107] In this way, the permissible current of the PM capacitor 30 and the MN capacitor 40 can be increased in inverter circuit 100a. Furthermore, in inverter circuit 100a, similar to the seventh embodiment, the current of each of the capacitors 30 to 50 can be reduced.

[0108] Although the present disclosure has been described according to the embodiments described above, it should be understood that the present disclosure is not limited to the embodiments and structures described above. The present disclosure includes various examples of modification or variations within the scope of equivalence. Furthermore, although various combinations and modes are described in the present disclosure, other combinations and modes, including only one or more elements added to or subtracted from it, are also within the scope and concept of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-005267

[0001] JP H10 - 201 249 A

[0004] < / wirkungen>

Claims

[1] Power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels through an output wiring, wherein the power conversion device comprises: a high-potential wiring (71) connected to a positive electrode of a power source, a low-potential wiring (72) connected to a negative electrode of the power source, at least one center wiring (73) which has a potential between the high-potential wiring and the low-potential wiring, a first power module (10) which is connected to the high-potential wiring, the low-potential wiring and the output wiring, a first capacitor (30) comprising a high-potential electrode connected to the high-potential wiring and a first center-point electrode connected to the center-point wiring, a second capacitor (40) comprising a low-potential electrode connected to the low-potential wiring and a second center-point electrode connected to the center-point wiring, and a second power module (20) connected to the center point wiring and the output wiring, wherein at least one center-tap wiring is a part between (i) the second power module and (ii) the first capacitor and the second capacitor, is arranged between the high-potential wiring and the low-potential wiring, and has a counter-section (73a) opposite the high-potential wiring and the low-potential wiring. [2] Power conversion device according to claim 1, wherein the first capacitor and the second capacitor are arranged such that the first central electrode and the second central electrode face each other, and the center point wiring between the first capacitor and the second capacitor is arranged in a sandwich-like manner and has a connecting section (73c) that is connected to the first center point electrode and the second center point electrode. [3] Power conversion device according to claim 1, wherein the center point wiring comprises: a connecting section (73c) which is connected to the first center point electrode and the second center point electrode, and a section which projects from the connecting section and is sandwiched between the first capacitor and the second capacitor. [4] Power conversion device according to claim 1, wherein the first capacitor and the second capacitor are arranged such that they have a first side surface connected to the first center electrode and the high-potential electrode, and a second side surface opposite the first side surface connected to the second center electrode and the low-potential electrode, and the center point wiring has two connecting sections (73c) that are connected to the first center point electrode and the second center point electrode, and a section connecting the two connecting sections is arranged between the first capacitor and the second capacitor. [5] Power conversion device according to claim 1, wherein the first capacitor and the second capacitor are arranged such that (i) the first center electrode and the low-potential electrode face each other, or (ii) the second center electrode and the high-potential electrode face each other, the center point wiring has two connecting sections (73c) which are connected to the first center point electrode and the second center point electrode, and one of the two connecting sections is located in an area where the first capacitor and the second capacitor face each other. [6] Power conversion device according to claim 1, wherein the first capacitor and the second capacitor are arranged such that they have a first side surface which is connected to the first center electrode and the high potential electrode, and a second side surface which is opposite the first side surface and is connected to the second center electrode and the low potential electrode, and the center wiring has two connecting sections (73c) which are connected to the first center electrode and the second center electrode, and a section which connects the two connecting sections is arranged along an arrangement direction of the first capacitor and the second capacitor. [7] Power conversion device according to any one of claims 1 to 6, wherein each of at least two center wiring sections has the opposite section (73a). [8] Power conversion device according to any one of claims 1 to 6, further comprising: at least a third capacitor (50) which is connected to the high-potential wiring and the low-potential wiring.

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