Light-emitting semiconductor element and method for manufacturing a light-emitting semiconductor element

Abstract

A light-emitting semiconductor element, exhibiting good light emission relative to the input power compared to conventional light-emitting elements, and capable of forming a protective film without voids, and a method for fabricating this light-emitting semiconductor element are provided. The light-emitting semiconductor element comprises a cladding layer of a first conductivity type, a light-emitting layer, and a cladding layer of a second conductivity type in the specified order, with the cladding layer of the second conductivity type serving as the light-absorbing side. The light-emitting layer is a III-V compound semiconductor comprising one or two or more types of Al, Ga, and In as group III elements, one or two or more types of As, Sb, and P as group V elements, and exhibiting a central emission wavelength of 1000 nm to 1900 nm.The cladding layer of a second conductivity type has a composition of In. x Ga y Al z As (0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1). The cladding layer of a second conductivity type exhibits a light-absorbing surface with a developed interface ratio (Sdr) of 4.0 or more.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a light-emitting semiconductor element and a method for manufacturing a light-emitting semiconductor element. BACKGROUND

[0002] III-V compound semiconductors, obtained by stacking epitaxial layers of InGaAsP, InGaAlAs, InAsSbP, etc., as disclosed in Patent Document (PTL) 1, are used as semiconductor materials for semiconductor layers in light-emitting semiconductor devices. By adjusting the composition ratio of a light-emitting layer formed using a III-V compound semiconductor material, the light emission wavelength of a light-emitting semiconductor device can be tuned over a wide range from green to infrared. For example, light-emitting semiconductor devices emitting at wavelengths in the infrared range of 1000 nm or more are widely used in applications such as sensors, gas analysis, surveillance cameras, and communication devices.

[0003] Furthermore, PTL 2 describes an attempt to attenuate multiple peaks in a light emission spectrum by including an n-type cladding layer, an active layer and a p-type cladding layer in the specified order in a semiconductor laminate in which a plurality of InGaAsP-III-V compound semiconductor layers containing In and P are stacked, and by forming a structure of irregularities in the n-type cladding layer that forms a light-sucking side. DOCUMENT LISTPatent documents PTL 1: JP 2021-077885 A PTL 2: JP 2018-101675 A SUMMARY (Technical Problem)

[0004] In recent years, there has been a need to further improve the light emission efficiency of light-emitting elements. The inventors have conducted research aimed at improving the light emission output relative to the power input in a light-emitting element. Furthermore, the inventors have attempted to improve light emission output by introducing surface irregularities on a light-absorbing surface. The surface irregularities in PTL 2, which result in an evolved surface area ratio (Sdr) of less than 1, are insufficient for improving light emission output, and there is a need for further improvements.

[0005] As a result of investigations carried out with the aim of obtaining irregularities on a light-taking surface suitable for improving light emission, the inventors found that there are cases in which hollowing occurs. The term "hollowing," as used in the present disclosure, refers to a condition that occurs when, in a situation where surface roughening is carried out by etching the surface of a III-V compound semiconductor layer in a condition where a film or the like, which blocks etching, is formed on part of the surface, the etching not only progresses in a perpendicular direction with respect to the thickness of the III-V semiconductor layer, but also in a horizontal direction around the perimeter of the film or the like, resulting in etching below the film or the like around its perimeter.The inventors have for the first time recognized a problem in that, in a situation where hollowing occurs, this acts as the cause of the formation of areas (cavities) where there is insufficient protective film formation when a protective film is formed on a light-taking surface by plasma CVD, sputtering or the like, and that problems arise in practical application.

[0006] Accordingly, it is an object of the present disclosure to provide a light-emitting semiconductor element which provides good light emission relative to the input power compared with conventional light-emitting elements, and in which a protective film can be formed without the formation of cavities, and also to provide a method for manufacturing this light-emitting semiconductor element. (Solution to the problem)

[0007] As a result of careful and extensive research to solve the aforementioned problem, the inventors have found that, in the case of an infrared-emitting semiconductor device with a light emission wavelength in the infrared range of wavelengths of 1000 nm or more, the use of InGaAlAs without phosphorus as the composition of a cladding layer forming a light-absorbing surface makes it easier to obtain surface irregularities suitable for improving light emission, compared to a case in which phosphorus is included. The inventors have also found that a high aluminum content in InGaAlAs makes it easier to obtain surface irregularities suitable for improving light emission.However, the inventors found that the occurrence of the hollowing described above becomes noticeable when the Al content becomes too high, and consequently the inventors obtained the present disclosure, which is given below.

[0008] In particular, the primary configurations of the present disclosure are as follows. (1) Light-emitting semiconductor element comprising a cladding layer of a first conductivity type, a light-emitting layer and a cladding layer of a second conductivity type in the specified order with the cladding layer of the second conductivity type as the light-absorbing side, wherein the light-emitting layer is a III-V compound semiconductor comprising one or two or more types of Al, Ga and In as group III elements, one or two or more types of As, Sb and P as group V elements, and has a central emission wavelength of 1000 nm to 1900 nm, the sheath of a second conductivity type is a composition of In x Ga y Al z As, where 0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1, has and The cladding layer of a second conductivity type has a light-absorbing surface with a developed interface ratio (Sdr) of 4.0 or more. (2) Light-emitting semiconductor element according to (1) above, wherein the cladding layer of a second conductivity type has an Al composition fraction z of 0.15 ≤ z ≤ 0.30. (3) Light-emitting semiconductor element according to (1) or (2) above, wherein the light-harvesting surface of the cladding layer of a second conductivity type has a mean arithmetic height (Sa) of 0.60 µm or less and an skewness (Ssk) of 0.30 or more. (4) Light-emitting semiconductor element according to any of the preceding (1) to (3), wherein a band gap of the cladding layer of a second conductivity type is larger than a band gap of the light-emitting layer. (5) Light-emitting semiconductor element according to any of the preceding (1) to (4), wherein the cladding layer of a second conductivity type has a thickness of not less than 2 µm and not more than 10 µm. (6) Light-emitting semiconductor element according to any of the preceding (1) to (5), wherein the light-emitting layer has a quantum well type structure in which an InGaAlAs well layer and an InGaAlAs junction layer are stacked alternately. (7) Light-emitting semiconductor element according to any of the preceding (1) to (6) comprising an undoped spacer layer between the cladding layer of a first conductivity type and the light-emitting layer and between the light-emitting layer and the cladding layer of a second conductivity type. (8) Light-emitting semiconductor element according to any of the preceding (1) to (7), comprising a support substrate, the cladding layer of a first conductivity type, the light-emitting layer and the cladding layer of a second conductivity type in the specified order and comprising a metal reflection layer between the support substrate and the cladding layer of a first conductivity type, wherein Furthermore, a dielectric layer and a contact section, arranged longitudinally to each other, are included between the metal reflection layer and the cladding layer of a first conductivity type. (9) Method for manufacturing a light-emitting semiconductor element comprising a cladding layer of a second conductivity type as a light-sucking side, comprising: a semiconductor laminate formation step of successively forming a cladding layer of a first conductivity type, a light-emitting layer and the cladding layer of a second conductivity type; and a surface roughening treatment step of immersing the mantle layer of a second conductivity type in concentrated nitric acid to perform surface roughening and thereby adjusting an developed interfacial ratio (Sdr) of a light-sucking surface of the mantle layer of a second conductivity type to 4.0 or more, wherein the light-emitting layer is a III-V compound semiconductor comprising one or two or more types of Al, Ga and In as group III elements, one or two or more types of As, Sb and P as group V elements, and has a central emission wavelength of 1000 nm to 1900 nm, and the sheath of a second conductivity type is a composition of In x Ga y Al z As, where 0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1, has. (10) Method for producing a light-emitting semiconductor element according to (9) above, wherein the concentrated nitric acid in the surface roughening treatment step has a temperature of less than 10 °C. (11) Method for producing a light-emitting semiconductor element according to (9) or (10) above, wherein the concentrated nitric acid in the surface roughening treatment step has a concentration of 60 wt.% or more. (12) Method for producing a light-emitting semiconductor element according to any of the preceding (9) to (11), wherein the cladding layer of a second conductivity type has an Al composition fraction z of 0.15 ≤ z ≤ 0.30. (13) Method for producing a light-emitting semiconductor element according to any of the preceding (9) to (12), wherein the surface roughening treatment in the surface roughening treatment step is carried out such that the light-absorbing surface of the cladding layer of a second conductivity type has a mean arithmetic height (Sa) of 0.6 µm or less and an skewness (Ssk) of 0.3 or more. (14) Method for producing a light-emitting semiconductor element according to any of the preceding (9) to (13), further comprising, after the surface roughening treatment step, a step of forming a mesa structure and a step of cutting a section that has been removed by a mesa to carry out segmentation. (15) Method for manufacturing a light-emitting semiconductor element, comprising: a semiconductor laminate formation step of successively forming an etch stop layer, a cladding layer of a second conductivity type, a light-emitting layer and a cladding layer of a first conductivity type on a growth substrate; a step of forming a dielectric layer and a contact section longitudinally to each other on the cladding layer of a first conductivity type; a metal reflection layer formation step of forming a metal reflection layer on the dielectric layer and the contact section; a connection step of joining a support substrate that differs from the growth substrate, using the metal reflection layer; a growth substrate removal step of removing the growth substrate to expose the etch stop layer; a step to expose the cladding layer of a second conductivity type by removing the etch stop layer to expose an upper surface of the cladding layer of a second conductivity type as the light pickup side; and a surface roughening treatment step of, after the step of exposing the sheath layer of a second conductivity type, immersion of the sheath layer of a second conductivity type in concentrated nitric acid to carry out surface roughening and thereby adjusting a developed interfacial area ratio (Sdr) of a light-sampling surface of the sheath layer of a second conductivity type to 4.0 or more, wherein the light-emitting layer is a III-V compound semiconductor comprising one or two or more types of Al, Ga and In as group III elements, one or two or more types of As, Sb and P as group V elements, and has a central emission wavelength of 1000 nm to 1900 nm, and the sheath of a second conductivity type is a composition of In x Ga y Al z As, where 0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1, has. (Beneficial effect)

[0009] According to the present disclosure, a light-emitting semiconductor element can be provided which has a good light emission output relative to the input power compared to conventional light-emitting elements, and in which a protective film can be formed without the formation of cavities, and a method for manufacturing this light-emitting semiconductor element can also be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the attached drawings: Fig. Figure 1 is a schematic cross-sectional view to describe a light-emitting semiconductor element according to an embodiment of the present disclosure; Fig. Figure 2 is a schematic cross-sectional view in a manufacturing process of a light-emitting semiconductor element according to an embodiment of the present disclosure; Fig. Figure 3 is a schematic cross-sectional view in a manufacturing process of a light-emitting semiconductor element according to an embodiment of the present disclosure, which differs from Fig. 2 continues; Fig. 4 is a schematic cross-sectional view to describe a preferred shape of the environment of a dielectric layer and a contact section in a light-emitting semiconductor element according to an embodiment of the present disclosure; Fig. Figure 5 is a schematic cross-sectional view in a manufacturing process of a light-emitting semiconductor element according to an embodiment of the present disclosure, which differs from Fig. 3 continues; Fig. Figure 6 is a schematic cross-sectional view in a manufacturing process of a light-emitting semiconductor element according to an embodiment of the present disclosure, which differs from Fig. 4 continues; Fig. Figure 7 is a schematic cross-sectional view to describe a light-emitting semiconductor element according to an embodiment of the present disclosure; Fig. Figure 8 is a schematic top view showing the structure of an electrode on the upper surface in Example 1; Fig. Figure 9 is a graph comparing an Al composition fraction and Sa in examples and comparative examples of the present revelation; Fig. Figure 10 is a graph comparing an Al composition fraction and Sdr in examples and comparative examples of the present disclosure; Fig. Figure 11 is a graph comparing an Al composition fraction and Ssk in examples and comparative examples of the present disclosure; Fig.Figure 12 is an electron micrograph of the environment of a light-taking surface of a cladding layer of a second conductivity type in comparison example 1; Fig. Figure 13 is an electron micrograph of the environment of a light-taking surface of a cladding layer of a second conductivity type in Example 1; and Fig. Figure 14 is an electron micrograph of the environment of a light-taking surface of a cladding layer of a second conductivity type in comparison example 4. DETAILED DESCRIPTION

[0011] The following points are described before the description of embodiments according to the present disclosure. <zusammensetzung>

[0012] First, if the present description simply refers to a "III-V compound semiconductor", its composition is given by the general formula: (In a Ga b Al c )(P x As y Sb z ). The following relationships apply to the proportions of the different elements.

[0013] For the elements of group III, c = 1 - a - b, 0 ≤ a ≤ 1, 0 ≤ b ≤ 1 and 0 ≤ c ≤ 1.

[0014] For the elements of the group V, z = 1 - x - y, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1.

[0015] A III-V compound semiconductor layer, as referred to in the present disclosure, comprises one or two or more types of Group III elements selected from the group consisting of Al, Ga and In, and one or two or more types of Group V elements selected from the group consisting of As, Sb and P.

[0016] When simply referring to "InGaAsP" without explicitly specifying compositional proportions, it is understood to indicate any compound in which the chemical compositional proportions of a Group III element (total amount of In and Ga) and a Group V element (As and P) are 1:1, and in which the proportions of the Group III elements In and Ga and the Group V elements As and P are not specified. This also includes cases where one or the other of In and Ga is not included by the Group III element, and cases where one or the other of As and P is not included by the Group V element. However, when InGaAsP is explicitly stated as "comprising at least In and P," this means that more than 0% and not more than 100% of In is included by the Group III element, and that more than 0% and not more than 100% of P is included by the Group V element.Furthermore, a reference to "InGaAs" means that phosphorus (P) is not included in the "InGaAsP" described above, except for P that is unavoidably mixed in during manufacture. Similarly, a reference to "InGaAlAs" is understood to indicate any compound in which the chemical composition of a Group III element (total amount of In, Ga, and Al) and a Group V element (As) is in a 1:1 ratio, and in which the proportions of the Group III elements In, Ga, and Al and the Group V element As are not specified. A reference to "InP" also means that Ga and As are not included in the "InGaAsP" described above, except for Ga and As that are unavoidably mixed in during manufacture.It should be noted that the compositional proportion of each component in InGaAsP, InGaAs, or the like can be determined by photoluminescence measurement, X-ray diffraction measurement, or similar methods. It should also be noted that the phrase "inevitably mixed in during production," as used here, does not only refer to unavoidable mixing due to a manufacturing device when a source gas is used, but also, for example, to diffusion of atoms at the interfaces of layers during crystal growth or concomitant with subsequent heat treatment. <Leitfähigkeitstyp>

[0017] In this description, a layer that behaves electrically as a p-type semiconductor layer is referred to as a p-type semiconductor layer (also abbreviated as "p-type layer"), and a layer that behaves electrically as an n-type semiconductor layer is referred to as an n-type semiconductor layer (also abbreviated as "n-type layer"). Conversely, a layer to which a specific foreign atom, such as Si, Zn, S, Sn, Mg, or Te, is not intentionally added is referred to as "undoped." An undoped III-V compound semiconductor layer may contain impurities or foreign atoms that are unavoidably introduced during a manufacturing process. This is particularly true if a layer has a low dopant concentration (for example, less than 5 × 10⁻⁶). 16 atoms / cm² 3 ), the layer is treated as “undoped” in the present description. Furthermore, in a case where a foreign atom is not intentionally added to a III-V compound semiconductor layer, this III-V compound semiconductor layer is treated as undoped even if an unavoidable impurity (O, C, H, etc.) is present in a concentration of 5 × 10⁻⁶ in a manufacturing process involving the decomposition of a source gas or the like. 16 atoms / cm² 3 or more. It should be noted that, since InAs behaves electrically as an n-type even when undoped, an undoped InAs layer and an n-type InAs layer are both InAs layers behaving as n-type. Values ​​for impurity concentrations of Si, Zn, S, Sn, Mg, Te, and the like are to be understood as values ​​obtained from a SIMS analysis. It should also be noted that values ​​for dopant concentrations are to be understood as the value for a dopant concentration at the center in the thickness direction of that layer, since values ​​for dopant concentrations change significantly near the boundaries of semiconductor layers. <Filmdicken und Zusammensetzungen von Schichten>

[0018] The thickness of each layer can be calculated by examining a cross-sectional area of ​​a grown layer using a transmission electron microscope (TEM). Solid-state fractions of layers in this description are to be understood as values ​​obtained by SIMS analysis. Solid-state fractions of light-emitting layers and spacer layers in this description are to be understood as values ​​obtained by implementing a SIMS analysis (quadrupole type) in one thickness direction of the light-emitting layer after exposing the surroundings of an uppermost layer of the light-emitting layer by etching (from the n-layer side).It should be noted that, with regard to SIMS analysis results, a value representing the average element concentration in half the thickness range of each layer is used at a central part of that layer in the thickness direction. During fabrication, a layer with target composition fractions can be stacked using growth conditions determined by calculating solid-phase fractions using a lattice constant obtained from an X-ray diffraction (XRD) measurement and a value determined by converting a central emission wavelength from a photoluminescence (PL) measurement into the Eg (i.e., the band gap) for a layer grown as a single film, such that the target composition fractions are obtained. <Oberflächenrauhigkeitsparameter>

[0019] The developed surface area ratio Sdr, used in this description, indicates the degree to which the developed surface area of ​​a given region is larger than the area of ​​that region. In the case of a perfectly flat surface, Sdr is zero. Furthermore, the skewness Ssk is a value that indicates the symmetry between peaks and troughs when a mean line is used as the center. An Ssk of zero indicates vertical symmetry (normal distribution) with respect to the mean line, whereas a positive Ssk indicates a sloping surface towards a lower side (trough side) with respect to the mean line, and a negative Ssk indicates a sloping surface towards a higher side (peak side) with respect to the mean line. Additionally, the mean arithmetic height Sa, used in this description, is a value that indicates the surface roughness (µm).All these indices are in accordance with ISO 25178.

[0020] Surface roughness parameters, such as the developed interfacial ratio (Sdr), skewness (Ssk), and mean arithmetic height (Sa), can be measured using a contactless profile analysis laser microscope (VK-X1000 / 1100, manufactured by Keyence Corporation). The surface roughness parameters are defined according to ISO 25178-2:2012.

[0021] In this description, the surface roughness parameters described above were measured as follows. Specifically, a profile analysis laser microscope (VK-X1000 / 1100, manufactured by Keyence Corporation) was used to measure the surface roughness at nine arbitrary locations on a rough surface after a surface roughening treatment step and to calculate an average surface roughness value. The measurement conditions were as follows. • Lens magnification: ×50 • Pixel count: 2048 × 1536 • Gaussian filter used (S-filter: 0.5 µm) Specific input parameters for the surface roughness measuring device were as follows. • Sxp: p = 2.5% • Vvv: p = 80.0 % • Vvc: p = 10.0%, q = 80.0% • Vmp: p = 10.0 % • Vmc: p = 10.0%, q = 80.0% The surface roughness parameters Sa (mean arithmetic height), Sz (maximum height), Sq (square mean height), Sdr (developed interface ratio), Spc (arithmetic mean peak curve), Sdr (hybrid parameter), Ssk (skewness) and Sku (kurtosis) are automatically calculated according to ISO 25178-2:2012.

[0022] Below is a detailed, illustrative description of embodiments of the present disclosure with reference to the drawings. It should be noted that identical components are generally assigned the same reference numerals, and their repeated descriptions are omitted. It should also be noted that the drawings illustrate ratios of the height and width of a substrate and each layer in a manner that is exaggerated compared to their actual proportions, thus facilitating description. (Light-emitting semiconductor element)

[0023] An example of an embodiment of a light-emitting semiconductor element 100 according to the present disclosure is described with reference to the Fig. 1 described. The light-emitting semiconductor element 100 is a light-emitting semiconductor element comprising a cladding layer of a first conductivity type 37, a light-emitting layer 35, and a cladding layer of a second conductivity type 31 in the specified order, with the cladding layer of the second conductivity type 31 serving as the light-absorbing side. The light-emitting layer 35 is a III-V compound semiconductor comprising one or two or more types of Al, Ga, and In as group III elements, one or two or more types of As, Sb, and P as group V elements, and exhibiting a central emission wavelength of 1000 nm to 1900 nm, wherein the cladding layer of the second conductivity type 31 comprises a composition of In x Ga y Al z As (0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1) has and the cladding layer of a second conductivity type 31 has a light-absorbing surface 31A with a developed interfacial ratio (Sdr) of 4.0 or more.

[0024] Each configuration is described below and is also described in more detail in the description of an embodiment of a manufacturing process further below. It should be noted that in the present embodiment, one case is described as an example in which a joining technique is used. In a case in which a joining technique described below is used in the manufacturing process, a substrate incorporated into the light-emitting element 100 is a support substrate 80. In a case in which no joining technique is used, the substrate incorporated into the light-emitting element 100 may be a growth substrate 10 (hereinafter referred to as follows). Fig. 2, etc., described), which serves for epitaxial growth of each semiconductor layer. <Mantelschicht eines ersten Leitfähigkeitstyps>

[0025] The composition of the cladding layer of a first conductivity type 37 can be any conventionally known composition without any specific restrictions. The cladding layer of a first conductivity type 37 can be a III-V compound semiconductor of InGaAlAs or of InGaAsP comprising at least In and P, and should be a layer exhibiting a low degree of lattice mismatch with the light-emitting layer described below and being transparent with respect to the central emission wavelength. In particular, the cladding layer of a first conductivity type 37 is preferably a III-V compound semiconductor of InGaAsP comprising at least In and P, and can, for example, be InP. <Lichtemittierende Schicht>

[0026] The light-emitting layer preferably has a quantum well-type structure in which an InGaAlAs well layer 35W and an InGaAlAs junction 35B are stacked alternately. Such a structure is referred to as a multiple quantum well (MQW) structure, and the inclusion of a multiple quantum well structure can improve light emission by inhibiting crystal defects. The central emission wavelength of the light-emitting semiconductor element 100 can be adjusted to 1000 nm to 1900 nm by changing the composition of the light-emitting layer. It should be noted that in the case of a quantum well structure, it is also preferred to adjust the composition difference between the well layer 35W and the junction 35B and to impart a voltage to the well layer 35W in addition to changing its composition. <Al-Zusammensetzungsanteil der Mantelschicht eines zweiten Leitfähigkeitstyps>

[0027] Experiments conducted by the inventors confirmed that hollowing occurs when the sheath layer of a second conductivity type 31 has a high aluminum composition. As also shown in the comparative examples described below, hollowing occurs when the surface roughening of the sheath layer of a second conductivity type 31 is carried out in a situation where the aluminum composition is, for example, 0.35 or higher.On the other hand, in a situation where the cladding layer of a second conductivity type 31 has a low Al composition fraction, the composition approaches one that absorbs light with a desired central emission wavelength of 1100 nm to 1900 nm, which is within the scope of the present disclosure, and this acts as a cause of a reduction in the light emission output of the light-emitting semiconductor element. In this respect, the composition of the cladding layer of a second conductivity type 31 must be x Ga y Al z As (0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1). In particular, it is preferred that the AI ​​composition fraction z satisfies 0.15 ≤ z ≤ 0.30, and it is more preferred that the AI ​​composition fraction z satisfies 0.20 ≤ z ≤ 0.30.

[0028] The term “hollowing out” used above refers to a condition that occurs when, in a situation where surface roughening is carried out by etching the surface of a III-V compound semiconductor layer in a condition where a film or the like, which blocks etching, is formed on part of the surface, the etching not only progresses in a perpendicular direction relative to the thickness of the III-V semiconductor layer, but also progresses in a horizontal direction around the perimeter of the film or the like, resulting in etching below the film or the like around its perimeter.For example, this refers to a condition where, upon examination of a cross-section, surface irregularities, corrosion, or cavities are found in a horizontal direction, relative to the thickness extending across a boundary line between an area undergoing surface roughening and an area where surface roughening does not occur due to a film or similar material blocking etching, directly below the area where surface roughening does not occur. Hollowing, such as that described above, occurs during etching in a surface roughening treatment step described above.Furthermore, in a subsequently described step of forming a protective film of SiO2 or the like after the surface roughening treatment step, hollowing acts as a cause for the formation of an imperfect protective film with sections (also referred to as cavities) where the protective film and the surface of the cladding layer of a second conductivity type 31 (light-taking surface) are not in contact, and it may not be possible to achieve lifetime characteristics in a power supply at a stage where a light-emitting semiconductor element, which can ultimately be incorporated into a device, is obtained. In addition to the above, hollowing can also cause inadequate application or removal of a photoresist. <Oberflächenunregelmäßigkeiten der Lichtentnahmeoberfläche der Mantelschicht eines zweiten Leitfähigkeitstyps>

[0029] In the light-emitting semiconductor element 100 in the Fig. 1. Light emitted by the light-emitting layer 35 passes through the surface of the cladding layer of a second conductivity type 31 at a section where no electrode or the like is formed and is emitted outwards. It should be noted that the term “light-absorbing side,” as used in this description, refers to a side where light emitted by the light-emitting layer 35 is emitted outwards in the light-emitting semiconductor element 100, and that the cladding layer of a second conductivity type 31 is used as the “light-absorbing side” in this embodiment. Furthermore, the term “light-absorbing surface” refers to a surface where no electrode or the like is formed on an upper surface of the cladding layer of a second conductivity type 31, which forms the “light-absorbing side.”In the light-emitting semiconductor element 100, the light-absorbing surface 31A of the cladding layer of a second conductivity type 31 exhibits a developed surface area ratio (Sdr) of 4.0 or more as a result of having undergone a surface roughening treatment. In a situation where the Sdr of the light-absorbing surface 31A of the cladding layer of a second conductivity type 31 is less than 4.0, it is not possible to achieve sufficient light emission in this light-emitting semiconductor element. The developed surface area ratio (Sdr) is preferably 4.4 or more. The Sdr is preferably 7.0 or less and more preferably 5.8 or less, so that the occurrence of the hollowing described above on the surface that has undergone surface roughening is reliably prevented.Furthermore, it is preferred that the light-absorbing surface 31A of the cladding layer of a second conductivity type 31 has a mean arithmetic height (Sa) of 0.60 µm or less and an skewness (Ssk) of 0.30 or more, and it is more preferred that Sa is 0.55 µm or less and Ssk is 0.40 or more. A low mean arithmetic height (Sa), such as 0.60 µm or less, can improve strong adhesion to a protective film. It should be noted that a side surface of the cladding layer of a second conductivity type 31 may or may not be roughened. <Bandlücke der Mantelschicht eines zweiten Leitfähigkeitstyps>

[0030] For the same reasons, it is preferred that the cladding layer of a second conductivity type 31 does not absorb light from the light-emitting layer, and consequently, it is particularly preferred that a band gap of the cladding layer of a second conductivity type 31 is larger than a band gap of the light-emitting layer 35. The band gap of the cladding layer of a second conductivity type 31 can be estimated from its composition, and the band gap of the light-emitting layer 35 can be measured by a PL measurement. <Dicke der Mantelschicht eines zweiten Leitfähigkeitstyps>

[0031] The thickness of the cladding layer of a second conductivity type 31 is preferably at least a certain thickness when surface roughening is taken into account; however, conversely, excessive thickness increases manufacturing costs. Therefore, the thickness of the cladding layer of a second conductivity type 31 is preferably not less than 2 µm and not more than 10 µm.

[0032] It should be noted that if the conductivity type of the cladding layer of a first conductivity type 37 is an n-type, the cladding layer of a second conductivity type 31 is a p-type. Conversely, if the conductivity type of the cladding layer of a first conductivity type 37 is a p-type, the cladding layer of a second conductivity type 31 is an n-type. <Abstandshalterschicht, Metallreflexionsschicht, Dielektrikumschicht und Kontaktabschnitt (Kontaktschicht und Ohm'scher Metallabschnitt)>

[0033] An undoped spacer layer can be included between the cladding layer of a first conductivity type 37 and the light-emitting layer 35, and between the light-emitting layer 35 and the cladding layer of a second conductivity type 31. Furthermore, a metal reflection layer 60 can be included between the support substrate 80 and the cladding layer of a first conductivity type 37. A dielectric layer 50 and a contact section 40, arranged longitudinally to each other, can also be included between the metal reflection layer 60 and the cladding layer of a first conductivity type 37. In addition, the contact section 40 can comprise a contact area 41A, which is formed as part of a contact layer 41 and an ohmic metal section 43, and can have the ohmic metal section 43 on the surface of the contact area 41A. <Elektrode der oberen Oberfläche und Elektrode der hinteren Oberfläche>

[0034] The light-emitting semiconductor element 100 can have an upper surface electrode 93 comprising a wiring section 93A and a contact section 93B formed on the cladding layer of a second conductivity type 31, and can further have a rear surface electrode 91 formed on a rear surface of the support substrate 80. (Method for manufacturing a light-emitting semiconductor element)

[0035] In a process for fabricating a light-emitting semiconductor device according to the present disclosure, a cladding layer of a second conductivity type is used as a light-absorbing surface. This fabrication process comprises a semiconductor laminate formation step of successively forming a cladding layer of a first conductivity type, a light-emitting layer, and a cladding layer of a second conductivity type, and a surface roughening treatment step of immersing the cladding layer of the second conductivity type in concentrated nitric acid to perform surface roughening and thereby adjusting the developed interfacial area ratio (Sdr) of a light-absorbing surface of the cladding layer of the second conductivity type to 4.0 or more.The light-emitting layer is a III-V compound semiconductor comprising one or two or more types of Al, Ga and In as group III elements, one or two or more types of As, Sb and P as group V elements, and having a central emission wavelength of 1000 nm to 1900 nm, and the cladding layer of a second conductivity type has a composition of In. x Ga y Al z As (0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1).

[0036] Next, an example of a method for manufacturing a light-emitting semiconductor element according to an embodiment of the present disclosure is given with reference to Fig. Sections 2 to 7 are described. In the present embodiment, a case is described as an example in which an interconnection technique is used. The method for fabricating a light-emitting semiconductor device may include a semiconductor laminate formation step, a metal reflective layer formation step, an interconnection step, a growth substrate removal step, a cladding layer exposure step of a second conductivity type, and a surface roughening treatment step. Details of these steps are described sequentially below. <halbleiterlaminat-bildungsschritt>

[0037] As it is in the Fig. As shown in Figure 2, in the semiconductor laminate formation step, an etch stop layer 20, a cladding layer of a second conductivity type 31, a light-emitting layer 35, and a cladding layer of a first conductivity type 37 are successively formed on a growth substrate 10, so that a semiconductor laminate 30 is formed. The light-emitting layer is a III-V compound semiconductor comprising one or two or more types of Al, Ga, and In as group III elements, one or two or more types of As, Sb, and P as group V elements, and has a central emission wavelength of 1000 nm to 1900 nm, wherein the cladding layer of a second conductivity type 31 has a composition of In x Ga y Al z As (0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1) and the Al composition fraction z is preferably 0.15 ≤ z ≤ 0.30. Details of this step are described below.

[0038] First, in the semiconductor laminate formation step, a growth substrate 10 is produced, as described in step 10 in the Fig. Figure 2 is shown. In the present embodiment, it is preferred to use an InP substrate as the growth substrate 10, since a p-type sheath layer is formed as the sheath layer of a first conductivity type 37 and an n-type sheath layer is formed as the sheath layer of a second conductivity type 31. It should be noted that a commonly available n-type InP substrate, a high-resistance (also referred to as semi-insulating) InP substrate (which, for example, is doped with Fe and has a resistivity of 1 × 10⁻⁶) 6 Ω · cm or more) or a p-type InP substrate can be used as the InP substrate. For convenience, the following is an illustrative description of a case in which an n-type InP substrate is used as the growth substrate 10. Therefore, in the embodiment described below, the sheath layer of a first conductivity type 37 can simply be referred to as the p-type sheath layer 37, and the sheath layer of a second conductivity type 31 can simply be referred to as the n-type sheath layer 31.

[0039] Next, an etch stop layer 20 is formed on the growth substrate 10, as described in step 20 in the Fig. Figure 2 shows that the etch stop layer 20 should exhibit etch selectivity with respect to the growth substrate 10. InGaAs is used as the etch stop layer 20 in this disclosure. This etch stop layer 20 can be used in the growth substrate removal step for the removal of the growth substrate 10 by etching. To achieve lattice matching between the n-type InP substrate and InGaAs, it is preferred to use InGaAs in which the In composition fraction of group III elements is adjusted to 0.3 to 0.7, and it is more preferred to use InGaAs in which this In composition fraction is adjusted to 0.5 to 0.6.

[0040] Next, an n-type cladding layer 31, a light-emitting layer 35, and a p-type cladding layer 37 are sequentially formed on the etched stop layer 20 to create a semiconductor laminate 30. The semiconductor laminate 30 can have a double heterodyne (DH) structure or a multiple quantum well (MQW) structure, in which the light-emitting layer 35 is positioned between the p-type cladding layer 37 and the n-type cladding layer 31. To improve light emission by inhibiting crystal defects, it is more preferred that the light-emitting layer 35 has a multiple quantum well structure. The multiple quantum well structure can be formed by a structure in which a well layer 35W and a barrier layer 35B are alternately repeated.The well layer 35W and the barrier layer 35B comprise one or two or more types of Al, Ga, and In as Group III elements and one or two or more types of As, Sb, and P as Group V elements. It is more preferred that one type of Group V element be included. For example, the well layer 35W can be configured as InGaAlAs, and the barrier layer 35B can be configured as InGaAlAs with a larger bandgap than the well layer 35W. The central emission wavelength can be adjusted to between 800 nm and 1650 nm by changing the composition of the well layer 35W. In the case of an MQW structure, the central emission wavelength can also be adjusted to between 1100 nm and 1900 nm by adjusting the composition difference between the well layer and the barrier layer and by imparting a voltage to the well layer.In other words, the light-emitting layer 35 can, for example, be designed to have a central emission wavelength within a range of 800 nm to 1900 nm. The central emission wavelength is preferably set to 1000 nm to 1900 nm. Furthermore, if the composition of components in the trough layer 35W is to be considered as In. xw Ga yw Al zw As shown, the composition should be selected appropriately from ranges of 0.50 ≤ xw ≤ 0.70, 0.00 ≤ yw ≤ 0.50, and 0.00 ≤ zw ≤ 0.50. Accordingly, if the composition of components in barrier layer 35B is to be considered as In xb Ga Yb Al zb As shown, the composition is selected in a suitable manner from ranges of 0.40 ≤ xb ≤ 0.60, 0.00 ≤ yb ≤ 0.60, and 0.00 ≤ zb ≤ 0.60.

[0041] Although there are no restrictions regarding the thickness of the entire semiconductor laminate 30, the thickness can be adjusted, for example, to 2.4 µm to 15 µm. Furthermore, although there are no restrictions regarding the thickness of the p-type cladding layer 37, the thickness can be adjusted, for example, to 0.4 µm to 5 µm. The thickness of the n-type cladding layer 31 can be adjusted to 2 µm to 10 µm, taking into account that the n-type cladding layer 31, as a cladding layer of a second conductivity type 31, is subjected to surface roughening on a light-taking side. In a case where the light-emitting layer 35 has a quantum well structure, the thickness of the well layer 35W can be set to 3 nm to 15 nm, the thickness of the barrier layer 35B can be set to 5 nm to 15 nm, and the number of pairs of both of these layers can be set to 1 to 50.

[0042] Furthermore, it is also preferred that the semiconductor laminate 30 comprises a p-type top layer 39, formed of InGaAsP comprising at least In and P, on the p-type cladding layer 37. Providing the p-type top layer 39 reduces lattice mismatch. Although there are no limitations regarding the thickness of the p-type top layer 39, the thickness can be adjusted, for example, to 50 nm to 200 nm. In the embodiment described below, an outermost layer of the semiconductor laminate 30 is arranged, for convenience, as the p-type top layer 39; however, the p-type top layer 39 is an optional configuration, and consequently, the outermost layer of the semiconductor laminate 30 can be arranged, for example, as the p-type cladding layer 37.

[0043] It should be noted that, although not shown in the drawings, the semiconductor laminate 30 preferably includes an i-type InGaAlAs spacer layer and an i-type InP spacer layer between the n-type cladding layer 31 and the light-emitting layer 35, and between the light-emitting layer 35 and the p-type cladding layer 37. The provision of spacer layers can prevent dopant diffusion. Although there are no restrictions regarding the thickness of the spacer layers, the thickness can be adjusted, for example, to 50 nm to 400 nm. Furthermore, the semiconductor laminate 30 can include window layers between the n-type and p-type cladding layers and the spacer layers.The window layers can have the same compositions as the cladding layers, or they can have compositions where the dopant concentration is changed, causing effective introduction of carriers into an active layer.

[0044] Each layer of the semiconductor laminate 30 can be formed by epitaxial growth. For example, each layer can be formed by a well-known thin-film growth process, such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or sputtering. For example, trimethylindium (TMIn) can be used as an intrinsic (In) source, trimethylgallium (TMGa) as a gallium (Ga) source, arsine (AsH3) as an astronautium (As) source, and phosphine (PH3) as a phosphorus (P) source in a specific mixing ratio. These source gases can be used to carry out gas-phase growth, while a carrier gas is also used to enable the formation of a semiconductor layer with a desired thickness according to the growth time.It should be noted that in a case where a layer is to be doped as a p-type or n-type, a dopant source gas should also be used in the desired manner.

[0045] In one example of the manufacturing process of the present embodiment, a contact section formation step and a dielectric layer formation step are included following the semiconductor laminate formation step. These steps are described below. < <kontaktabschnitt-bildungsschritt>>

[0046] In the contact section formation step, a contact layer 41, formed from a III-V compound semiconductor, is first formed on the semiconductor laminate 30. For example, a p-type contact layer 41 can be formed on the p-type top layer 39, as described in step 30 of the Fig. Figure 2 shows the p-type contact layer 41. This layer is in contact with the ohmic metal sections 43 and is located between the ohmic metal sections 43 and the semiconductor laminate 30. The p-type contact layer 41 should have a composition that results in a reduced contact resistance with the ohmic metal sections 43 compared to the semiconductor laminate 30, and can, for example, be a p-type InGaAs layer. Although there are no restrictions regarding the thickness of the contact layer 41, the thickness can be adjusted, for example, to 50 nm to 200 nm.

[0047] Next, ohmic metal sections 43 are formed on a part of the contact layer 41 such that an exposed area remains on the surface of the contact layer 41, as described in step 40 in the Fig. Figure 3 shows that the Ohm's metal sections 43 can be formed with distributed island shapes in a specific structure. In a case where a p-type InGaAs layer is used as the p-type contact layer 41, for example, Au, AuZn, AuBe, AuTi, or the like can be used as the Ohm's metal sections 43. The use of a layered structure of these metals is also preferred. For example, Au / AuZn / Au can be used as the Ohm's metal sections 43. Although there are no restrictions regarding the thickness (or total thickness) of the Ohm's metal sections 43, the thickness can be adjusted, for example, to 300 nm to 1300 nm and more, preferably to 350 nm to 800 nm.

[0048] An exposed area can be left on the surface of the contact layer 41, for example, by forming a photoresist structure on the surface of the contact layer 41, performing a vapor deposition of the ohmic metal sections 43, and then performing a lifting of the photoresist structure to form the ohmic metal sections 43. Alternatively, the ohmic metal sections 43 can be formed by forming a specific metal layer on the entire surface of the contact layer 41, forming a mask on the metal layer, and then performing etching or the like. In each case, the ohmic metal sections 43 are formed on a portion of the contact layer 41, and a surface that is not in contact with the ohmic metal sections 43 (i.e., an exposed area) can be formed on the surface of the contact layer 41, as described in step 40 in the Fig. 3 is shown.

[0049] Although the Ohm metal sections 43 may have a trapezoidal shape in a cross-sectional view, as shown in step 40 in the Fig. Figure 3 shows that this is only a schematic representation of the shape of the Ohm's metal sections 43. The Ohm's metal sections 43 can have a rectangular shape in a cross-sectional view and can have a shape with rounded corners.

[0050] Furthermore, in the contact section formation step, the contact layer 41 in the exposed area is removed until the surface of the semiconductor laminate 30 is exposed, thereby forming contact sections 40, each consisting of an ohmic metal section 43 and a contact area 41A, as described in step S50 in the Fig. Figure 3 shows this. In other words, the contact layer 41 is etched until the surface of the p-type top layer 39, which is an outermost layer of the semiconductor laminate 30, is exposed at locations different from those where the ohmic metal sections 43 were previously formed, and consequently the contact layer 41 becomes the contact regions 41A. For example, a photoresist mask can be formed on and around the ohmic metal sections 43 (about 2 µm to 5 µm), and then the exposed area of ​​the contact layer 41 can be wet-etched using a tartaric acid-hydrogen peroxide etchant or the like. Alternatively, the wet etching can be carried out using an inorganic acid-hydrogen peroxide etchant, an organic acid-hydrogen peroxide etchant, or the like.Furthermore, in a case where the Ohmian metal sections 43 have been formed by forming a mask on a specific metal layer and subsequent etching during the formation of the exposed area, the etching can be carried out continuously.

[0051] It should be noted that the thickness of each of the contact sections 40 corresponds to the total thickness of the contact layer 41 (contact area 41A) and the ohmic metal section 43 and can be set to 350 nm to 1500 nm and more, preferably to 400 nm to 1000 nm. < <dielektrikumschicht-bildungsschritt>>

[0052] In the dielectric layer formation step, a dielectric layer 50 is formed on at least a part of the cover layer 39 of the semiconductor laminate 30, as described in step S60 in the Fig. Figure 3 shows that such a dielectric layer 50 can be formed, for example, in the manner described below.

[0053] First, a dielectric layer is deposited over the entire surface of the semiconductor laminate 30, for example, to cover the semiconductor laminate 30 and the contact sections 40. A conventionally known technique, such as plasma CVD or sputtering, can be used as the deposition method. If a dielectric is formed on the contact sections 40 in the dielectric layer 50 on the surface of the deposited dielectric layer above the contact sections 40, the dielectric on the contact sections 40 can be removed in a desired manner by forming a mask and performing etching or the like. For example, the dielectric on the contact sections 40 can be wet-etched using buffered hydrofluoric acid (BHF) or the like.

[0054] It should be noted that it is also preferred to form the dielectric layer 50 on a portion of the cover layer 39 of the semiconductor laminate 30 and to configure surrounding areas of the contact sections 40 as exposed sections, as described in the Fig. Figure 4 shows that such a dielectric layer 50 and such exposed sections can be formed, for example, in the manner described below. First, a dielectric layer is deposited over the entire surface of the semiconductor laminate 30, and then a window structure, which completely surrounds the contact sections 40, is formed by a photoresist above the contact sections 40 on the surface of the deposited dielectric layer. In this situation, it is preferred that the window structure is widened by about 1 µm to 5 µm with respect to the lengths in the width and length directions of the contact sections 40. By using a photoresist structure that has been formed in this way for etching and thereby removing the dielectric near the contact sections 40, a dielectric layer 50 is formed and surrounding areas of the contact sections 40 become exposed sections.

[0055] To reliably maintain this shape, the width W of the exposed sections is preferably set to not less than 0.5 µm and not more than 5 µm, and more preferably to not less than 1 µm and not more than 3.5 µm.

[0056] It is also preferred that the contact area ratio of the contact between the dielectric layer 50 and the semiconductor laminate 30 be set to not less than 80% and not more than 95%. This is because reducing the area of ​​the contact sections 40 and increasing the area of ​​the dielectric layer 50 allows light absorption by the contact sections 40 to be inhibited. It should be noted that the contact area ratio can be measured while the wafer is in its final form or after segmentation.

[0057] Although there are no specific restrictions regarding the relationship between the thickness H1 of the dielectric layer 50 formed in the dielectric layer formation step and the thickness H2 of the contact sections 40, where the thickness of the dielectric layer 50 is designated as H1 and the thickness of the contact sections 40 is designated as H2, these thicknesses can be set as H1 ≥ H2, and it is also preferred to set the thicknesses as H1 > H2, as described in the Fig. Figure 4 shows that under this condition, the thickness of the dielectric layer 50 can be adjusted, for example, to 360 nm to 1600 nm and preferably to 410 nm to 1100 nm. Furthermore, it is also preferred that the difference H1 - H2 between the thickness H1 of the dielectric layer 50 and the thickness H2 of the contact sections 40 be adjusted to not less than 10 nm and not more than 100 nm.

[0058] SiO2, SiN, ITO, AIN, or the like can be used as the dielectric layer 50. In particular, it is preferred that the dielectric layer 50 be made of SiO2. This is because SiO2 is easily processed by etching using BHF or the like. <metallreflexionsschicht-bildungsschritt>

[0059] In the metal reflective layer formation step, a metal reflective layer 60, which reflects light emitted by the light-emitting layer 35, is formed on the dielectric layer 50 and the contact sections 40, which are formed longitudinally to each other, as described in step 70 in the Fig. Figure 5 is shown. It should be noted that if exposed sections have been formed in the dielectric layer formation step, the metal reflection layer 60 is also formed on the exposed sections. Au, Al, Pt, Ti, Ag, or the like can be used in the metal reflection layer 60, and it is particularly preferred that Au is a major component of the metal reflection layer 60. In this case, Au preferably constitutes more than 50% by mass in the composition of the metal reflection layer 60 and more preferably constitutes 80% by mass or more in the composition of the metal reflection layer 60.Although the metal reflection layer 60 may comprise a plurality of metal layers, in a case where the metal reflection layer 60 comprises a metal layer formed of Au (hereinafter referred to as the “Au metal layer”), it is preferred that the thickness of the Au metal layer constitutes more than 50% of the total thickness of the metal reflection layer 60. For example, the metal reflection layer may be a single layer formed only of Au, or two or more Au metal layers may be included in the metal reflection layer. For reliable joining in the subsequent joining step, it is preferred that an outermost layer of the metal reflection layer (i.e., a surface on the side facing the semiconductor laminate 30) is formed as the Au metal layer.For example, metal layers of Al, Au, Pt, and Au can be deposited in that order on the dielectric layer 50, the exposed sections, and the contact sections 40, and these metal layers can form the metal reflection layer. The thickness of an Au metal layer in the metal reflection layer can be adjusted, for example, from 400 nm to 2000 nm, and the thickness of a metal layer formed from a metal other than Au in the metal reflection layer can be adjusted, for example, from 5 nm to 200 nm. The metal reflection layer 60 can be deposited and formed on the dielectric layer 50, the exposed sections, and the contact sections 40 by a typical technique, such as vapor deposition. <verbindungsschritt>

[0060] In the joining step, a carrier substrate 80, which differs from the growth substrate 10, is joined by means of the metal reflection layer 60, as described in step 80 in the Fig. Figure 5 shows that a metal compound layer 70 can be pre-formed on the surface of the support substrate 80 by sputtering, vapor deposition, or the like. This metal compound layer 70 and the metal reflection layer 60 can be joined together by arranging the metal compound layer 70 and the metal reflection layer 60 opposite each other and then performing a hot press joining at a temperature of approximately 250 °C to 500 °C.

[0061] A metal such as Ti, Pt, or Au, or a metal (Sn, etc.) that forms a eutectic alloy with gold, can be used in the metal compound layer 70, which is connected to the metal reflection layer 60, and a layer in which these metals are stacked is preferred. For example, a layer obtained by stacking Ti with a thickness of 400 nm to 800 nm, Pt with a thickness of 5 nm to 20 nm, and Au with a thickness of 700 nm to 1200 nm in that order from the surface of the support substrate 80 can be used as the metal compound layer 70.It should be noted that, to facilitate the joining of the metal reflection layer 60 and the metal compound layer 70, it is preferred that an Au metal layer is used as an outermost layer on the side of the metal compound layer 70, that Au is also used as a metal layer on the side of the metal compound layer 70 of the metal reflection layer 60, and that joining between Au is carried out by Au-Au diffusion.

[0062] It should be noted that, for example, a conductive Si substrate can be used as the support substrate 80. Alternatively, a conductive GaAs or Ge substrate can be used. Furthermore, in addition to a semiconductor substrate, as described above, a metal substrate can also be used, or a mounting base substrate can be used in which a heat-dissipating insulating substrate made of calcined AIN or the like is employed. <wachstumssubstrat-entfernungsschritt>

[0063] In the growth substrate removal step, the growth substrate 10 is removed to expose the etch stop layer 20, as described in step 90 in the Fig. Figure 6 shows that the growth substrate 10 can be removed, for example, by wet etching using dilute hydrochloric acid, and the etch stop layer 20 can be used as the endpoint of the wet etching. <Schritt des Freilegens der Mantelschicht eines zweiten Leitfähigkeitstyps>

[0064] In the step of exposing the cladding layer of a second conductivity type, an n-sided electrode 93 is formed as an electrode of the upper surface on an n-sided electrode formation area 20A of the etch stop layer 20, which has been exposed while the etch stop layer 20 is also partially removed, as described in step 100 and step 110 in the Fig. Figure 6 shows this. This allows the semiconductor laminate 30 to be provided with a light-taking surface 31A. The etch stop layer 20 can be partially removed after the n-sided electrode 93 has been prepared on the n-sided electrode formation area 20A, or the etch stop layer 20 can be removed beforehand, except in the n-sided electrode formation area 20A, and the n-sided electrode 93 can then be formed. The etch stop layer 20 can be removed by wet etching using a sulfuric acid-hydrogen peroxide etchant or a tartaric acid-hydrogen peroxide etchant.

[0065] It should be noted that the etch stop layer 20 on the cladding layer of a second conductivity type 31 at the light-taking surface 31A can alternatively be etched in the surface roughening treatment step described below, and consequently, the removal of the etch stop layer 20 can be carried out simultaneously with the surface roughening treatment. Accordingly, one of the previously described steps for removing the etch stop layer 20 can be omitted, and it is also preferred to use the etch stop layer 20 as a mask to delay the start of etching the cladding layer of a second conductivity type 31 and to adjust the shape of surface irregularities of the cladding layer of a second conductivity type 31 at the light-taking surface 31A. <Oberflächenaufrauhung-Behandlungsschritt>

[0066] In the subsequent surface roughening treatment step, the exposed cladding layer of a second conductivity type 31, excluding the n-side electrode 93, is immersed in concentrated nitric acid to perform surface roughening. This adjusts the developed surface area ratio (Sdr) of the light-taking surface 31A of the cladding layer of the second conductivity type 31 to 4.0 or more. The concentrated nitric acid used in the surface roughening treatment can be an etchant prepared at a concentration of 61 wt.% or a commercially available etchant, such as nitric acid for the electronics industry (manufactured by Kanto Chemical Co., Inc.; Nitric Acid 1.38). Furthermore, Sdr is preferably adjusted to 4.4 or more. Sdr is also preferably adjusted to 7.0 or less, and more preferably to 5.8 or less.The temperature of the concentrated nitric acid is preferably lower than 10 °C, more preferably lower than 9 °C, and even more preferably lower than 8 °C. If the concentrated nitric acid is at a high temperature, this leads to a high etching rate and can cause penetration or loss of the coating layer. Furthermore, the concentration of the concentrated nitric acid is preferably 60 wt.% or more, more preferably 61 wt.% or more, and even more preferably 62 wt.% or more. If the concentration of the concentrated nitric acid is less than 60 wt.%, this can lead to the formation of an unacceptably rough surface.The surface roughening treatment is preferably carried out such that the light-absorbing surface 31A of the cladding layer of a second conductivity type 31 has a mean arithmetic height (Sa) of 0.60 µm or less and an skewness (Ssk) of 0.30 or more, and is more preferably carried out such that Sa is 0.55 µm or less and Ssk is 0.40 or more. Furthermore, a step of forming a mesa structure and a step of cutting a section removed by the mesa can be included to perform segmentation after the surface roughening treatment step.Furthermore, in a different situation where the surface roughening treatment step is to be performed with the electrode of the upper surface exposed, a step of masking an electrode area of ​​the upper surface, or a section not to be subjected to surface roughening, using a photoresist or the like, can be included before immersion in the etching agent. In this way, a light-emitting semiconductor element 200, which is in the . Fig. As shown in 7, they are manufactured. <<Schritt zur Bildung eines Schutzfilms> >

[0067] Although not shown, the light-emitting semiconductor element can be obtained by providing a protective film on the surface, including the light-absorbing surface 31A of the cladding layer of a second conductivity type 31, after the surface roughening treatment step. The protective film can be formed by a generally known technique, such as plasma CVD or sputtering. SiO2, SiN, ITO, AlN, or the like can be used as the protective film. The protective film has an effect of increasing light emission by reducing the refractive index difference between the n-type cladding layer 31 and air and also has an effect of improving the lifetime characteristics when the light-emitting semiconductor element is powered.In the case of the cladding layer of a second conductivity type 31, which has been subjected to the surface roughening treatment step according to the present disclosure, the protective film can be formed without the formation of sections where the protective film and the cladding layer of a second conductivity type 31 are not in contact (i.e., cavities), since hollowing does not occur at a boundary between an area where the surface of the cladding layer of a second conductivity type 31 is subjected to surface roughening and an area that is not subjected to surface roughening. It should also be noted that a protective film can be provided that protects a side surface of the semiconductor laminate 30.

[0068] The present embodiment is intended to be an embodiment in which, for a convenient description, an n-type InP substrate is used as the growth substrate 10, and consequently the n- and p-types of layers formed on the growth substrate 10 are as described above, however, it should be clear that the conductivity types (n-type / p-type) of layers can be reversed.

[0069] Although one embodiment has been described above, embodiments are not limited to this embodiment, and various modifications can be carried out within the scope of this disclosure using generally known techniques. For example, in a situation where a compounding method is not used, if an n-TypeP substrate is used as the growth substrate 10, e.g.the cladding layer of a first conductivity type can be changed to an n-type and the cladding layer of a second conductivity type 31 can be changed to a p-type, the cladding layer of a first conductivity type 37, the light-emitting layer 35 and the cladding layer of a second conductivity type 31 can be formed in this order as the semiconductor laminate 30 on the growth substrate 10, the contact layer 41 can be formed on the cladding layer of a second conductivity type 31, the ohmic metal sections 43 can subsequently be formed on the surface of the contact layer 41, as described in steps 40 and 50 in the . Fig. 3 is shown, and an upper surface of the sheath layer of a second conductivity type (sheath layer of a first conductivity type 37 and cover layer 39 in the Fig. 3), which has been exposed by subsequent removal of part of the contact layer 41, can be subjected to the surface roughening treatment step as a light-taking surface 31A. Furthermore, the rear surface electrode 91 can be formed on a rear surface of the growth substrate 10. In this case, the Ohmic metal sections 43 fulfill the role of a top surface electrode. In a situation where a joining process is not used, the etch stop layer 20 may or may not be included. It should also be noted that, although the side surface of the semiconductor laminate 30 shown is drawn perpendicular, the side surface of the semiconductor laminate 30 may be inclined as a result of mesa etching in the mesa structure formation step.Although a more detailed description of the present disclosure is given below by means of examples, the present disclosure is in no way limited by the following examples. EXAMPLES

[0070] Light-emitting semiconductor elements according to Examples 1 to 5 and Comparative Examples 1 to 6 were fabricated using a compounding method with a central target emission wavelength of 1000 nm to 1900 nm. Although a more detailed description of the present disclosure is given below by means of examples, the present disclosure is in no way limited by the following examples. (Example 1)

[0071] The thickness and dopant concentration of each component of a light-emitting semiconductor element according to Example 1 are shown in Table 1 for a state after growth on a growth substrate but before joining with a support substrate.

[0072] The light-emitting semiconductor element according to Example 1 was produced according to the flowchart for a process for producing a light-emitting semiconductor element of the compound type described in Fig. Figures 2 to 4 are shown. In particular, the light-emitting semiconductor element was fabricated as follows. First, an initial n-type InP growth layer (100 nm) was deposited on a (100) area of ​​an n-type InP substrate, followed by an n-type InP substrate. 0,57 Ga 0,43 As etch stop layer (20 nm), an n-type in 0,52 Ga 0,18 Al 0,30 As (i.e., Al composition fraction 30%) sheath layer (thickness: 4800 nm; dopant concentration: 5.0 × 10 17 atoms / cm² 3 ), an i-type in 0,52 Ga 0,18 Al 0,30 As spacer layer (thickness: 100 nm), a light-emitting layer (total 188 nm) with a quantum well structure with a light emission wavelength of 1490 nm, an i-type InP spacer layer (thickness: 320 nm), a p-type InP cladding layer (2400 nm; dopant concentration: 7.0 × 10 17 atoms / cm² 3 ), a p-type in 0,8 Ga 0,20 As 0,5 P 0,5 -Cover layer (thickness: 50 nm; dopant concentration: 5.0 × 10 18 atoms / cm² 3 ) and a p-type in 0,57 Ga 0,43 As contact layer (thickness: 100 nm; dopant concentration: 1.5 × 10 19 atoms / cm² 3 ) formed sequentially using a MOCVD device. It should be noted that during the formation of the light-emitting layer with a quantum well structure, an in 0,526 Ga 0,398 Al 0,076 An acetylene barrier layer (thickness: 8 nm) was formed, and then an in 0,567 Ga 0,352 Al 0,081 As trough layer (thickness: 10 nm) and an In 0,526 Ga 0,398 Al 0,076 As barrier layer (thickness: 8 nm) was stacked alternately for 10 pairs.

[0073] Ohmic electrode sections of the p-type (Au / AuZn / Au; total thickness: 530 nm) were arranged in distributed island shapes on the p-type in 0,57 Ga 0,43 An acetylene contact layer was formed to create contact sections. During this process, a photoresist structure was created, followed by the vapor deposition of an ohmic electrode. The photoresist structure was then lifted to form the contact area. After examining the top surface of a semiconductor laminate on a wafer in this state using an optical microscope, the contact area ratio of the p-type ohmic electrode sections to the semiconductor laminate was found to be 0.95%. To create the ohmic contact, a heat treatment at 300 °C for 1 minute was performed.

[0074] Next, a photoresist mask was formed on the Ohm's electrode sections and the p-type in 0,57 Ga 0,43 The acetylene contact layer was removed by wet etching with tartaric acid-hydrogen peroxide at locations different from where the ohmic electrode sections had formed. After removal of the photoresist, a dielectric layer of SiO₂ (thickness: 700 nm) was deposited over the entire surface of the p-type ln 0,80 Ga 0,20 As 0,50 P 0,50 A top layer was formed by plasma-CVD. A window structure with a shape provided with a width of 10 µm in a region above the p-type ohmic electrode sections was formed by a photoresist, and the dielectric layer was applied by wet deposition using BHF to the p-type ohmic electrode sections and their surroundings to expose the p-type ln. 0,80 Ga 0,20 As 0,50 P 0,50 A cover layer is formed. The height H1 (700 nm) of the dielectric layer on the p-type in 0,80 Ga 0,20 As 0,50 P 0,50 The top layer is 30 nm larger than the height H2 (670 nm) of a contact layer formed from the p-type contact layer (thickness: 120 nm) and the p-type ohmic electrode sections (thickness: 530 nm). It should be noted that when examining the top surface of a semiconductor laminate of a wafer using a light microscope in this state, the contact area ratio of the dielectric layer (SiO2) was 93%.

[0075] Next, a metal reflective layer (Ti / Au / Pt / Au) was applied to the entire surface of the p-type in 0,80 Ga 0,20 As 0,50 P 0,50 The top layer and the dielectric layer are formed by vapor deposition. The thicknesses of the metal layers in the metal reflection layer are, in this order: 2 nm Ti, 650 nm Au, 10 nm Pt, and 900 nm Au.

[0076] Furthermore, a metal compound layer (Ti / Pt / Au) was formed on a conductive Si substrate (thickness: 300 µm), which serves as the support substrate. The thicknesses of the metal layers in the metal compound layer are, in this order, 650 nm Ti, 10 nm Pt, and 900 nm Au.

[0077] The metal reflective layer and the metal bonding layer were positioned opposite each other and joined by hot pressing at 315 °C. The InP substrate was then removed by wet etching using dilute hydrochloric acid.

[0078] Next, the upper surface of the ohmic electrode was formed. An electrode structure of the upper surface was created by forming a photoresist structure at locations different from those where the upper surface electrode was to be formed, vapor deposition of an n-type electrode (Au (thickness: 10 nm) / Ge (thickness: 33 nm) / Au (thickness: 57 nm) / Ni (thickness: 34 nm) / Au (thickness: 800 nm) / Ti (thickness: 100 nm) / Au (thickness: 1000 nm)) and lifting the photoresist structure. A contact section (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) was then further formed on a circular section in the center of the n-type electrode, thus obtaining an electrode structure of the upper surface as described, for example, in the Fig. 8 is shown.

[0079] The etch stop layer was removed by etching using a tartaric acid-hydrogen peroxide etchant.

[0080] Next, the light-tapping surface of the n-type cladding layer underwent a surface roughening treatment. First, a photoresist structure was formed over areas that were not to be roughened (the planned mesa etching position on the top surface of the n-type cladding layer, as described below, and the top and perimeter of the electrode on the top surface). The photoresist acts as a film that blocks etching. Areas where this photoresist structure is not present are those where surface roughening is to be performed. Following this, immersion in concentrated nitric acid (61 wt%) for semiconductors, cooled to 8 °C, was carried out for a residence time of 5 seconds.The product was immediately removed and subjected to a 60-second wash with running water by shaking it in pure water, an 80-second alkaline wash by shaking it in ammonia solution, another 60-second wash with running water by shaking it in pure water, and then blow-drying. The photoresist structure was then removed.

[0081] Next, a dividing line was formed by mesa etching. A photoresist structure was formed over areas distinct from the dividing line, and the semiconductor laminate above the dividing line was removed by dry etching. Subsequently, a 190 nm thick SiN protective film was formed over the entire surface by plasma CVD, covering the surface, including an inclined side surface (mesa side surface) of the semiconductor laminate formed by dry etching and the light-taking surface described above. The protective film (SiN) on the contact electrode was partially removed to expose a portion of the contact electrode surface required for wire bonding.After the light-emitting layer was protected using a photoresist, a grinding tool was used to grind the substrate (Si substrate) until its thickness reached 150 µm. Next, a back-surface electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on a back surface corresponding to the ground surface of the Si substrate. Chip segmentation was then performed by cutting, resulting in a light-emitting semiconductor device as shown in Example 1. The chip size is 250 µm × 250 µm. (Examples 2 to 4 and comparative examples 1 to 6)

[0082] In the following examples and comparison examples, light-emitting semiconductor devices were produced in which the Al composition fraction of the n-type cladding layer made of InGaAlAs was suitably changed in a range from 48% to 0%, and light-emitting semiconductor devices in which the composition of the n-type cladding layer was changed to InP or GaAs. (Example 2)

[0083] A light-emitting semiconductor element according to Example 2 was obtained in the same way as in Example 1, except that the composition of the n-type cladding layer of In 0,52 Ga 0,18 Al 0,30 As to In 0,52 Ga 0,23 A 10,25 As was changed (i.e., the Al composition percentage was changed to 25%). (Example 3)

[0084] A light-emitting semiconductor element according to Example 3 was obtained in the same way as in Example 1, except that the composition of the n-type cladding layer of In 0,52 Ga 0,18 Al 0,30 As to In 0,52 Ga 0,28 Al 0,20 As was changed (i.e., the Al composition percentage was changed to 20%). (Example 4)

[0085] A light-emitting semiconductor element according to Example 4 was obtained in the same way as in Example 1, except that the composition of the n-type cladding layer of In 0,52 Ga 0,18 Al 0,30 As to In 0,52 Ga 0,33 Al 0,15 As was changed (i.e., the Al composition percentage was changed to 15%). (Example 5)

[0086] A light-emitting semiconductor element according to Example 5 was obtained in the same way as in Example 1, except that the composition of the n-type cladding layer of In 0,52 Ga 0,18 Al 0,30 As to In 0,52 Ga 0,38 Al 0,10 As was changed (i.e., the Al composition percentage was changed to 10%). (Comparative example 1)

[0087] A light-emitting semiconductor element according to Comparative Example 1 was obtained in the same way as in Example 1, except that the composition of the n-type cladding layer of In 0,52 Ga 0,18 Al 0,30 As to In 0,52 Al 0,48 As was changed (i.e., the Al composition percentage was changed to 48%). (Comparative example 2)

[0088] A light-emitting semiconductor element according to Comparative Example 2 was obtained in the same way as in Example 1, except that the composition of the n-type cladding layer of In 0,52 Ga 0,18 Al 0,30 As to In 0,52 Ga 0,13 Al 0,35 As was changed (i.e., the Al composition percentage was changed to 35%). (Comparative example 3)

[0089] A light-emitting semiconductor element according to Comparative Example 3 was obtained in the same way as in Example 1, except that the composition of the n-type cladding layer of In 0,52 Ga 0,18 Al 0,30 As to In 0,52 Ga 0,43 Al 0,05 As was changed (i.e., the Al composition percentage was changed to 5%). (Comparative example 4)

[0090] A light-emitting semiconductor element according to Comparative Example 4 was obtained in the same way as in Example 1, except that the composition of the n-type cladding layer of In 0,52 Ga 0,18 Al 0,30 As to In 0,52 Ga 0,43 As was changed (i.e., the Al composition percentage was changed to 0%). (Comparative example 5)

[0091] A light-emitting semiconductor element according to Comparative Example 5 was obtained in the same way as in Example 1, except that the composition of the n-type cladding layer of In 0,52 Ga 0,18 Al 0,30 As was changed to InP. (Comparative example 6)

[0092] A light-emitting semiconductor element according to Comparative Example 6 was obtained in the same way as in Example 1, except that the composition of the n-type cladding layer of In 0,52 Ga 0,18 Al 0,30 As was changed to GaAs. (Evaluation of light emission properties)

[0093] For each of the light-emitting semiconductor elements according to Examples 1 to 4 and Comparison Examples 1 to 6, the forward voltage Vf (V) and the luminous efficacy Po (mW) were measured using an integrating sphere when forward currents If (mA) of 30 mA and 36 mA were applied using a constant current / voltage power supply. The central emission wavelength λp (nm) and the full width at half maximum (FWHM; unit: nm) were also measured using a spectral analyzer (AQ6374, manufactured by Yokogawa Test & Measurement Corporation). It should be noted that in these measurements, an average value of the results for three samples was determined. Next, the luminous efficacy was divided by the applied power to calculate Po / (Vf · If), the value of which was used as the index of luminous efficacy relative to the applied power.Furthermore, in each example or comparison example, an assessment was made regarding the rate of increase in light emission relative to a reference product manufactured using the exact same process, except that surface roughening of the cladding layer of a second conductivity type was omitted. The various measurement and calculation results are shown in Table 2. A rate of increase in Po of 120% or more was rated as 'A', a rate of increase in Po of 110% or more was rated as 'B', and a rate of increase in Po of less than 110% was rated as 'C'. Although not shown in Table 2, the central emission wavelength in each example or comparison example was within a range of 1490 nm ± 10 nm. [Table 2] Composition components Sa(µm) Sdr Ssk Buttock growth rate* SEM cross-section hollowing composition In (%) Ga (%) Al (%) Comparative example 1 InAlAs 52 0 48 0,69 6,78 0,24 A Yes Comparative example 2 InGaAlAs 52 13 35 0,63 5,91 0,26 A Yes Example 1 InGaAlAs 52 18 30 0,59 5,46 0,34 A No Example 2 InGaAlAs 52 23 25 0,55 5,24 0,43 A No Example 3 InGaAlAs 52 28 20 0,52 4,81 0,50 A No Example 4 InGaAlAs 52 33 15 0,50 4,44 0,61 A No Example 5 InGaAlAs 52 38 10 0,63 4,86 0,47 A No Comparative example 3 InGaAlAs 52 43 5 0,63 4,39 0,54 B No Comparative example 4 InGaAs 52 48 0 0,55 3,33 0,65 C No Comparative example 5 n-InP 100 0 0 - - - C - Comparative example 6 n-GaAs 0 100 0 0,11 0,11 1,66 C No * Buttock growth rate A: ≥120%, B: ≥110%, C: <110% (Measurement of the roughness of the light pickup surface)

[0094] As previously described, a profile analysis laser microscope (VK-X1000 / 1100, manufactured by Keyence Corporation) was used to measure the rough surface shape of an n-type cladding layer (a cladding layer of a second conductivity type) on a chip after surface roughening treatment (post-slicing). The objective magnification was set to 50x and the pixel count was set to 2048x1536.

[0095] During data measurement, surface roughness parameters (Sa, Sz, Spc, Sdr, Ssk, etc.) are automatically calculated based on ISO 25178. Of these values, Sa, Sdr, and Ssk are shown above in Table 2, and their relationships with the Al composition fraction are described in [reference missing]. Fig. Figures 9 to 11 show that the influence of surface roughness from etching increases with increasing Al composition and that, in particular, there is a clear first-order correlation with Sdr. It should be noted that the surface roughness parameters for comparison example 5 in Table 2 are given as "-" because InP is not etched.

[0096] Fig. Figures 12 to 14 show electron micrographs around the surface of an n-type cladding layer after a surface roughening treatment in a cross-section obtained by slitting such that it passes through an n-sided electrode formation region of a light-emitting element in Comparative Example 1, Example 1, and Comparative Example 4, which are used as representative examples. As is shown in the Fig. As shown in Figure 13, the formation of a rough surface with sufficient roughness on the surface of the sheath layer of a second conductivity type in Example 1 is observed, which satisfies the scope of the present disclosure. On the other hand, in Comparative Example 1, which has a high Al composition content exceeding the scope of the present disclosure, the occurrence of hollowing out at a boundary between an area where a photoresist structure was used, so that surface roughening was not carried out, and an area where surface roughening was carried out, as shown in the Fig. 12 is shown (it should be noted that the frame line and the dashed line were added by the applicant), whereas a hollowing out, as is shown, for example, in the Fig. 12 is shown, but was not found in example 1 and in comparison example 4. COMMERCIAL APPLICABILITY

[0097] According to the present disclosure, a light-emitting semiconductor element can be provided which has a good light emission output relative to the input power compared to conventional light-emitting elements, and in which a protective film can be formed without the formation of cavities, and a method for manufacturing this light-emitting semiconductor element can also be provided. REFERENCE MARK LIST 10 Growth substrate 20 Etching stop layer 30 Semiconductor laminate 31. Sheath layer of a second conductivity type 31A Light pickup surface 35 Light-emitting layer 35W recessed layer 35B Barrier layer 37. Sheath layer of a first conductivity type 39 Top layer 40 Contact section 41 Contact layer 41A Contact area 43 Ohm metal section 50 Dielectric layer 60 Metal reflective layer 70 Metal compound layer 80 carrier substrate 100 Light-emitting semiconductor element 91 Electrode of the rear surface 93 Electrode of the upper surface QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2021-077885 A

[0003] JP 2018-101675 A

[0003] Cited non-patent literature

[0000] ISO 25178-2:2012

[0020] < / verbindungsschritt> < / zusammensetzung>

Claims

[1] Light-emitting semiconductor element comprising a cladding layer of a first conductivity type, a light-emitting layer and a cladding layer of a second conductivity type in the specified order with the cladding layer of a second conductivity type as the light-sucking side, wherein the light-emitting layer is a III-V compound semiconductor comprising one or two or more types of Al, Ga and In as group III elements, one or two or more types of As, Sb and P as group V elements, and has a central emission wavelength of 1000 nm to 1900 nm, the sheath of a second conductivity type is a composition of In x Ga y Al z As (0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1) has and The cladding layer of a second conductivity type has a light-absorbing surface with a developed interface ratio (Sdr) of 4.0 or more. [2] Light-emitting semiconductor element according to claim 1, wherein the cladding layer of a second conductivity type has an Al composition fraction z of 0.15 ≤ z ≤ 0.

30. [3] Light-emitting semiconductor element according to claim 1, wherein the light-harvesting surface of the cladding layer of a second conductivity type has a mean arithmetic height (Sa) of 0.60 µm or less and an skewness (Ssk) of 0.30 or more. [4] Light-emitting semiconductor element according to claim 1, wherein a band gap of the cladding layer of a second conductivity type is larger than a band gap of the light-emitting layer. [5] Light-emitting semiconductor element according to claim 1, wherein the cladding layer of a second conductivity type has a thickness of not less than 2 µm and not more than 10 µm. [6] Light-emitting semiconductor element according to claim 1, wherein the light-emitting layer has a quantum well type structure in which an InGaAlAs well layer and an InGaAlAs junction layer are stacked alternately. [7] Light-emitting semiconductor element according to claim 1, comprising an undoped spacer layer between the cladding layer of a first conductivity type and the light-emitting layer and between the light-emitting layer and the cladding layer of a second conductivity type. [8] Light-emitting semiconductor element according to claim 1, comprising a support substrate, the cladding layer of a first conductivity type, the light-emitting layer and the cladding layer of a second conductivity type in the specified order and comprising a metal reflection layer between the support substrate and the cladding layer of a first conductivity type, wherein Furthermore, a dielectric layer and a contact section, arranged longitudinally to each other, are included between the metal reflection layer and the cladding layer of a first conductivity type. [9] Method for producing a light-emitting semiconductor element comprising a cladding layer of a second conductivity type as a light-sucking side, comprising: a semiconductor laminate formation step of successively forming a cladding layer of a first conductivity type, a light-emitting layer and the cladding layer of a second conductivity type; and a surface roughening treatment step of immersing the mantle layer of a second conductivity type in concentrated nitric acid to perform surface roughening and thereby adjusting an developed interfacial ratio (Sdr) of a light-sucking surface of the mantle layer of a second conductivity type to 4.0 or more, wherein the light-emitting layer is a III-V compound semiconductor comprising one or two or more types of Al, Ga and In as group III elements, one or two or more types of As, Sb and P as group V elements, and has a central emission wavelength of 1000 nm to 1900 nm, and the sheath of a second conductivity type is a composition of In x Ga y Al z As (0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1) has. [10] Method for producing a light-emitting semiconductor element according to claim 9, wherein the concentrated nitric acid in the surface roughening treatment step has a temperature of less than 10 °C. [11] Method for producing a light-emitting semiconductor element according to claim 9, wherein the concentrated nitric acid in the surface roughening treatment step has a concentration of 60 wt.% or more. [12] Method for producing a light-emitting semiconductor element according to claim 9, wherein the cladding layer of a second conductivity type has an Al composition fraction z of 0.15 ≤ z ≤ 0.

30. [13] Method for producing a light-emitting semiconductor element according to claim 9, wherein the surface roughening treatment in the surface roughening treatment step is carried out such that the light-absorbing surface of the cladding layer of a second conductivity type has a mean arithmetic height (Sa) of 0.6 µm or less and an skewness (Ssk) of 0.3 or more. [14] Method for producing a light-emitting semiconductor element according to claim 9, further comprising, after the surface roughening treatment step, a step of forming a mesa structure and a step of cutting a section that has been removed by a mesa to carry out segmentation. [15] Method for producing a light-emitting semiconductor element, comprising: a semiconductor laminate formation step of successively forming an etch stop layer, a cladding layer of a second conductivity type, a light-emitting layer and a cladding layer of a first conductivity type on a growth substrate; a step of forming a dielectric layer and a contact section longitudinally to each other on the cladding layer of a first conductivity type; a metal reflection layer formation step of forming a metal reflection layer on the dielectric layer and the contact section; a connection step of joining a support substrate that differs from the growth substrate, using the metal reflection layer; a growth substrate removal step of removing the growth substrate to expose the etch stop layer; a step to expose the cladding layer of a second conductivity type by removing the etch stop layer to expose an upper surface of the cladding layer of a second conductivity type as the light pickup side; and a surface roughening treatment step of, after the step of exposing the sheath layer of a second conductivity type, immersion of the sheath layer of a second conductivity type in concentrated nitric acid to carry out surface roughening and thereby adjusting a developed interfacial area ratio (Sdr) of a light-sampling surface of the sheath layer of a second conductivity type to 4.0 or more, wherein the light-emitting layer is a III-V compound semiconductor comprising one or two or more types of Al, Ga and In as group III elements, one or two or more types of As, Sb and P as group V elements, and has a central emission wavelength of 1000 nm to 1900 nm, and the sheath of a second conductivity type is a composition of In x Ga y Al z As (0.49 ≤ x ≤ 0.55, 0.10 ≤ z < 0.35, x + y + z = 1) has.

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