FIELD PLATTENWIDERSTAND

Abstract

A semiconductor device (100A) includes a semiconductor substrate (101). A tray resistor (120) is located in the semiconductor substrate (101). A field plate (130) is located above the tray resistor (120). An insulator (125) is located between the tray resistor (120) and the field plate (130). The tray resistor (120) includes a first terminal (145A) and a second terminal (145B). The field plate (130) can be coupled to either the first terminal (145A) or the second terminal (145B).

Description

BACKGROUND

[0001] A tray resistor is a type of resistor formed within the substrate of an integrated circuit. It is created by doping the substrate with a semiconductor material to form a region of increased dopant concentration. Tray resistors can be used in analog circuits, such as amplifiers and filters, and in digital circuits, such as logic gates and registers. For example, a tray resistor can be used as a pull-up resistor in a logic gate or as a load resistor or bias resistor in an amplifier. Tray resistors are popular because they can be implemented without additional masks or processing steps. SUMMARY

[0002] In one example, a semiconductor device includes a semiconductor substrate. A tray resistor is located within the semiconductor substrate. A field plate is positioned above the tray resistor. An insulator is located between the tray resistor and the field plate.

[0003] In one example, an integrated circuit has a resistive well extending into a semiconductor substrate. A dielectric layer extends into the resistive well. Above the dielectric layer is a conductive field plate. The conductive field plate is designed to modulate a majority carrier distribution within the resistive well while the resistive well conducts current.

[0004] In another example, a process involves forming an insulating layer on a semiconductor substrate and doping a resistive well that extends into the semiconductor substrate. The process also involves depositing a layer of conductive material, spaced apart from the semiconductor substrate by the insulating layer, and etching the conductive material to form a field plate over the resistive well. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A is a side cross-sectional view of an exemplary field plate tray resistor. Fig. Figure 1B is a side cross-sectional view of another exemplary field plate tray resistor. Fig. Figure 2 is a top view of an exemplary field plate-tray resistor, e.g., the field plate-tray resistor of Fig. 1A. Fig. Figure 3 illustrates the majority carrier (hole) concentration in exemplary tray resistors as a functional depth into the resistor substrate. Fig. Figure 4 illustrates IV curves of the exemplary bath resistances of Fig. 3. Fig. Figure 5 is a flowchart of an exemplary procedure for manufacturing a field plate trough resistor. Fig. 6A-6M are cross-sectional views that illustrate the different manufacturing stages of the process of Fig. Show 5. Fig. Figure 7 is a side cross-sectional view of an exemplary integrated circuit that includes a field plate resistor coupled to a transistor. Fig. Figure 8 is a block diagram of an example driver circuit that includes a field plate dish resistor. DETAILED DESCRIPTION OF EXAMPLES OF EXECUTION

[0005] Various disclosed methods and devices of the present disclosure can be advantageously applied to a resistor with a reduced or adjustable voltage resistance coefficient. Although such embodiments may be expected to provide improved circuit performance in some implementations, no particular result is a requirement unless expressly stated in a specific claim.

[0006] A resistor can generally have a non-zero voltage coefficient of resistance, often simply referred to as the voltage coefficient. The voltage coefficient of a resistor is a measure of how much its resistance changes when a voltage is applied. For example, a resistor with a voltage coefficient of 100 ppm / V (100 parts per million per volt) will have a resistance change of 0.01% for every 1 V change in the applied voltage. A low voltage coefficient is desirable in some applications. For example, a low voltage coefficient may be desirable for a resistor used in a current-limiting application to reduce the variation in power dissipated by the resistor. A high voltage coefficient may be desirable in other applications.

[0007] The voltage coefficient of the resistors described here can be decreased or increased. These resistors consist of a tray resistor with a field plate positioned above it. An insulating layer is provided between the tray resistor and the field plate. The field plate can be conductively coupled to one of the two terminals of the tray resistor. Connecting the field plate to a lower-voltage terminal (current sink) of a p-tray resistor causes charge carriers to accumulate under the field plate, thus decreasing the voltage coefficient of the resistor. Connecting the field plate to a higher-voltage terminal (current source) of the p-tray resistor leads to a depletion of charge carriers under the field plate, thereby increasing the voltage coefficient of the resistor. For n-tray resistors, the effect on the voltage coefficient is reversed.In some other examples, the field plate is connected to a controllable voltage source that provides modulation of the voltage coefficient independent of the current flow through the resistor.

[0008] Fig. Figure 1A is a side cross-sectional view of an exemplary electronic device, a field-plate dish resistor 100A, located above and extending into a semiconductor substrate 101. The semiconductor substrate 101 includes a handle layer 105, a buried oxide (BOX) layer 110, and an epitaxial layer 115. The handle layer 105 can be bulk silicon or another semiconductor material. The BOX layer 110, which may be omitted in some examples, can be part of a silicon-on-insulator (SOI) substrate. Although the epitaxial layer 115 in the illustrated example is lightly doped p-type silicon (active silicon), the handle layer 105 and the epitaxial layer 115 can be any other combination of n-type or p-type material.

[0009] The 100A tray resistor further comprises a p-type resistance tray 120 extending into the epitaxial layer 115. The resistance tray 120 can be formed by doping the epitaxial layer 115 with a p-type dopant. An insulating layer 125 (e.g., an oxide layer) isolates the resistance tray 120 from a field plate 130. In the illustrated example, the field plate 130 is formed from a conductive material, e.g., polysilicon. The illustrated example also includes a silicide layer 135 on the field plate 130 to provide high conductivity. In some other examples, a field plate can be provided by a metal structure within an interlayer (a metal interlayer).

[0010] A first vertical connection or via 140 connects the field plate 130 via a second vertical connection 142 and a horizontal connection or conductor 150 in a first metal layer (M1) to a first terminal 145A of the resistive tray 120. A third vertical connection 144 is conductively connected to a second terminal 145B of the resistive tray 120 and to a horizontal connection 155. For reference, the first terminal 145A can be designated with a voltage V1 and the second terminal 145B with a voltage V2. The resistive tray 120 can be conductively coupled to other components formed in or above the semiconductor substrate 101 via other interconnections, such as unreferenced vertical connections and unreferenced horizontal connections in a second metal layer (M2).The various interconnections are located within the insulation layers 160 (e.g., one or more oxide or nitride layers). Although two metal layers (horizontal interconnection layers) are shown, the 100A field-plate junction box resistor can incorporate any number of metal layers. The illustrated interconnection configuration serves only as an example and does not exclude other examples.

[0011] The insulating layer 125 in the illustrated example is an STI structure (STI - Shallow Trench Insulation). In other examples, the field plate well resistor 100A can include any number of layers between the resistor well 120 and the field plate 130, for example, a field oxide layer or a LOCOS layer (LOCOS - Local Oxidation of Silicon), one or more silicon oxide layers, and / or one or more silicon nitride or silicon oxynitride layers. The distance between the resistor well 120 and the field plate 130 (e.g., the thickness of the insulating layer 125) can be selected based on the voltage (e.g., a maximum operating voltage) across the resistor well 120, for example, between the field plate 130 and the handle layer 105. At a higher voltage, the distance between the resistor well 120 and the field plate 130 can be increased.For example, the field plate 130 can be formed in the M2 metal layer to provide a greater distance between the resistor tray 120 and the field plate 130. At a lower voltage, the distance between the resistor tray 120 and the field plate 130 can be reduced. For example, the field plate tray resistor 100A can be formed in a polysilicon layer or the M1 metal layer to provide a smaller distance between the resistor tray 120 and the field plate 130.

[0012] The field-plate well resistor 100A can also include an insulating trench structure 165 (e.g., a deep trench insulator) around the resistor well 120 and the field plate 130. The insulating trench structure 165 comprises a trench in the semiconductor substrate 101 around the resistor well 120 and the field plate 130. The trench can be lined or filled with a dielectric material, such as silicon dioxide. In some examples, the dielectric material can be filled with a conductor, such as polysilicon. If the substrate is an SOI substrate, the insulating trench structure 165 can, as illustrated, contact the BOX layer 110 and thereby electrically isolate the resistor well 120 from other devices that share the substrate 101.Similarly, in examples that include a buried insulation layer, such as a buried n-type layer, the insulation trench can contain n-type polysilicon, thereby isolating the resistance tray 120 by a barrier layer insulation.

[0013] In general, the 100A well resistor can incorporate any known or future discovered configuration of a resistance well and / or other implanted areas, such as may be useful for isolating the resistance well. Accordingly, some other non-exclusive examples include a p-type resistance well within an n-type isolation well located within a p-type epitaxy layer; a p-type resistance well within an n-type epitaxy layer; an n-type resistance well within a p-type isolation well located within an n-type epitaxy layer; an n-type resistance well within a p-type isolation well located within an n-type epitaxy layer; and an n-type resistance well within an n-type epitaxy layer.The illustrated BOX layer 110 and / or the isolation trench structure 165 can both be optionally omitted, the BOX layer 110 can be included and the isolation trench structure 165 excluded, or the isolation trench structure 165 can be included and the BOX layer 110 excluded. Furthermore, in some examples, the epitaxial layer can be excluded, so that the resistive basin is formed within a bulk semiconductor (e.g., silicon).

[0014] Fig. Figure 2 is a top view of the field plate trough resistor 100, as shown in the illustration in Fig. Figure 1A shows the resistance trough 120 in the illustrated example, which is designed as a rectangular strip. The dimensions of the strip can be chosen to achieve structural resistance and comply with the relevant design rules. In other examples, the resistance trough 120 may have a different geometry, e.g., a serpentine shape. The isolation trench structure 165 surrounds the resistance trough 120 and the field plate 130.

[0015] Fig. Figure 1B illustrates a field-plate junction box resistor 100B, in which the field plate 130 is conductively connected to a horizontal intermediate connection 170 via a vertical intermediate connection 146. The intermediate connection 170 provides a third terminal to which a voltage Vc can be applied. This third terminal provides a connection to the field plate 130 that can be biased independently of V1 and V2 if such independent control is desirable.

[0016] The 100A or 100B field-plate sump resistor can be connected in an integrated circuit to implement a resistance between two circuit nodes. In one example, terminal 145A is connected to a circuit node that has a first voltage during operation, and terminal 145B is connected to a circuit node that has a lower second voltage during operation. Accordingly, in this example, the current flow in the 120-cell resistor sump is from terminal 145A to terminal 145B. In another example, terminal 145B has a higher voltage during operation, and terminal 145A has a lower voltage, so the current flow in the 120-cell resistor sump is from terminal 145B to terminal 145A. This aspect is discussed in more detail below.

[0017] Since the resistance tray 120 can generally have a non-zero voltage coefficient, the field plate 130 makes it possible to at least partially reduce the magnitude of the voltage coefficient by modulating the charge carrier concentration within the resistance tray 120. With further reference to Fig. 1A, the resistivity of the resistor tray 120 can be decreased by increasing the majority carrier concentration in a part of the resistor tray 120. Conversely, the resistivity can be increased by decreasing the majority carrier concentration in a part of the resistor tray 120. It should be noted that when current flows from terminal 145A to terminal 145B, terminal 145B will have a lower voltage than terminal 145A due to an IR voltage drop. The opposite is true when current flows from terminal 145B to terminal 145A.

[0018] The inventor discovered that this voltage difference can be used to selectively modify the voltage coefficient of the resistance tray 120. For example, when current flows from terminal 145B to terminal 145A, terminal 145B will have a higher voltage than terminal 145A. The terminal with the higher voltage can be called the "high-side terminal," and the terminal with the lower voltage can be called the "low-side terminal." If the resistance tray 120 is of the p-type, the field plate 130 can be connected to the low-side terminal, e.g., terminal 145A. The lower voltage of the field plate 130 attracts holes into the area of ​​the resistance tray 120 closest to the field plate, creating a path of lower resistance that reduces the overall resistance of the resistance tray 120.In another example with the same current flow direction, the field plate 130 can be connected to the high-side terminal, e.g., terminal 145B. The higher voltage of the field plate 130 repels holes from the area of ​​the resistor tray 120 closest to the field plate, creating a path of higher resistance that increases the overall resistance of the resistor tray 120. If the resistor tray 120 is of the n-type, the effects are reversed. In addition to modulating the conductivity of the resistor tray 120, the field plate 130 can also shield the resistor tray 120 from noise and signals above the resistor tray 120. Accordingly, the field plate 130 enables the routing of high-voltage signals above the field plate tray resistor 100A.

[0019] The Fig. 3 and Fig. Figure 4 graphically illustrates aspects of the operation of the 100A field plate resistor using the example of a current flow from terminal 145B to terminal 145A. Fig. Figure 3 contains characteristic curves derived from the modeling of three examples of hole concentration (logarithmic scale) as a function of depth between the insulation layer 125 and the buried oxide layer 110. Accordingly, these characteristic curves represent a hole concentration within the p-type resistor tray 120 with increasing depth below the insulation layer 125. A first characteristic curve 302 illustrates the hole concentration for a resistor similar to the model resistor 100A, but without the field plate 130. The hole concentration rises rapidly from zero to a maximum value and then decreases uniformly with increasing depth. A second characteristic curve 304 illustrates the hole concentration for a resistor that, according to the representation in Figure 3, is designed as follows: Fig. 1A is implemented, and terminal 145A is the low-side terminal for the direction of current flow. Thus, the field plate 130 is connected to the low-side terminal of the resistance tray 120. In this case, it is observed that the hole concentration decreases from a maximum value near the insulation layer 125 to a local minimum, after which the concentration closely follows the characteristic curve 302 of the resistor without the field plate. A third characteristic curve 306 illustrates the hole concentration for a resistor that is otherwise as in Fig. 1A is shown, except that the field plate is connected to the high-side terminal 145B of the resistance tray 120. (It should be noted that this example is equivalent to current flowing from terminal 145A to terminal 145B in the device 100A, as shown in Fig. (1A shown.) In this case, it is observed that the hole concentration increases from a low value to the maximum value of characteristic curve 302, but with a reduced hole concentration compared to characteristic curve 302 near the insulation layer 125.

[0020] Fig. Figure 4 illustrates IV characteristics for the same exemplary model resistors of Fig. Figure 3, where the current is shown as a function of |V1-V2| to account for the bidirectionality of the 100A field-plate reservoir. Characteristic curve 402 corresponds to the reservoir without the field plate, characteristic curve 404 corresponds to the 100A field-plate reservoir with the field plate 130 connected to the low-side terminal, and characteristic curve 406 corresponds to the 100A field-plate reservoir with the field plate 130 connected to the high-side terminal. Additionally, an "ideal" IV characteristic curve 408 with a zero voltage coefficient is included for visual reference. Each of the characteristic curves 402, 404, and 406 lies below the ideal characteristic curve 408, indicating that the resistance of these curves increases with increasing voltage across the reservoir 120 and thus exhibits a positive voltage coefficient.Characteristic curve 402 (without field plate) lies approximately midway between characteristic curve 404 (field plate connected to the low-side terminal) and characteristic curve 406 (field plate connected to the high-side terminal). Accordingly, it is obvious that the voltage coefficient of the p-type resistor tray 120 can be reduced by including the field plate 130, which is connected to the low-side terminal, and, if desired, increased by including the field plate 130, which is connected to the high-side terminal. It should be noted again that these effects are reversed for an n-type resistor tray, thus providing design flexibility to reduce or increase the voltage coefficient of a resistor tray as desired in different circuit configurations.Furthermore, it should be noted that modulation of the voltage coefficient can be carried out independently of the direction of current flow and the majority carrier type using the configuration of the field plate tub resistor 100B and an additional circuit arrangement to provide a defined bias voltage at the field plate 130.

[0021] Now on Fig. With reference to section 5, a flowchart of an exemplary process 500 for the manufacture of a field plate slab resistor corresponding to the field plate slab resistor 100A is presented. Fig. 6A-6M are cross-sectional views that illustrate the different manufacturing stages of the process of Fig. 5 show, and are simultaneously with Fig. 5. Although they are shown sequentially for convenience, at least some of the actions shown can be performed in a different order and / or in parallel. Furthermore, some implementations can only perform some of the actions shown.

[0022] Block 502 provides a semiconductor substrate 101. Fig. Figure 6A shows the field-plate dish resistor 100A in an early manufacturing stage. The semiconductor substrate 101 can include a handle layer 105, a buried oxide (BOX) layer 110, and an epitaxial layer 115. The handle layer 105 can be bulk silicon or another semiconductor material. The BOX layer 110, which can be omitted in some examples, can be part of a silicon-on-insulator (SOI) substrate. Although the epitaxial layer 115 in the illustrated example is lightly doped p-type silicon (active silicon), the handle layer 105 and the epitaxial layer 115 can be any other combination of n-type or p-type material.

[0023] In block 504, an insulating trench structure 165 (e.g., a deep trench insulator) is etched around a region of the semiconductor substrate 101. The insulating trench structure 165 includes a trench in the semiconductor substrate 101. The trench may be lined or filled with a dielectric material, such as silicon dioxide. In some examples, the dielectric material may be filled with a conductor, such as polysilicon. If the substrate is an SOI substrate, the insulating trench structure 165 may be, as in Fig. Figure 6B illustrates that the BOX layer 110 touches and thereby electrically isolates the resistance well 120 from other devices sharing the substrate 101. Similarly, in examples involving a buried insulation layer, such as a buried n-type layer, the insulation trench can contain n-type polysilicon, thus isolating the resistance well 120 by a barrier layer insulation.

[0024] In block 506, an insulating layer 125 (e.g., an STI oxide, LOCOS, or nitride layer) is formed on the epitaxial layer 15. Chemical vapor deposition or thermal oxidation processes can be used to deposit the insulating layer. Fig. Figure 6B shows the insulating layer 125, which is provided on the epitaxial layer 115. The insulating layer 125 can be structured to provide access to the epitaxial layer for connections of the resistance tray to be formed.

[0025] In block 508, a resistive well 120 is formed within the enclosed region of the semiconductor substrate 101. The resistive well 120 can be formed by doping a well region of the semiconductor substrate 101 with a selected dopant. For example, a p-type dopant (e.g., boron) can be deposited onto a well region of the semiconductor substrate 102, where the semiconductor substrate 102 is of either n-type or p-type. Fig. Figure 6C shows the resistance well 120 in the semiconductor substrate 101. The resistance well 120 includes a first terminal 145A and a second terminal 145B, which pass through the insulating layer 125.

[0026] In block 508, an insulating trench structure 165 (e.g., a deep trench insulator) is etched around the resistor well 120. The insulating trench structure 165 comprises a trench in the semiconductor substrate 101 surrounding the resistor well 120. The trench may be lined or filled with a dielectric material, such as silicon dioxide. In some examples, the dielectric material may be filled with a conductor, such as polysilicon. If the substrate is an SOI substrate, the insulating trench structure 165 may be, as in Fig. Figure 6D illustrates that the BOX layer 110 touches and thereby electrically isolates the resistance well 120 from other devices sharing the substrate 101. Similarly, in examples involving a buried insulation layer, such as a buried n-type layer, the insulation trench can contain n-type polysilicon, thus isolating the resistance well 120 by a barrier layer insulation.

[0027] In block 510, a polysilicon layer 602 is deposited onto the insulating layer 125. The polysilicon layer 602 can be deposited using chemical vapor deposition (CVD). Fig. Figure 6E shows the polysilicon layer 602 on the insulating layer 125.

[0028] In block 512, the polysilicon layer 602 is structured and etched to form the field plate 130. The field plate 130 is located above the resistance tray 120 and is insulated from the resistance tray 120 by the insulating layer 125.

[0029] In block 514, sidewall spacers can be formed on the sides of the field plate 130, for example by first forming a conformal CVD silicon nitride layer over the field plate 130, then forming a CVD silicon oxide layer over the silicon nitride layer, and then performing a full-surface back-etching of the silicon nitride and silicon oxide layers. Fig. Figure 6G shows the resulting unreferenced sidewall spacer 604 on the sides of the field plate 130.

[0030] In block 516, a silicide layer 135 is formed on the field plate 130. The silicide layer can be formed by depositing a metal layer (e.g., titanium, tungsten, or cobalt) on the field plate 130 and annealing to form the silicide layer 135. Fig. 6H shows the silicide layer 135 on the field plate 130.

[0031] In block 518, a dielectric layer 606 is deposited on the field plate 130 and the insulating layer 125. The dielectric layer 606 can comprise an oxide, a nitride, or another insulating material. The dielectric layer 606 can be deposited by chemical vapor deposition, physical vapor deposition, or other deposition techniques. Fig. Figure 6I shows the dielectric layer 606 on the field plate 130 and the insulating layer 125.

[0032] In block 520, the dielectric layer 606 is etched to create passages through the dielectric layer 606 to terminals 145A and 145B and the field plate 130. The passages can be etched using a dry etching process. Fig. 6J shows the passages etched through the dielectric layer 606 to terminals 145A and 145B and the field plate 130.

[0033] In block 522, conductive material is deposited into the passages etched in block 520 to form the vertical intermediate connections 140, 142, and 144. The conductive material may include tungsten, copper, aluminum, or another material and may be deposited by physical vapor deposition, chemical vapor deposition, or other deposition techniques. Fig. 6K shows the vertical intermediate connections 140, 142 and 144.

[0034] In block 524, a layer of conductive material (e.g., a first metal layer (M1)) is deposited onto the dielectric layer 606. The conductive material can be copper, aluminum, or another conductive material. The conductive layer is etched to form the horizontal connections 150 and 155 in the first metal layer (M1). The horizontal connection 150 connects the field plate 130 and terminal 145 of the resistance tray 120 via the vertical connections 140 and 142. The horizontal connection 155 is connected to terminal 145B of the resistance tray 120 via the vertical connection 144. Fig. 6L shows the horizontal intermediate connections 150 and 155.

[0035] In block 526, additional insulating layers can be deposited over the dielectric layer 606 to complete the insulating layers 160, and additional intermediate connections can be formed within the insulating layers 160. For example, shows Fig. 6M non-referenced vertical connections and non-referenced horizontal connections of a second metal layer (M2). Such connections can be used to connect the 100A field plate junction resistor to other components of the integrated circuit.

[0036] Fig. Figure 7 is a side cross-sectional view of an integrated circuit 700. The integrated circuit 700 includes the field-plate well resistor 100A and a transistor 702. In practice, the integrated circuit 700 can include any number of transistors and other components in addition to the field-plate well resistor 100A. In some examples, the transistor 702 can include a p-well 710, the p-well 710 being located within an n-well 705 formed in the epitaxial layer 115. One terminal (e.g., drain or source) of the transistor 702 is conductively coupled to a terminal of the field-plate well resistor 100A via a horizontal intermediate 715, while in other examples, a gate electrode of the transistor 702 can be conductively coupled to one of the terminals of the resistor 100A.In some examples, another transistor or other device can be coupled to the field plate slab resistor 100A via the horizontal intermediate connection 150.

[0037] Fig.Figure 8 is a circuit diagram of an example driver circuit 800. The driver circuit 800 includes the field-plate resistor 802, a high-side transistor 804, a transistor 806, and a driver control circuit 808. The field-plate resistor 802 includes a field plate 810. The field-plate resistor 100A can be an example of the field-plate resistor 802, and the field plate 130 can be an example of the field plate 810. In the illustrated example, the field plate 810 is conductively connected to the drain of the transistor 806 (low-side of the resistor 802), but in other examples, the field plate 810 can be conductively connected to the drain of the transistor 804 (high-side of the resistor 802). The 806 transistor can be an n-channel field-effect transistor (NFET), and the 804 transistor can be a p-channel field-effect transistor (PFET). The 702 transistor can be an example of either the 804 or the 806 transistor.The field-plate resistor 802 is coupled between a current terminal (e.g., drain) of transistor 804 and a current terminal (e.g., drain) of transistor 806. An output signal from the driver circuit 800 is provided at node 812, which connects the field-plate resistor 802 to the current terminal of transistor 804. The driver control circuit 808 is coupled to the control inputs (e.g., gate) of transistor 804 and transistor 806. The driver control circuit 808 generates pulses that control the switching of transistor 804 and transistor 806. In some examples, node 812 may be coupled to an ultrasonic transducer.

[0038] In some implementations of the 800 driver circuit, transistor 804 can be a drain-expanded p-type metal-oxide-semiconductor (DEPMOS) transistor; and transistor 806 can be a laterally diffused metal-oxide-semiconductor (LDMOS) transistor. Transistor 806 can have a significantly lower on-resistance than transistor 804. The field-plate dish resistor 100 is coupled between transistor 806 and transistor 804 to provide matching of the pull-up and pull-down currents when transistors 806 and 804 are biased in the linear region. Accordingly, field-plate dish resistor 802 is on the pull-down side of node 812. Matching the pull-up and pull-down currents reduces distortion.The low voltage coefficient of the field plate dish resistor 802 reduces distortion and power loss in the field plate dish resistor 802, which improves the performance of the driver circuit 800.

[0039] The same reference numbers or other reference symbols are used in the drawings to denote the same or similar features (regarding function and / or structure).

[0040] In this description, the term "couple" can encompass connections, communications, or signal paths that enable a functional relationship corresponding to this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intermediary component C, provided that the intermediary component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0041] Furthermore, in this description, the use of "based on" means "at least partially based on". Therefore, if X is based on Y, then X can be a function of Y and any number of other factors.

[0042] A device "designed" to perform a task or function can be designed (e.g., programmed and / or hardwired) by a manufacturer to perform that function at a point during its manufacture, and / or it can be configured (or reconfigured) by a user after its manufacture to perform that function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and circuitry, or a combination thereof.

[0043] As used herein, the terms "terminal," "node," "connection," "pin," and "conduit" are used interchangeably. Unless expressly stated otherwise, these terms are generally used to denote a connection between, or an endpoint of, a device element, circuit element, integrated circuit, appliance, other electronics, or other semiconductor component.

[0044] A circuit or device that, according to the present description, includes certain components, may instead be designed to couple with these components to form the described circuit arrangement or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead only include the semiconductor elements within a single physical device (e.g., a circuit board, a power supply, or a power supply).a semiconductor die and / or an IC package (IC, integrated circuit)) and may be designed to be coupled with at least some of the passive elements and / or sources to form the described structure either at the time of manufacture or after a time of manufacture, for example by an end user and / or a third party.

[0045] While the use of specific transistors is described here, other transistors (or equivalent devices) can be used instead with little or no change to the rest of the circuit design. For example, a field-effect transistor (“FET”) (such as an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT – e.g., an NPN or PNP transistor), insulated-gate bipolar transistors (IGBTs), and / or a junction field-effect transistor (JFET) can be used instead of, or in conjunction with, the devices described here. The transistors can be depletion-mode devices, drain-expanded devices, enhancement-mode devices, natural transistors, or other types of device-structure transistors.Furthermore, the devices can be implemented in / over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

[0046] The claims may refer to the control input of a transistor and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and the source. In the context of a BJT, the control input is the base, and the current terminals are the collector and the emitter.

[0047] References herein to a FET being "turned on" mean that the FET's conduction channel is present and drain current can flow through the FET. References herein to a FET being "turned off" mean that the conduction channel is not present and no drain current flows through the FET. However, current can still flow through the transistor's body diode in a "turned-off" FET.

[0048] The circuits described here are reconfigurable to include additional or different components to provide functionality at least partially similar to that available before the component exchange. Unless otherwise specified, components shown as resistors generally represent one or more elements connected in series and / or parallel to provide an impedance value represented by the resistor shown. For example, a resistor or capacitor shown and described here as a single component may instead be multiple resistors or capacitors connected in parallel between the same nodes.These are capacitors that are connected in series between the same two nodes as the single resistor or capacitor.

[0049] While certain elements of the described examples are contained within an integrated circuit and other elements are located outside the integrated circuit, in other embodiments additional or fewer features may be integrated within the integrated circuit. Furthermore, some or all of the features shown to be external to the integrated circuit may be contained within the integrated circuit, and / or some features shown to be internal to the integrated circuit may be integrated outside the integrated circuit. As used herein, the term “integrated circuit” means one or more circuits that are: (i) integrated in / over a semiconductor substrate; (ii) integrated within a single semiconductor package; (iii) integrated within the same module; and / or (iv) integrated in / on the same printed circuit board.

[0050] Within the scope of protection of the claims, modifications of the described embodiments as well as other embodiments are possible.

Claims

[1] Semiconductor device comprising: a semiconductor substrate; a tray resistor in the semiconductor substrate; a field plate above the tank resistor; and an insulator between the tank resistor and the field plate. [2] Semiconductor device according to claim 1, wherein: The tank resistor includes a first connection and a second connection; and The field plate is conductively connected to the first terminal or the second terminal. [3] Semiconductor device according to claim 2, wherein: the tray resistor is a p-type resistor; the second connection is designed to receive current from a power source; and The field plate is conductively connected to the first terminal. [4] Semiconductor device according to claim 2, wherein: the tray resistor is an n-type resistor; the first connection is a connection with a higher voltage; the second terminal is a terminal with a lower voltage; and the field plate is connected to the first connection. [5] Semiconductor device according to claim 1, wherein the field plate comprises a polysilicon layer. [6] Semiconductor device according to claim 1, wherein the field plate comprises a metal interleaving layer. [7] Semiconductor device according to claim 1, further comprising an insulation trench in the semiconductor substrate around the tray resistor. [8] Semiconductor device according to claim 1, wherein the field plate is connected to a voltage source designed to bias the field plate independently of any voltage at terminals of the tray resistor. [9] Integrated circuit comprising: a resistor tray extending into a semiconductor substrate; a dielectric layer extending into the resistor tray; and a conductive field plate located above the dielectric layer, wherein the conductive field plate is designed to modulate a majority carrier distribution within the resistive well while the resistive well conducts a current. [10] Integrated circuit according to claim 9, wherein: the resistance tray is of the p-type; the conductive field plate is conductively connected to a low-side terminal of the resistance tray; and The conductive field plate is designed to reduce the voltage coefficient of the resistance tray. [11] Integrated circuit according to claim 9, wherein: the resistance tray is of the n-type; the conductive field plate is coupled to a high-side connection of the resistance tray; and The conductive field plate is designed to reduce the voltage coefficient of the resistance tray. [12] Integrated circuit according to claim 9, wherein the conductive field plate includes a polysilicon layer. [13] Integrated circuit according to claim 9, further comprising an insulation trench that electrically isolates the resistance tray from the substrate. [14] Integrated circuit according to claim 9, wherein the conductive field plate is designed to increase a voltage coefficient of the resistance tray. [15] Procedures, including: Forming an insulating layer on a semiconductor substrate; Doping a resistive well extending into the semiconductor substrate below the insulating layer; Deposition of a layer of conductive material, spaced apart from the resistance tray by the insulating layer; and Etching of the conductive material to form a field plate above the resistance tray. [16] Method according to claim 15, wherein the conductive material comprises polysilicon. [17] Method according to claim 15, wherein the conductive material is metal and the layer is an intermediate compound layer. [18] Method according to claim 15, further comprising conductively connecting the field plate to the resistance tray. [19] Method according to claim 15, further comprising forming a first and a second terminal which are connected to the resistance tray, wherein the first terminal is designed to have a higher voltage than the second terminal when conducting a current, and wherein the field plate is conductively connected to the second terminal. [20] Method according to claim 15, further comprising forming a first and a second terminal which are connected to the resistor tray, and connecting the first or the second terminal to a terminal of a transistor which is formed above the semiconductor substrate.

Images