ARRAY SUBSTRATE AND DISPLAY DEVICE

Abstract

An array substrate is provided. The array substrate comprises a plurality of pixel driver circuits. Each pixel driver circuit within the plurality of pixel driver circuits comprises a driver transistor, a light-shielding element, and a node interconnect. An orthographic projection of the light-shielding element onto a base substrate essentially covers an orthographic projection of an active layer of the driver transistor onto the base substrate. The light-shielding element is electrically connected to a gate electrode of the driver transistor via the node interconnect. The light-shielding element, the node interconnect, and the gate electrode of the driver transistor are located in three different layers.

Description

TECHNICAL AREA

[0001] The present invention relates to the display technology, in particular an array substrate and a display device. STATE OF THE ART

[0002] Organic light-emitting diode (OLED) displays are currently a hotspot in flat panel display research. Unlike thin-film transistor liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a drive current that must be kept constant to control the illuminance. The OLED display array comprises numerous pixel units configured with pixel driver circuits arranged in multiple rows and columns. Each pixel driver circuit includes a driver transistor with a gate terminal connected to one gate line per row and a drain terminal connected to one data line per column.When the line containing the pixel unit is switched on, a switching transistor connected to the driver transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driver transistor. This causes the driver transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is thus driven to emit light at the appropriate brightness. REVELATION OF THE INVENTION

[0003] In one aspect, the present disclosure provides an array substrate comprising a plurality of pixel driver circuits; wherein each pixel driver circuit of the plurality of pixel driver circuits comprises a driver transistor, a light-shielding element, and a node interconnect; wherein an orthographic projection of the light-shielding element onto a base substrate essentially covers an orthographic projection of an active layer of the driver transistor onto the base substrate; wherein the light-shielding element is electrically connected to a gate electrode of the driver transistor via the node interconnect; wherein the light-shielding element, the node interconnect, and the gate electrode of the driver transistor are located in three different layers.

[0004] Optionally, the respective pixel driver circuit also includes a first reset transistor; wherein the light shielding element is electrically connected to a second electrode of the first reset transistor via the node connection line.

[0005] Optionally, the respective pixel driver circuit further includes a storage capacitor; wherein the orthographic projection of the light-shielding element on the base substrate essentially covers an orthographic projection of a gate electrode of the driver transistor on the base substrate and essentially covers an orthographic projection of a second capacitor electrode of the storage capacitor on the base substrate.

[0006] Optionally, the array substrate further comprises a plurality of third power supply lines; wherein each pixel driver circuit further comprises a light emission control transistor and a second reset transistor; wherein an orthographic projection of each third power supply line of the plurality of third power supply lines on the base substrate essentially covers an orthographic projection of an active layer of the light emission control transistor in the respective pixel driver circuit on the base substrate, essentially covers an orthographic projection of an active layer of the second reset transistor on the base substrate, and overlaps at least partially with the orthographic projection of the active layer of the driver transistor on the base substrate.

[0007] Optionally, the orthographic projection of each third power supply line of the plurality of third power supply lines on the base substrate essentially covers an orthographic projection of a combination of an active layer, a first electrode and a second electrode of the light emission control transistor in the respective pixel driver circuit on the base substrate; essentially covers an orthographic projection of a combination of an active layer, a first electrode and a second electrode of the second reset transistor on the base substrate; essentially covers an orthographic projection of a combination of a first electrode and a second electrode of the driver transistor on the base substrate; and overlaps at least partially with an orthographic projection of an active layer of the driver transistor on the base substrate.

[0008] Optionally, the array substrate further comprises a plurality of fourth power supply lines; wherein each pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein in a first column of pixel driver circuits, an orthographic projection of each fourth power supply line of the plurality of fourth power supply lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in each pixel driver circuit in the first column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in each pixel driver circuit in the first column of pixel driver circuits on the base substrate.

[0009] Optionally, in the first column of pixel driver circuits, the orthographic projection of a respective fourth power supply line of the multitude of fourth power supply lines on the base substrate essentially covers an orthographic projection of a combination of an active layer, a first electrode and a second electrode of the first reset transistor in the first respective pixel driver circuit in the first column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of a combination of an active layer and a second electrode of the data write transistor in the first respective pixel driver circuit in the first column of pixel driver circuits on the base substrate.

[0010] Optionally, the array substrate further comprises a plurality of fourth reset signal lines; wherein each pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein in a second column of pixel driver circuits, an orthographic projection of each fourth reset signal line of the plurality of fourth reset signal lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate.

[0011] Optionally, in the second column of pixel driver circuits, the orthographic projection of a respective fourth reset signal line of the plurality of fourth reset signal lines on the base substrate essentially covers an orthographic projection of a combination of an active layer, a first electrode and a second electrode of the first reset transistor in the second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate; and essentially covers an orthographic projection of a combination of an active layer and a second electrode of the data write transistor in the second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate.

[0012] Optionally, the array substrate further comprises a plurality of third reset signal lines; wherein each pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein in a third column of pixel driver circuits, an orthographic projection of a respective third reset signal line of the plurality of third reset signal lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a third respective pixel driver circuit in the third column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the third respective pixel driver circuit in the third column of pixel driver circuits on the base substrate.

[0013] Optionally, in the third column of pixel driver circuits, the orthographic projection of a respective third reset signal line of the plurality of third reset signal lines on the base substrate essentially covers an orthographic projection of a combination of an active layer, a first electrode and a second electrode of the first reset transistor in the third respective pixel driver circuit in the third column of pixel driver circuits on the base substrate; and essentially covers an orthographic projection of a combination of an active layer and a second electrode of the data write transistor in the third respective pixel driver circuit in the third column of pixel driver circuits on the base substrate.

[0014] Optionally, the array substrate further comprises a plurality of fourth power supply lines; wherein each pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein the pixel driver circuits of the array substrate are arranged in columns comprising a (3k-2)th column, a (3k-1)th column and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3);wherein in the (3k-2)th column of pixel driver circuits an orthographic projection of a respective fourth power supply line of the plurality of fourth power supply lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a first respective pixel driver circuit in the (3k-2)th column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the first respective pixel driver circuit in the (3k-2)th column of pixel driver circuits on the base substrate.;

[0015] Optionally, the array substrate further comprises a plurality of fourth reset signal lines; wherein each pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein the pixel driver circuits of the array substrate are arranged in columns comprising a (3k-2)th column, a (3k-1)th column and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3);wherein in the (3k-1)th column of pixel driver circuits an orthographic projection of a respective fourth reset signal line of the plurality of fourth reset signal lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a second respective pixel driver circuit in the (3k-1)th column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the second respective pixel driver circuit in the (3k-1)th column of pixel driver circuits on the base substrate.;

[0016] Optionally, the array substrate further comprises a plurality of third reset signal lines; wherein each pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein the pixel driver circuits of the array substrate are arranged in columns comprising a (3k-2)th column, a (3k-1)th column and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3);wherein in the (3k)th column of pixel driver circuits an orthographic projection of a respective third reset signal line of the plurality of third reset signal lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a third respective pixel driver circuit in the (3k)th column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the third respective pixel driver circuit in the (3k)th column of pixel driver circuits on the base substrate.;

[0017] Optionally, the array substrate further comprises a plurality of fourth power supply lines, a plurality of fourth reset signal lines, and a plurality of third reset signal lines located in the same layer; wherein the pixel driver circuits of the array substrate are arranged in columns comprising a (3k-2)th column, a (3k-1)th column, and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); wherein the (3k-2)th column comprises a fourth power supply line of the plurality of fourth power supply lines; wherein the (3k-1)th column comprises a fourth reset signal line of the plurality of fourth reset signal lines; and wherein the (3k)th column comprises a third reset signal line of the plurality of third reset signal lines.

[0018] Optionally, the plurality of fourth power supply lines is not present in the (3k - 1)th column and is not present in the (3k)th column; wherein the plurality of fourth reset signal lines is not present in the (3k-2)th column and is not present in the (3k)th column; and wherein the plurality of third reset signal lines is not present in the (3k-2)th column and is not present in the (3k-1)th column.

[0019] Optionally, the array substrate further comprises a first power supply network and a second power supply network; wherein the first power supply network comprises a plurality of first power supply lines and a plurality of third power supply lines interconnected; the plurality of first power supply lines running in a direction substantially parallel to a first direction; the plurality of third power supply lines running in a direction substantially parallel to a second direction; each first power supply line of the plurality of first power supply lines is connected to one or more third power supply lines of the plurality of third power supply lines;a respective third voltage supply line of the plurality of third voltage supply lines is connected to one or more first voltage supply lines of the plurality of first voltage supply lines; and wherein the second voltage supply network comprises a plurality of second voltage supply lines and a plurality of fourth voltage supply lines connected to one another; the plurality of second voltage supply lines runs in a direction substantially parallel to the first direction; the plurality of fourth voltage supply lines runs in a direction substantially parallel to the second direction; a respective second voltage supply line of the plurality of second voltage supply lines is connected to one or more fourth voltage supply lines of the plurality of fourth voltage supply lines;and each fourth power supply line of the plurality of fourth power supply lines is connected to one or more second power supply lines of the plurality of second power supply lines; wherein the pixel driver circuits of the array substrate are arranged in columns comprising a (3k-2)th column, a (3k-1)th column, and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); the plurality of third power supply lines is present in the (3k-2)th column, in the (3k-1)th column, and in the (3k)th column; the plurality of fourth power supply lines is not present in the (3k-1)th column and is not present in the (3k)th column.

[0020] Optionally, the array substrate further comprises a first reset signal network; wherein the first reset signal network comprises a plurality of first reset signal lines and a plurality of third reset signal lines interconnected; the plurality of first reset signal lines running in a direction substantially parallel to a first direction; the plurality of third reset signal lines running in a direction substantially parallel to a second direction; each first reset signal line of the plurality of first reset signal lines is connected to one or more third reset signal lines of the plurality of third reset signal lines; and each third reset signal line of the plurality of third reset signal lines is connected to one or more first reset signal lines of the plurality of first reset signal lines;wherein the pixel driver circuits of the array substrate are arranged in columns that are a (3k-2)th column, a (3k-1)th column and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); and the plurality of third reset signal lines is not present in the (3k-2)th column and is not present in the (3k-1)th column.;

[0021] Optionally, the array substrate further comprises a second reset signal network; wherein the second reset signal network comprises a plurality of second reset signal lines and a plurality of fourth reset signal lines interconnected; the plurality of second reset signal lines running in a direction substantially parallel to a first direction; the plurality of fourth reset signal lines running in a direction substantially parallel to a second direction; each second reset signal line of the plurality of second reset signal lines is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines; and each fourth reset signal line of the plurality of fourth reset signal lines is connected to one or more second reset signal lines of the plurality of second reset signal lines;wherein the pixel driver circuits of the array substrate are arranged in columns comprising a (3k-2)th column, a (3k-1)th column, and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); and the plurality of fourth reset signal lines is not present in the (3k-2)th column and is not present in the (3k)th column.

[0022] In another aspect, the present disclosure provides a display device comprising the array substrate described herein and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings serve only as examples for illustration and are not intended to limit the scope of the invention. Fig. Figure 1 is a top view of an array substrate in some embodiments according to the present disclosure. Fig. Figure 2A is a circuit diagram illustrating the structure of a pixel driver circuit in some embodiments according to the present disclosure. Fig. Figure 2B is a timing diagram illustrating the operation of a pixel driver circuit in some embodiments according to the present disclosure. Fig. Figure 3A is a schematic diagram illustrating the structure of part of an array substrate in some embodiments according to the present disclosure. Fig. 3B is a schematic diagram showing the arrangement of several pixel driver circuits in a portion of the array substrate as shown in Fig. 3A is illustrated. Fig. 3C is a schematic diagram showing the structure of a light-shielding layer in a part of the array substrate as in Fig. 3A is illustrated. Fig. 3D is a schematic diagram showing the structure of a first conductive layer in a portion of the array substrate, as in Fig. 3A is illustrated. Fig. 3E is a schematic diagram showing the structure of a first gate insulating layer in a portion of the array substrate as shown in Fig. 3A is illustrated. Fig. 3F is a schematic diagram showing the structure of a semiconductor material layer in a portion of the array substrate as shown in Fig. 3A is illustrated. Fig. 3G is a schematic diagram showing the structure of a second conductive layer in a part of the array substrate as in Fig. 3A is illustrated. Fig. 3H is a schematic diagram showing the structure of a passivation layer in a part of the array substrate as in Fig. 3A is illustrated. Fig. 3A 3I is a schematic diagram showing the structure of a first signal transmission layer in a part of the array substrate as shown in Fig. 3A is illustrated. Fig. 3J is a schematic diagram showing the structure of a first planarization layer in a portion of the array substrate as in Fig. 3A is illustrated. Fig. 3K a schematic diagram showing the structure of a second signal transmission layer in a part of the array substrate as in Fig. 3A is illustrated. Fig. 3L a schematic diagram showing the structure of a second planarization layer in a part of the array substrate as in Fig. 3A is illustrated. Fig. 4A is a cross-sectional view along line AA' in Fig. 3A. Fig. 4B is a cross-sectional view along line BB' in Fig. 3A. Fig. Figure 5 is a schematic diagram illustrating the structure of a first power supply network in a part of an array substrate in some embodiments according to the present disclosure. Fig. Figure 6 is a schematic diagram illustrating the structure of a second power supply network in a part of an array substrate in some embodiments according to the present disclosure. Fig. Figure 7 is a schematic diagram illustrating the structure of a first reset signal network in a part of an array substrate in some embodiments according to the present disclosure. Fig. Figure 8 is a schematic diagram illustrating the structure of a second reset signal network in a part of an array substrate in some embodiments according to the present disclosure. Fig. Figure 9 is a schematic diagram showing the structure of a semiconductor material layer and a second signal transmission layer in a portion of the array substrate as shown in Fig. 3A is illustrated. FORMS OF EXECUTION OF THE INVENTION

[0024] The disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following descriptions of some of the embodiments presented here serve only for illustration and description. They are not exhaustive or limited to the exact disclosed form.

[0025] The present disclosure provides, in particular, an array substrate and a display device that substantially overcome one or more of the problems caused by limitations and disadvantages of the prior art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate comprises a plurality of pixel driver circuits. Optionally, each pixel driver circuit of the plurality of pixel driver circuits comprises a driver transistor, a light-shielding element, and a node connection line. Optionally, an orthographic projection of the light-shielding element onto a base substrate essentially covers an orthographic projection of an active layer of the driver transistor onto the base substrate. Optionally, the light-shielding element is electrically connected to a gate electrode of the driver transistor via the node connection line.Optionally, the light shielding element, the node connection line and the gate electrode of the driver transistor are located in three different layers.

[0026] Various suitable pixel driver circuits can be used in the array substrate described in this disclosure. Examples of suitable driver circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, a particular pixel driver circuit from the plurality of pixel driver circuits is a 5T1C driver circuit. In some embodiments, a particular pixel driver circuit from the plurality of pixel driver circuits is a 5T2C driver circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes, and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode.Optionally, the light-emitting element is an organic light-emitting diode with an organic luminescent layer.

[0027] Fig. Figure 1 is a top view of an array substrate in some embodiments according to the present disclosure. With reference to Fig. 1. The array substrate comprises an array of subpixels Sp. Each subpixel contains an electronic component, e.g., a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driver circuit PDC. The array substrate comprises a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power supply lines Vdd (e.g., a plurality of first power supply lines or a plurality of third power supply lines). Each subpixel Sp is driven by a corresponding pixel driver circuit PDC to emit light. In one example, a high-voltage signal (e.g., a VDD signal) is input via a corresponding power supply line of the plurality of power supply lines Vdd into the corresponding pixel driver circuit PDC, which is connected to an anode of the light-emitting element; a low-voltage signal (e.g.,A high-voltage signal (e.g., a VSS signal) is applied to the cathode of the light-emitting element via a low-voltage supply line. A voltage difference between the high-voltage signal (e.g., the VDD signal) and the low-voltage signal (e.g., the VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0028] Fig. Figure 2A is a circuit diagram illustrating the structure of a pixel driver circuit in some embodiments according to the present disclosure. With reference to Fig. 2A In some embodiments, the pixel driver circuit comprises a driver transistor Td; a storage capacitor Cst with a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a data write transistor Tw, which has a gate electrode connected to a corresponding gate line GL of the plurality of gate lines, a first electrode connected to a corresponding data line DL of the plurality of data lines and a second electrode connected to the gate electrode of the driver transistor Td;a first reset transistor Tr1, which has a gate electrode connected to a corresponding first reset control signal line of a plurality of first reset control signal lines rst1, a first electrode connected to a corresponding first reset signal line of a plurality of first reset signal lines Vint1 and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst, the second electrode of the data write transistor Tw and the gate electrode of the driver transistor Td;a second reset transistor Tr2, comprising a gate electrode connected to a second reset control signal line of a plurality of second reset control signal lines rst2, a first electrode connected to a corresponding second reset signal line of a plurality of second reset signal lines Vint2, and a second electrode connected to the second electrode of the driver transistor, the second capacitor electrode Ce2 of the storage capacitor Cst, and an anode of a corresponding light-emitting element LE;and a light emission control transistor Te, comprising a gate electrode connected to a corresponding light emission control signal line from a plurality of light emission control signal lines em, a first electrode connected to a corresponding voltage supply line from a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driver transistor Td.

[0029] The pixel driver circuit further comprises a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the gate electrode of the driver transistor Td, the first capacitor electrode Ce1, the second electrode of the data write transistor Tw, and the second electrode of the first reset transistor Tr1. The second node N2 is connected to the second electrode of the driver transistor Td, the second electrode of the second reset transistor Tr2, the second capacitor electrode Ce2 of the storage capacitor Cst, and the anode of the corresponding light-emitting element LE. The third node N3 is connected to the second electrode of the light-emitting control transistor Te and the first electrode of the driver transistor Td.

[0030] As used here, a first electrode or a second electrode refers to a first terminal and a second terminal of a transistor, the first terminal and the second terminal being connected to an active layer of the transistor. The direction of any current flowing through the transistor can be configured to flow from a first electrode to a second electrode or from a second electrode to a first electrode. Depending on the direction of the current flowing through the transistor, in one example the first electrode is configured to receive an input signal, and the second electrode is configured to output a signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output a signal.

[0031] Fig. 2B is a timing diagram illustrating the operation of a pixel driver circuit in some embodiments according to the present disclosure. With reference to Fig. 2A and Fig. 2B, the operation of the pixel driver circuit during a picture frame includes a reset sub-phase t1, a compensation sub-phase t2, a data write sub-phase t3 and a light emission sub-phase t4.

[0032] In the reset subphase t1, a turn-on reset control signal is provided via the respective first reset control signal line of the plurality of first reset control signal lines rst1 to the gate electrode of the first reset transistor Tr1 to turn on the first reset transistor Tr1; so that an initialization voltage signal from the respective first reset signal line of the plurality of first reset signal lines Vint1 is transmitted from a first electrode of the first reset transistor Tr1 to a second electrode of the first reset transistor Tr1 and then to the first capacitor electrode Ce1, the gate electrode of the driver transistor Td and the node N1. The gate electrode of the driver transistor Td is initialized.A turn-on / reset control signal is provided via the respective second reset control signal line of the plurality of second reset control signal lines rst2 to the gate electrode of the second reset transistor Tr2 to turn on the second reset transistor Tr2; so that an initialization voltage signal is transmitted from the respective second reset signal line of the plurality of second reset signal lines Vint2 from a first electrode of the second reset transistor Tr2 to a second electrode of the second reset transistor Tr2; and then transmitted to node N2. The anode of the light-emitting element LE is initialized.

[0033] In the compensation subphase t2, a switch-on light emission control signal is provided via the respective light emission control signal line of the multitude of light emission control signal lines to the gate electrode of the light emission control transistor Te in order to switch on the light emission control transistor Te. The second electrode of the driver transistor Td (e.g., the one in Fig. 2A (N2 node shown) is charged until the voltage level at the second electrode of the driver transistor Td reaches the level of a reset signal provided by the respective first reset signal line of the plurality of first reset signal lines Vint1, minus the voltage level of the threshold voltage Vth of the driver transistor Td.

[0034] In the data write subphase t3, a turn-on gate scan signal is provided via the respective gate line of the plurality of gate lines GL to the gate electrode of the data write transistor Tw to turn on the data write transistor Tw, so that a data signal is transferred from the first electrode of the data write transistor Tw to the second electrode of the data write transistor Tw and then to node N1. A voltage level at the gate electrode of the driver transistor Td reaches the voltage level of the data signal written to the gate electrode of the driver transistor Td. The value of the capacitance of the storage capacitor Cst is significantly lower than the capacitance of the parasitic capacitance between the cathode of the light-emitting element and the second capacitor electrode Ce2.Changing the voltage level at the gate electrode of the driver transistor Td has no effect on the voltage level at the second electrode of the driver transistor Td (e.g., node N2). The voltage level at the second electrode of the driver transistor Td remains at the level of the reset signal provided by the respective first reset signal line of the plurality of first reset signal lines Vint1, minus the voltage level of the threshold voltage Vth of the driver transistor Td.

[0035] In the light emission subphase t4, a switch-on light emission control signal is provided via the respective light emission control signal line of the plurality of light emission control signal lines em to the gate electrode of the light emission control transistor Te in order to switch on the light emission control transistor Te. In the light emission subphase t4, the driver transistor Td remains switched on. The light-emitting element emits light. The voltage level at node N2 becomes (Voled + Vss), where Voled represents the voltage level for driving the light-emitting element to emit light and Vss represents the voltage level at the cathode of the light-emitting element.The change in the voltage level at node N2 is thus (Voled + Vss - (Vint1 - Vth)), where Vint1 represents the level of the reset signal provided by the respective first reset signal line of the plurality of first reset signal lines Vint1, and Vth represents the voltage level of the threshold voltage Vth of the driver transistor Td. Due to the bootstrapping effect of the storage capacitor Cst, the voltage level at node N1 (the gate electrode of the driver transistor Td) becomes (Vdata + Vn2), where Vdata represents the voltage level of the data signal and Vn2 represents the change in the voltage level at node N2. The voltage level at node N1 is Vdata + Voled + Vss - Vint1 + Vth. The voltage difference Vgs between the gate electrode of the driver transistor Td and the second electrode is (Vdata - Vint1 + Vth). The driver current I flowing through the driver transistor correlates with (Vdata - Vint1). 2 .

[0036] The present disclosure can be implemented in a pixel driver circuit with transistors of various types, including a pixel driver circuit with p-type transistors, a pixel driver circuit with n-type transistors, and a pixel driver circuit with one or more p-type transistors and one or more n-type transistors. For a p-type transistor, an effective control signal (e.g., a turn-on control signal) is a low-voltage signal, and an ineffective control signal (e.g., a turn-off control signal) is a high-voltage signal. For an n-type transistor, an effective control signal (e.g., a turn-on control signal) is a high-voltage signal, and an ineffective control signal (e.g., a turn-off control signal) is a low-voltage signal. With reference to Fig. 2A, in some embodiments all transistors in the pixel driver circuit are n-type transistors, such as a metal oxide transistor.

[0037] In some embodiments, the array substrate comprises a plurality of subpixels. In some embodiments, the plurality of subpixels comprises a first subpixel, a second subpixel, and a third subpixel. Optionally, each pixel of the array substrate comprises the first subpixel, the second subpixel, and the third subpixel. The plurality of subpixels in the array substrate is arranged in an array. In one example, the array of the plurality of subpixels comprises a repeating array in the S1-S2-S3 format, where S1 represents the first subpixel, S2 the second subpixel, and S3 the third subpixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, where C1 represents the first subpixel of a first color, C2 the second subpixel of a second color, and C3 the third subpixel of a third color.In another example, the C1-C2-C3 format is an RGB format, where the first subpixel in each case is a red subpixel, the second subpixel in each case is a green subpixel, and the third subpixel in each case is a blue subpixel.

[0038] In another example, the array of multiple subpixels comprises a repeating array in the S1-S2-S3-S4 format, where S1 represents the first subpixel, S2 the second subpixel, S3 the third subpixel, and S4 the fourth subpixel. In yet another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents the first subpixel of a first color, C2 the second subpixel of a second color, C3 the third subpixel of a third color, and C4 the fourth subpixel of a fourth color. In a further example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents the first subpixel of a first color, C2 the second subpixel of a second color, C3 the third subpixel of a third color, and C2' the fourth subpixel of the second color.In another example, the C1-C2-C3-C2' format is an RGBG format, where the first subpixel in each case is a red subpixel, the second subpixel in each case is a green subpixel, the third subpixel in each case is a blue subpixel, and the fourth subpixel in each case is a green subpixel.

[0039] In some embodiments, a minimum repetition unit of the plurality of subpixels of the array substrate comprises a respective first subpixel, a respective second subpixel, and a respective third subpixel. Optionally, each of the respective first subpixels, the respective second subpixels, and the respective third subpixel comprises the data write transistor Tw, the first reset transistor Tr1, the second reset transistor Tr2, the light emission control transistor Te, the driver transistor Td, and the storage capacitor Cst.

[0040] In alternative embodiments, a minimum repetition unit of the plurality of subpixels of the array substrate comprises a respective first subpixel, a respective second subpixel, a respective third subpixel, and a respective fourth subpixel. Optionally, each of the respective first subpixel, the respective second subpixel, the respective third subpixel, and the respective fourth subpixel comprises the data write transistor Tw, the first reset transistor Tr1, the second reset transistor Tr2, the light emission control transistor Te, the driver transistor Td, and the storage capacitor Cst.

[0041] Fig. Figure 3A is a schematic diagram illustrating the structure of part of an array substrate in some embodiments according to the present disclosure. Fig. 3B is a schematic diagram showing the arrangement of the multitude of pixel driver circuits in a portion of the array substrate as shown in Fig. 3A is illustrated. Fig. 3A and Fig. 3B represents part of the array substrate with three pixel driver circuits (comprising PDC1, PDC2 and PDC3).

[0042] Fig. 3C is a schematic diagram showing the structure of a light-shielding layer in a part of the array substrate as in Fig. 3A is illustrated. Fig. 3D is a schematic diagram showing the structure of a first conductive layer in a portion of the array substrate, as in Fig. 3A is illustrated. Fig. 3E is a schematic diagram showing the structure of a first gate insulating layer in a portion of the array substrate as shown in Fig. 3A is illustrated. Fig. 3F is a schematic diagram showing the structure of a semiconductor material layer in a portion of the array substrate as shown in Fig. 3A is illustrated. Fig. 3G is a schematic diagram showing the structure of a second conductive layer in a part of the array substrate as in Fig. 3A is illustrated. Fig. 3H is a schematic diagram showing the structure of a passivation layer in a part of the array substrate as in Fig. 3A is illustrated. Fig. 3I is a schematic diagram showing the structure of a first signal transmission layer in a portion of the array substrate as shown in Fig. 3A is illustrated. Fig. 3J is a schematic diagram showing the structure of a first planarization layer in a portion of the array substrate as in Fig. 3A is illustrated. Fig. 3K is a schematic diagram showing the structure of a second signal transmission layer in a portion of the array substrate as shown in Fig. 3A is illustrated. Fig. 3L is a schematic diagram showing the structure of a second planarization layer in a portion of the array substrate as in Fig. 3A is illustrated. Fig. 4A is a cross-sectional view along line AA' in Fig. 3A. Fig. 4B is a cross-sectional view along line BB' in Fig. 3A.

[0043] With reference to Fig. 3A to Fig. 3L and Fig. 4A to Fig. 4B, in some embodiments, the array substrate comprises a base substrate BS; a light-shielding layer LSL located on the base substrate BS; an insulating layer IN located on a side of the light-shielding layer LSL facing away from the base substrate BS; a first conductive layer CT1 located on a side of the insulating layer IN facing away from the light-shielding layer LSL; a first gate insulating layer GI1 located on a side of the first conductive layer CT1 facing away from the insulating layer IN; a semiconductor material layer SML located on a side of the first gate insulating layer GI1 facing away from the first conductive layer CT1; a second gate insulating layer GI2 located on a side of the semiconductor material layer SML facing away from the first gate insulating layer GI1;a second conductive layer CT2 located on the side of the second gate insulating layer GI2 facing away from the semiconductor material layer SML; a passivation layer PVX located on the side of the second conductive layer CT2 facing away from the second gate insulating layer GI2; a first signal conduction layer SD1 located on the side of the passivation layer PVX facing away from the second conductive layer CT2; a first planarization layer PLN1 located on the side of the first signal conduction layer SD1 facing away from the passivation layer PVX; a second signal conduction layer SD2 located on the side of the first planarization layer PLN1 facing away from the first signal conduction layer SD1; and a second planarization layer PLN2 located on the side of the second signal conduction layer SD2 facing away from the first planarization layer PLN1.

[0044] With reference to Fig. 2A, Fig. 3A and Fig. In 3C, the light-shielding layer LSL comprises a light-shielding element LS in some embodiments. Various suitable materials and manufacturing processes can be used to produce the light-shielding layer LSL. For example, a metallic material can be deposited onto the substrate by plasma-enhanced chemical vapor deposition (PECVD). Examples of suitable metallic materials for producing the light-shielding layer LSL include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or laminates containing these materials.

[0045] In some embodiments, the array substrate comprises a plurality of light-shielding elements, each located within a plurality of pixel driver circuits. The plurality of light-shielding elements are spaced apart from one another.

[0046] In some embodiments, with reference to Fig. 2A, Fig. 3A, Fig. 3C and Fig. 4A, an orthographic projection of the light-shielding element LS on the base substrate BS substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of the active layer ACTd of the driver transistor Td on the base substrate BS. The inventors of the present disclosure have determined that this structure can protect and stabilize the active layer ACTd of the driver transistor Td from irradiation.

[0047] In some embodiments, the light-shielding element LS is electrically connected to the gate electrode of the driver transistor Td (e.g., the first capacitor electrode Ce1 of the storage capacitor Cst, which acts as the light-shielding element LS). Optionally, the light-shielding element LS is connected to the gate electrode of the driver transistor Td via a node connection line Cln located in the first signal transmission layer SD1. The inventors of the present disclosure have surprisingly and unexpectedly found that by electrically connecting the light-shielding element LS to the gate electrode of the driver transistor Td, the drive capability of the driver transistor Td at low gray levels can be significantly improved, thereby improving the performance of the driver transistor Td.

[0048] In some embodiments, the light shielding element LS is electrically connected to the second electrode Dr1 of the first reset transistor Tr1. Optionally, the light shielding element LS is connected to the second electrode Dr1 of the first reset transistor Tr1 via the node connection line Cln located in the first signal line layer SD1.

[0049] In some embodiments, an orthographic projection of the light shielding element LS on the base substrate BS substantially covers (e.g. at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of the gate electrode of the driver transistor Td on the base substrate BS.

[0050] In some embodiments, an orthographic projection of the light shielding element LS on the base substrate BS substantially covers (e.g. at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of the second capacitor electrode Ce2 of the storage capacitor Cst on the base substrate BS.

[0051] With reference to Fig. 2A, Fig. 3A and Fig. In some embodiments of the 3D device, the first conductive layer comprises a second capacitor electrode Ce2 of the storage capacitor Cst, a first gate electrode section Gw-1 of the gate electrode of the data write transistor Tw, a first gate electrode section Gr1-1 of the gate electrode of the first reset transistor Tr1, a first gate electrode section Gr2-1 of the gate electrode of the second reset transistor Tr2, and a first gate electrode section Ge-1 of the gate electrode of the light emission control transistor Te. Various suitable electrode materials and various suitable fabrication methods can be used to produce the first conductive layer. For example, a conductive material can be deposited and structured on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process.Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, and the like. Optionally, the second capacitor electrode Ce2 of the storage capacitor Cst, the first gate electrode section Gw-1 of the gate electrode of the data write transistor Tw, the first gate electrode section Gr1-1 of the gate electrode of the first reset transistor Tr1, the first gate electrode section Gr2-1 of the gate electrode of the second reset transistor Tr2, and the first gate electrode section Ge-1 of the gate electrode of the light emission control transistor Te are located in the same layer.

[0052] As used here, the term "same layer" refers to the relationship between layers that are formed simultaneously in the same step. In one example, the second capacitor electrode Ce2 and the first gate electrode section Gw-1 are in the same layer if they are formed as a result of one or more steps of the same structuring process performed in the same material layer. In another example, the second capacitor electrode Ce2 and the first gate electrode section Gw-1 can be formed in the same layer by performing the step to form the second capacitor electrode Ce2 and the step to form the first gate electrode section Gw-1 simultaneously. The term "same layer" does not always mean that the layer thickness or cross-sectional height is the same.

[0053] With reference to Fig. 2A, Fig. 3A, Fig. 3D and Fig. 31, the gate electrode of the data write transistor Tw comprises one or more sections in some embodiments. In some embodiments, the first gate electrode section Gw-1 of the gate electrode of the data write transistor Tw is connected to a respective gate line of the plurality of gate lines GL.

[0054] With reference to Fig. 2A, Fig. 3A, Fig. 3D and Fig. 31, the gate electrode of the first reset transistor Tr1 comprises one or more sections in some embodiments. In some embodiments, the first gate electrode section Gr1-1 of the gate electrode of the first reset transistor Tr1 is connected to a respective first reset control signal line of the plurality of first reset control signal lines rst1.

[0055] With reference to Fig. 2A, Fig. 3A, Fig. 3D and Fig. 31, the gate electrode of the second reset transistor Tr2 comprises one or more sections in some embodiments. In some embodiments, the first gate electrode section Gr2-1 of the gate electrode of the second reset transistor Tr2 is connected to a respective second reset control signal line of the plurality of second reset control signal lines rst2.

[0056] With reference to Fig. 2A, Fig. 3A, Fig. 3D and Fig. 3I, the gate electrode of the light emission control transistor Te comprises one or more sections in some embodiments. In some embodiments, the first gate electrode section Ge-1 of the gate electrode of the light emission control transistor Te is connected to a respective light emission control signal line of the plurality of light emission control signal lines em.

[0057] Vias passing through the first gate insulating layer GI1 are in Fig. 3E is shown.

[0058] With reference to Fig. 2A, Fig. 3A and Fig. In embodiment 3F, the semiconductor material layer SML comprises, in some embodiments, at least one active layer ACTd of the driver transistor Td, one active layer ACTr1 of the first reset transistor Tr1, one active layer ACTr2 of the second reset transistor Tr2, one active layer ACTw of the data write transistor Tw, and one active layer ACTe of the light emission control transistor Te. Optionally, the semiconductor material layer SML also comprises at least a portion of a first electrode Sd of the driver transistor Td, at least a portion of a first electrode Sr1 of the first reset transistor Tr1, at least a portion of a first electrode Sr2 of the second reset transistor Tr2, at least a portion of a first electrode Sw of the data write transistor Tw, and at least a portion of a first electrode Se of the light emission control transistor Te.Optionally, the semiconductor material layer SML further comprises at least a part of the second electrode Dd of the driver transistor Td, at least a part of the second electrode Dr1 of the first reset transistor Tr1, at least a part of the second electrode Dr2 of the second reset transistor Tr2, at least a part of the second electrode Dw of the data write transistor Tw and at least a part of the second electrode De of the light emission control transistor Te.Optionally, the semiconductor material layer (SML) comprises the active layer ACTd, the first electrode Sd and the second electrode Dd of the driver transistor Td; the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1; the active layer ACTr2, the first electrode Sr2 and the second electrode Dr2 of the second reset transistor Tr2; the active layer ACTw, the first electrode Sw and the second electrode Dw of the data write transistor Tw; and the active layer ACTe, the first electrode Se and the second electrode De of the light emission control transistor Te. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer SML. Examples of semiconductor materials for fabricating the semiconductor material layer SML include metal oxide-based semiconductor materials such as indium gallium zinc oxide and metal oxynitride-based semiconductor materials such as zinc oxynitride.

[0059] As used here, the active layer refers to a component of the transistor that comprises at least a portion of the semiconductor material layer whose orthographic projection on the base substrate overlaps with an orthographic projection of a gate electrode on the base substrate. A first electrode refers to a component of the transistor connected to one side of the active layer, and a second electrode refers to a component of the transistor connected to the other side of the active layer.In the context of a dual-gate transistor, the active layer refers to a component of the transistor comprising a first section of a semiconductor material layer, a second section of the semiconductor material layer, and a third section between the first section and the second section, wherein an orthographic projection of the first section of the semiconductor material layer on the base substrate overlaps with an orthographic projection of the first gate on the base substrate, and an orthographic projection of the second section of the semiconductor material layer on the base substrate overlaps with an orthographic projection of the second gate on the base substrate.In the context of a dual-gate transistor, a first electrode refers to a component of the transistor that is connected to a side of the first section facing away from the third section, and a second electrode refers to a component of the transistor that is connected to a side of the second section facing away from the third section.

[0060] Fig. 3F is designated with reference symbols representing the components of the transistors in the pixel driver circuit. For example, the driver transistor Td comprises an active layer ACTd, a first electrode Sd, and a second electrode Dd; the data write transistor Tw comprises an active layer ACTw, a first electrode Sw, and a second electrode Dw; the light emission control transistor Tw comprises an active layer ACTe, a first electrode Se, and a second electrode De; the first reset transistor Tr1 comprises an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1; and the second reset transistor Tr2 comprises an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. Optionally, the active layer ACTd of the driver transistor Td, the active layer ACTe of the light emission control transistor Te, and the active layer ACTr2 of the second reset transistor Tr2 are parts of a first integral structure.Optionally, the active layer ACTd, the first electrode Sd and the second electrode Dd of the driver transistor Td; the active layer ACTe, the first electrode Se and the second electrode De of the light emission control transistor Te; and the active layer ACTr2, the first electrode Sr2 and the second electrode Dr2 of the second reset transistor Tr2 are parts of the first integral structure. Optionally, the active layer ACTw of the data write transistor Tw and the active layer ACTr1 of the first reset transistor Tr1 are parts of a second integral structure. Optionally, the active layer ACTw, the first electrode Sw and the second electrode Dw of the data write transistor Tw, as well as the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 are parts of the second integral structure.

[0061] With reference to Fig. 2A, Fig. 3A and Fig. In some embodiments, the second conductive layer of 3G comprises a first capacitor electrode Ce1 of the storage capacitor Cst, a second gate electrode section Gw-2 of the gate electrode of the data write transistor Tw, a second gate electrode section Gr1-2 of the gate electrode of the first reset transistor Tr1, a second gate electrode section Gr2-2 of the gate electrode of the second reset transistor Tr2, and a second gate electrode section Ge-2 of the gate electrode of the light emission control transistor Te. Various suitable electrode materials and various suitable fabrication methods can be used to produce the second conductive layer. For example, a conductive material can be deposited and structured on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process.Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, and the like. Optionally, the first capacitor electrode Ce1 of the storage capacitor Cst, the second gate electrode section Gw-2 of the gate electrode of the data write transistor Tw, the second gate electrode section Gr1-2 of the gate electrode of the first reset transistor Tr1, the second gate electrode section Gr2-2 of the gate electrode of the second reset transistor Tr2, and the second gate electrode section Ge-2 of the gate electrode of the light emission control transistor Te are located in the same layer.

[0062] With reference to Fig. 2A, Fig. 3A, Fig. 3G and Fig. In some embodiments, the gate electrode of the data write transistor Tw comprises one or more sections. In some embodiments, the second gate electrode section Gw-2 of the gate electrode of the data write transistor Tw is connected to a respective gate line of the plurality of gate lines GL.

[0063] With reference to Fig. 2A, Fig. 3A, Fig. 3G and Fig. In some embodiments, the gate electrode of the first reset transistor Tr1 comprises one or more sections. In some embodiments, the second gate electrode section Gr1-2 of the gate electrode of the first reset transistor Tr1 is connected to a respective first reset control signal line of the plurality of first reset control signal lines rst1.

[0064] With reference to Fig. 2A, Fig. 3A, Fig. 3G and Fig. In some embodiments, the gate electrode of the second reset transistor Tr2 comprises one or more sections. In some embodiments, the second gate electrode section Gr2-2 of the gate electrode of the second reset transistor Tr2 is connected to a respective second reset control signal line of the plurality of second reset control signal lines rst2.

[0065] With reference to Fig. 2A, Fig. 3A, Fig. 3G and Fig. 3I The gate electrode of the light emission control transistor Te comprises one or more sections in some embodiments. In some embodiments, the second gate electrode section Ge-2 of the gate electrode of the light emission control transistor Te is connected to a respective light emission control signal line of the plurality of light emission control signal lines em.

[0066] Vias passing through the PVX passivation layer are in Fig. 3H shown.

[0067] With reference to Fig. 2A, Fig. 3A and Fig. 3I comprises the first signal line layer in some embodiments a node connection line Cln, a plurality of first power supply lines Vdd1, a plurality of second power supply lines Vss1, a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, a plurality of first reset control signal lines rst1, a plurality of second reset control signal lines rst2, a plurality of gate lines GL, a plurality of light emission control signal lines em, a relay electrode RE and a data signal connection pad DCP.

[0068] Various suitable conductive materials and conductive fabrication methods can be used to fabricate the first signal transmission layer. For example, a conductive material can be deposited and structured on the substrate by plasma-enhanced chemical vapor deposition (PECVD). Examples of suitable conductive materials for fabricating the first signal transmission layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, and the like. In some embodiments, the first signal transmission layer comprises multiple stacked sublayers.In one example, the first signal transmission layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal transmission layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the node connection line Cln, the plurality of first power supply lines Vdd1, the plurality of second power supply lines Vss1, the plurality of first reset signal lines Vint1, the plurality of second reset signal lines Vint2, the plurality of first reset control signal lines rst1, the plurality of second reset control signal lines rst2, the plurality of gate lines GL, the plurality of light emission control signal lines em, the relay electrode RE, and the anode connection pad ACP are located in the same layer.

[0069] In some embodiments, the plurality of first power supply lines Vdd1, the plurality of second power supply lines Vss1, the plurality of first reset signal lines Vint1, the plurality of second reset signal lines Vint2, the plurality of first reset control signal lines rst1, the plurality of second reset control signal lines rst2, the plurality of gate lines GL, and the plurality of light emission control signal lines em each run in a direction substantially parallel to the first direction DR1. As used here, the term "substantially parallel" means that there is an angle in the range of 0 degrees to about 45 degrees, e.g., 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees.

[0070] In some embodiments, the plurality of first voltage supply lines Vdd1 is configured to provide a first reference voltage signal (e.g., a high reference voltage signal); and the plurality of second voltage supply lines Vss1 is configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and a voltage level of the first reference voltage signal is higher than a voltage level of the second reference voltage signal.

[0071] The node connection line Cln connects the gate electrode of the driver transistor Td in a given pixel driver circuit to the second electrode of the first reset transistor Tr1 and the light shielding element in the respective pixel driver circuit. With reference to Fig. In 4A, the node connection line Cln is connected in some embodiments via a first via v1 to the second electrode Dr1 of the first reset transistor Tr1, via a second via v2 to the light shielding element LS, and via a third via v3 to the gate electrode of the driver transistor Td. Optionally, the first node connection line Cin1 corresponds to node N1 shown in 2A.

[0072] In one example, the first via v1 passes through the passivation layer PVX and the second gate insulating layer GI2; the second via v2 passes through the passivation layer PVX, the second gate insulating layer GI2, the first gate insulating layer GI1 and the insulating layer IN; and the third via v3 passes through the passivation layer PVX.

[0073] The data signal connection pad DCP connects each data line of the multitude of data lines DL to the first electrode of the data write transistor Tw.

[0074] The relay electrode RE connects an anode pad to the second capacitor electrode Ce2 and / or the second electrode Dd of the driver transistor Td in a respective pixel driver circuit. The anode pad is connected to the anode of a respective light-emitting element. With reference to Fig. In some embodiments, the relay electrode RE (4B) is connected to the second capacitor electrode Ce2 via a fourth via v4 and to the second electrode Dd of the driver transistor Td via a fifth via v5. The anode connection pad ACP is connected to the relay electrode RE via a sixth via v6. Optionally, the relay electrode RE corresponds to the one shown in Fig. 2A shown node N2.

[0075] In one example, the fourth via v4 passes through the passivation layer PVX, the second gate insulating layer GI2 and the first gate insulating layer GI1; the fifth via v5 passes through the passivation layer PVX and the second gate insulating layer GI2; the sixth via v6 passes through the first planarization layer PLN1.

[0076] In some embodiments, each first power supply line of the plurality of first power supply lines Vdd1 is connected to first electrodes of several light emission control transistors (e.g., several light emission control transistors in the same row).

[0077] In some embodiments, the plurality of second voltage supply lines Vss1 is electrically connected to a cathode of the plurality of light-emitting elements.

[0078] In some embodiments, each first reset signal line of the plurality of first reset signal lines Vint1 is connected to first electrodes of several first reset transistors (e.g., several first reset transistors in the same row).

[0079] In some embodiments, each second reset signal line of the plurality of second reset signal lines Vint2 is connected to first electrodes of several second reset transistors (e.g., several second reset transistors in the same row).

[0080] In some embodiments, each gate line of the plurality of gate lines GL comprises a third gate electrode section Gw-3 of the gate electrode of the data write transistor Tw. Optionally, an orthographic projection of the third gate electrode section Gw-3 of the gate electrode of the data write transistor Tw onto a base substrate overlaps at least partially with an orthographic projection of the second gate electrode section Gw-2 of the gate electrode of the data write transistor Tw onto the base substrate; and overlaps at least partially with an orthographic projection of the first gate electrode section Gw-1 of the gate electrode of the data write transistor Tw onto the base substrate.Optionally, the orthographic projection of the second gate electrode section Gw-2 of the gate electrode of the data writing transistor Tw on the base substrate overlaps at least partially with the orthographic projection of the first gate electrode section Gw-1 of the gate electrode of the data writing transistor Tw on the base substrate.

[0081] In some embodiments, each second reset control signal line of the plurality of second reset control signal lines rst2 comprises a third gate electrode section Gr2-3 of the gate electrode of the second reset transistor Tr2. Optionally, an orthographic projection of the third gate electrode section Gr2-3 of the gate electrode of the second reset transistor Tr2 onto a base substrate overlaps at least partially with an orthographic projection of the second gate electrode section Gr2-2 of the gate electrode of the second reset transistor Tr2 onto the base substrate; and overlaps at least partially with an orthographic projection of the first gate electrode section Gr2-1 of the gate electrode of the second reset transistor Tr2 onto the base substrate.Optionally, the orthographic projection of the second gate electrode section Gr2-2 of the gate electrode of the second reset transistor Tr2 on the base substrate overlaps at least partially with the orthographic projection of the first gate electrode section Gr2-1 of the gate electrode of the second reset transistor Tr2 on the base substrate.

[0082] Through-hole connections passing through the first planarization layer PLN1 are in Fig. 3J shown.

[0083] With reference to Fig. 2A, Fig. 3A and Fig. In some embodiments, the second signal transmission layer 3K comprises a plurality of third power supply lines Vdd2, a plurality of fourth power supply lines Vss2, a plurality of data lines DL, a plurality of third reset signal lines Vint3, a plurality of fourth reset signal lines Vint4, and an anode connection pad ACP. Each data line of the plurality of data lines DL is electrically connected via a data signal connection pad to a first electrode of the data write transistor Tw. The anode connection pad ACP is connected via the relay electrode to the second capacitor electrode and / or the second electrode of the driver transistor in a respective pixel driver circuit, as well as to the anode of a respective light-emitting element.

[0084] Various suitable conductive materials and manufacturing processes can be used to fabricate the second signal transmission layer. For example, a conductive material can be deposited and structured on the substrate using plasma-enhanced chemical vapor deposition (PECVD). Examples of suitable conductive materials for fabricating the second signal transmission layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, and the like. In some embodiments, the second signal transmission layer comprises multiple stacked sublayers. In one example, the second signal transmission layer comprises a stacked titanium / aluminum / titanium multilayer structure.In another example, the second signal transmission layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the plurality of third power supply lines Vdd2, the plurality of fourth power supply lines Vss2, the plurality of data lines DL, the plurality of third reset signal lines Vint3, the plurality of fourth reset signal lines Vint4, and the anode terminal pad ACP are located in the same layer.

[0085] In some embodiments, the plurality of third voltage supply lines Vdd2 is configured to provide a first reference voltage signal (e.g., a high reference voltage signal); and the plurality of fourth voltage supply lines Vss2 is configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and a voltage level of the first reference voltage signal is higher than a voltage level of the second reference voltage signal.

[0086] With reference to Fig. 3I and Fig. In some embodiments, the plurality of third power supply lines Vdd2 in the second signal layer is connected to a plurality of first power supply lines Vdd1 in the first signal layer. Each first power supply line of the plurality of first power supply lines Vdd1 is connected to the first electrodes of several light emission control transistors (e.g., several light emission control transistors in the same row). Optionally, the plurality of third power supply lines Vdd2 runs in a direction substantially parallel to the second direction DR2; and the plurality of first power supply lines Vdd1 runs in a direction substantially parallel to the first direction DR1.

[0087] In some embodiments, the plurality of fourth power supply lines Vss2 in the second signal layer is connected to a plurality of second power supply lines Vss1 in the first signal layer. Optionally, the plurality of fourth power supply lines Vss2 runs in a direction substantially parallel to the second direction DR2; and the plurality of second power supply lines Vss1 runs in a direction substantially parallel to the first direction DR1.

[0088] In some embodiments, the plurality of third reset signal lines Vint3 in the second signal layer is connected to a plurality of first reset signal lines Vint1 in the first signal layer. Optionally, each first reset signal line of the plurality of first reset signal lines Vint1 is connected to the first electrodes of several first reset transistors (e.g., several first reset transistors in the same row). Optionally, the plurality of third reset signal lines Vint3 runs in a direction substantially parallel to a second direction DR2; and the plurality of first reset signal lines Vint1 runs in a direction substantially parallel to the first direction DR1.

[0089] In some embodiments, the plurality of fourth reset signal lines Vint4 in the second signal layer is connected to a plurality of second reset signal lines Vint2 in the first signal layer. Optionally, each second reset signal line of the plurality of second reset signal lines Vint2 is connected to the first electrodes of several second reset transistors (e.g., several second reset transistors in the same row). Optionally, the plurality of fourth reset signal lines Vint4 runs in a direction substantially parallel to a second direction DR2; and the plurality of second reset signal lines Vint2 runs in a direction substantially parallel to the first direction DR1.

[0090] In some embodiments, the first column of pixel driver circuits, the second column of pixel driver circuits, and the third column of pixel driver circuits are three adjacent columns of pixel driver circuits. Optionally, the first column of pixel driver circuits, the second column of pixel driver circuits, and the third column of pixel driver circuits are arranged sequentially along the first direction DR1.

[0091] In some embodiments, each data line of the plurality of data lines DL in the second signal layer is connected to a data signal connection pad DCP in the first signal layer, and the data signal connection pad DCP is connected to a first electrode of the data write transistor Tw. Optionally, the plurality of data lines DL runs in one direction that is substantially parallel to a second direction DR2.

[0092] Through-hole connections passing through the second planarization layer PLN2 are in Fig. 3L is shown. An anode of a light-emitting element is connected via a via that passes through the second planarization layer PLN2 to an anode connection pad in the second signal transmission layer.

[0093] Fig. Figure 5 is a schematic diagram illustrating the structure of a first power supply network in a portion of an array substrate in some embodiments according to the present disclosure. With reference to Fig. 5. In some embodiments, the first power supply network comprises a plurality of first power supply lines Vdd1 and a plurality of third power supply lines Vdd2, which are interconnected. Optionally, the plurality of first power supply lines Vdd1 runs in a direction substantially parallel to a first direction DR1. Optionally, the plurality of third power supply lines Vdd2 runs in a direction substantially parallel to a second direction DR2. Optionally, each first power supply line of the plurality of first power supply lines Vdd1 is connected to one or more third power supply lines of the plurality of third power supply lines Vdd2.Optionally, each third power supply line of the plurality of third power supply lines Vdd2 is connected to one or more first power supply lines of the plurality of first power supply lines Vdd1.

[0094] In one example, the multitude of first power supply lines Vdd1 is located in the first signal layer. Optionally, the multitude of third power supply lines Vdd2 is located in the second signal layer.

[0095] Fig. Figure 6 is a schematic diagram illustrating the structure of a second power supply network in a portion of an array substrate in some embodiments according to the present disclosure. With reference to Fig. 6. In some embodiments, the second power supply network comprises a plurality of second power supply lines Vss1 and a plurality of fourth power supply lines Vss2, which are interconnected. Optionally, the plurality of second power supply lines Vss1 runs in a direction substantially parallel to the first direction DR1. Optionally, the plurality of fourth power supply lines Vss2 runs in a direction substantially parallel to the second direction DR2. Optionally, each second power supply line of the plurality of second power supply lines Vss1 is connected to one or more fourth power supply lines of the plurality of fourth power supply lines Vss2.Optionally, each fourth power supply line of the multitude of fourth power supply lines Vss2 is connected to one or more second power supply lines of the multitude of second power supply lines Vss1.

[0096] In one example, the multitude of second power supply lines Vss1 is located in the first signal layer. Optionally, the multitude of fourth power supply lines Vss2 is located in the second signal layer.

[0097] Fig. Figure 7 is a schematic diagram illustrating the structure of a first reset signal network in a portion of an array substrate in some embodiments according to the present disclosure. With reference to Fig. 7. In some embodiments, the first reset signal network comprises a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3, which are interconnected. Optionally, the plurality of first reset signal lines Vint1 runs in a direction substantially parallel to a first direction DR1. Optionally, the plurality of third reset signal lines Vint3 runs in a direction substantially parallel to a second direction DR2. Optionally, each first reset signal line of the plurality of first reset signal lines Vint1 is connected to one or more third reset signal lines of the plurality of third reset signal lines Vint3.Optionally, each third reset signal line of the plurality of third reset signal lines Vint3 is connected to one or more first reset signal lines of the plurality of first reset signal lines Vint1.

[0098] In one example, the multitude of first reset signal lines Vint1 is located in the first signal line layer. Optionally, the multitude of third reset signal lines Vint3 is located in the second signal line layer.

[0099] Fig. Figure 8 is a schematic diagram illustrating the structure of a second reset signal network in a portion of an array substrate in some embodiments according to the present disclosure. With reference to Fig. 8. In some embodiments, the second reset signal network comprises a plurality of second reset signal lines Vint2 and a plurality of fourth reset signal lines Vint4, which are interconnected. Optionally, the plurality of second reset signal lines Vint2 runs in a direction substantially parallel to a first direction DR1. Optionally, the plurality of fourth reset signal lines Vint4 runs in a direction substantially parallel to a second direction DR2. Optionally, each second reset signal line of the plurality of second reset signal lines Vint2 is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines Vint4.Optionally, each fourth reset signal line of the plurality of fourth reset signal lines Vint4 is connected to one or more second reset signal lines of the plurality of second reset signal lines Vint2.

[0100] In one example, the multitude of second reset signal lines Vint2 is located in the first signal line layer. Optionally, the multitude of fourth reset signal lines Vint4 is located in the second signal line layer.

[0101] With reference to Fig. 3A to Fig. In some embodiments, the pixel driver circuits of the array substrate are arranged in columns, including the (3k - 2)th column C(3k - 2), the (3k - 1)th column C(3k - 1) and the (3k)th column C(3k) of the K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3).

[0102] As used here, the terms "(3k-2)th column," "(3k-1)th column," and "(3k)th column" are used in the context of the K columns. The array substrate may or may not include additional column(s) before the first column of the K columns and / or additional column(s) after the last column of the K columns. In the context of the array substrate, the term "(3k-1)th column" does not necessarily mean an odd column, and the terms "(3k-2)th column" or "(3k)th column" do not necessarily mean an even column. In one example, the (3k-2)th column is an even column in the context of the K columns but may be an odd column in the context of the array substrate. In another example, the (3k-2)th column is an even column in the context of the K columns and also an even column in the context of the array substrate.In one example, the (3k-1)th column is an odd column in the context of the K columns, but can be an even column in the context of the array substrate. In another example, the (3k-1)th column is an odd column in the context of the K columns and also an odd column in the context of the array substrate. In one example, the (3k)th column is an even column in the context of the K columns, but can be an odd column in the context of the array substrate. In another example, the (3k)th column is an even column in the context of the K columns and also an even column in the context of the array substrate.

[0103] In some embodiments, the (3k-2)th column C(3k-2) comprises a (3k-2)th pixel driver circuit, the (3k-1)th column C(3k-1) comprises a (3k-1)th pixel driver circuit, and the (3k)th column C(3k) comprises a (3k)th pixel driver circuit. The (3k-2)th pixel driver circuit, the (3k-1)th pixel driver circuit, and the (3k)th pixel driver circuit are located in the same row.

[0104] In some embodiments, the (3k-2)th column C(3k-2) comprises a fourth power supply line of the plurality of fourth power supply lines Vss2; the (3k-1)th column C(3k-1) comprises a fourth reset signal line of the plurality of fourth reset signal lines Vint4; and the (3k)th column C(3k) comprises a third reset signal line of the plurality of third reset signal lines Vint3.

[0105] Optionally, the multitude of fourth voltage supply lines Vss2 is not present in the (3k-1)th column C(3k-1) and is not present in the (3k)th column C(3k).

[0106] Optionally, the multitude of fourth reset signal lines Vint4 is not present in the (3k-2)th column C(3k-2) and is not present in the (3k)th column C(3k).

[0107] Optionally, the multiple third reset signal lines Vint3 are not present in the (3k-2)th column C(3k-2) and are not present in the (3k-1)th column C(3k-1).

[0108] In some embodiments, the pixel driver circuits of the (3k-2)th column C(3k-2) are configured to drive subpixels of a first color in the (3k-2)th column C(3k-2) to emit light, the pixel driver circuits of the (3k)th column C(3k) are configured to drive subpixels of a second color in the (3k)th column C(3k) to emit light, and the pixel driver circuits of the (3k-1)th column C(3k-1) are configured to drive subpixels of a third color in the (3k-1)th column C(3k-1) to emit light. Optionally, the first color, the second color, and the third color are three different colors selected from red, green, and blue.

[0109] Fig. Figure 9 is a schematic diagram showing the structure of a semiconductor material layer and a second signal transmission layer in a portion of the array substrate as shown in Fig. 3A illustrates this. In some embodiments, with reference to Fig. 3A to Fig. 3K and Fig.9, an orthographic projection of a respective third voltage supply line of a plurality of third voltage supply lines Vdd2 on the base substrate substantially covers (e.g. at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of an active layer ACTe of the light emission control transistor Te in the respective pixel driver circuit on the base substrate, it substantially covers (e.g. at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of an active layer ACTr2 of the second reset transistor Tr2 on the base substrate and overlaps at least partially with an orthographic projection of an active layer ACTd of the driver transistor Td on the base substrate.The inventors of the present disclosure have determined that this structure can protect and stabilize the active layer ACTe of the light emission control transistor Te, the active layer ACTr2 of the second reset transistor Tr2 and the active layer ACTd of the driver transistor Td from irradiation.

[0110] In some embodiments, the orthographic projection of a respective third power supply line of a plurality of third power supply lines Vdd2 on the base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of a combination of an active layer ACTe, a first electrode Se, and a second electrode De of the light emission control transistor Te in the respective pixel driver circuit on the base substrate; substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of a combination of an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2 of the second reset transistor Tr2 on the base substrate; substantially covers (e.g.,at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of a combination of a first electrode Sd and a second electrode Dd of the driver transistor Td onto the base substrate; and overlaps at least partially with an orthographic projection of an active layer ACTd of the driver transistor Td onto the base substrate.

[0111] In some embodiments, the active layer ACTd, the first electrode Sd and the second electrode Dd of the driver transistor Td; the active layer ACTe, the first electrode Se and the second electrode De of the light emission control transistor Te; and the active layer ACTr2, the first electrode Sr2 and the second electrode Dr2 of the second reset transistor Tr2 are parts of a first integral structure. Optionally, the orientation of the first integral structure is substantially parallel to the orientation of the respective third voltage supply line Vdd2 of a plurality of third voltage supply lines.

[0112] In some embodiments, in a first column of pixel driver circuits, an orthographic projection of a respective fourth power supply line of the plurality of fourth power supply lines Vss2 on a base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of an active layer ACTr1 of the first reset transistor Tr1 in a first respective pixel driver circuit in the first column of pixel driver circuits on the base substrate, and substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of an active layer ACTw of the data write transistor Tw in the first respective pixel driver circuit in the first column of pixel driver circuits on the base substrate.The inventors of the present disclosure have determined that this structure can protect and stabilize the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw from radiation.

[0113] In some embodiments, in the first column of pixel driver circuits, the orthographic projection of a respective fourth power supply line of the plurality of fourth power supply lines Vss2 on the base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of a combination of an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1 of the first reset transistor Tr1 in a first respective pixel driver circuit in the first column of pixel driver circuits on the base substrate and substantially covers (e.g.,at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of a combination of an active layer ACTw and a second electrode Dw of the data write transistor Tw in the first respective pixel driver circuit in the first column of pixel driver circuits on the base substrate.

[0114] In some embodiments, in the first column of pixel driver circuits, the active layer ACTw, the first electrode Sw and the second electrode Dw of the data write transistor Tw, and the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 are parts of a second integral structure in the first column of pixel driver circuits. Optionally, the orientation of the second integral structure in the first column of pixel driver circuits is substantially parallel to the orientation of the respective fourth power supply line of the plurality of fourth power supply lines Vss2.

[0115] In some embodiments, in a second column of pixel driver circuits, an orthographic projection of a respective fourth reset signal line of the plurality of fourth reset signal lines Vint4 on the base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of an active layer ACTr1 of the first reset transistor Tr1 in a second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate, and substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of an active layer ACTw of the data write transistor Tw in the second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate.The inventors of the present disclosure have determined that this structure can protect and stabilize the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw from radiation.

[0116] In some embodiments, in the second column of pixel driver circuits, the orthographic projection of a respective fourth reset signal line of the plurality of fourth reset signal lines Vint4 on the base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of a combination of an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1 of the first reset transistor Tr1 in a second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate; and substantially covers (e.g.,at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of a combination of a second electrode Dw and an active layer ACTw of the data writing transistor Tw in the second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate.

[0117] In some embodiments, in the second column of pixel driver circuits, the active layer ACTw, the first electrode Sw and the second electrode Dw of the data write transistor Tw, and the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 are parts of a second integral structure in the second column of pixel driver circuits. Optionally, the direction of extension of the second integral structure in the second column of pixel driver circuits is substantially parallel to the direction of extension of the respective fourth reset signal line of the plurality of fourth reset signal lines Vint4.

[0118] In some embodiments, in a third column of pixel driver circuits, an orthographic projection of a respective third reset signal line of the plurality of third reset signal lines Vint3 on the base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of an active layer ACTr1 of the first reset transistor Tr1 in a third respective pixel driver circuit in the third column of pixel driver circuits on the base substrate, and substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of an active layer ACTw of the data write transistor Tw in the third respective pixel driver circuit in the third column of pixel driver circuits on the base substrate.The inventors of the present disclosure have determined that this structure can protect and stabilize the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw from radiation.

[0119] In some embodiments, in the third column of pixel driver circuits, the orthographic projection of a respective third reset signal line of the plurality of third reset signal lines Vint3 on the base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of a combination of an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1 of the first reset transistor Tr1 in a respective third pixel driver circuit in the third column of pixel driver circuits on the base substrate; and substantially covers (e.g.,at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of a combination of an active layer ACTw and a second electrode Dw of the data write transistor Tw in the respective third pixel driver circuit in the third column of pixel driver circuits on the base substrate.

[0120] In some embodiments, in the third column of pixel driver circuits, the active layer ACTw, the first electrode Sw and the second electrode Dw of the data write transistor Tw, and the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 are parts of a second integral structure in the third column of pixel driver circuits. Optionally, the direction of extension of the second integral structure in the third column of pixel driver circuits is substantially parallel to the direction of extension of the respective third reset signal line of the plurality of third reset signal lines Vint3.

[0121] In some embodiments, in the (3k-2)th column C(3k-2) of pixel driver circuits, an orthographic projection of a respective fourth power supply line of the plurality of fourth power supply lines Vss2 on the base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of an active layer ACTr1 of the first reset transistor Tr1 in a first respective pixel driver circuit in the (3k-2)th column C(3k-2) of pixel driver circuits on the base substrate, and substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of an active layer ACTw of the data write transistor Tw in the first respective pixel driver circuit in the (3k-2)th column C(3k-2) of pixel driver circuits on the Base substrate off.The inventors of the present disclosure have determined that this structure can protect and stabilize the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw from radiation.

[0122] In some embodiments, in the (3k-2)th column C(3k-2) of pixel driver circuits, the orthographic projection of a respective fourth power supply line of the plurality of fourth power supply lines Vss2 on the base substrate substantially covers (e.g. at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of a combination of an active layer ACTr1, a first electrode Sr1 and a second electrode Dr1 of the first reset transistor Tr1 in a first respective pixel driver circuit in the (3k-2)th column C(3k-2) of pixel driver circuits on the base substrate and substantially covers (e.g.at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of a combination of an active layer ACTw and a second electrode Dw of the data write transistor Tw in the first respective pixel driver circuit in the (3k-2)th column C(3k-2) of pixel driver circuits on the base substrate.

[0123] In some embodiments, in the (3k-2)th column C(3k-2) of pixel driver circuits, the active layer ACTw, the first electrode Sw and the second electrode Dw of the data write transistor Tw, as well as the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1, are parts of a second integral structure in the (3k-2)th column C(3k-2) of pixel driver circuits. Optionally, the orientation of the second integral structure in the (3k-2)th column C(3k-2) of pixel driver circuits is substantially parallel to the orientation of the respective fourth power supply line of the plurality of fourth power supply lines Vss2.

[0124] In some embodiments, in the (3k-1)th column C(3k-1) of pixel driver circuits, an orthographic projection of a respective fourth reset signal line of the plurality of fourth reset signal lines Vint4 on the base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of an active layer ACTr1 of the first reset transistor Tr1 in a second respective pixel driver circuit in the (3k-1)th column C(3k-1) of pixel driver circuits on the base substrate, and substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of an active layer ACTw of the data write transistor Tw in the second respective pixel driver circuit in the (3k-1)th column C(3k-1) of pixel driver circuits on the Base substrate off.The inventors of the present disclosure have determined that this structure can protect and stabilize the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw from radiation.

[0125] In some embodiments, in the (3k - 1)th column C(3k - 1) of pixel driver circuits, the orthographic projection of a respective fourth reset signal line of the plurality of fourth reset signal lines Vint4 on the base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of a combination of an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1 of the first reset transistor Tr1 in a second respective pixel driver circuit in the (3k - 1)th column C(3k - 1) of pixel driver circuits on the base substrate; and substantially covers (e.g.,at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of a combination of an active layer ACTw and a second electrode Dw of the data write transistor Tw in the second respective pixel driver circuit in the (3k-1)th column C(3k-1) of pixel driver circuits on the base substrate.

[0126] In some embodiments, in the (3k-1)th column C(3k-1) of pixel driver circuits, the active layer ACTw, the first electrode Sw and the second electrode Dw of the data write transistor Tw, as well as the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1, are parts of a second integral structure in the (3k-1)th column C(3k-1) of pixel driver circuits. Optionally, the direction of extension of the second integral structure in the (3k-1)th column C(3k-1) of pixel driver circuits is substantially parallel to the direction of extension of the respective fourth reset signal line of the plurality of fourth reset signal lines Vint4.

[0127] In some embodiments, in the (3k)th column C(3k) of pixel driver circuits, an orthographic projection of a respective third reset signal line of the plurality of third reset signal lines Vint3 on the base substrate substantially covers (e.g. at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of an active layer ACTr1 of the first reset transistor Tr1 in a third respective pixel driver circuit in the (3k)th column C(3k) of pixel driver circuits on the base substrate and substantially covers (e.g. at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of an active layer ACTw of the data write transistor Tw in the third respective pixel driver circuit in the (3k)th column C(3k) of pixel driver circuits on the base substrate.The inventors of the present disclosure have determined that this structure can protect and stabilize the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw from radiation.

[0128] In some embodiments, in the (3k)th column C(3k) of pixel driver circuits, the orthographic projection of a respective third reset signal line of the plurality of third reset signal lines Vint3 on the base substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely) an orthographic projection of a combination of an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1 of the first reset transistor Tr1 in a third respective pixel driver circuit in the (3k)th column C(3k) of pixel driver circuits on the base substrate; and substantially covers (e.g.,at least 80%, at least 85%, at least 90%, at least 95%, at least 99% or completely) an orthographic projection of a combination of an active layer ACTw and a second electrode Dw of the data write transistor Tw in the third respective pixel driver circuit in the (3k)th column C(3k) of pixel driver circuits on the base substrate.

[0129] In some embodiments, in the (3k)th column C(3k) of pixel driver circuits, the active layer ACTw, the first electrode Sw and the second electrode Dw of the data write transistor Tw, as well as the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1, are parts of a second integral structure in the (3k)th column C(3k) of pixel driver circuits. Optionally, the direction of extension of the second integral structure in the (3k)th column C(3k) of pixel driver circuits is substantially parallel to the direction of extension of the respective third reset signal line of the plurality of third reset signal lines Vint3.

[0130] In another aspect, the present invention provides a display device comprising the array substrate described herein or produced by a method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebooks, digital albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a micro-LED display device. Optionally, the display device is a mini-LED display device.

[0131] In another aspect, the present disclosure provides a method for fabricating an array substrate. In some embodiments, the method comprises: forming a plurality of pixel driver circuits. Optionally, forming each pixel driver circuit of the plurality of pixel driver circuits comprises forming a driver transistor, forming a light-shielding element, and forming a node interconnect. Optionally, an orthographic projection of the light-shielding element onto a base substrate essentially covers an orthographic projection of an active layer of the driver transistor onto the base substrate. Optionally, the light-shielding element is electrically connected to a gate electrode of the driver transistor via the node interconnect. Optionally, the light-shielding element, the node interconnect, and the gate electrode of the driver transistor are formed in three different layers.

[0132] The foregoing description of the embodiments of the invention is provided for illustrative and descriptive purposes. It is not exhaustive and is not intended to limit the invention to the disclosed exact form or embodiments. Accordingly, the foregoing description is to be understood as illustrative and not as limiting. Naturally, numerous modifications and variations are obvious to those skilled in the art. The embodiments are selected and described to explain the principles of the invention and their optimal practical application, so that those skilled in the art can understand various embodiments of the invention as well as various modifications suitable for specific applications or implementations under consideration.The scope of the invention shall be defined by the appended claims and their equivalents, all terms being to be understood in their broadest sense unless otherwise specified. Therefore, the term "the invention," "the present invention," or similar terms do not necessarily limit the scope of the claims to a particular embodiment, and reference to exemplary embodiments of the invention does not constitute a limitation of the invention, nor should it be inferred as such. The invention is limited solely by the spirit and scope of the appended claims. Furthermore, these claims may refer to the use of "first," "second," etc., followed by a noun or element. These terms are to be understood as nomenclature and not as limiting the number of elements modified by this nomenclature unless a specific number has been indicated.The described advantages and benefits may not apply to all embodiments of the invention. It is understood that those skilled in the art can modify the described embodiments without departing from the scope of protection of the present invention as defined in the appended claims. Furthermore, no element or component of the present disclosure is intended for public disclosure, regardless of whether the element or component is expressly mentioned in the appended claims.

Claims

[1] Array substrate comprising a variety of pixel driver circuits; wherein each pixel driver circuit of the plurality of pixel driver circuits comprises a driver transistor, a light shielding element and a node connection line; wherein an orthographic projection of the light-shielding element onto a base substrate essentially covers an orthographic projection of an active layer of the driver transistor onto the base substrate; wherein the light shielding element is electrically connected to a gate electrode of the driver transistor via the node connection line; wherein the light shielding element, the node connection line and the gate electrode of the driver transistor are located in three different layers. [2] The array substrate according to claim 1, wherein the respective pixel driver circuit further comprises a first reset transistor; wherein the light shielding element is electrically connected to a second electrode of the first reset transistor via the node connection line. [3] The array substrate according to claim 1, wherein the respective pixel driver circuit further comprises a storage capacitor; wherein the orthographic projection of the light shielding element on the base substrate substantially covers an orthographic projection of a gate electrode of the driver transistor on the base substrate and substantially covers an orthographic projection of a second capacitor electrode of the storage capacitor on the base substrate. [4] The array substrate according to any one of claims 1 to 3, further comprising a plurality of third power supply lines; wherein the respective pixel driver circuit further comprises a light emission control transistor and a second reset transistor; wherein an orthographic projection of a respective third power supply line of the plurality of third power supply lines on the base substrate essentially covers an orthographic projection of an active layer of the light emission control transistor in the respective pixel driver circuit on the base substrate, essentially covers an orthographic projection of an active layer of the second reset transistor on the base substrate, and overlaps at least partially with the orthographic projection of the active layer of the driver transistor on the base substrate. [5] The array substrate according to claim 4, wherein the orthographic projection of each third power supply line of the plurality of third power supply lines on the base substrate essentially covers an orthographic projection of a combination of an active layer, a first electrode and a second electrode of the light emission control transistor in the respective pixel driver circuit on the base substrate; essentially covers an orthographic projection of a combination of an active layer, a first electrode and a second electrode of the second reset transistor on the base substrate; essentially covers an orthographic projection of a combination of a first electrode and a second electrode of the driver transistor on the base substrate; and overlaps at least partially with an orthographic projection of an active layer of the driver transistor on the base substrate. [6] The array substrate according to any one of claims 1 to 3, further comprising a plurality of fourth power supply lines; wherein the respective pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein in a first column of pixel driver circuits an orthographic projection of a respective fourth power supply line of the plurality of fourth power supply lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a first respective pixel driver circuit in the first column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the first respective pixel driver circuit in the first column of pixel driver circuits on the base substrate. [7] The array substrate according to claim 6, wherein in the first column of pixel driver circuits the orthographic projection of a respective fourth power supply line of the plurality of fourth power supply lines on the base substrate essentially covers an orthographic projection of a combination of an active layer, a first electrode and a second electrode of the first reset transistor in the first respective pixel driver circuit in the first column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of a combination of an active layer and a second electrode of the data write transistor in the first respective pixel driver circuit in the first column of pixel driver circuits on the base substrate. [8] The array substrate according to any one of claims 1 to 3, further comprising a plurality of fourth reset signal lines; wherein the respective pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein in a second column of pixel driver circuits an orthographic projection of a respective fourth reset signal line of the plurality of fourth reset signal lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate. [9] The array substrate according to claim 8, wherein in the second column of pixel driver circuits the orthographic projection of a respective fourth reset signal line of the plurality of fourth reset signal lines on the base substrate essentially covers an orthographic projection of a combination of an active layer, a first electrode and a second electrode of the first reset transistor in the second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate; and essentially covers an orthographic projection of a combination of an active layer and a second electrode of the data write transistor in the second respective pixel driver circuit in the second column of pixel driver circuits on the base substrate. [10] The array substrate according to any one of claims 1 to 3, further comprising a plurality of third reset signal lines; wherein the respective pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein in a third column of pixel driver circuits an orthographic projection of a respective third reset signal line of the plurality of third reset signal lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a third respective pixel driver circuit in the third column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the third respective pixel driver circuit in the third column of pixel driver circuits on the base substrate. [11] The array substrate according to claim 10, wherein in the third column of pixel driver circuits the orthographic projection of a respective third reset signal line of the plurality of third reset signal lines on the base substrate essentially covers an orthographic projection of a combination of an active layer, a first electrode and a second electrode of the first reset transistor in the third respective pixel driver circuit in the third column of pixel driver circuits on the base substrate; and essentially covers an orthographic projection of a combination of an active layer and a second electrode of the data write transistor in the third respective pixel driver circuit in the third column of pixel driver circuits on the base substrate. [12] The array substrate according to any one of claims 1 to 3, further comprising a plurality of fourth power supply lines; wherein the respective pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein the pixel driver circuits of the array substrate are arranged in columns that encompass a (3k-2)th column, a (3k-1)th column and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); wherein in the (3k-2)th column of pixel driver circuits an orthographic projection of a respective fourth power supply line of the plurality of fourth power supply lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a first respective pixel driver circuit in the (3k-2)th column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the first respective pixel driver circuit in the (3k-2)th column of pixel driver circuits on the base substrate. [13] The array substrate according to any one of claims 1 to 3, further comprising a plurality of fourth reset signal lines; wherein the respective pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein the pixel driver circuits of the array substrate are arranged in columns that encompass a (3k-2)th column, a (3k-1)th column and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); wherein in the (3k-1)th column of pixel driver circuits an orthographic projection of a respective fourth reset signal line of the plurality of fourth reset signal lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a second respective pixel driver circuit in the (3k-1)th column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the second respective pixel driver circuit in the (3k-1)th column of pixel driver circuits on the base substrate. [14] The array substrate according to any one of claims 1 to 3, further comprising a plurality of third reset signal lines; wherein the respective pixel driver circuit further comprises a data write transistor and a first reset transistor; wherein the pixel driver circuits of the array substrate are arranged in columns comprising a (3k-2)th column, a (3k-1)th column and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); wherein in the (3k)th column of pixel driver circuits an orthographic projection of a respective third reset signal line of the plurality of third reset signal lines on the base substrate essentially covers an orthographic projection of an active layer of the first reset transistor in a third respective pixel driver circuit in the (3k)th column of pixel driver circuits on the base substrate and essentially covers an orthographic projection of an active layer of the data write transistor in the third respective pixel driver circuit in the (3k)th column of pixel driver circuits on the base substrate. [15] The array substrate according to claim 1, further comprising a plurality of fourth power supply lines, a plurality of fourth reset signal lines and a plurality of third reset signal lines located in the same layer; wherein the pixel driver circuits of the array substrate are arranged in columns comprising a (3k-2)th column, a (3k-1)th column and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); where the (3k-2)th column comprises a fourth power supply line of the plurality of fourth power supply lines; wherein the (3k-1)th column comprises a fourth reset signal line of the plurality of fourth reset signal lines; and wherein the (3k)th column comprises a third reset signal line of the plurality of third reset signal lines. [16] The array substrate according to claim 15, wherein the plurality of fourth power supply lines is not present in the (3k - 1)th column and is not present in the (3k)th column; where the multitude of fourth reset signal lines is not present in the (3k-2)th column and is not present in the (3k)th column; and where the multitude of third reset signal lines is not present in the (3k-2)th column and is not present in the (3k-1)th column. [17] The array substrate according to claim 1, further comprising a first power supply network and a second power supply network; wherein the first voltage supply network comprises a plurality of first voltage supply lines and a plurality of third voltage supply lines interconnected; the multitude of first power supply lines run in a direction that is essentially parallel to a first direction; the multitude of third power supply lines run in one direction that is essentially parallel to a second direction; a respective first power supply line of the multitude of first power supply lines is connected to one or more third power supply lines of the multitude of third power supply lines; a respective third power supply line of the plurality of third power supply lines is connected to one or more first power supply lines of the plurality of first power supply lines; and wherein the second voltage supply network comprises a plurality of second voltage supply lines and a plurality of fourth voltage supply lines interconnected; the multitude of second power supply lines run in a direction that is essentially parallel to the first direction; the multitude of fourth voltage supply lines runs in a direction that is essentially parallel to the second direction; a respective second power supply line of the plurality of second power supply lines is connected to one or more fourth power supply lines of the plurality of fourth power supply lines; and a respective fourth power supply line of the plurality of fourth power supply lines is connected to one or more second power supply lines of the plurality of second power supply lines; wherein the pixel driver circuits of the array substrate are arranged in columns comprising a (3k-2)th column, a (3k-1)th column and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); the multitude of third voltage supply lines is present in the (3k-2)th column, in the (3k-1)th column and in the (3k)th column; the multitude of fourth power supply lines is not present in the (3k-1)th column and is not present in the (3k)th column. [18] The array substrate according to claim 1, further comprising a first reset signal network; wherein the first reset signal network comprises a plurality of first reset signal lines and a plurality of third reset signal lines interconnected; the multitude of first reset signal lines runs in a direction that is essentially parallel to a first direction; the multitude of third reset signal lines runs in one direction that essentially runs parallel to a second direction; a respective first reset signal line of the plurality of first reset signal lines is connected to one or more third reset signal lines of the plurality of third reset signal lines; and a respective third reset signal line of the plurality of third reset signal lines is connected to one or more first reset signal lines of the plurality of first reset signal lines; wherein the pixel driver circuits of the array substrate are arranged in columns that are a (3k-2)th column, a (3k-1)th column and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); and the multitude of third reset signal lines is not present in the (3k-2)th column and is not present in the (3k-1)th column. [19] The array substrate according to claim 1, further comprising a second reset signal network; wherein the second reset signal network comprises a plurality of second reset signal lines and a plurality of fourth reset signal lines interconnected; the multitude of second reset signal lines runs in a direction that is essentially parallel to a first direction; the multitude of fourth reset signal lines runs in one direction that essentially runs parallel to a second direction; a respective second reset signal line of the plurality of second reset signal lines is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines; and a respective fourth reset signal line of the plurality of fourth reset signal lines is connected to one or more second reset signal lines of the plurality of second reset signal lines; wherein the pixel driver circuits of the array substrate are arranged in columns comprising a (3k-2)th column, a (3k-1)th column, and a (3k)th column of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 3); and the multitude of fourth reset signal lines is not present in the (3k-2)th column and is not present in the (3k)th column. [20] A display device comprising an array substrate according to any one of claims 1 to 19 and one or more integrated circuits connected to the array substrate.

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