DEVICE WITH TSV STRUCTURE

Abstract

According to one or more embodiments of the invention, a device comprises a logic chip having a plurality of first silicon vias (TSVs) and a core chip on the logic chip having a plurality of second TSVs. The number of first TSVs in the logic chip differs from the number of second TSVs in the core chip.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority over preliminary U.S. application No. 63 / 508,498, filed on June 15, 2023. That application is hereby incorporated in its entirety and for all purposes by reference. BACKGROUND

[0002] High data reliability, high memory access speed, low power consumption, and reduced chip size are required characteristics of semiconductor memory. Some three-dimensional (3D) memory devices can be formed by vertically stacking memory chips (or memory modules) and connecting the stacked chips using silicon through-hole vias (TSVs). Advantages of 3D memory devices include shorter interconnects, which reduce signal latency and power consumption; a greater number of vertical through-holes between layers, enabling high-bandwidth buses between functional blocks in different layers; and a significantly smaller footprint. Thus, 3D memory devices contribute to higher memory access speeds, lower power consumption, and a reduction in chip size.Examples of 3D memory devices include High Bandwidth Memory (HBM) and Hybrid Memory Cube (HMC). HBM is a type of memory that incorporates a high-performance dynamic random-access memory interface chip (DRAM interface chip) and vertically stacked DRAM chips. HMC is another type of such memory. SUMMARY

[0003] One or more embodiments of the invention provide a device comprising: a logic chip that has a plurality of first silicon vias (TSVs); and a core chip on the logic chip that has a plurality of second TSVs, where the number of first TSVs in the logic chip differs from the number of second TSVs in the core chip.

[0004] One or more embodiments of the invention provide a device comprising: a logic chip and a core chip, each having a plurality of silicon vias (TSVs), wherein at least one of the logic chip and the core chip has a TSV-free area, and the number of TSVs in the TSV-free area in one of the logic chip and the core chip is smaller than the number of TSVs in another of the logic chip and the core chip.

[0005] One or more embodiments of the invention provide a device comprising: a logic chip, comprising: a plurality of first conductive multi-level structures; a plurality of first silicon vias (TSVs) electrically connected to the first conductive multi-level structures; and a plurality of first bumps electrically connected to the first TSVs; and a plurality of core chips on the logic chip, each of which comprises: a plurality of second conductive multi-level structures; a plurality of second TSVs electrically connected to the second conductive multi-level structures; and a plurality of second bumps electrically connected to the second TSVs, whereby at least one of the logic chip and the core chip has a plurality of TSV-free areas where no TSVs are intended, and The TSV-free areas have a plurality of dummy bumps instead of at least one of the first bumps and the second bumps. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows an example of at least one part of a storage device comprising a logic chip and a plurality of core chips in a cross-sectional view, according to an embodiment of the invention. Fig. Figure 2 shows an example of at least one part of a storage device comprising a logic chip and a plurality of core chips, in an enlarged cross-sectional view, according to an embodiment of the invention. Fig. Figure 3 shows an example of at least one part of a storage device comprising a logic chip and a plurality of core chips in a cross-sectional view, according to an embodiment of the invention. Fig. 4A and Fig. Figure 4B shows an example of at least one part of a logic chip and a core chip, in a top view, according to an embodiment of the invention. Fig. Figure 5 shows an example of a structure with a frontside bump and TSVs, in a cross-sectional view, according to an embodiment of the invention. Fig. Figure 6 shows an example of at least one part of a storage device comprising a logic chip and a plurality of core chips in a cross-sectional view, according to an embodiment of the invention. Fig. 7A and Fig. Figure 7B shows an example of at least one part of a logic chip and a core chip, in a top view, according to an embodiment of the invention. Fig. Figure 8 shows an example of a schematic configuration of a semiconductor system according to an embodiment of the invention. DETAILED DESCRIPTION

[0006] Various embodiments of the invention are described in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects in which embodiments of the invention can be realized. These embodiments are described in sufficient detail to enable those skilled in the art to put the invention into practice. Other embodiments may also be used, and structural, logical, and electrical modifications may be made without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, since some of the disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

[0007] In the description, common or related elements and elements that are substantially the same are designated with the same reference numerals, and descriptions thereof may be reduced or omitted. In the drawings, some of the identical reference numerals for identical or substantially the same elements may be omitted for the sake of clarity. In the drawings, the dimensions and dimensional ratios of the individual units do not necessarily correspond to the actual dimensions and dimensional ratios in the embodiments.

[0008] According to some embodiments of the invention, a semiconductor device, such as a memory device, and another semiconductor device, such as a processor, can be provided on a packing substrate. In some embodiments, a memory device can be dynamic random-access memory (DRAM), high-bandwidth memory (HBM), or a hybrid memory cube (HMC). In some embodiments, a processor can be a central processing unit (CPU), a graphics processing unit (GPU), a memory controller, or the like. In some embodiments, an interposer can be provided between the semiconductor devices and the packing substrate. The semiconductor devices can be coupled to the interposer via external connections, such as bumps or micro-bumps. The external connections can form electrodes between the semiconductor devices and the interposer.The interposer can, for example, be stacked on the packing substrate and coupled to it using solder balls.

[0009] According to some embodiments of the invention, a semiconductor device can have a layered structure in which a plurality of core chips (or core components) are stacked with another logic chip (or logic component). The logic chip can also be referred to as a base logic chip. The logic chip can include an interface chip (IF chip) (or interface component). The logic chip can be coupled to an interposer via external connections. In some embodiments, the core chips and the logic chip can be semiconductor chips, each containing semiconductor substrates, such as silicon substrates (Si substrates), and further circuitry, such as a command circuit, a control circuit, and a buffer circuit.In some embodiments, each individual chip can also be referred to as a semiconductor device, and a plurality of chips form a layered or stacked structure of multiple semiconductor devices. In some embodiments, each of the core chips comprises a plurality of wiring layers, such as metal layers, which are provided, for example, by a back-end-of-line (BEOL) process and / or a middle-of-line (MOL) process on the semiconductor substrate. The wiring layers can be stacked and interconnected via contacts, such as conductive contacts. In some embodiments, the core chips can be arranged in an upward-facing manner, with a topmost wiring layer facing upward beneath the wiring layers of each chip.In some embodiments, the core chips may be provided in a downward-facing manner, with a top wiring layer pointing downwards beneath the wiring layers of each chip.

[0010] In the case of a storage device, the majority of core chips can comprise a plurality of memory chips (or memory modules) stacked on the base logic chip. The number of memory chips can be four or eight, but is not limited to these. Each memory chip can contain a memory array for storing data and also include circuitry for performing memory operations, such as read and write operations.

[0011] In some embodiments, the multiple core chips and the logic chip can be coupled by one or more conductive multi-level structures and one or more conductive vias. The logic chip can provide one or more interfaces that send signals to the core chips and / or receive signals from the core chips. The signals can be external signals transmitted by the logic chip. The conductive multi-level structure and the conductive vias can be electrically connected to each other and to the logic chip, and can also provide input / output (I / O) lines between the core chips and the logic chip. The conductive multi-level structures can include multi-level wiring and multi-level contacts that are electrically interconnected. The multi-level wiring can comprise multiple conductive (e.g., metallic) connections across several layers.The multi-level contacts can include conductive contact connectors in multiple layers. The conductive multi-level structures can optionally include other conductive elements, components, substructures, and the like. The conductive vias can be silicon vias (TSVs). The TSVs can be provided to the core chips and the logic chip, vertically penetrating the respective chips, including their semiconductor substrates, in the respective layers. Bumps can also be provided between adjacent chips in upper and lower layers. The bumps can be aligned with the TSVs and with at least one part (for example, the connectors) of the conductive structures in a horizontal plane. The TSVs, the bumps, and the conductive structures provide electrical paths to electrically connect or couple the adjacent chips.

[0012] The TSVs of the respective chips can be aligned with each other to form TSV columns or TSV supports that extend vertically as connectors, providing connections between the chips in upper and lower layers. The TSV columns can provide the I / Os between the chips. In some embodiments, in the case of a horizontal plane with an XY coordinate plane containing an X-axis and a Y-axis perpendicular to each other, a TSV of a chip in an upper layer can have the same (or substantially the same, within reasonable tolerances in manufacturing, measurement, etc.) X-axis and Y-axis coordinates as another TSV of a different chip in an adjacent lower layer. The two TSVs thus traverse the front and back faces of the two chips along a vertical plane perpendicular to the horizontal plane at the same (or substantially the same) XY coordinates.The bumps can also have the same (or substantially the same) XY coordinates as the corresponding TSVs in the horizontal plane. As described in detail here with reference to the accompanying drawings, in some embodiments, no TSVs may be provided in certain areas within the chips or between adjacent chips.

[0013] Fig. Figures 1-3 show an example of at least one part of a storage device 100, comprising a logic chip LD and a plurality of core chips CDs (CD0-CD3) in a cross-sectional view or an enlarged cross-sectional view, according to some embodiments of the invention. The logic chip LD is provided on a substrate 101 and attached to it by an adhesive layer 102. The substrate can comprise a silicon substrate or a glass substrate. The plurality of core chips CDs are stacked on the logic chip LD, forming a stacked or layered structure in a vertical direction (or, for example, in a direction along a Z-axis shown in the drawing). The core chips CDs are stacked with their front faces downwards. Although four core chips CD0-CD3 are shown in the drawing, the number of core chips is not limited to this.

[0014] The logic chip LD has a plurality of TSVs (also called first TSVs) 103a. Each of the plurality of core chips CDs has a plurality of TSVs (also called second TSVs) 103b. The first TSVs 103a and the second TSVs 103b can be collectively referred to as TSVs 103. The TSVs 103 are aligned with each other and provide electrical paths between adjacent lower and upper chips in the vertical direction.

[0015] Bumps 104a and 104b are provided between the adjacent TSVs 103. Bumps 104a are located on the topmost layers of the respective core chips CDs. Bumps 104b are located on the bottommost layers of the respective core chips CDs. In the example where the core chips CDs are stacked with their front faces down, bumps 104a and 104b can also be referred to as front bumps and back bumps, respectively. The front bumps 104a are at least electrically coupled or connected to the topmost metal wiring (or the topmost metal wiring layers) of the core chips CDs. The topmost metal wiring can be part of conductive multi-level structures of the respective core chips CDs. The conductive multi-level structures contain a plurality of conductive multi-level wirings (such as metal wirings) and a plurality of conductive multi-level contacts (such as contact plugs), as shown.The wiring and contacts are electrically interconnected to form conductive paths within the respective core chips CDs. The logic chip LD may include conductive multi-level structures identical or similar to those of the core chips CDs. The front bumps 104a may be part of the conductive multi-level structures or at least electrically connected to them. The rear bumps 104b are electrically connected to the front bumps 104a and also to the ends of the TSVs 103. Each end can be referred to as a bottom end, which, in the front-facing stacking diagram, is located on the top of each TSV 103. Through the front bumps 104a and the rear bumps 104b, the adjacent core chips CDs in the bottom and top stack layers are electrically interconnected.The front bumps 104a and the rear bumps 104b are aligned with the TSVs 103a and 103b. The front bumps 104a, the rear bumps 104b, and the TSVs 103a and 103b form vertical paths to electrically couple or connect the adjacent chips CDs and LD. The bumps 104a and 104b may, for example, comprise copper (Cu), nickel (Ni), tin (Sn), indium (In), or a combination thereof, but are not limited to these materials.

[0016] The logic chip LD includes one or more regions 110 where no TSVs 103a are provided. Because of these regions 110, the logic chip LD has a smaller number of TSVs 103a than the core chips CDs, and the logic chip LD has a lower density of TSVs 103 in the corresponding regions than the core chips CDs. These regions 110 can be referred to as TSV-free or TSC-depleted regions. The number of TSVs 103a in the logic chip LD is therefore smaller than the number of TSVs 103b in each of the core chips CDs. This allows for further variations and greater flexibility regarding the number of TSVs 103 between the logic chip LD and the core chips CDs.

[0017] In an HBM, for example, a logic chip has a different footprint than the core chips. The core chips may require a significantly larger number of power and ground TSVs for adequate power supply. A larger number of power and ground TSVs has a greater impact on the logic chip due to constraints on the placement of the required circuitry at specific locations on the logic chip. The present embodiments and examples achieve both improved power supply to the core chips and better circuit placement on a logic chip by reducing the number of TSVs on the logic chip compared to the number on each of the core chips, resulting in a less dense TSV configuration on the logic chip. The improved power supply leads to better performance of a memory device.Improved circuit placement also leads to better performance and therefore lower costs for a storage device.

[0018] Fig. 4A and Fig. Figure 4B shows an example of at least one part of the logic chip LD and the core chip CD of the storage device 100 in a top view, according to an embodiment of the invention. The TSVs 103a and 103b can be provided in peripheral regions adjacent to the logical array regions 120 and the cell array regions 130 in the logic chip LD and in the core chip CD. Some peripheral regions can be located, in a top view as shown in the drawing, on the left and right sides as well as on the top and bottom sides of the array regions 120 / 130. Some peripheral regions can be located in the central regions of the chips where the array regions 120 / 130 are not provided, in a top view as shown in the drawing.The edge regions of the logic chip LD may contain various circuits and elements, such as built-in self-test circuits (BIST circuits), anti-fuse circuits, voltage regulators, power supply units, and amplifiers. While some of the edge regions of the logic chip LD have sufficient space for the TSVs 103a, others may have less TSV space than the corresponding regions in the core chip CD. For example, the upper edge region above array region 120 in the logic chip LD in the Y direction, as shown in the drawing, may have a smaller TSV space than the corresponding region in the core chip CD. According to some embodiments of the invention, the number of TSVs 103a in this upper edge region of the logic chip LD may be significantly reduced, for example, to half, one-third, or less than the number of TSVs 103b in the corresponding region of the core chip CD.Such a low density or thinning of the TSVs 103a effectively improves the IR drop by, for example, a few mV or more. Furthermore, a significant improvement in TSV electromigration is achieved. The TSV-free region(s) can, if necessary, be located in other peripheral regions of the logic chip LD.

[0019] With renewed reference to Fig. In areas 1 to 3 with no or no back pressure (TSV) or low back pressure (TSV) properties, rear dummy bumps 104c are provided instead of rear bumps 104b. The rear dummy bumps 104c can, for example, be thermal bumps. The structure of each of the rear dummy bumps 104c can be the same as, or substantially the same as, that of a thermal bump. The thermal bump can function as a solid-state thermal bump, adding thermal management functionality to the surface of the chip. The structure of the thermal bump can be any suitable conventional structure. The rear dummy bumps 104c can function like, or similarly to, the thermal bumps. In a case where the backside bump 104b is an Sn / Cu bump, the backside dummy bump 104c, which is not an Sn / Cu bump, forms a metal barrier between the frontside bump 104a and the silicon (Si) of a semiconductor chip substrate and effectively reduces the risk of copper diffusion.In a case where the front bump 104a is a Ni) / Sn bump, no rear dummy bumps 104c need to be provided.

[0020] With reference to Fig. 3. One or more ground voltage bumps (VSS bumps) 105a, one or more power supply bumps (PWR bumps) 105b, and one or more signal bumps (SIG bumps) 105c may be provided, connecting a top layer of the front-facing stacked logic chip LD to the carrier layer 101. Such bumps 105a, 105b, and 105c may be micro-bumps. The TSV-free areas 110 (110a and 110b) may then be provided with respect to at least one of the VSS bumps 105a and at least one of the PWR bumps 105b. The TSV-free areas 110a and 110b effectively reduce the risk of electromigration and contribute to the optimization of the VSS and PWR current flow.

[0021] Fig. Figure 5 shows an example of a configuration of the front bump 104a and the TSVs 103 in a cross-sectional view according to an embodiment of the invention. Conductive multi-level structures 106 are also provided, which are electrically connected to the corresponding TSVs 103 and the front bump 104a. In this example, the number of front bumps 104 is smaller than the number of TSVs 103, in contrast to the examples in Figure 5. Fig. 1-3, where the earlier and later numbers are the same. This bump TSV configuration helps to further optimize the current flow of the TSVs 103.

[0022] Fig. Figure 6 shows a cross-sectional view of at least one part of a storage device 600, comprising a logic chip LD and a plurality of core chips CDs (CD0-CD3), according to an embodiment of the invention. The logic chip LD, the core chips CDs, a carrier layer 601, an adhesive layer 602, a plurality of TSVs 603a and 603b, a plurality of front bumps 604a, and a plurality of back bumps 604b are identical or substantially identical to the logic chip LD, the core chips CDs, the carrier layer 101, the adhesive layer 102, the TSVs 103a and 103b, the front bumps 104a, and the back bumps 104b. The chips LD / CD have conductive multi-level structures, which are similar to those of the Fig. The chips shown in section 1 are identical or similar to the LD / CD chips shown.

[0023] In the Fig. In the example shown in Figure 6, at least one of the core chips CDs has one or more regions 610 where the TSVs 603b are not provided. Because of the regions 610, the core chip CD has a smaller number of TSVs 603b than the logic chip LD has a smaller number of TSVs 603a, and the core chip CD has a lower density of TSVs 603 in the corresponding regions than the logic chip LD. These regions 610 can be referred to as TSV-free or TSV-depleted regions. The number of TSVs 603b in the core chip CD is therefore smaller than the number of TSVs 603a in the logic chip LD. This allows for further variations and greater flexibility regarding the number of TSVs 603 between the logic chip LD and the core chips CDs, especially for an HBM, which may have different footprints between a logic chip and a core chip. Furthermore, the power supply between the chips, and thus the device's performance and cost, is effectively improved.

[0024] In the TSV-free areas 610 of the core chips CDs, front-side dummy bumps 604d are provided instead of front-side bumps 604a. The front-side dummy bumps 604d can, for example, be thermal bumps. The structure of each of the front-side dummy bumps 604d can be the same as, or substantially the same as, that of a thermal bump. The thermal bump can function as a solid-state thermal bump and add a thermal management function to the surface of the chip. The structure of the thermal bump can be any suitable conventional structure. The front-side dummy bumps 604d can function like, or similarly to, the thermal bumps. In other examples, in addition to or as an alternative to the front dummy bumps 604d, rear dummy bumps similar to the rear dummy bumps 104c may be provided in the TSV-free areas 610 in the core chips CDs.

[0025] Fig. 7A and Fig. Figures 7B each show an example of at least one part of the logic chip LD and the core chip CD of the storage device 600 in a top view, according to an embodiment of the invention. Similar to the one in Fig. 4A and Fig. In the example shown in Figure 4B, the TSVs 603a and 603b can be located in the boundary regions next to the logical array regions 620 and the cell array regions 630 in the logic chip LD and the core chip CD.

[0026] The difference to the example in Fig. 4A and Fig. Feature 4B consists of the upper boundary region of the core chip CD having a TSV-free or TSC-depleted region 603b. By removing or thinning the TSVs 603b, the number of TSVs 603a appears to be increased compared to the number of TSVs 603b. This effectively improves the power supply, which in turn improves the IR drop, for example, by several mV or more. Furthermore, a significant improvement in TSV electromigration is achieved. The TSV-free region(s) can optionally also be provided in other boundary regions of the core chip CD.

[0027] With reference to Fig. 7A The logic chip LD can have a greater number of TSVs 603a than the TSVs 603b in the core chip CD. For example, at least one of the edge regions (such as the right and left edge regions shown in the diagram) can have a higher density of TSVs 603 than the corresponding region in the core chip CD. This is because there is more space available in the edge regions of the logic chip LD than in the core chip CD. This allows for greater flexibility in the TSV arrangement.

[0028] Fig.Figure 8 shows an example of a schematic configuration of a semiconductor system 800 according to an embodiment of the invention. The semiconductor system 800 comprises a device, which in one embodiment of the invention is a storage device 801. The semiconductor system 800 can also include a central processing unit (CPU) and a memory controller 804, which can be a controller chip, on an interposer 805 on a package substrate 808. The interposer 805 can have one or more power lines 810 that can supply a voltage from the package substrate 808. The interposer 805 can have a plurality of channels 811 that can connect the CPU and the memory controller 804 and the semiconductor storage device 801. For example, the semiconductor storage device 801 can be a dynamic random-access memory (DRAM).The 804 memory controller can provide a clock signal and a command signal, and can also send and receive data signals. Multiple 811 channels can transmit the data signals between the memory controller and the 801 memory device. The 801 memory device can contain multiple 802 chips (or modules), including at least one 803 interface chip (IF chip or IF module) and multiple 806 memory core chips (or memory modules) stacked on top of each other. The number of 806 memory core chips is not limited to four and can be greater or lesser as needed. Each 806 memory core chip can include multiple memory cells and circuitry that accesses the memory cells. The memory cells can be, for example, DRAM cells. The memory cells can be arranged in an array.The memory device 801 can have conductive vias 807 that couple the IF chip 803 and the memory core chips 806 by penetrating the IF chips 803 and the memory core chips 806. The conductive vias 807 can be TSVs. The TSVs can be TSVs 103 or TSVs 603. The IF chip 803 can be coupled to the interposer 805 via intermediate connections 809. The intermediate connections 809 can, for example, be micro-bumps with a bump spacing of less than approximately 100 micrometers and can be exposed on an outside surface of the IF chip 803. A portion of each of the intermediate connections 809 can be coupled to the one or more power lines 810. Another section of each of the intermediate connections 809 can be coupled to one or more of the channels 811.

[0029] DRAM is only one example of the memory device 801, and the embodiments and descriptions above are not intended to be limited to DRAM. Memory devices other than DRAM, such as static random-access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random-access memory (MRAM), and phase-change memory, can also be used as the memory device 801. Furthermore, devices other than memory, including logic ICs such as a microprocessor and an application-specific integrated circuit (ASIC), are also applicable as semiconductor devices according to the present embodiments.

[0030] Although various embodiments of the invention have been described in detail, it will be clear to those skilled in the art that the embodiments of the invention can be extended beyond those specifically described to other alternative embodiments and / or uses, modifications, and equivalents thereof. Furthermore, other modifications within the scope of the invention will be readily apparent to those skilled in the art based on the described embodiments. It is also conceivable that various combinations or subcombinations of the specific features and aspects of the embodiments can be produced and still fall within the scope of the invention. It is understood that various features and aspects of the embodiments can be combined with one another or exchanged for one another to form different embodiments.Therefore, the scope of the invention should not be limited by the special embodiments described above. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 508,498

[0001]

Claims

Device comprising: a logic chip having a plurality of first silicon vias (TSVs); and a core chip on the logic chip having a plurality of second TSVs, wherein a number of first TSVs in the logic chip differs from a number of second TSVs in the core chip. Device according to claim 1, wherein the number of first TSVs in the logic chip is less than the number of second TSVs in the core chip. Device according to claim 2, wherein the logic chip has a TSV-free area. Device according to claim 3, wherein the TSV-free area has a rear dummy bump. Device according to claim 4, wherein the rear dummy bump has the same structure as a thermal bump. Device according to claim 1, wherein the number of second TSVs in the core chip is less than the number of first TSVs in the logic chip. Device according to claim 6, wherein the core chip has a TSV-free area. Device according to claim 7, wherein the TSV-free area has a frontal dummy bump. Device according to claim 8, wherein the front dummy bump has the same structure as a thermal bump. Device according to claim 1, wherein a number of front-side bumps in the logic chip and / or in the core chip is less than the number of first TSVs and / or the number of second TSVs. Device according to claim 1, wherein the first and second TSVs comprise: current TSVs and / or mass TSVs. Device according to claim 1, wherein the logic chip comprises an interface chip, and the core chip comprises a plurality of core chips stacked on the logic chip. Device according to claim 1, wherein the core chip comprises a memory chip. Device according to claim 1, wherein the device comprises a storage device. Device according to claim 1, wherein the device further comprises a plurality of conductive multi-level structures, each comprising a plurality of multi-level wiring and a plurality of multi-level contacts electrically connected to each other, the logic chip and the core chip, with the TSVs thereon, electrically connected to the conductive multi-level structures, and at least one of the logic chip and the core chip has a TSV-free area in which no TSVs are provided. Device according to claim 15, wherein the device further comprises a plurality of bumps electrically connected to the conductive multi-level structures and the TSVs, and the TSV-free area comprises a plurality of dummy bumps instead of the plurality of bumps. Device comprising: a logic chip and a core chip, each having a plurality of silicon vias (TSVs), wherein at least one of the logic chip and the core chip comprises a TSV-free region, and the number of TSVs in the TSV-free region in one of the logic chip and the core chip is less than the number of TSVs in another of the logic chip and the core chip. Device according to claim 17, wherein the TSV-free area has a dummy bump, and the dummy bump is a thermal bump. Device according to claim 17, wherein the device further comprises: a plurality of conductive multi-level structures, each comprising a plurality of multi-level wiring and a plurality of multi-level contacts electrically connected to one another; and a plurality of bumps electrically connected to the conductive multi-level structures, wherein the logic chip and the core chip, with the TSVs on them, are electrically connected to the conductive multi-level structures via the bumps, and the TSV-free area has a plurality of dummy bumps instead of the bumps. Device comprising: a logic chip, comprising: a plurality of first conductive multi-level structures; a plurality of first silicon vias (TSVs) electrically connected to the first conductive multi-level structures; and a plurality of first bumps electrically connected to the first TSVs; and a plurality of core chips on the logic chip, each of the core chips comprising: a plurality of second conductive multi-level structures; a plurality of second TSVs electrically connected to the second conductive multi-level structures; and a plurality of second bumps electrically connected to the second TSVs, wherein at least one of the logic chip and the core chip has a plurality of TSV-free regions where no TSVs are provided, and the TSV-free regions have a plurality of dummy bumps instead of at least one of the first bumps and the second bumps.

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