PQC and SM2 / 9 cooperative operation cryptographic chip and method based on RISC-V architecture

Abstract

The invention provides a PQC and SM2 / 9 cooperative operation cryptographic chip and method based on an RISC-V architecture, and belongs to the technical field of cryptographic security. The chip comprises an RISC-V core and a configurable password collaborative operation unit, wherein the configurable password collaborative operation unit comprises a collaborative control state machine and a unified operation unit capable of being dynamically reconfigured. The method comprises the following steps: receiving and decoding a single cooperative operation instruction from an RISC-V core through a cooperative control state machine, and obtaining operation data feature information; the data length and the security level identification are extracted, and the optimal collaborative operation process is selected in a self-adaptive mode through comparison with a preset threshold value; and finally, dynamically configuring and scheduling a unified operation unit according to the selected process, and completing cooperative operation of the post-quantum cryptography algorithm and the SM2 / SM9 algorithm in an atomization mode. According to the method, deep fusion and intelligent scheduling of the two algorithms are realized on the hardware level, and the efficiency, the resource utilization rate and the safety of cooperative operation are improved.

Description

Technical Field

[0001] This invention relates to the field of cryptographic security technology, and in particular to a PQC and SM2 / 9 collaborative cryptographic chip and method based on the RISC-V architecture. Background Technology

[0002] With the evolution of quantum computing technology, existing public-key cryptography systems based on large number factorization and the discrete logarithm problem face potential threats, driving post-quantum cryptography to become a global research focus, and related standardization efforts have been launched in various countries. Meanwhile, commercial cryptographic algorithms such as SM2 and SM9, widely used in my country, continue to play a crucial role in various critical systems. In the foreseeable transition phase of cryptographic systems, practical applications will require systems to be compatible with and able to operate collaboratively with both post-quantum cryptographic algorithms and current national cryptographic algorithms, in order to achieve a balance between long-term security and current compliance requirements.

[0003] Current technical approaches for achieving collaborative computation between two types of algorithms mainly include discrete accelerators, instruction set extensions, and dual-core isolation or pure software libraries. Discrete accelerator solutions integrate independent hardware modules to process different algorithms, but when executing complex tasks, they frequently rely on the main processor for scheduling and data transfer, resulting in low efficiency and an inability to share underlying computing resources. While instruction set extensions can accelerate specific algorithms, they struggle to achieve deep collaboration across cryptographic systems at the architectural level, and software scheduling overhead remains significant. Dual-core isolation or pure software implementations, on the other hand, have inherent limitations such as high interaction latency, prominent performance bottlenecks, and weak side-channel protection.

[0004] In summary, existing solutions generally lack native support for efficient, flexible, and secure collaboration between post-quantum cryptography and Chinese national cryptographic algorithms at the hardware architecture level. The fundamental problem lies in physically or logically separating the two types of cryptographic tasks, relying on complex scheduling and data transfer at the software layer, thus introducing significant performance losses, low resource utilization, and blurred security boundaries. Therefore, the industry urgently needs an innovative technical solution that can achieve deep hardware-level integration and adaptive collaboration of the two algorithms, starting from the processor instruction set and microarchitecture level. Summary of the Invention

[0005] The purpose of this invention is to provide a PQC and SM2 / SM9 collaborative cryptographic chip and method based on the RISC-V architecture. It aims to solve the problems of large software scheduling overhead, low hardware resource utilization, and easy exposure of sensitive data when post-quantum cryptography algorithms and national cryptographic SM2 / SM9 algorithms are used in collaborative operation from the processor microarchitecture level. It realizes the deep integration and collaborative execution of the two types of algorithms at the hardware level in an adaptive, efficient and secure manner.

[0006] To achieve the above objectives, this invention provides a PQC and SM2 / 9 collaborative cryptographic chip based on a RISC-V architecture, comprising: The RISC-V core is configured to issue single cooperative computing instructions carrying computational data characteristic information. The configurable cryptographic cooperative computing unit is directly coupled to the RISC-V core. The configurable cryptographic cooperative computing unit includes a cooperative control state machine and a dynamically reconfigurable unified computing unit. The cooperative control state machine is configured to perform the following operations: Receive and decode a single cooperative operation instruction from the RISC-V core to obtain the characteristic information of the operation data; Based on the comparison result of at least one parameter in the computational data feature information with the corresponding preset threshold, a composite cryptographic operation process is adaptively selected from multiple pre-stored hardware execution processes, wherein each composite cryptographic operation process defines a specific cooperative execution logic between the post-quantum cryptographic algorithm operation and the SM2 or SM9 algorithm operation. Based on the selected complex cryptographic operation process, a microcontroller sequence is generated and a unified operation unit is scheduled to complete the execution of the selected complex cryptographic operation process in an atomic manner and output the operation result.

[0007] This invention also provides a PQC and SM2 / 9 collaborative operation method based on a RISC-V architecture, executed by a configurable cryptographic collaborative operation unit in a cryptographic chip. The configurable cryptographic collaborative operation unit includes a collaborative control state machine and a dynamically reconfigurable unified operation unit. The method includes: Step S1: The cooperative control state machine receives a single cooperative operation instruction from the RISC-V core, which carries or points to the characteristic information of the operation data; Step S2: The collaborative control state machine decodes a single collaborative operation instruction and obtains the operation data feature information; Step S3: The collaborative control state machine extracts the data length and security level identifier from the computational data feature information, compares the data length with a first preset threshold, and compares the security level identifier with a second preset threshold. Based on the comparison results, it adaptively selects a predefined collaborative computation process. The selected collaborative computation process defines the execution order and resource sharing strategy between the post-quantum cryptography algorithm operation and the SM2 or SM9 algorithm operation. Step S4: The collaborative control state machine generates corresponding control signals according to the selected collaborative operation process to dynamically configure the computing mode of the unified operation unit, and schedules the unified operation unit to execute, completing the collaborative operation of the quantum cryptography algorithm and the SM2 / SM9 algorithm in an atomic manner and outputting the result.

[0008] Preferably, step S2 specifically includes: Step S21: The cooperative control state machine decodes the opcode of a single cooperative operation instruction to determine the instruction type; Step S22: Based on the instruction type, read the operation data characteristic information from the register or memory address specified by the single cooperative operation instruction.

[0009] Preferably, in step S3, adaptively selecting a predefined collaborative computation process based on the comparison results includes: If the data length is lower than the first preset threshold, the first collaborative operation process is selected. After the first collaborative operation process is defined, the quantum cryptography algorithm operation and the SM2 / SM9 algorithm operation are executed sequentially. If the data length is higher than or equal to the first preset threshold and the security level indicator is lower than the second preset threshold, then the second collaborative operation process is selected. After the second collaborative operation process is defined, the quantum cryptography algorithm operation and the SM2 / SM9 algorithm operation are executed in parallel. If the security level indicator is higher than or equal to the second preset threshold, the third collaborative operation process is selected. The third collaborative operation process is defined as inserting anti-side channel interference operation between the post-quantum cryptography algorithm operation and the SM2 / SM9 algorithm operation.

[0010] Preferably, step S4 specifically includes: Step S41: The cooperative control state machine generates a microcontrol sequence containing at least one first cooperative operation instruction and at least one second cooperative operation instruction according to the selected cooperative operation process; wherein, the first cooperative operation instruction corresponds to the post-quantum cryptography algorithm operation, and the second cooperative operation instruction corresponds to the SM2 or SM9 algorithm operation. Step S42: The cooperative control state machine schedules and executes each cooperative operation instruction sequentially according to the micro-control sequence; wherein, the execution of each cooperative operation instruction includes: generating configuration information according to the instruction type of the cooperative operation instruction to configure the unified operation unit, and then triggering the unified operation unit to complete the specified cryptographic calculation; Step S43: After all the cooperative operation instructions in the microcontroller sequence have been executed, the cooperative control state machine collects the final operation result and returns.

[0011] Preferably, when executing the first cooperative operation process, step S42 specifically involves: sequentially executing the first cooperative operation instruction and the second cooperative operation instruction, and during the execution of the first cooperative operation instruction and the second cooperative operation instruction, dynamically reconfiguring the unified operation unit through configuration information to support the different arithmetic operation modes corresponding to the post-quantum cryptography algorithm and the SM2 / SM9 algorithm in turn.

[0012] Preferably, when executing the second collaborative operation process, step S42 specifically involves: executing the first collaborative operation instruction and the second collaborative operation instruction in parallel; the first collaborative operation instruction is scheduled and executed by the first computing channel, and the second collaborative operation instruction is scheduled and executed by the second computing channel; the first computing channel and the second computing channel are configured to independently access the storage resources within the configurable cryptographic collaborative operation unit.

[0013] Preferably, when executing the third cooperative operation process, step S42 specifically involves inserting a disturbance operation controlled by the cooperative control state machine between the sequential execution of the first cooperative operation instruction and the second cooperative operation instruction; Interference operations include: Calculate interference intensity parameters ,in , For security level identification, The second preset threshold, For data length, The preset data length baseline value; Based on interference strength parameters Intermediate results generated by the first cooperative operation instruction Generate random delay duration ,in , For the preset hash function, The preset delay range, Minimum delay time, For splicing operations; Waiting for random delay time ; For intermediate results conduct The scrambling operation consists of rounds of scrambling. , This is the preset maximum number of scrambling rounds.

[0014] Preferably, the single cooperative operation instruction issued in step S1 is an atomic instruction, and steps S2 to S4 are completed atomically by the cooperative control state machine without the intervention of the RISC-V core.

[0015] Preferably, during the execution of step S42, the output data generated by the previously executed cooperative operation instruction is directly used as the input data for the subsequently executed cooperative operation instruction. The output data is transmitted through the shared memory or dedicated data path inside the configurable cryptographic cooperative operation unit, without passing through the general-purpose registers of the RISC-V core or the main memory of the chip system.

[0016] Therefore, the present invention employs the aforementioned RISC-V architecture-based PQC and SM2 / 9 collaborative cryptographic chip and method, and the beneficial technical effects are as follows: (1) This invention encapsulates the complex cross-cryptographic computation that originally required multiple software scheduling and frequent data transfer into a process triggered by a single instruction and completed atomically within the hardware by using a configurable cryptographic collaborative computation unit and a collaborative control state machine. This not only eliminates the software scheduling and bus transmission overhead of the traditional discrete accelerator mode, but also achieves a significant systematic improvement in key indicators such as overall throughput, response latency and energy efficiency ratio of PQC and national cryptographic SM2 / SM9 through adaptive selection of the optimal collaborative strategy (sequential, parallel or security hardening mode) and dynamic configuration of hardware resources according to data characteristics.

[0017] (2) The unified computing unit proposed in this invention can be dynamically reconfigured to support the PQC algorithm or the SM2 / SM9 algorithm according to real-time requirements, realizing time-division multiplexing of the underlying arithmetic logic (such as the large number modular arithmetic unit) between the two types of algorithms. Compared with the traditional discrete accelerator solution that fixes two independent hardware resources for the two types of algorithms, this invention reduces the number of dedicated computing units, reduces the silicon area and static power consumption of the chip, and optimizes the computing density and energy efficiency ratio while ensuring the same or even better throughput.

[0018] (3) By atomically executing the composite operation process within the hardware, this invention ensures that sensitive data such as keys and intermediate results flow only within a dedicated path or shared cryptographic memory within the configurable cryptographic collaborative operation unit, avoiding their exposure to the system bus or general memory, thus fundamentally reducing the attack interface. Simultaneously, the adaptive anti-side-channel interference process (third collaborative operation process) for high-security scenarios can dynamically inject random delays and data scrambling based on security level and data characteristics, effectively disrupting side-channel information such as power consumption and electromagnetic interference. This achieves an intrinsic hardware fusion of algorithm collaboration and security protection, improving the overall robustness of the solution. Attached Figure Description

[0019] Figure 1 This is an architecture diagram of the PQC and SM2 / 9 collaborative cryptographic chip based on the RISC-V architecture of this invention; Figure 2 A flowchart of the PQC and SM2 / 9 collaborative computing method based on RISC-V architecture; Figure 3 This is an adaptive decision logic diagram. Detailed Implementation

[0020] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0022] Example 1 This embodiment provides a cryptographic chip based on the Reduced Instruction Set Computing (RISC) architecture and the fifth-generation open standard instruction set (RISC-V) for post-quantum cryptography (PQC) and SM2 / 9 cooperating, and its application method in a specific cryptographic task—"hybrid key encapsulation and data signing." This task requires: first, encapsulating a session key using a post-quantum cryptography algorithm (taking CRYSTALS-Kyber as an example); then, signing a piece of business data using the national standard SM2 algorithm; and the entire process must be efficient and secure.

[0023] 1. Chip hardware implementation.

[0024] like Figure 1 As shown, the cryptographic chip in this embodiment adopts a system-on-a-chip (SoC) design, mainly including: RISC-V core: Uses a 64-bit RISC-V processor core (such as C906) that supports the IMAFD instruction set as the main control core.

[0025] Configurable Cryptographic Cooperative Processing Unit (C3PU): Connected to the RISC-V core via a tightly coupled dedicated interface, it is the core of this invention. Its specific hardware implementation includes: Cooperative Control State Machine (CSM): Composed of hard-wired logic and microcode memory, it is responsible for instruction decoding, process decision-making and scheduling.

[0026] Unified Computing Unit (UIU): The core is a reconfigurable... The large arithmetic logic array of the bit-modular multiplication-accumulation can be reconfigured via the mode configuration register to perform NTT (number-theoretic transformation) friendly modular multiplication-accumulation operations on the polynomial ring required for the Kyber algorithm, or Montgomery modular multiplication operations on the prime field required for the SM2 algorithm.

[0027] Reconfigurable Sample and Hash Unit (RHU): Integrates the SM3 hash hardware engine and a configurable random sampler that can generate random numbers required for SM2 signatures as well as long-tailed noise polynomials required for the Kyber algorithm.

[0028] Shared cryptographic memory (SPM): A 32KB tightly coupled memory used to store sensitive data such as keys and intermediate results, accessible only to internal units of the C3PU.

[0029] 2. Implementation of methods and procedures.

[0030] like Figure 2 As shown, the specific steps for completing the above "hybrid key encapsulation and data signing" task are as follows: Step S1: Issuance of instructions.

[0031] The RISC-V core prepares a single cooperative computation instruction named C3.HYBRID_KEM_SIGN. The operand of this instruction points to a task descriptor structure, which contains the computation data characteristic information. Its fields include: : The address that points to the business data to be signed.

[0032] ( ): The length of the business data, which is 1024 bytes in this example.

[0033] ( : The preset security level identifier, which is 3 (high security level) in this example.

[0034] Algorithm parameter pointers: These point to the field parameters of Kyber-768 and SM2, respectively.

[0035] The RISC-V core executes a C3.HYBRID_KEM_SIGN instruction and sends it to the C3PU.

[0036] The single cooperative operation instruction issued in step S1 is an atomic instruction, and steps S2 to S4 are completed atomically by the cooperative control state machine without the intervention of the RISC-V core.

[0037] Step S2: Decoding and Information Acquisition.

[0038] The Cooperative Control State Machine (CSM) within the C3PU captures the instruction.

[0039] Step S21: CSM decoding instruction opcode C3.HYBRID_KEM_SIGN, which identifies this as a composite task type of "PQC encapsulation followed by SM2 signature".

[0040] Step S22: CSM reads the task descriptor from the memory address specified by the instruction based on the instruction type, and obtains the complete task descriptor. ,in , .

[0041] Step S3: Adaptive decision-making process.

[0042] like Figure 3 As shown, the CSM execution decision logic is as follows: The collaborative control state machine extracts the data length and security level identifier from the feature information of the computational data, compares the data length with a first preset threshold, and compares the security level identifier with a second preset threshold. Based on the comparison results, it adaptively selects a predefined collaborative computation process. The selected collaborative operation process defines the execution order and resource sharing strategy between post-quantum cryptography algorithm operations and SM2 or SM9 algorithm operations.

[0043] The predefined collaborative computation process is adaptively selected based on the comparison results, including: If the data length is lower than the first preset threshold, the first collaborative operation process is selected. After the first collaborative operation process is defined, the quantum cryptography algorithm operation and the SM2 / SM9 algorithm operation are executed sequentially. If the data length is higher than or equal to the first preset threshold and the security level indicator is lower than the second preset threshold, then the second collaborative operation process is selected. After the second collaborative operation process is defined, the quantum cryptography algorithm operation and the SM2 / SM9 algorithm operation are executed in parallel. If the security level indicator is higher than or equal to the second preset threshold, the third collaborative operation process is selected. The third collaborative operation process is defined as inserting anti-side channel interference operation between the post-quantum cryptography algorithm operation and the SM2 / SM9 algorithm operation.

[0044] In this embodiment, extraction In , .

[0045] Compare with a preset threshold. Assume a preset first threshold. (bytes), second threshold .

[0046] Application selection rules: ≥ It is true.

[0047] ≥ It is true.

[0048] Therefore, the third cooperative operation process is chosen. This process is defined as follows: first, perform the post-quantum cryptography algorithm operation (Kyber wrapper), then insert the anti-side-channel interference operation, and finally perform the SM2 signature operation.

[0049] Step S4: Process execution and output.

[0050] The collaborative control state machine generates corresponding control signals to dynamically configure the computation mode of the unified computing unit according to the selected collaborative computation process, and schedules the unified computing unit to execute, completing the collaborative computation of the quantum cryptography algorithm and the SM2 / SM9 algorithm in an atomic manner and outputting the result.

[0051] Step S41: The cooperative control state machine generates a microcontrol sequence containing at least one first cooperative operation instruction and at least one second cooperative operation instruction according to the selected cooperative operation process; wherein, the first cooperative operation instruction corresponds to the post-quantum cryptography algorithm operation, and the second cooperative operation instruction corresponds to the SM2 or SM9 algorithm operation. Step S42: The cooperative control state machine schedules and executes each cooperative operation instruction sequentially according to the micro-control sequence; wherein, the execution of each cooperative operation instruction includes: generating configuration information according to the instruction type of the cooperative operation instruction to configure the unified operation unit, and then triggering the unified operation unit to complete the specified cryptographic calculation; Step S43: After all the cooperative operation instructions in the microcontroller sequence have been executed, the cooperative control state machine collects the final operation result and returns.

[0052] When the first cooperative operation process is executed, step S42 specifically involves: sequentially executing the first cooperative operation instruction and the second cooperative operation instruction, and during the execution of the first and second cooperative operation instructions, dynamically reconfiguring the unified operation unit through configuration information to support different arithmetic operation modes corresponding to the post-quantum cryptography algorithm and the SM2 / SM9 algorithm.

[0053] When the second collaborative operation process is executed, step S42 specifically involves: executing the first collaborative operation instruction and the second collaborative operation instruction in parallel; the first collaborative operation instruction is scheduled and executed by the first computing channel, and the second collaborative operation instruction is scheduled and executed by the second computing channel; the first computing channel and the second computing channel are configured to independently access the storage resources within the configurable cryptographic collaborative operation unit.

[0054] When the third cooperative operation process is executed, step S42 specifically involves inserting a disturbance operation controlled by the cooperative control state machine between the sequential execution of the first cooperative operation instruction and the second cooperative operation instruction. Interference operations include: Calculate interference intensity parameters ,in , For security level identification, The second preset threshold, For data length, The preset data length baseline value; Based on interference strength parameters Intermediate results generated by the first cooperative operation instruction Generate random delay duration ,in , For the preset hash function, The preset delay range, Minimum delay time, For splicing operations; Waiting for random delay time ; For intermediate results conduct The scrambling operation consists of rounds of scrambling. , This is the preset maximum number of scrambling rounds.

[0055] During the execution of step S42, the output data generated by the previously executed cooperative operation instruction is directly used as the input data for the subsequently executed cooperative operation instruction. The output data is transmitted through the shared memory or dedicated data path inside the configurable cryptographic cooperative operation unit, without going through the general-purpose registers of the RISC-V core or the main memory of the chip system.

[0056] In this embodiment, the cooperative control state machine controls the hardware to execute the following steps sequentially according to the selected third cooperative operation process: The collaborative control state machine first generates a microcontroller sequence containing three core instructions: the first is a post-quantum cryptography encapsulation instruction, used to perform the Kyber algorithm encapsulation operation and generate the corresponding ciphertext and shared key; the second is a side-channel interference resistance instruction, used to perform security enhancement operations; and the third is a national cryptographic signature instruction, used to digitally sign the specified business data using the SM2 private key.

[0057] The collaborative control state machine then schedules execution sequentially according to this sequence: First, the post-quantum cryptographic encapsulation instructions are executed: the cooperative control state machine loads the configuration vector for post-quantum cryptographic operations into the mode configuration register of the unified operation unit, configuring its computation mode to a number-theoretic transformation mode suitable for polynomial ring operations. Simultaneously, the cooperative control state machine schedules the noisy polynomial required by the reconstructible sampling and hashing unit generation algorithm. Next, the cooperative control state machine controls the unified operation unit to execute the core modular multiplication and accumulation operation, completing the Kyber encapsulation algorithm. The resulting ciphertext and shared key are stored at a designated address in the shared cryptographic memory.

[0058] Next, the anti-side-channel interference command is executed: The cooperative control state machine first calculates the interference strength parameter based on the security level identifier, the second preset threshold, the data length, and the preset data length benchmark value obtained in the aforementioned process decision steps. Then, based on the calculated interference strength parameter and the specific intermediate result data generated by the post-quantum cryptography encapsulation command, a specific number of random delay clock cycles is calculated using a preset hash function and concatenation operation, and with reference to a preset delay range and minimum delay time. The cooperative control state machine controls the hardware to insert the corresponding delay operation. Finally, based on the interference strength parameter and the preset maximum number of scrambling rounds, the number of rounds to scramble the intermediate result data is determined, and the corresponding number of position swap operations are executed.

[0059] Finally, the national cryptographic signature instruction is executed: the cooperative control state machine loads the configuration vector used for the national cryptographic algorithm operation into the mode configuration register of the unified computing unit, dynamically reconfiguring its calculation mode to the prime field Montgomery operation mode suitable for the SM2 algorithm. Business data is loaded from system memory to shared cryptographic memory via direct memory access, and SM3 hash calculation is performed by the reconfigurable sampling and hashing unit. The cooperative control state machine controls the unified computing unit to perform the core scalar multiplication and modular inverse operations required for SM2 signature. During this process, the random numbers required for the signature operation are directly generated by the sampler inside the reconfigurable sampling and hashing unit and provided to the unified computing unit; all intermediate values ​​are processed and temporarily stored in the unified computing unit's internal registers or shared cryptographic memory, ensuring that the data is not exposed to the wider system bus. The final signature result is stored in the shared cryptographic memory.

[0060] After all instructions have been executed, the cooperative control state machine packages the final computation result (including ciphertext and digital signature) from the shared cryptographic memory and notifies the RISC-V core to read it via an interrupt mechanism. The entire process from instruction decoding to result output is autonomously controlled by the cooperative control state machine. After triggering this single cooperative computation instruction, the RISC-V core can process other tasks until it is notified by an interrupt that the result is ready.

[0061] This embodiment specifically demonstrates the following advantages of the present invention: Hardware atomization collaboration: A complex task involving two types of algorithms (Kyber wrapper + SM2 signature) is triggered by a single instruction from the RISC-V core and completed atomically by the C3PU, which greatly reduces the host's burden and improves efficiency.

[0062] Adaptive intelligent scheduling: Based on the specific data length (1024B) and security level (high), CSM automatically selects the third collaborative computing process. While ensuring high performance, it incorporates anti-side channel interference measures to meet high security requirements, thus achieving a balance between security and performance.

[0063] Dynamic hardware reuse: The same UIU is reconfigured to support two different computing modes, namely the post-quantum cryptography algorithm and the national cryptographic SM2 / SM9 algorithm, respectively serving the Kyber and SM2 algorithms. This achieves efficient reuse of the core computing unit and saves chip area.

[0064] Secure data isolation: All sensitive data, such as shared keys and signature intermediate values, are generated, used, and transmitted only within the UIU, RHU, and SPM of the C3PU, and never enter the RISC-V general-purpose registers or system main memory, effectively curbing the risk of side-channel attacks and data leakage.

[0065] As can be seen from this embodiment, the chip and method provided by the present invention can flexibly, efficiently and securely meet the complex hybrid cryptographic operation requirements during the cryptographic transition period, verifying its outstanding practicality and inventiveness.

[0066] It is worth noting that all contents not described in detail in this invention are existing technologies and are well known to those skilled in the art.

[0067] Therefore, this invention adopts the above-mentioned PQC and SM2 / 9 collaborative cryptographic chip and method based on the RISC-V architecture. By designing a configurable cryptographic collaborative computing hardware unit, and having the collaborative control state machine adaptively make decisions and schedule based on instruction and data characteristics, it realizes an atomic cross-cryptographic collaborative computing process triggered by a single instruction. This improves execution efficiency, optimizes resource utilization, and enhances the security protection capability of the computing process at the hardware level.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A PQC and SM2 / 9 collaborative cryptographic chip based on RISC-V architecture, characterized in that, include: The RISC-V core is configured to issue single cooperative computing instructions carrying computational data characteristic information. The configurable cryptographic cooperative computing unit is directly coupled to the RISC-V core. The configurable cryptographic cooperative computing unit includes a cooperative control state machine and a dynamically reconfigurable unified computing unit. The cooperative control state machine is configured to perform the following operations: Receive and decode a single cooperative operation instruction from the RISC-V core to obtain the characteristic information of the operation data; Based on the comparison result of at least one parameter in the computational data feature information with the corresponding preset threshold, a composite cryptographic operation process is adaptively selected from multiple pre-stored hardware execution processes, wherein each composite cryptographic operation process defines a specific cooperative execution logic between the post-quantum cryptographic algorithm operation and the SM2 or SM9 algorithm operation. Based on the selected complex cryptographic operation process, a microcontroller sequence is generated and a unified operation unit is scheduled to complete the execution of the selected complex cryptographic operation process in an atomic manner and output the operation result.

2. A PQC and SM2 / 9 collaborative computing method based on RISC-V architecture, characterized in that, Executed by a configurable cryptographic cooperative computation unit in the cryptographic chip, the configurable cryptographic cooperative computation unit includes a cooperative control state machine and a dynamically reconfigurable unified computation unit, the method comprising: Step S1: The cooperative control state machine receives a single cooperative operation instruction from the RISC-V core, which carries or points to the characteristic information of the operation data; Step S2: The collaborative control state machine decodes a single collaborative operation instruction and obtains the operation data feature information; Step S3: The collaborative control state machine extracts the data length and security level identifier from the computational data feature information, compares the data length with a first preset threshold, and compares the security level identifier with a second preset threshold. Based on the comparison results, it adaptively selects a predefined collaborative computation process. The selected collaborative computation process defines the execution order and resource sharing strategy between the post-quantum cryptography algorithm operation and the SM2 or SM9 algorithm operation. Step S4: The collaborative control state machine generates corresponding control signals according to the selected collaborative operation process to dynamically configure the computing mode of the unified operation unit, and schedules the unified operation unit to execute, completing the collaborative operation of the quantum cryptography algorithm and the SM2 / SM9 algorithm in an atomic manner and outputting the result.

3. The PQC and SM2 / 9 collaborative computing method based on RISC-V architecture according to claim 2, characterized in that, Step S2 specifically includes: Step S21: The cooperative control state machine decodes the opcode of a single cooperative operation instruction to determine the instruction type; Step S22: Based on the instruction type, read the operation data characteristic information from the register or memory address specified by the single cooperative operation instruction.

4. The PQC and SM2 / 9 collaborative computing method based on RISC-V architecture according to claim 3, characterized in that, In step S3, adaptively selecting a predefined collaborative computation process based on the comparison results includes: If the data length is lower than the first preset threshold, the first collaborative operation process is selected. After the first collaborative operation process is defined, the quantum cryptography algorithm operation and the SM2 / SM9 algorithm operation are executed sequentially. If the data length is higher than or equal to the first preset threshold and the security level indicator is lower than the second preset threshold, then the second collaborative operation process is selected. After the second collaborative operation process is defined, the quantum cryptography algorithm operation and the SM2 / SM9 algorithm operation are executed in parallel. If the security level indicator is higher than or equal to the second preset threshold, the third collaborative operation process is selected. The third collaborative operation process is defined as inserting anti-side channel interference operation between the post-quantum cryptography algorithm operation and the SM2 / SM9 algorithm operation.

5. The PQC and SM2 / 9 collaborative computing method based on RISC-V architecture according to claim 2, characterized in that, Step S4 specifically includes: Step S41: The cooperative control state machine generates a microcontrol sequence containing at least one first cooperative operation instruction and at least one second cooperative operation instruction according to the selected cooperative operation process; wherein, the first cooperative operation instruction corresponds to the post-quantum cryptography algorithm operation, and the second cooperative operation instruction corresponds to the SM2 or SM9 algorithm operation. Step S42: The cooperative control state machine schedules and executes each cooperative operation instruction sequentially according to the micro-control sequence; wherein, the execution of each cooperative operation instruction includes: generating configuration information according to the instruction type of the cooperative operation instruction to configure the unified operation unit, and then triggering the unified operation unit to complete the specified cryptographic calculation; Step S43: After all the cooperative operation instructions in the microcontroller sequence have been executed, the cooperative control state machine collects the final operation result and returns.

6. The PQC and SM2 / 9 collaborative computing method based on RISC-V architecture according to claim 5, characterized in that, When the first cooperative operation process is executed, step S42 specifically involves: sequentially executing the first cooperative operation instruction and the second cooperative operation instruction, and during the execution of the first and second cooperative operation instructions, dynamically reconfiguring the unified operation unit through configuration information to support different arithmetic operation modes corresponding to the post-quantum cryptography algorithm and the SM2 / SM9 algorithm.

7. The PQC and SM2 / 9 collaborative computing method based on RISC-V architecture according to claim 5, characterized in that, When the second collaborative operation process is executed, step S42 specifically involves: executing the first collaborative operation instruction and the second collaborative operation instruction in parallel; the first collaborative operation instruction is scheduled and executed by the first computing channel, and the second collaborative operation instruction is scheduled and executed by the second computing channel; the first computing channel and the second computing channel are configured to independently access the storage resources within the configurable cryptographic collaborative operation unit.

8. The PQC and SM2 / 9 collaborative computing method based on RISC-V architecture according to claim 5, characterized in that, When the third cooperative operation process is executed, step S42 specifically involves inserting a disturbance operation controlled by the cooperative control state machine between the sequential execution of the first cooperative operation instruction and the second cooperative operation instruction. Interference operations include: Calculate interference intensity parameters ,in , For security level identification, The second preset threshold, For data length, The preset data length baseline value; Based on interference strength parameters Intermediate results generated by the first cooperative operation instruction Generate random delay duration ,in , For the preset hash function, The preset delay range, Minimum delay time, For splicing operations; Waiting for random delay time ; For intermediate results conduct The scrambling operation consists of rounds of scrambling. , This is the preset maximum number of scrambling rounds.

9. The PQC and SM2 / 9 collaborative computing method based on RISC-V architecture according to claim 2, characterized in that, The single cooperative operation instruction issued in step S1 is an atomic instruction, and steps S2 to S4 are completed atomically by the cooperative control state machine without the intervention of the RISC-V core.

10. The PQC and SM2 / 9 collaborative computing method based on RISC-V architecture according to claim 5, characterized in that, During the execution of step S42, the output data generated by the previously executed cooperative operation instruction is directly used as the input data for the subsequently executed cooperative operation instruction. The output data is transmitted through the shared memory or dedicated data path inside the configurable cryptographic cooperative operation unit, without going through the general-purpose registers of the RISC-V core or the main memory of the chip system.

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