ARE-SELECTIVE DEPARTURE OF HARD MASKS FOR VACUUM GAP FORMATION

Abstract

A vacuum gap formation method on a dielectric substrate uses area-selective deposition (ASD), such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), of a hard mask material onto a substrate patterned with a self-organizing monolayer (SAM) and metal features. Due to the presence of the SAM, the hard mask material reaches the metal features but does not touch them, leaving areas that form gaps on the resulting hard mask when the SAM is removed from the substrate. Etching the dielectric substrate creates trenches in these gap areas. When a nonconforming coating is deposited onto the dielectric substrate, vacuum gaps form in the trenches as the nonconforming coating enters the trenches but terminates at the substrate surface before completely filling the trench.

Description

TECHNICAL AREA

[0001] The present invention relates generally to semiconductor manufacturing and in particular to a method for generating vacuum gaps in a thin film by area-selective deposition of a hard mask material on a substrate. BACKGROUND OF THE INVENTION

[0002] As semiconductor devices continue to scale up, the spacing requirements for metallization levels on the thin films used to fabricate dielectric materials must be reduced. To decrease the metallization of dielectric materials, the space between metal signal lines on thin films must be reduced. However, reducing the spacing between metal signal lines has the associated problems of increasing the capacitance of the thin films, leading to increased electrical signal delays (i.e., resistance-capacitance (RC) time delays) and signal corruption due to crosstalk (i.e., the unwanted coupling of signals between adjacent wires or devices). To overcome these signal problems, the semiconductor industry has proposed the use of vacuum gaps between metal signal lines on dielectric materials.Vacuum gaps reduce the capacitance between metal conductors by decreasing the dielectric constant of the material surrounding the metal signal lines. Vacuum gaps between metal conductors are currently defined using photolithography, employing photoresists as a masking material for reactive ion etching into the thin films surrounding the metal signal lines. The use of photolithography for vacuum gap formation on thin films has the following disadvantages: (1) its application is limited by the wavelength of light used; (2) it can only be used on perfectly flat substrates; (3) it must be performed in a cleanroom; and (4) it requires expensive equipment. Given the above, there is a need in the engineering field for a more forgiving and affordable method for vacuum gap formation on dielectric materials. SUMMARY OF THE INVENTION

[0003] The present invention overcomes a need in the technology with a thin-film fabrication process that produces a hard mask pattern with vacuum gaps adjacent to metal elements on a dielectric substrate. The presence of the vacuum gaps on the dielectric substrate reduces high-frequency signal distortion due to crosstalk and / or RC time delays and eliminates the need for a photolithography step to define a vacuum gap trench.

[0004] In one embodiment, the present invention relates to a method for forming a vacuum gap in a dielectric substrate, comprising: depositing a self-organizing monolayer with reactive head groups on a dielectric substrate with metal elements, wherein the reactive head groups bond to the metal elements; forming a hard mask on the dielectric substrate by selectively depositing a hard mask material on the dielectric substrate, wherein (i) due to the self-organizing monolayer bonded to the metal elements, the hard mask material reaches but does not touch the metal elements, (ii) the metal elements and the hard mask material together form the hard mask, and (iii) the hard mask has gaps in regions located between the metal elements and the selectively deposited hard mask material;Etching the dielectric substrate, wherein the etching forms trenches in the gaps defined by the hard mask and undercuts the hard mask at the trench opening, resulting in trenches with depths greater than the widths of the trench openings; and depositing a non-conforming coating onto the dielectric substrate, wherein the non-conforming coating closes the trench openings to create vacuum gaps in the trenches.

[0005] In another embodiment, the present invention relates to a method for forming a vacuum gap in a dielectric substrate, comprising: depositing a self-organizing monolayer with a reactive head group bonding to copper on a dielectric substrate with copper elements; forming a hard mask on the dielectric substrate by selectively depositing zinc oxide on the dielectric substrate, wherein (i) due to the self-organizing monolayer bonded to the copper elements, the hard mask material reaches but does not touch the copper elements, (ii) the copper elements and the zinc oxide together form the hard mask, and (iii) the hard mask has gaps in regions located between the copper elements and the selectively deposited zinc oxide;the reactive ion etching of the dielectric substrate, wherein the etching forms trenches in the gaps defined by the hard mask and undercuts the hard mask at the trench opening, resulting in trenches with depths greater than the widths of the trench openings; and the deposition of a non-conforming coating onto the dielectric substrate, wherein the fluorocarbon closes the trench openings to create vacuum gaps in the trenches.

[0006] In another embodiment, the dielectric substrate comprises a material selected from the group consisting of ceramics, glass and silicon.

[0007] In another embodiment, the self-assembling monolayer comprises a material selected from the group consisting of alcohols, amines, carboxylic acids, disulfides, phosphates, phosphonates, organophosphonates, silanes, thiols and combinations thereof.

[0008] In another embodiment, the hard mask material is selected from the group consisting of aluminium fluoride, aluminium oxide, lanthanum trifluoride, magnesium oxide, silicon dioxide, tantalum oxide, zinc oxide and aluminium fluoride.

[0009] In another embodiment, the non-conforming coating comprises silicon dioxide and / or silicon.

[0010] In another embodiment, the non-conforming coating is tetraethyl orthosilicate and / or silicon dioxide.

[0011] In another embodiment, the hard mask material is selectively deposited onto the dielectric substrate by means of atomic layer deposition or chemical vapor deposition.

[0012] In another embodiment, the self-organizing monolayer is removed from the metallic features of the dielectric substrate after selective deposition of the hard mask material.

[0013] In another embodiment, the self-organizing monolayer is removed from the metal features using hydrogen plasma.

[0014] In another embodiment, etching removes the self-organizing monolayer from the metallic features of the dielectric substrate.

[0015] In another embodiment, the hard mask is etched using a technique selected from the group consisting of reactive ion etching, reactive ion deep etching, plasma etching, gas phase etching, sputter etching and ion beam etching.

[0016] In another embodiment, the hard mask is etched using reactive fluorocarbon ion etching.

[0017] In another embodiment, the dielectric substrate is planarized with the vacuum gaps to form a smooth surface on the dielectric substrate.

[0018] In another embodiment, the metal elements on the dielectric substrate are configured to form grooves in the hard mask that have a rectangular shape.

[0019] In another embodiment, the metal elements on the dielectric substrate are configured to form grooves in the hard mask that have a trapezoidal shape.

[0020] Additional aspects and / or embodiments of the invention are provided without limitation in the detailed description of the invention set forth below. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figures 1A-1F are schematic diagrams of the steps leading to the formation of a dielectric layer according to the vacuum gap formation process described herein. Fig. 2A-2C are bright-field transmission electron microscope images of a dielectric organosilicate substrate with a copper feature and a zinc oxide hard mask, where the positions of the vacuum gaps are marked with rectangles ( Fig. 2A and Fig. 2B) or trapezoids ( Fig. 2C) are shown. DETAILED DESCRIPTION OF THE INVENTION

[0021] The following is a description of what are currently considered preferred aspects and / or embodiments of the claimed invention. All alternatives or modifications with respect to function, purpose, or structure are intended to be covered by the appended claims. As used in this description and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly indicates otherwise. The terms "comprise," "includes," "includes," and / or "comprehensive," as used in the description and the appended claims, indicate the presence of the expressly mentioned components, elements, features, and / or steps but do not exclude the presence or addition of one or more other components, elements, features, and / or steps.

[0022] As used herein, the terms "thin film" and "film" refer to an electrically insulating layer used in the manufacture of dielectric materials. Thin films deposited on a substrate generally have a thickness on the order of 0.1 µm or less and enclose a metal.

[0023] As used herein, the terms “substrate” and “dielectric substrate” are used interchangeably to refer to mechanical support materials for dielectric materials, which may contain non-conductive (i.e., dielectric) and conductive (i.e., metallic) thin films. Examples of dielectric substrates include ceramic, glass, and silicon wafers.

[0024] As used herein, the terms “self-assembling monolayer” and “SAM” refer to a single-molecule-thick layer of material that binds in an ordered manner to a substrate surface as a result of physical or chemical forces during a deposition process. SAMs are mounted onto the substrate surface by adsorption from a solution. All SAMs possess a surfactant head group that binds to the substrate, a hydrophobic body, and a terminal tail group that can be functionalized. Common head groups include, without limitation, alcohols, amines, carboxylic acids, disulfides, phosphates, phosphonates, organophosphonates, silanes, thiols, and combinations thereof. The choice of a SAM typically depends on the substrate to which the SAM binds. For example, phosphonates and silanes can be applied to hydroxylated surfaces (e.g., silicon dioxide, glass, aluminum oxide); silanes can be applied to oxide surfaces (e.g.,Iron oxide); organophosphonates, disulfides, and thiols can be applied to precious and / or coinage metals (e.g., gold, silver, copper); amines and alcohols can be applied to platinum surfaces; carboxylic acids can be applied to aluminum oxide surfaces; and phosphates can be applied to titanium or tantalum surfaces. It is understood that the foregoing list is illustrative and that SAMs other than those listed above can be modified to bind to substances other than those listed above. SAMs can be uncrosslinked or crosslinked, the latter exhibiting improved thermal and chemical stability compared to the former. As a person skilled in the art will recognize, each of the SAMS disclosed herein can be crosslinked by techniques known in the prior art (such as reaction with a crosslinking agent or exposure to UV light).

[0025] As used herein, the term “hard mask material” refers to a high-density material used in thin-film fabrication that is deposited onto a substrate to protect specific areas of the substrate from etching chemicals. Examples of hard mask materials that can be deposited onto a dielectric substrate, as described herein, include, without limitation, aluminum fluoride (AlF3), aluminum oxide (Al2O3), lanthanum trifluoride (LaF3), magnesium oxide (MgO), silicon dioxide (SiO2), tantalum oxide (Ta2O3), zinc oxide (ZnO), and combinations thereof.

[0026] As used herein, the term “hard mask” refers to a coating on a substrate that facilitates the etching of the substrate. In the context of the present invention, a hard mask comprises the combination of the metal features integrated into or on a substrate and the hard mask material deposited on the substrate.

[0027] As used herein, the term “area-selective deposition” of “ASD” refers to a bottom-up process that results in uniform deposition in selected areas of a structured substrate. In the context of the present invention, ASD techniques used to deposit the hard mask materials described herein include atomic layer deposition (ALD) and chemical vapor deposition (CVD). CVD is a form of ASD that uses a vacuum to produce thin films. In CVD, a substrate is exposed to one or more volatile precursors that react and / or decompose on the substrate surface to deposit a material. Volatile byproducts can be produced in CVD, which are typically removed by a gas stream through a reaction chamber. ALD is a form of ASD that uses a chemical vapor phase process to produce thin films.ALD reactions use two precursor chemicals that react sequentially with the substrate surface in a non-overlapping manner. In this way, a thin film is slowly deposited through repeated exposure to separate precursors. ALD is considered a subclass of CVD in that CVD is a continuous process where all reactants are applied simultaneously to build the film, whereas ALD is carried out with sequential reactions. While ALD deposits layers one atom at a time, CVD can deposit films with a wider range of thickness.

[0028] As used herein, the terms "etching" and "etching" refer to a microfabrication process that chemically removes layers from the surface of a thin film. Examples of dry thin-film etching techniques include, without limitation, reactive ion etching (RIE), deep reactive ion etching (DRIE), plasma etching, gas-phase etching, sputter etching, and ion beam etching.

[0029] RIE is a dry etching process for thin films in which a substrate is subjected to a reaction involving the introduction of several gases. This creates a chemically reactive plasma within the gas mixture using a radio frequency (RF) energy source that breaks the gas molecules into ions. These ions then react at the surface of the material being etched, knocking atoms out of the material without a chemical reaction. RIE achieves a maximum etching depth of approximately 10 µm at a rate of up to 1 µm / min. Examples of gases used in RIE include, but are not limited to, trifluoromethane (CF3), tetrafluoromethane (CF4), hexafluorobutadiene (C4F6), sulfur hexafluoride (SF6), nitrogen trifluoride (F3N), chlorine (Cl2), fluorine (F2), oxygen (O2), and combinations thereof.

[0030] DRIE is a highly anisotropic RIE technique that uses a passivation layer and a superimposed DC voltage to etch to depths exceeding those achievable with standard RIE. DRIE exhibits etch depths of up to 600 µm at rates of up to 20 µm / min. Examples of etching materials for DRIE include, but are not limited to, tetrafluoromethane (CF4), carbon tetrachloride (CCl4), boron trichloride (BCl3), sulfur hexafluoride (SF6) + octafluorocyclobutane (C4F8), sulfur hexafluoride (SF6) + oxygen (O2) at cryogenic temperatures, and combinations thereof.

[0031] In plasma etching, the substrate in the reactor is exposed to a high-speed stream of plasma (generated by exciting ions in a gas) to remove material from the substrate. Examples of gases used in plasma etching include tetrafluoromethane (CF4) and oxygen (O2), which can be used alone or in combination.

[0032] In gas-phase etching, the substrate is dissolved at the surface of the reactor through a combination of a chemical reaction and exposure to one or more gases. Examples of gas-phase etching materials include hydrogen fluoride (HF) and xenon difluoride (XeF₂), which can be used alone or in combination.

[0033] Sputter etching is RIE etching without reactive ions. In sputter etching, the substrate in the reactor is bombarded with ions instead of the target material. Etching materials used for sputter etching include, without limitation, the noble inert gases helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe), which can be used alone or in combination.

[0034] In ion beam etching, the substrate in the reactor is exposed to a beam of ions to remove material from the substrate surface. Etching materials used for ion beam etching include, without limitation, the noble inert gases helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe), which can be used alone or in combination.

[0035] As used herein, the terms “nonconforming” and “nonconforming coating” refer to a film that does not deposit on all exposed surfaces at the same deposition rate. For example, a film deposited on an exposed horizontal surface may be thicker than a film deposited on a vertically oriented surface. Furthermore, different films may be inherently nonconforming or tuned to be nonconforming. For example, a thin film evaporated is nonconforming, whereas sputtering may be tuned to be nonconforming. Depending on the material and deposition parameters, a nonconforming coating may be applied to a dielectric substrate via ALD, CVD, or physical vapor deposition (PVD). Examples of materials used to form nonconforming coatings include silicon dioxide and / or silicon.Two non-restrictive examples of non-conforming coating materials are tetraethyl orthosilicate (TEOS) and silicon dioxide (SiO2).

[0036] As used herein, the term "physical vapor deposition" or "PVD" refers to a vacuum deposition process that can produce thin films and coatings on substrates. In PVD, the material forming the thin film or coating transitions from a condensed phase to a gas phase and then back to a condensed thin-film phase. Examples of PVD techniques include sputtering and thermal or electron beam evaporation.

[0037] As used herein, the terms “planarization”, “planarize”, and “planarized” refer to flattening or smoothing the surface of a thin film by filling trench areas and / or through-holes. Examples of planarization techniques include, without limitation, oxidation, chemical-mechanical polishing, chemical etching, sacrificial back-etching, resputtering deposited films to smooth them, spin-on-glass deposition followed by a reflow process or baking, deposition of organic planarization layers, and combinations thereof.

[0038] This document describes a method for forming a structured thin film that includes vacuum gaps, which is schematically illustrated in Fig. 1A-1F is shown.

[0039] With reference to Fig. 1A The first step in the process comprises the deposition of a self-assembled monolayer (SAM) 3 onto a substrate 1 suitable for thin-film fabrication, which contains metal elements 2. The SAM is typically bonded to the substrate by immersing the substrate in a solution containing the SAM in a solvent, whereby at this point the reactive head groups of the SAM bind to the metal lines, leaving the central and terminal parts of the SAM unbound. Fig. Figure 1A shows that the metal elements are made of copper; it is understood that the metal elements on the substrate surface can be any suitable metal for a thin film. While the metal elements are typically metal lines (as in Figure 1A), the following diagram shows that the metal elements can be made of copper. Fig. (as shown in Figure 1A), other metal micro- or nanostructures, such as vias, can also be used to form a pattern on a thin film. As shown in Figure 1A. Fig. As shown in Figure 1A, the SAM 3 binds to the metal elements 2 to form a chemical prepatent on the substrate surface. The application of the SAM to and adjacent with the metal elements forms an inhibitory layer on the substrate surface.

[0040] With reference to Fig. In step 1B, a hard mask material 4 is applied to the pre-structured substrate surface by ASD to form a film that grows only on the areas of the substrate that do not enclose the SAM inhibitory layer. Due to the presence of the SAM on the metal elements, the hard mask material forms film layers on the substrate surface that border the metal elements but do not reach them. The combination of the SAM on the metal elements and the hard mask material forms the pattern for the thin film.

[0041] With reference to Fig. In 1C, the SAM is removed from the substrate surface either with hydrogen (H2) plasma (described in Example 1) or as part of the etching process (described in Example 2). If fluorocarbon RIE is used for etching, the SAM does not survive the process, and thus a separate SAM removal step is unnecessary. Upon removal of the SAM (either by the etching process or as a separate step), the areas adjacent to the metal elements that do not enclose the film formed from the hard mask material are exposed as uncoated trench regions 5. To create vacuum gaps, the trench depth 6 must be greater than the width of the trench opening 7 at the substrate surface.As a result of the deposition of the SAM in the areas adjacent to the metal elements 4, the formation of the trench 5 upon removal of the SAM (either with or without etching) causes the hard mask to be under-etched 8, forming an overhang 9 of the hard mask at the location of the trench, which causes a reduction in the width of the trench opening 7 at the substrate surface compared to the depth 6 of the trench.

[0042] With reference to Fig. For etching the structured hard mask in 1D, any etching technique described herein or known in the prior art can be used. Fig. Figure 1D schematically shows the application of a covering technique with an etching material, such as fluorocarbon RIE, to the structured substrate surface 10. During deposition, the etching material covers the metal elements, the area of ​​the substrate coated with the hard mask material, and the trenches. Since the depth of the trenches 6 is greater than the width of the trenches on the substrate surface 7, the etching material encounters the top of the trench 11 (i.e., at the trench opening) before the trench is filled with the etching material, thus forming a keyhole pattern within the trench, with the unfilled portion of the trench 12 forming a cavity or vacuum gap.

[0043] With reference to Fig. 1E Once the thin film has been etched, the film can be planarized to smooth the surface of the film 13 using one or more of the planarization methods described herein.

[0044] With reference to Fig. 1F A final chemical and / or mechanical polishing or photolithography step can be applied to the planarized thin film surface to remove excess hard mask or etching materials 14 that remain on the thin film.

[0045] The method described herein is a self-aligning process in that the selective SAM deposition step defines the position of the vacuum gap(s) in the resulting structured thin film. Structured thin films enclosing vacuum gaps, as described herein, reduce radio frequency signal distortion due to crosstalk and / or RC time delays and eliminate the need for a photolithography step to define a vacuum gap trench.

[0046] Fig. Figure 2A is a bright-field transmission electron microscope (TEM-BF) image of a dielectric organosilicate glass (SiCOH) substrate with copper lines and a ZnO ALD hard mask showing the position of the vacuum gaps. Due to the SiCOH etch selectivity for Cu and ZnO, the hard mask is self-aligned to the edges of the metal lines, thus forming the vacuum gaps; consequently, no photolithography step is required to etch the substrate. While the gaps in the substrate are schematically shown as rectangles with a trench depth greater than the trench opening width, it is understood that the gap may have a different shape, such as a trapezoid ( Fig. 2C); the only requirement for the shape is that the width of the opening of the trench is smaller than the depth of the trench. Fig. Figure 2B shows how a dielectric film covers an etched surface on a substrate and fills the vacuum gap trenches to form a keyhole formation. Because the vacuum gap has a depth greater than the width of the trench opening at the substrate surface, the dielectric film falls into the trench and forms a keyhole formation within the trench, with the keyhole formation causing the dielectric film to create a seal at the trench opening at the substrate surface.

[0047] In one embodiment, the method for forming vacuum gaps in a thin film comprises depositing a self-organizing monolayer (SAM) onto a substrate comprising metal elements, wherein the self-organizing monolayer has a reactive head group that binds to the metal elements; selectively depositing a hard mask material onto the substrate via ASD (ALD or CVD), wherein (i) the hard mask material binds to areas of the substrate that are not bound to the SAM, (ii) the metal elements and the hard mask material together form a hard mask on the substrate, and (iii) the hard mask has gaps in the areas of the substrate that do not contain the metal elements or the hard mask material; removing the SAM via hydrogen plasma; and etching the substrate, wherein the etching forms trenches at the location of the gaps, the trenches having a depth greater than the width of the trench opening at the substrate surface.and the deposition of a non-conforming coating covering the hard mask on the substrate surface, including the trenches, with vacuum gaps being formed by the non-conforming coating, which seals the entrance at the trench openings before the trenches are completely filled with the non-conforming coating.

[0048] In another embodiment, the method for forming vacuum gaps in a thin film comprises depositing a self-organizing monolayer (SAM) onto a substrate comprising metal elements, wherein the self-organizing monolayer has a reactive head group that binds to the metal elements; selectively depositing a hard mask material onto the substrate via ASD (ALD or CVD), wherein (i) the hard mask material binds to areas of the substrate that are not bound to the SAM, (ii) the metal elements and the hard mask material together form a hard mask on the substrate, and (iii) the hard mask has gaps in the areas of the substrate that do not contain the metal elements or the hard mask material; etching the substrate, wherein the etching simultaneously removes the SAM and forms trenches at the location of the gaps, the trenches having a depth greater than the width of the trench opening at the substrate surface;and the deposition of a non-conforming coating covering the hard mask on the substrate surface, including the trenches, with vacuum gaps being formed by the non-conforming coating, which seals the entrance at the trench openings before the trenches are completely filled with the non-conforming coating.

[0049] In another embodiment, the substrate is a dielectric substrate consisting of a material selected from the group consisting of ceramics, glass and silicon.

[0050] In another embodiment, the dielectric substrate is a silicon wafer.

[0051] In another embodiment, the metallic elements comprise a metal selected from the group consisting of aluminium, chromium, copper, germanium, gold, nickel, platinum, silver, tantalum, titanium, tungsten and combinations thereof.

[0052] In another embodiment, the metal elements are configured on the dielectric substrate to form grooves that have a rectangular shape.

[0053] In another embodiment, the metal elements are configured on the dielectric substrate to form grooves that have a trapezoidal shape.

[0054] In another embodiment, the SAM comprises a material selected from the group consisting of alcohols, amines, carboxylic acids, disulfides, phosphates, phosphonates, organophosphonates, silanes and thiols.

[0055] In another embodiment, the substrate has copper elements and the SAM has a reactive binding head that binds to copper, the latter being selected from the group consisting of organophosphonates, disulfides and thiols.

[0056] In another embodiment, the substrate is an organosilicate glass and the SAM is an organophosphonate.

[0057] In another embodiment, the hard mask material is selected from the group consisting of aluminium fluoride (AlF3), aluminium oxide (Al2O3), lanthanum trifluoride (LaF3), magnesium oxide (MgO), silicon dioxide (SiO2), tantalum oxide (Ta2O5) and zinc oxide (ZnO).

[0058] For the process described herein to be most effective, the substrate material, the metal elements, and the hard mask material should be selected such that the substrate material is selective for the metal elements and the hard mask material. For example, an organosilicon substrate exhibits etch selectivity for copper metal and ZnO (Examples 1 and 2).

[0059] In another embodiment, the hard mask is etched using a technique selected from the group consisting of reactive ion etching, reactive ion deep etching, plasma etching, gas phase etching, sputter etching and ion beam etching.

[0060] In another embodiment, the hard mask is etched using a technique selected from the group consisting of reactive ion etching (RIE), reactive ion deep etching (DRIE), plasma etching, gas phase etching, sputter etching and ion beam etching.

[0061] In another embodiment, the etching is fluorocarbon RIE etching, wherein the fluorocarbon is selected from the group consisting of trifluoromethane, tetrafluoromethane, hexafluorobutadiene and combinations thereof.

[0062] In another embodiment, the non-conforming coating comprises silicon dioxide and / or silicon.

[0063] In another embodiment, the non-conforming coating is tetraethyl orthosilicate (TEOS) and / or silicon dioxide (SiO2).

[0064] In another embodiment, the substrate with the non-conforming coating is planarized to smooth the substrate surface.

[0065] In another embodiment, planarization comprises a process selected from the group consisting of oxidation, chemical-mechanical polishing, chemical etching, sacrificial back-etching, resputtering of deposited films and spin-on-glass deposition.

[0066] The descriptions of the various aspects and / or embodiments of the present invention have been provided for illustrative purposes and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be obvious to those skilled in the art without deviating from the scope and spirit of the described embodiments. The terminology used here has been chosen to best explain the principles of the aspects and / or embodiments, their practical application, or technical improvements over technologies available on the market, or to enable other skilled persons to understand the aspects and / or embodiments disclosed herein. EXPERIMENTAL

[0067] The following examples are presented to give those skilled in the art a complete disclosure of how to manufacture and use the aspects and embodiments of the invention as set forth herein. Although every effort has been made to ensure accuracy with respect to variables, experimental errors and deviations should be taken into account. Unless otherwise stated, the parts are measured by weight, the temperature is degrees Celsius, and the pressure is at or near atmospheric pressure. All components were commercially sourced unless otherwise stated. EXAMPLE 1: CREATING A VACUUM GAP ON A STRUCTURED DIELECTRIC SUBSTRATE MADE OF ORGANOSILICATE GLASS

[0068] A dielectric substrate made of organosilicate glass (SiCOH) (SiCOH / dielectric) with structured copper lines was immersed in a solution of an organophosphonic acid (N-phosphonomethyl-butyramide) SAM (SAM XL) in 0.1 wt% 4-methyl-2-pentanol for 30 minutes (but no longer than 30 minutes to avoid potential agglomeration of coupling agents in the SAM XL / solvent), during which time the head group of the SAM XL selectively bound to the copper lines on the substrate surface. The substrate surface was then rinsed with 4-ethyl-2-pentanol, and the substrate was subsequently placed under nitrogen to allow the monolayer to dry. In a dry nitrogen environment, the dried monolayer remained stable on the substrate surface for several weeks.

[0069] The structured substrate was treated with zinc oxide (ZnO) via ALD, resulting in a hard mask on the surface of the SiCOH / dielectric. During deposition, the ZnO did not bond to the copper lines coated with SAM XL and also left uncoated areas adjacent to the copper lines, i.e., vacuum gaps with widths much smaller than the depths of the trenches formed by the copper lines. The SAM XL was removed from the SiCOH / dielectric surface using H2 plasma. EXAMPLE 2: IMAGING A KEYHOLE STRUCTURE ON AN ETACHED DIELECTRIC FILM

[0070] On a hard mask prepared according to the method described in Example 1, the SAM XL is not removed from the SiCOH / dielectric by H2; instead, the SAM XL is removed during the etching of the hard mask. The application of RIE to deposit a fluorocarbon, such as CF4, onto the sidewalls of the SiCOH / dielectric removes the bonded SAM XL, leaving grooves in the substrate in the areas adjacent to the copper lines and undercuts in the substrate at the substrate openings. Fig. 1C). The subsequent deposition of a non-conforming coating, such as TEOS or SiO2, applied via CVD or PVD, creates vacuum gaps in the trenches, with the non-conforming coating closing off the top of the trenches before the trenches are completely filled ( Fig. 1).

Claims

[1] Method for forming a vacuum gap in a dielectric substrate, comprising: Deposition of a self-organizing monolayer with reactive head groups on a dielectric substrate with metal elements, wherein the reactive head groups bind to the metal elements; Forming a hard mask on the dielectric substrate by selectively depositing a hard mask material on the dielectric substrate, wherein (i) due to the self-organizing monolayer bonded to the metal elements, the hard mask material reaches the metal elements but does not touch them, (ii) the metal elements and the hard mask material together form the hard mask, and (iii) the hard mask has gaps in areas located between the metal elements and the selectively deposited hard mask material; Etching of the dielectric substrate, wherein the etching forms trenches in the gaps defined by the hard mask and undercuts the hard mask at the trench opening, resulting in trenches with depths greater than the trench opening widths; and Deposition of a non-conforming coating onto the dielectric substrate, wherein the non-conforming coating creates the trench openings to generate vacuum gaps in the trenches. [2] Method according to claim 1, wherein the hard mask material is selectively deposited onto the dielectric substrate by means of atomic layer deposition or chemical vapor deposition. [3] Method according to claim 1, wherein the self-organizing monolayer is removed from the metal features of the dielectric substrate by hydrogen plasma treatment after selective deposition of the hard mask material. [4] Method according to claim 1, wherein the etching removes the self-organizing monolayer from the metallic features of the dielectric substrate. [5] Method according to claim 1, wherein the hard mask is etched using a technique selected from the group consisting of reactive ion etching, reactive ion deep etching, plasma etching, gas phase etching, sputter etching and ion beam etching. [6] Method according to claim 1, wherein the dielectric substrate comprises a material selected from the group consisting of ceramics, glass and silicon. [7] Method according to claim 1, wherein the self-assembling monolayer comprises a material selected from the group consisting of alcohols, amines, carboxylic acids, disulfides, phosphates, phosphonates, organophosphonates, silanes, thiols and combinations thereof. [8] Method according to claim 1, wherein the hard mask material is selected from the group consisting of aluminium fluoride, aluminium oxide, lanthanum trifluoride, magnesium oxide, silicon dioxide, tantalum oxide, zinc oxide and combinations thereof. [9] Method according to claim 1, wherein the non-conforming coating comprises silicon dioxide and / or silicon. [10] Method for forming a vacuum gap in a dielectric substrate, comprising: Deposition of a self-organizing monolayer with a reactive head group that binds to copper on a dielectric substrate with copper elements; Forming a hard mask on the dielectric substrate by selectively depositing zinc oxide on the dielectric substrate, wherein (i) due to the self-organizing monolayer bonded to the copper elements, the hard mask material reaches the copper elements but does not touch them, (ii) the copper elements and the zinc oxide together form the hard mask, and (iii) the hard mask has gaps in areas located between the copper elements and the selectively deposited zinc oxide; Etching of the dielectric substrate, wherein the etching forms trenches in the gaps defined by the hard mask and undercuts the hard mask at the trench opening, resulting in trenches with depths greater than the trench opening widths; and Deposition of a non-conforming coating onto the dielectric substrate, wherein the fluorocarbon closes the trench openings to create vacuum gaps in the trenches. [11] Method according to claim 10, wherein the reactive head group of the self-assembling monolayer is selected from the group consisting of organophosphonates, disulfides, thiols and combinations thereof. [12] Method according to claim 10, wherein the zinc oxide is selectively deposited onto the dielectric substrate by means of atomic layer deposition or chemical vapor deposition. [13] Method according to claim 10, wherein the self-organizing monolayer is removed from the copper features of the dielectric substrate by hydrogen plasma treatment after selective deposition of the zinc oxide. [14] Method according to claim 10, wherein the etching removes the self-organizing monolayer from the copper features of the dielectric substrate. [15] Method according to claim 10, wherein the hard mask is etched using a technique selected from the group consisting of reactive ion etching, reactive ion deep etching, plasma etching, gas phase etching, sputter etching and ion beam etching. [16] Method according to claim 10, wherein the dielectric substrate comprises a material selected from the group consisting of ceramics, glass and silicon. [17] Method according to claim 10, wherein the non-conforming coating is tetraethyl orthosilicate and / or silicon dioxide. [18] Method for forming a vacuum gap in a dielectric substrate, comprising: Deposition of a self-organizing monolayer with reactive head groups on a dielectric substrate with metal elements, wherein the reactive head groups bind to the metal elements; Forming a hard mask on the dielectric substrate by selectively depositing a hard mask material on the dielectric substrate, wherein (i) due to the self-organizing monolayer bonded to the metal elements, the hard mask material reaches the metal elements but does not touch them, (ii) the metal elements and the hard mask material together form the hard mask, and (iii) the hard mask has gaps in areas located between the metal elements and the selectively deposited hard mask material; Removal of the self-organizing monolayer from the dielectric substrate; Etching of the dielectric substrate, wherein the etching forms trenches in the gaps defined by the hard mask and undercuts the hard mask at the trench opening, resulting in trenches with depths greater than the trench opening widths; Deposition of a non-conforming coating onto the dielectric substrate, wherein the non-conforming coating closes the trench openings to create vacuum gaps in the trenches; and Planarizing the dielectric substrate to create a smooth surface on the dielectric substrate. [19] Method according to claim 18, wherein the self-organizing monolayer is removed from the dielectric substrate by hydrogen plasma treatment. [20] Method according to claim 18, wherein the metal elements are configured on the dielectric substrate to form trenches in the hard mask having a rectangular shape. [21] Method according to claim 18, wherein the metal elements are configured on the dielectric substrate to form trenches in the hard mask having a trapezoidal shape. [22] Method for forming a vacuum gap in a dielectric substrate, comprising: Deposition of a self-organizing monolayer with reactive head groups on a dielectric substrate with metal elements, wherein the reactive head groups bind to the metal elements; Forming a hard mask on the dielectric substrate by selectively depositing a hard mask material on the dielectric substrate, wherein (i) due to the self-organizing monolayer bonded to the metal elements, the hard mask material reaches the metal elements but does not touch them, (ii) the metal elements and the hard mask material together form the hard mask, and (iii) the hard mask has gaps in areas located between the metal elements and the selectively deposited hard mask material; Etching of the dielectric substrate, wherein the etching forms trenches in the gaps defined by the hard mask and undercuts the hard mask at the trench opening, resulting in trenches with depths greater than the trench opening widths, and wherein furthermore the etching removes the self-organizing monolayer from the dielectric substrate; Deposition of a non-conforming coating onto the dielectric substrate, wherein the non-conforming coating closes the trench openings to create vacuum gaps in the trenches; and Planarizing the dielectric substrate to create a smooth surface on the dielectric substrate. [23] Method according to claim 22, wherein the metal elements are configured on the dielectric substrate to form trenches in the hard mask having a rectangular shape. [24] Method according to claim 22, wherein the metal elements are configured on the dielectric substrate to form trenches in the hard mask having a trapezoidal shape. [25] Method according to claim 22, wherein the hard mask is etched by reactive ion etching.

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