Method for compensating gate heights in an embedded non-volatile memory based on HKMG technology

Abstract

A method for fabricating a semiconductor device, comprising: subdividing a substrate (504) into a first region (308) and a second region (318); forming a first recess (552) to a first depth in the first region (308); forming an NVM transistor (326) and a selection transistor (327) at least partially within the first recess (552), further comprising: forming a non-volatile dielectric stack (810, 812, 814) in the first recess (552), wherein the non-volatile dielectric stack (810, 812, 814) comprises a barrier oxide (814) arranged above a charge-trapping layer (812) and a tunnel oxide (810); performing at least one silicon oxide deposition process in an atomic layer deposition tool to deposit a gate dielectric layer (816) of the selection transistor (327) adjacent to to form the non-volatile dielectric stack (810, 812, 814) in the first recess (552);Performing a calibrated or time-controlled oxide dilution process on the barrier oxide (814') such that a predetermined thickness of the barrier oxide (814) remains; forming a high-k dielectric layer (835) above the barrier oxide (814) and the gate dielectric layer (816) respectively; forming sacrificial polysilicon gates (840') above the high-k dielectric layer (835) of the non-volatile dielectric stack (810, 812, 814) and the gate dielectric layer (816); and replacing the sacrificial polysilicon gates (840') with metal gates (834).

Description

REFERENCE TO RELATED REGISTRATIONS

[0001] This application is an international application of the non-provisional US patent application No. 18 / 658,027 filed on May 8, 2024, the entire contents of which are incorporated herein by reference. AREA OF TECHNOLOGY

[0002] The present disclosure relates generally to semiconductor devices and in particular to memory cells and methods for their fabrication, including an embedded or integrally formed charge-capture gate stack and a selection gate stack, both comprising a high-K or Hi-K dielectric (HK) and a metal gate (MG), in an existing HKMG-complementary-metal-oxide-semiconductor(CMOS)-foundry logic technology. GENERAL STATE OF THE ART

[0003] Non-volatile memory (NVM) is widely used to store data in computer systems and typically comprises a memory array with a large number of NVM cells arranged in rows and columns or other configurations. In recent decades, the scaling of features in integrated circuits has been a driving force behind the steady growth of the semiconductor industry. Scaling down to ever smaller features enables increased densities of functional units on the limited area of ​​semiconductor chips. However, the pursuit of ever greater capacity is not without its challenges. The need to optimize the performance of each device during scaling is becoming increasingly critical.

[0004] In some embodiments, NVM cells may include at least one non-volatile element, such as a charge-trapping field-effect transistor (FET), a floating-gate transistor, which is programmed or erased by applying a voltage of the correct polarity, magnitude, and duration between a control / memory gate and the substrate or drain / source regions. In some embodiments, silicon oxide-nitride-oxide-silicon (SONOS)-based memory arrays are used and operated as data storage devices in which binary (0 and 1) or analog data is stored on the different V T - or I D-levels or values ​​of the SONOS cells. The charge-trapping gate stack is typically fabricated using materials and processes that differ significantly from those of the basic CMOS process flow and can adversely affect, or be affected by, the fabrication of the MOS transistors. In particular, forming a gate oxide or dielectric of a MOS transistor can significantly degrade the performance of a previously formed charge-trapping gate stack by altering the thickness or composition of one or more charge-trapping layers. Furthermore, this integration can also affect the basic CMOS process flow and generally requires a considerable number of mask sets and process steps, which can result in increased fabrication costs and reduced tool yield.

[0005] Furthermore, it may be important that the integrated manufacturing process allows for control of the upper dielectric or barrier dielectric thickness of NVM transistors to meet requirements such as desirable threshold voltages Vts and / or an equivalent oxide thickness (EOT), while fulfilling the (physical or electrical) gate oxide thickness targets of MOS transistors, especially if these MOS transistors are HV transistors (HV = high voltage) or I / O transistors (I / A = input / output).

[0006] As technology nodes become smaller, for example at 22 nm and below, high-k metal-gate (HKMG) stacks have become more important. HKMG stacks can switch using a thin high-k dielectric in addition to, or as an alternative to, the barrier silicon oxide or silicon oxynitride layer and a metal gate instead of a polysilicon gate. Among other advantages, HKMG stacks can reduce leakage loss and improve the overall performance of MOS transistors, as well as the data storage of SONOS transistors. Therefore, there is a need to integrate SONOS into the HKMG-CMOS process flow. By introducing metal gates into SONOS transistors, the device can take the form of a metal oxide nitride oxide semiconductor (MONOS) or "HKMG SONOS." It is understood that the two terms, SONOS and MONOS, are used synonymously in this patent document.

[0007] It is therefore an object of the present invention to propose an improved manufacturing process for the formation of the ONO stacks in SONOS memory cells and to integrate such a process into the basic HKMG-CMOS process flow. BRIEF DESCRIPTION OF THE FIGURES

[0008] The present invention will be more clearly understood with reference to the following detailed description and the accompanying drawings and claims below, wherein: Fig. 1 is a block diagram that represents a cross-sectional side view of a SONOS-based non-volatile storage transistor or SONOS-based non-volatile storage device; Fig. 2 a corresponding schematic representation of the SONOS-based non-volatile storage transistor or SONOS-based non-volatile storage device, which is in Fig. 1 are depicted; Fig. 3 is a representative block diagram that represents an embodiment of an embedded SONOS- or MONOS-based NVM device 300 according to the present disclosure; Fig. 4 is a flowchart that represents an embodiment of a method for manufacturing memory cells of embedded SONOS-based NVM transistors and two-transistor (2T) MOS transistors; the Fig. Figures 5A-5H are representative representations that show cross-sectional views of a section of a 2T memory cell and of CMOS devices during manufacturing according to the process flow in Fig. 4 represent; Fig. 6 is a block diagram representing a cross-sectional side view of a SONOS-based non-volatile storage transistor or a SONOS-based non-volatile storage device formed in recesses according to the present disclosure; Fig. 7 is a flowchart that represents an embodiment of a method for manufacturing memory cells of embedded SONOS-based NVM transistors and two-transistor (2T) MOS transistors; the Fig. Figures 8A-8B are representative representations that show cross-sectional views of a section of a 2T memory cell and CMOS devices during manufacturing according to the process flow in Fig. 7 represent; Fig. 9A is a flowchart that represents an embodiment of a method for manufacturing memory cells of embedded SONOS-based NVM transistors and two-transistor (2T) MOS transistors; Fig. 9B is a block diagram showing a cross-sectional side view of a SONOS-based non-volatile storage transistor or SONOS-based non-volatile storage device formed in recesses; and the Fig. 10A-10G representative representations are cross-sectional views of a section of a 2T memory cell and of CMOS devices during manufacturing according to the process flow in Fig. 9A. DETAILED DESCRIPTION

[0009] The following description sets out numerous specific details, such as exemplary special systems, components, processes, and so on, in order to provide a sufficient understanding of several embodiments of the subject matter.

[0010] However, it is obvious to a person skilled in the art that at least some embodiments can be practically implemented even without these specific details. In other cases, well-known components or methods are not described in detail or are illustrated using a simple block diagram so as not to complicate the understanding of the techniques described herein. Therefore, the specific details presented below are purely exemplary. Certain implementations may deviate from these exemplary details and still be considered compatible with the concept of the present invention and within its scope of protection.

[0011] This document describes, with reference to the figures, embodiments of a memory cell with two transistors (2T), comprising an embedded NVM transistor (NVM = non-volatile memory) and an embedded metal-oxide-semiconductor transistor (MOS transistor), both featuring a high-k-metal-gate (HKMG) stack, and methods for their fabrication. However, certain embodiments can also be practically implemented without one or more of these specific details or in combination with other methods, materials, and devices known in the prior art. Numerous specific details, such as special materials, dimensions, concentrations, and process parameters, etc., are presented in the following description to provide a thorough understanding of the subject matter.In other cases, widely known techniques for the design and manufacture of semiconductors were not described in detail in order to avoid complicating the understanding of the subject matter. References in the description to "one embodiment," "an exemplary embodiment," "some embodiments," or "various embodiments" mean that a particular feature, structure, or property described in connection with the one or more embodiments is included in at least one embodiment of the subject matter. Furthermore, expressions such as "one embodiment," "an exemplary embodiment," "some embodiments," and "various embodiments," appearing at different points in the description, do not necessarily all refer to the same one or several identical embodiments.

[0012] The description includes references to the accompanying drawings, which form part of the detailed description. The drawings depict embodiments according to exemplary embodiments. These embodiments, which may also be referred to herein as "examples," are described in sufficient detail to enable a person skilled in the art to practically implement the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be used, or structural, logical, and electrical modifications may be made without departing from the scope of protection and the concept of the claimed subject matter. It is understood that the embodiments described herein are not intended to limit the scope of protection of the subject matter, but rather to enable a person skilled in the art to practically implement, manufacture, and / or use the subject matter.

[0013] The terms “above,” “below,” “between,” and “on,” as used herein, refer to a layer’s relative position with respect to other layers. For example, a layer deposited or arranged above or below another layer may directly touch the other layer or have one or more intervening layers. Furthermore, a layer deposited or arranged between layers may directly touch the layers or have one or more intervening layers. Additionally, the relative position of a layer with respect to other layers is provided under the assumption that operations involve depositing, modifying, and removing thin layers relative to a starting substrate without regard to the substrate’s absolute orientation.

[0014] Unless expressly stated otherwise, it is understood that, as will be evident from the following discussions, throughout this description discussions in which terms such as "process", "calculate", "determine" or the like are used, refer to the operations and / or processes of a computer or computing system or similar electronic computing device that manipulate and / or convert data represented as physical, such as electronic, quantities within the registers and / or memories of the computing system into other data, likewise represented as physical quantities within the memories, registers or other such devices for storing, transmitting or displaying information.

[0015] The NVM transistor can comprise storage transistors or devices implemented with respect to silicon oxide-nitride-oxide-silicon (SONOS), metal oxide-nitride-oxide-silicon (MONOS), or floating-gate technology. An embodiment of a method for integrating or embedding NVM transistors into a standard or basic HKMG CMOS process flow for fabricating one or more types of MOS transistors, which may include HV select gates, HV gates, I / O gates (I / O = input / output), LV gates (LV = low voltage) with high-k metal gates (HKMGs), is now described with reference to the Fig. 1 to 10G described in detail. SUMMARY OF THE SUBJECT

[0016] According to one embodiment of a method for manufacturing a semiconductor device, the method may comprise the process sequence of subdividing a substrate into a first and a second region, forming a first recess to a first depth in the first region, forming an NVM transistor (NVM = non-volatile memory) and a selection transistor at least partially in the first recess, wherein the method further comprises forming a non-volatile (NV) dielectric stack in the first recess, the non-volatile dielectric stack comprising a barrier oxide arranged above a charge-trapping layer and a tunnel oxide, performing at least one silicon oxide deposition process in an atomic layer deposition (ALD) tool to form a gate dielectric layer of the selection transistor adjacent to the non-volatile dielectric stack in the first recess, and performing an oxide removal process step.to thin the thickness of the barrier oxide of the non-volatile dielectric stack, may include forming a high-k dielectric layer over the barrier oxide or gate dielectric layer, forming a sacrificial polysilicon gate over the high-k dielectric layers of the non-volatile dielectric stack or gate dielectric layer, or replacing the sacrificial polysilicon gates with metal gates.

[0017] In one embodiment, the method can be configured to form a two-transistor (2T) NVM cell.

[0018] In one embodiment, forming the first recess may include the steps of structuring a photoresist to expose the first region, performing an oxidation process in which an upper section of the substrate in the first region is consumed to form a first recess oxide layer to the first depth within the substrate, and performing an oxide cleaning process to completely remove the first recess oxide layer in the first region.

[0019] In one embodiment, the oxide removal process step of the non-volatile dielectric stack may include the steps of structuring a photoresist to expose the non-volatile dielectric stack, performing an oxide cleaning process on the barrier oxide, and calibrating the oxide cleaning process to control the thickness of the barrier oxide.

[0020] In one embodiment, the gate dielectric layer formed by the at least one silicon oxide deposition process can be deposited substantially over an upper surface of the substrate in the first recess.

[0021] In one embodiment, the increase in the upper surfaces of the sacrificial polysilicon gates of the NVM transistor and the selection transistor has a height difference of less than 50 Å.

[0022] In one embodiment, replacing the sacrificial polysilicon gates may further include the steps of forming a voltage-inducing silicon nitride layer and an interplane dielectric layer (ILD) lying over the substrate in the first region, performing a first chemical-mechanical polishing (CMP) process until at least one of the sacrificial polysilicon gates of the NVM transistor and the selection transistor is exposed, performing polysilicon etching to remove the sacrificial polysilicon gates in the NVM transistor and the selection transistor to create gate openings, forming a metal gate lying over each of the high-k dielectric layers, and performing a second CMP process to equalize the gate heights of the NVM transistor and the selection transistor.

[0023] In one embodiment, the elevation of the upper surfaces of the metal gates of the NVM transistor and the selection transistor is essentially coplanar.

[0024] In one embodiment, the manufacturing process may further comprise the steps of forming an I / O transistor (I / A = input / output), an LV transistor (LV = low voltage), and an HV transistor (HV = high voltage) outside the first recess in the second region, wherein a gate dielectric layer of the HV transistor is thicker than a gate dielectric layer of the I / O transistor, the gate dielectric of the I / O transistor is thicker than a gate dielectric layer of the LV transistor, each of the HV transistor, the I / O transistor, and the LV transistor comprises a high-k metal gate, and wherein the upper surfaces of the high-k metal gates of the NVM transistor and the selector transistor, which are located within the first recess, and the upper surfaces of the high-k metal gates of the HV transistor, the I / O transistor, and the LV transistors located outside the first recess are essentially coplanar.

[0025] In one embodiment, the manufacturing process may further include the steps of forming a second recess to the first depth in the second region simultaneously with the first recess, wherein the selection transistor and the HV transistor have the same structural features and the HV transistor can be formed within the second recess.

[0026] In one embodiment, the manufacturing process may further comprise the steps of forming a second recess to a second depth within the first recess in the first region and forming the NVM transistor within the second recess, wherein the second depth is greater than the first depth and the selection transistor is formed outside the second recess.

[0027] According to another embodiment, a method for manufacturing a semiconductor device may comprise the process sequence of subdividing a substrate into a first and a second region, forming a first recess to a first depth in the first region, forming a second recess to a second depth in the first recess, wherein the second depth is greater than the first depth, forming an NVM transistor (NVM = non-volatile memory) and a selection transistor in the first recess, forming a non-volatile (NV) dielectric stack at least partially in the second recess, wherein the non-volatile dielectric stack comprises a barrier oxide arranged above a charge-trapping layer and a tunnel oxide, and forming a gate dielectric layer of the selection transistor adjacent to the non-volatile dielectric stack and outside the second recess.the formation of an HV transistor (HV = high voltage), an I / O transistor (I / A = input / output), and an LV transistor (LV = low voltage), each containing a gate dielectric layer, in the second region outside the first recess; the formation of a high-k dielectric layer over each of the non-volatile dielectric stack and gate dielectric layer of the select transistor, the HV transistor, the I / O transistor, and the LV transistor, respectively; the formation of sacrificial polysilicon gates over the high-k dielectric layers; and the replacement of the sacrificial polysilicon gates with metal gates, with the increase of the upper surfaces of the metal gates of the NVM transistor and the select transistor in the first region and the increase of the upper surfaces of the metal gates of the HV transistor, the I / O transistor, and the LV transistor in the The second region is essentially the same.

[0028] In one embodiment, the manufacturing process may also include the steps of structuring a photoresist to expose the first region, performing an oxidation process in which an upper section of the substrate in the first region is consumed to form a first recess oxide layer to the first depth within the substrate, and performing an oxide cleaning process to completely remove the first recess oxide layer in the first region.

[0029] In one embodiment, forming the second recess may further comprise the steps of forming a recess nitride layer overlying a sacrificial oxide layer in the first region, structuring a photoresist to expose an NVM region in which the NVM transistor is to be formed, removing the recess nitride layer in the NVM region, performing a first oxidation process in the NVM region, wherein in the first oxidation process an upper portion of the substrate in the NVM region is consumed to form a second recess oxide layer within the substrate, removing the recess nitride layer in the first region, performing a second oxidation process in the first region, wherein in the second oxidation process the second recess oxide layer is further extended to the second depth in the substrate, and performing an oxide purification process.to completely remove the second recession oxide layer in the NVM area.

[0030] In one embodiment, the formation of the gate dielectric layer of the selection transistor may include the steps of performing at least one silicon oxide deposition process in an atomic layer deposition (ALD) tool to form the gate dielectric layer of the selection transistor alongside the non-volatile dielectric stack in the first recess, and performing an oxide removal process step to reduce the thickness of the barrier oxide of the non-volatile dielectric stack.

[0031] In one embodiment, replacing the sacrificial polysilicon gates may further include the steps of forming a voltage-inducing silicon nitride layer and an interplane dielectric layer (ILD) lying over the substrate in the first region, performing a first chemical-mechanical polishing (CMP) process until at least one of the sacrificial polysilicon gates of the NVM transistor and the selection transistor is exposed, performing polysilicon etching to remove the sacrificial polysilicon gates in the NVM transistor and the selection transistor to create gate openings, forming a metal gate lying over each of the high-k dielectric layers, and performing a second CMP process to equalize the gate heights of the NVM transistor and the selection transistor.

[0032] According to yet another embodiment, a method for manufacturing a semiconductor memory device may comprise the process sequence of subdividing a substrate into a first and a second region, forming a first recess to a first depth in the first region, forming a second recess to a second depth in the first recess, the second depth being greater than the first depth, forming a third recess of the first depth in the second region, forming an NVM transistor (NVM = non-volatile memory) comprising a non-volatile (NV) dielectric stack in the second recess, the non-volatile dielectric stack comprising a barrier oxide arranged above a charge-trapping layer and a tunnel oxide, and forming a selection transistor adjacent to the non-volatile dielectric stack comprising a selection-gate dielectric.that is located in the first recess and outside the second recess, forming an HV transistor (HV = high voltage), an I / O transistor (I / A = input / output), and an LV transistor (LV = low voltage), each comprising a gate dielectric layer, in the second region outside the first recess, with the HV transistor located inside the third recess, forming a high-k dielectric layer over each of the blocking oxide of the non-volatile dielectric stack, the selection gate dielectric, and the gate dielectric layers of the HV transistor, the I / O transistor, and the LV transistor, and forming a sacrificial polysilicon gate over each of the high-k dielectric layers.

[0033] In one embodiment, the elevation of the upper surfaces of the sacrificial polysilicon gates of the NVM transistor and the selection transistor in the first region and of the upper surfaces of the sacrificial polysilicon gates of the HV transistor, the I / O transistor and the LV transistor in the first and second regions has a height difference of less than 50 Å.

[0034] In one embodiment, the method may also include the step of replacing the sacrificial polysilicon gates with metal gates, wherein the increase in the upper surface area of ​​the metal gates of the NVM transistor and the selection transistor in the first region and the upper surface area of ​​the high-k metal gates of the HV transistor, the I / O transistor and the LV transistor in the second region is essentially the same. DESCRIPTION OF THE EXECUTION FORMS

[0035] Fig. Figure 1 is a block diagram representing a cross-sectional side view of a non-volatile memory cell, and its corresponding schematic representation is in Fig. Figure 2 shows that an NVM array or device (NVM = non-volatile memory) can comprise NVM cells with an NVM transistor or device implemented using silicon (semiconductor) oxide nitride oxide silicon (semiconductor) (SONOS) or floating-gate technology, and a field-effect transistor (FET) arranged side by side or coupled together.

[0036] In one embodiment, which is in Fig. As shown in Figure 1, the NVM transistor is a SONOS charge-capture NVM transistor. Referring to Fig. In Figure 1, an NVM cell 90 comprises a control gate (CG) or memory gate (MG) stack of an NV transistor 94 formed on a substrate 98. The NVM cell 90 further comprises source regions 97 / drain regions 88 formed in the substrate 98 or optionally within a positive well (PW) 93 in the substrate 98 on both sides of the NV transistor 94. The PW 93 may be at least partially embedded within a deep negative well (DNW) 99. In one embodiment, the source / drain regions 88 and 97 are connected by a channel region 91 below the NV transistor 94. The NV transistor 94 can comprise an oxide tunnel dielectric layer, a nitride or oxynitride charge-trapping layer 92, an oxide top layer, or a barrier layer forming the ONO stack. In one embodiment, the charge-trapping layer 92 can be multilayered and trap charges injected from the substrate 98 through Fowler-Nordheim (FN) tunnels.The values ​​of the threshold voltage (V. T ) and the drain current (I D The properties of the NV transistor 94 can change, at least partially, due to the amount of trapped charges. In one embodiment, a high-k dielectric layer can form at least a portion of the depletion region. A polysilicon (poly) or metal gate layer arranged above the ONO layer can serve as a control gate (CG) or memory gate (MG). As is best described in Fig. As shown in Figure 1, the NVM cell 90 further comprises a FET or selection transistor 96 arranged adjacent to the NV transistor 94. In one embodiment, the FET 96 comprises a metal or polysilicon selection gate (SG) arranged over an oxide or high-k dielectric gate dielectric layer. The FET 96 further comprises a gate oxide layer 82, source / drain regions 86 and 97 formed in the substrate 98 or optionally within the well 93 in the substrate 98 on both sides of the FET 96. As best described in Figure 1, the FET 96 is arranged in a metal or polysilicon selection gate (SG) arranged over an oxide or high-k dielectric gate dielectric layer. The FET 96 further comprises a gate oxide layer 82, source / drain regions 86 and 97 formed in the substrate 98 or, optionally, within the well 93 in the substrate 98 on both sides of the FET 96. Fig. As shown in Figure 1, the FET 96 and the NV transistor 94 can share the source / drain region 97 arranged between them, or be referred to as an internal node 97. SG is biased accordingly. SG , to open or close channel 95 below FET 96. It is assumed that the NVM cell 90, as in Fig. Figure 1 shows a two-transistor (2T) architecture, wherein the NV transistor 94 and the FET 96 can be considered in this patent document to be the storage or NVM transistor and the selection or switching transistor, respectively. In one embodiment, the selection transistor 96 can have a relatively thin gate oxide layer 82 in a range of approximately 50 Å–150 Å and can be operated in a voltage range of approximately 1.8 V–5.1 V. In embodiments, the NV transistor 94 can have a height of up to approximately 120–150 Å or more. Due to the height difference between the ONO layer of the NV transistor 94 and the oxide layer 82, a step height difference 80 can exist between the two transistors 94 and 96. As will be shown below, the step height difference 80 between different transistors, such as the NV transistor 94 and the FET 96, can cause practical difficulties during metal gate fabrication in an HKMG process flow.In embodiments, the present disclosure is directed to equalize the gate heights of the NV transistor 94 and the FET 96 or to minimize the step height difference 80 between them. As will be shown and described in later sections, the high step height difference 80, especially when it exceeds approximately 50 Å, can lead to undesirable silicon nitride deposits on the selection and HV MOS transistors or other MOS transistors during a chemical-mechanical planarization (CMP) process in HKMG fabrication.

[0037] In another embodiment, the NV transistor 94 can be a floating-gate MOS field-effect transistor (FGMOS) or an FGMOS device. In general, an FGMOS transistor is structurally similar to the SONOS-based NV transistor 94 described above, differing mainly in that, instead of the nitride or oxynitride charge-trapping layer 92, an FGMOS transistor comprises a polysilicon (poly) floating gate capacitively coupled to inputs of the device. Therefore, the FGMOS device can be described with reference to Fig. 1 described and operated in a similar manner.

[0038] Fig. Figure 2 is a schematic representation depicting a section of an NVM array 100 according to one embodiment of the subject matter. In one embodiment, which is described in Fig. As shown in Figure 2, the memory cells 90 can have a 2T architecture and, in addition to an NVM transistor, each comprise a switching or selection transistor, for example, an HV MOSFET, which shares a substrate connection or an internal node with the memory transistor. In one embodiment, the NVM array 100 comprises NVM cells 90 with a SONOS transistor 326 and selection transistors 327, arranged in N rows or sides (horizontally) and M columns (vertically) and connected by word lines, bit lines, and other links. The NVM array 100 can be embedded in another semiconductor device or semiconductor system, such as microcontrollers, which include MOSFETs and other semiconductor devices.

[0039] Fig. Figure 3 is a representative block diagram depicting an embedded SONOS or MONOS-based NVM device 300, as specified in Fig. 4, the Fig. 5A-5H, Fig. 7, the Fig. 8A-8B, the Fig. 9A-9B and the Fig. 10A-10G. In one embodiment, the embedded SONOS- or MONOS-based NVM device 300 is formed on a single semiconductor chip or substrate 310. The semiconductor chip or substrate 310 is subdivided at least into the first region or memory region 308 for the embedded memory, such as the NVM array 100, and the second region or CMOS or logic region 318 for HV-MOS transistors 312, I / O-MOS transistors 314, or LV-MOS transistors 316, respectively. In some embodiments, MOS transistors may be present in the first region 308 because some NVM memory arrays may include HV selection transistors. For example, a two-transistor (2T memory gate / selection gate) configuration memory array that incorporates HV transistors as selection transistors. The second region 318 can further be subdivided into an HV-MOS area 302, an I / O_MOS area 304 and an LV-MOS or core area 306.It is understood that the embedded SONOS- or MONOS-based NVM device 300 may include further devices such as processors, power circuits, etc. In various embodiments, one or more of the first and second regions 308 and 318 may spatially overlap, and the HV MOS area 302, the I / O MOS area 304, and the LV MOS or core area 306 may overlap. It is understood that the in . Fig. The embodiment shown in Figure 3 is purely exemplary and one or more of the first region 308 and the HV-MOS area 302, the I / A_MOS area 304 and the LV-MOS or core area 306 may be located at any point on a single substrate 300 or several substrates and may consist of different regions.

[0040] In one embodiment, the HV-MOS 312 and the selection transistors in the SONOS / MONOS arrangement can have the same or similar structural features (e.g., the same gate oxide thickness) and be supplied with a high voltage in the range of 4.5 V–2 V or other voltages to program NVM transistors in the NVM 100 arrangement and / or remove a charge from them. The I / O_MOS 314 can be coupled to the I / O interface and supplied with an operating voltage in the range of 1.6 V–3.6 V or other voltages. The LV-MOS or core MOS 312 can be supplied with an operating voltage in the range of 0.8 V–1.4 V or other voltages for various operations and connections.

[0041] This disclosure introduces and describes processes for embedding an oxide-nitride-oxide (ONO) or ONONO charge-trapping stack with single-layer or double-layer nitride in a CMOS process that includes high-frequency manifolds (HMMs) and / or a thick gate oxide for the selection gate and high-voltage (HV) devices. In embodiments, the ONO or ONONO charge-trapping stack is thicker than the gate oxide layers of other CMOS devices that include a gate oxide for the selection gate and HV devices. The gate height difference can cause problems during the CMP process of interlayer dielectric materials, such as nitride, prior to dummy or sacrificial polysilicon gate removal. The residual nitride covering over selection gates can act as a mask during the polysilicon removal process. The residual polysilicon in selection gates will inadvertently have a significant negative impact on the operation of the selection gates and the overall yield.Therefore, it is advantageous to equalize the gate heights or to minimize the gate height difference or to compensate for the increase in the upper surfaces of NVM devices and CMOS devices.

[0042] Fig. Figure 4 is a representative flowchart illustrating an embodiment of a method for fabricating a SONOS-based non-volatile memory cell using HKMGs, such as the NVM cell 90, comprising the NV transistor 94 and the FET 96, as best described in Fig. Figure 1 shows an embodiment of the present disclosure. With reference to Fig. 4 and Fig. 5A The process begins with an optional pre-cleaning step of the substrate 504. In one embodiment, the substrate 504 can be subdivided into one or more memory regions or first regions 308 and CMOS regions or second regions 318. The substrate 504 may be a solid substrate consisting of any single-crystal material suitable for semiconductor device fabrication, or it may comprise an upper epitaxial layer formed on a substrate of a suitable material. In one embodiment, suitable materials for the substrate 504 include, among others, silicon, germanium, silicon-germanium, or a group III-V compound semiconductor material. In some embodiments, MOS transistors, such as HV-MOS transistors 312, may be present in the first region 308. This is because certain NVM memory arrays may include HV-MOS transistors as selection transistors, for example, in a two-transistor (2T) memory array, such as e.g. the NVM cell 90 in Fig. 1. In one embodiment, at the beginning of the manufacturing process, in Fig. 4 the upper surface of substrate 504 in memory and CMOS regions 308 and 318 be coplanar.

[0043] With reference to Fig. 5A An oxide layer 534 can be formed over both the memory region 308 and the CMOS region 318 in the substrate 504. In embodiments, the oxide layer 534 can be formed by a rapid thermal dry oxidation (RTO) process, a conventional oxidation or furnace oxidation process, a rapid and radical wet oxidation process such as in-situ vapor generation (ISSG), a chemical vapor deposition (CVD) process, or other oxide formation processes known in the art, or a combination thereof. Subsequently, a nitride layer 532 can be formed over or directly above the oxide layer. In embodiments, the nitride layer 532 can be deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) and consists of a dielectric layer, which may include silicon oxynitride or silicon nitride, among other materials.In one embodiment, the oxide layer 534 can be formed in a range of approximately 100 Å to 200 Å thickness and the nitride layer 532 in a range of approximately 500 Å to 1,000 Å.

[0044] Next, with reference to Fig. 4 and Fig. 5B in step 408, a nitride etching was performed at least in the NVM transistor or SONOS area 326. How best to do this in Fig. As shown in Figure 5B, a structured mask layer 530 can be formed and structured on or over the substrate 504. The structured mask layer 530 can open or expose at least the NVM transistor region 326 in the first region 308 for one or more subsequent etching processes of the nitride layer 532 or the oxide layer 534. The structured mask layer 530 can comprise a photoresist layer that is structured using standard lithography techniques, a hard mask layer, or other techniques known in the art. In one embodiment, the nitride layer 532 in the NVM transistor region 326 is then removed using a plasma etching process or similar etching processes known in the art. The plasma etching process can terminate at the oxide layer 534, as best shown in Figure 5B. Fig. 5C can be seen. Alternatively, the plasma etching process can end on an upper surface of the substrate 504 in the NVM transistor area 326, so that the oxide layer 534 is also removed.

[0045] With reference to Fig. In 5D, the structured mask layer 530 located above the substrate 504 can be removed. In one embodiment, the structured mask layer 530 is completely removed from both the memory region 308 and the CMOS region 318. Photoresist material in the structured mask layer 530 can be ashed or stripped using oxygen plasma. Alternatively, it can be removed using a wet or dry etching process.

[0046] With reference to Fig. 4 and Fig. In step 410, the NVM oxide layer 536 is produced or formed in the NVM transistor region 326 by growth. In one embodiment, the NVM oxide layer 536 is formed using RTO, furnace oxidation, radical oxidation, or other oxidation processes in which the substrate 504 is used or consumed as at least one of the silicon sources. Since silicon from the substrate 504 is required or otherwise consumed during the formation of the NVM oxide layer 536, the NVM oxide layer 536 can grow both above and below, or elsewhere within, the substrate 504 in the NVM transistor region 326 to a thickness of approximately 100 Å to 200 Å, as best described in Fig. 5D shown. The NVM oxide layer 536 can be grown to a depth D1 below the upper surfaces of the substrate 504 in other areas / regions. In one embodiment, areas other than the NVM transistor region 326, which include the CMOS region 318 and the selection transistor region 327, are protected by at least the nitride layer 532, with no or very little oxide being grown in these areas. With reference to Fig. In 5D, an oxide pre-cleaning process is performed to thin or etch the NVM oxide layer 536. The NVM oxide pre-cleaning may, for example, include a wet cleaning process using a 10:1 buffered oxide etching (BOE) containing a surfactant. Alternatively, the wet cleaning process may be performed using a 20:1 BOE wet etching, a 50:1 hydrogen fluoride (HF) wet etching, pad etching, or another similar hydrogen fluoride-based wet chemical etching. In one embodiment, the wet cleaning process is calibrated or time-controlled such that a predetermined thickness of the NVM oxide layer 536', as best described in Fig. 5E can be seen protecting the surface of the substrate 504 in the NVM transistor area 326 during a plasma etching process in one or more subsequent steps.

[0047] Next, with reference to Fig. 4 and Fig. 5E created an NVM array resist mask over CMOS region 318. In the previous step for 410 and Fig. In the embodiment described in Figure 5D, in which the structured mask layer 530 is completely removed from both the memory region 308 and the CMOS region 318, a memory mask layer 531 can be formed and structured on or over the substrate 504. In one embodiment, the memory mask layer 531 can open or expose at least the memory region 308 for the subsequent process of removing the nitride layer 532 (step 412). The memory mask layer 531 can comprise a photoresist layer that is structured using standard lithography techniques, a hard mask layer, or other techniques known in the prior art. In one embodiment, the nitride layer 532 in the memory region 308 is then completely removed, as is best described in Figure 5D. Fig. 5E. The nitride layer 532 can be removed by a dry or plasma-assisted etching process, or by a selective wet etching process using a phosphoric acid solution in water, or by other etching methods known from the prior art. In one embodiment, the nitride removal process can terminate at the oxide layer 534 and the NVM oxide layer 536' in the storage region 308, as best shown in Fig. 5F can be seen. In one embodiment, the nitride layer 532 in the CMOS region 318 remains intact because it is protected by the memory mask layer 531.

[0048] Next, the memory mask layer 531 over the substrate 504 in the CMOS region 318 can be completely or partially removed. Photoresist material in the structured mask layer 530 can be ashed or stripped using oxygen plasma. Alternatively, it can be removed using a wet or dry etching process or other removal processes known to and practically feasible for a person skilled in the art.

[0049] With reference to Fig. 4 and Fig. In step 414, the NVM cavity oxide layer 538 is formed in the memory region 308. In one embodiment, the NVM cavity oxide layer 538 is formed using RTO, furnace oxidation, radical oxidation, or other oxidation processes, in which the substrate 504 is used or consumed as at least one of the silicon sources. Since silicon is consumed from the substrate 504 to form the NVM cavity oxide layer 538, it can grow both above and below, or elsewhere within, the substrate 504 in the SONOS transistor region 326 and the selection transistor region 327, as best described in Fig. 5G is visible. In one embodiment, in the SONOS transistor region 326, during the oxidation carried out in step 414, the previously formed NVM oxide layer 536' can further grow to a depth of D2 within the substrate 504. In the selection transistor region 327, the NVM recess oxide layer 538 can also grow within the substrate 504 to a depth of D3. As is best described in Fig. As can be seen in step 414, the CMOS region 318 is protected from the oxidation process by the nitride layer 532, so that no or minimal oxide is produced from or formed in the oxide layer 534 by growth. Consequently, the increase in the upper surface area 520 of the substrate 504 in the CMOS region 318 can remain essentially unchanged.

[0050] The remaining nitride layer 532 in CMOS region 318 can then be removed by a dry or plasma-assisted etching process, a selective wet etching process using a phosphoric acid solution in water, or other etching methods known from the prior art. In one embodiment, the nitride removal process can terminate at the oxide layer 534 in CMOS region 318.

[0051] With reference to Fig. 4 and Fig. In step 416, oxide layers are removed from both memory region 308 and CMOS region 318, which lie above substrate 504. How best to proceed is described in... Fig. As can be seen in Figure 5H, the oxide layer 534 in the CMOS region 318 and the NVM recess oxide layer 536 in the memory region 308 are removed from the surfaces of the substrate 504. In one embodiment, the oxide layers 534 and 538 can be removed by a plasma etching process or a wet cleaning process using a 10:1 buffered oxide etch (BOE) containing a surfactant. Alternatively, the wet cleaning process can be performed using a 20:1 BOE wet etch, a 50:1 hydrogen fluoride (HF) wet etch, pad etching, or another similar hydrogen fluoride-based wet chemical etch. After oxide removal, the surfaces are treated as best described in Figure 5H. Fig. As can be seen in Figure 5H, the NVM array recess 552 is created in the memory region 308, with the NVM transistor 326 and the selection transistor 327 being fabricated therein. In one embodiment, the lower surface 522 of the NVM array recess 552 is located at a depth D3 relative to the upper surface 520 of the substrate 504 in the CMOS region 318. A SONOS trench or SONOS recess 550 is also created in the SONOS transistor region 326, with the lower surface 524 of the SONOS trench 550 located at a depth D2 in a range of approximately 30 Å to 60 Å relative to the lower surface 522 of the NVM array recess 552. In one embodiment, NVM transistors, such as the NVM transistor 94 in Fig. 1, at least partially formed within the SONOS trench 550, whereas selection transistors, such as the selection transistors 96, are formed at least partially within the NVM array recess 552. In other embodiments, the HV-MOS 302, which may have similar structural features and dimensions to the selection transistors 96, may also be formed within an HV recess area 553 formed in the CMOS region 318. In one embodiment, the HV recess area 553 may be formed in a similar manner to the NVM array recess 522 in the memory region 308, as previously described in the Fig. 5D-5G shown and described.

[0052] Fig. Figure 6 is a representative diagram depicting an NVM cell 600 formed in the NVM array recess 552. In embodiments, the NVM array recess 552 can be shaped according to the manufacturing process, as shown in the Fig. 4 and Fig. 5A-5H, or other similar processes carried out practically according to the prior art. With reference to Fig. 6. The NVM cell 600 may be a 2T memory cell with a structure as similar as the NVM cell 90, as in Fig. Figure 1 shows a control gate (CG) or memory gate (MG) stack of an NVM transistor 326, formed at least partially within the SONOS trench 550 above the substrate 504, and a select transistor 327, located adjacent to the NVM transistor 326, which is formed at least partially within the NVM array recess 552. As previously explained, due to the height or thickness difference between the ONO layer 602 of the NVM transistor 326 and the relatively thinner gate dielectric layer 604 of the select transistor 327, a step height difference of up to 150 Å can exist between the two transistors 326 and 327, as best illustrated in Figure 1. Fig. Figure 1 shows that in one embodiment, the formation of the NVM transistor 326 in the SONOS trench 550, which has a lower elevation than the NVM array recess 552, can compensate for the height difference between the two transistors 326 and 327. In another embodiment, by controlling the depth D3 and / or the depth D2, the gate height difference 606 can be eliminated or at least minimized within an operationally acceptable range of less than approximately 50 Å for the subsequent HKMG process. In other embodiments, the depth D3 and the depth D2 can be calibrated or adjusted by calibrating or adjusting operating parameters of the oxidation processes, as described in the following descriptions: Fig. 4, Fig. 5D and Fig. 5G is explained in more detail and can be manipulated.

[0053] Fig. Figure 7 is a representative flowchart illustrating a method for fabricating a SONOS-based non-volatile memory cell using HKMGs, such as the NVM cell 600, which includes the NVM transistor 326 and the selection transistor 327, as best described in Fig. Figure 6 shows another embodiment of the present disclosure. With reference to Fig. 7 and Fig. In step 708, an NVM array resist mask is formed over CMOS region 318. The mask layer 802 can be formed and patterned on or over substrate 504. In one embodiment, the mask layer 802 can at least open or expose memory region 308 for the subsequent oxide growth process (step 710). In another embodiment, the memory mask layer 802 can additionally open or expose at least the HV-MOS area 302 in CMOS region 318. The mask layer 802 can comprise a photoresist layer patterned using standard lithography techniques, a hard mask layer, or other techniques known in the art. Next, in step 710, the NVM recess oxide layer 806 is formed in memory region 308.In one embodiment, the cavity oxide layer 806 is formed in at least the memory region 308 or additionally in the HV-MOS region 302 using RTO, furnace oxidation, radical oxidation, or other oxidation processes, in which the substrate 504 is used or consumed as at least one of the silicon sources. Since silicon from the substrate 504 is consumed to form the cavity oxide layer 806, it can grow both above and below, or elsewhere within, the substrate 504 in the SONOS transistor region 326 and the selection transistor region 327 to a thickness of approximately 100 Å to 200 Å, as best illustrated in Figure 1. Fig. Figure 8A shows that in one embodiment, the recess oxide layer 806 can grow within the substrate 504 to a depth of D4. In another embodiment, the CMOS region 318 (unlike possibly the HV-MOS region 302) is protected from the oxidation process in step 710 by the mask layer 802, so that no or minimal oxide is generated therein by growth. Consequently, the increase in the upper surface area 520 of the substrate 504 in the CMOS region 318 can remain essentially unchanged. In another embodiment, the HV-MOS region 302, which is not protected by the mask layer 802, can also form the recess oxide layer 806 to a depth of D4 within it.

[0054] Next, the mask layer 802 over the substrate 504 in the CMOS region 318 can be completely or partially removed. Photoresist material in the structured mask layer 802 can be ashed or stripped using oxygen plasma. Alternatively, it can be removed using a wet or dry etching process or other removal processes known to and practically feasible for a person skilled in the art.

[0055] With reference to Fig. 7 and Fig. In step 712, the recess oxide layers 806 are removed from both the memory region 308 and the CMOS region 318, which lie above the substrate 504. As is best done in Fig. As shown in Figure 8B, one or more recess oxide layers 806 in the memory region 308 or the CMOS region 318 are removed from the surfaces of the substrate 504. In one embodiment, the recess oxide layer 806 can be removed by a plasma etching process or a wet cleaning process using a 10:1 buffered oxide etch (BOE) containing a surfactant. Alternatively, the wet cleaning process can be performed using a 20:1 BOE wet etch, a 50:1 hydrogen fluoride (HF) wet etch, pad etching, or another similar hydrogen fluoride-based wet chemical etch. After oxide removal, as is best done in Fig. Figure 8B shows an NVM array recess 552 created in memory region 308, where both the NVM transistor 326 and the selection transistor 327 are fabricated. Additionally, a similar HV recess 553 with a depth of D4 can be created in CMOS region 318. In one embodiment, the lower surface 804 of the NVM array recess 552 or the HV recess 553 is located at a depth D4 relative to the upper surface 520 of the substrate 504 in the CMOS region 318. In embodiments, the depth D4 can compensate for the height difference between the NVM transistor 326, the selection transistor 327, or the HV MOS 312 formed within one or more recesses, and the I / O MOS 314 and the LV MOS 316 formed outside one or more recesses in the CMOS region 318.

[0056] Fig. Figure 9A is a representative flowchart describing a method for fabricating a SONOS-based non-volatile storage device 1000 using HKMGs, such as the NVM cell 600, which includes the SONOS transistor 326 and the selection transistor 327, as best described in Fig. Figure 6 shows an embodiment of the present disclosure. With reference to Fig. 9A the process can be applied to the in Fig. 5H embodiment in which the SONOS trench 550 is formed in the NVM array recess 552, or which is shown in Fig. The embodiment shown in Figure 8B, in which no SONOS Trench 550 was formed, is to be followed. It is understood that the process flow described in Figure 8B is the same as the embodiment shown in Figure 8B. Fig. 9A, Fig. 9B and the Fig. Figure 10A-10G shows that the SONOS-based NVM device 1000 can be used regardless of whether the NVM transistors 326 are formed within the SONOS trench 550 or not. In one embodiment, the NVM device 1000 resembles the NVM device 300 in Figure 10A-10G. Fig. 3, in which both one or more NVM arrays and the logic devices are arranged within a single substrate.

[0057] With reference to Fig. 9A and Fig. 9B The process can include the formation of multiple features within the substrate 504 in step 948. In one embodiment, the process can begin with the formation of a number of isolation structures or a shallow trench isolation (STI) 502 in a wafer or substrate 504 (step 948). The STIs 502 isolate the memory cell being formed from memory cells being formed in (not shown) adjacent regions of the substrate 504. Optionally and additionally, isolation structures 502 can be integrated to isolate the one or more formed NVM transistors 326 from the one or more HV selection transistors 327 in the memory region 308 of the substrate 504 and from one or more of the MOS transistors, which include the HV-MOS 312, the I / O_MOS 314 and the LV-MOS 316, which are formed in the CMOS region 318.In embodiments, isolation structures 502 can be formed to isolate the HV-MOS area 302, the I / O_MOS area 304, and the LV-MOS area 306 from each other and / or from these areas in order to isolate transistors formed therein. It is understood that isolation structures 502 can be formed anywhere in the substrate 504 according to the design and requirements of the system and are not limited to those specified in the system. Fig. Figure 9B and the following figures may or may not show the insulating structures. In one embodiment, the insulating structures 502 may comprise a dielectric, such as an oxide or nitride, and may be formed by any conventional technique, including, but not limited to, trench insulation (STI) or spot oxidation of silicon (LOCOS). In another embodiment, a pad oxide (not shown) may be formed to cover the entire surface of the substrate 504. The pad oxide may be silicon dioxide (SiO2) with a thickness of about 10 nanometers (nm) to about 20 nm or other thicknesses and may be formed by a thermal oxidation process, an in-situ vapor generation (ISSG) process, or other oxidation or deposition processes known in the art. It is understood that in some embodiments, a pad oxide may not be required or formed.

[0058] Next, dopants are implanted through the pad oxide (if present) into the substrate 504 to form wells in which one or more NVM transistors and / or HV-MOS transistors can be formed, and channels for the HV-MOS transistors or other MOS transistors (step 948). According to the system design, the insulating structures 502 may or may not be arranged between the first region 308 and the second region 318. The implanted dopants can be of any type and concentration and can be implanted at any energy, including energies necessary to form wells 510 or deep wells 511 for the NVM transistors and / or the HV-MOS transistors and to form channels 518 for the HV-MOS transistors. In a particular embodiment, which is described in Fig. As illustrated by example in Figure 9B, dopants of a suitable ion species are implanted to form a P-well 510 in the second region 318 above or within the HV-MOS transistor region 302, in which one or more N-type or N-channel transistors can be formed. In other embodiments, wells or deep wells can also be formed for the NVM array 100, which includes the SONOS 326 and / or the selection transistor 327 in the first region 308. It is further understood that the wells, such as the P-well 510, can be formed by depositing and structuring a mask layer, such as a photoresist layer, over the surface of the substrate 504 and implanting a suitable ion species at a suitable energy up to a suitable concentration.It is understood that both P-type and N-type transistors may be present in the first region 308 and / or the second region 318, and the doping implantation conditions may be adjusted accordingly. The locations, quantity, and types of the one or more NVM transistors 326, the one or more selection transistors 327, the HV-MOS 312, the I / O_MOS 314, and the LV-MOS 316, which are in . Fig. Figures 9B and others are for illustrative purposes only and are not to be interpreted as restrictive. It is clear to those skilled in the art that several first and second regions, MOS regions 302, 304, 306, can be formed within the substrate 504. One or more corresponding NVM transistors 326, selection transistors 327, an HV-MOS 312, an I / O_MOS 314, and an LV-MOS 316 can be formed simultaneously, subsequently, or in groups using the process steps disclosed herein.

[0059] In one embodiment, the channels 518 for one or more of the selection transistor 327 in the first region 308 and the HV-MOS transistors 312 in the second region 318 of the substrate 504 can be formed. It is understood that the channels 518 of the selection transistors 327 and the HV-MOS transistors 312 can be formed simultaneously or separately. As with the well implantation method, the channels 518 can be formed by depositing and structuring a mask layer, such as a photoresist layer, over the surface of the substrate 504 and implanting a suitable ion species at a suitable energy up to a suitable concentration.It is understood that the implantation can also be used to form channels in all three of the MOS regions 302, 304, and 306 simultaneously or at different times using standard lithography techniques, including a structured photoresist layer, to mask one of the channels for the MOS transistors 312, 314, and 316. It is understood that one or more of the STI formation, channel formation, and well / deep well formation, as mentioned above, can be performed for one or more devices after these devices, such as the NVM transistor 326, the selection transistor 327, or the MOS transistors 312, 314, and 316, have been formed in step 966.

[0060] With reference to Fig. 9 and Fig. In step 950, several dielectric layers, comprising the tunnel dielectric 810, the charge-trapping layer 812, and the barrier dielectric 814, are formed and patterned in the NVM array recess 552. In embodiments, the patterned dielectric layers (810, 812, 814) can be formed in the SONOS trench 550 (not shown), if present, or simply within the NVM array recess 552 at depth D4. In one embodiment, the tunnel dielectric 810, the charge-trapping layer 812, and the barrier dielectric 814 are first formed to lie over the memory region 308 and the CMOS region 318, and then patterned to completely remove them in areas outside the SONOS transistor region 326. The total height of the structured dielectric layers (810, 812, 814) can be in a range of approximately 120 Å to 150 Å or other thicknesses.

[0061] In one embodiment, the tunnel dielectric 810 can be any material and have any thickness suitable to allow charge carriers to tunnel into an overlying charge-trapping layer 812 when a gate bias is applied, while maintaining a suitable barrier against leakage currents when the NVM transistor 326 is not biased. In some embodiments, the tunnel dielectric 810 can be silicon dioxide, silicon oxynitride, or a combination thereof, and can be produced by a thermal oxidation process via ISSG or radical oxidation by growth.In embodiments, the charge-trapping layer 812 can be a single- or multi-layer charge-trapping layer 812 comprising several layers, including at least a lower or first charge-trapping layer located physically closer to the tunnel dielectric 810, and an upper or second charge-trapping layer that is oxygen-deficient relative to the first charge-trapping layer and contains a large proportion of charge-trapping sites distributed throughout the multi-layer charge-trapping layer 812. In one embodiment, the first and second charge-trapping layers of the multi-layer charge-trapping layer 812 may comprise a silicon nitride or silicon oxynitride layer, each with a different stoichiometric ratio of oxygen, nitrogen, and / or silicon.In another embodiment, a thin dielectric layer and / or oxide layer may be formed between the first and second charge-trapping layers, thereby transforming the charge-trapping layer 812 into a nitride-oxide-nitride (NON) layer. In one embodiment, the barrier dielectric 814 can be any material and have any thickness suitable for insulating the charge-trapping layer 812 from the gate of the NVM transistor 326. In some embodiments, the barrier dielectric 814 can be silicon dioxide, silicon oxynitride, or a combination thereof, and can be produced by a thermal oxidation process by ISSG or radical oxidation, or by conventional deposition processes known from the prior art.

[0062] How best to Fig. As shown in Figure 10A, in one embodiment the structuring step can terminate at the top surface 804 in the memory region 308, the top surface 520 in the CMOS region 318, or the top surface 804 in the HV-MOS region 302. The structuring step can involve the use of a photoresist layer structured using standard lithography techniques, and the non-volatile dielectric layers (810, 812, 814) outside the NVM transistor 326 can be etched or removed using a dry etching process comprising one or more distinct steps to terminate at the surfaces of substrate 504 (520 and 804).

[0063] Next, with reference to Fig. 9 and Fig. In step 952, the HV-gate dielectric layer 816 is a silicon oxide layer formed in the selection transistor region 327 in the NVM array recess 552 or in the HV-MOS region 302 in the HV recess 553. In one embodiment, the HV-gate dielectric layer 816 can be formed over the entire substrate 504 in a single in-situ atomic layer deposition (ALD) chamber designed for thermal ALD or plasma-enhanced ALD (PEALD), using either a batch or single-processing unit. In one embodiment, chlorosilane, such as hexachlorosilane Si₂Cl₆ (HCD), can be the precursor or silicon source gas. Hydrogen (H2) and oxygen (O2) gas are introduced into the ALD chamber in a ratio of approximately 1:4 to each other without an external ignition event, such as the formation of a plasma.The H₂ and O₂ are allowed to react at a temperature in the range of approximately 300°C to approximately 400°C and a pressure in the range of approximately 0.5 Torr to approximately 10 Torr to form radicals, such as an OH radical, an HO₂ radical, or an O diradical, which ultimately react with HCD to form the deposited silicon oxide above the surface of the substrate 504. The sequential, self-limiting surface reaction properties of ALD deposition and the uniformity control with atomic-scale accuracy at a relatively low thermal budget (such as below 650°C) enable the HV-gate dielectric layer 816 to form with no or minimal reaction with silicon in the substrate 504.Consequently, the HV-gate dielectric layer 816 is formed substantially above the substrate surface 804 in the NVM array recess 552 or the HV recess 553 (if present) and would not adversely increase the height difference between the non-volatile dielectric layers (810, 812, 814) of the NVM transistor 326 and the HV-gate dielectric layer 816 of the selection transistor 327 or the HV-MOS 312. In another embodiment, the HV-gate dielectric layer 816 can also be formed by chemical vapor deposition, physical vapor deposition, or other oxide deposition processes to avoid reaction with or consumption of the substrate 504. Next, the HV gate dielectric layer 816 is structured to form a gate dielectric for the HV MOS 312 and the selection transistor 327.

[0064] How best to Fig. As can be seen in Figure 10B, the thickness of the blocking dielectric 814' can increase due to the deposition of the HV-gate dielectric layer 816, since the dielectric layers (810, 812, 814) of the NVM transistor 326 are also subject to the deposition process of the HV-gate dielectric layer 816. Next, with reference to Fig. 10C the barrier dielectric 814" is thinned or etched in step 952. In one embodiment, the thinning step may include the use of a photoresist layer 819, which is patterned using standard lithography techniques to expose the non-volatile dielectric layers (810, 812, 814') of the NVM transistor 326, as best described in Fig. 10B and Fig. 10C can be seen. The barrier dielectric thinning process can, for example, include a wet cleaning process using a 10:1 buffered oxide etching (BOE) containing a surfactant. Alternatively, the wet cleaning process can be performed using a 20:1 BOE wet etching, a 50:1 hydrogen fluoride (HF) wet etching, pad etching, or another similar hydrogen fluoride-based wet chemical etching. In one embodiment, the wet cleaning process is calibrated or time-controlled such that a predetermined or ideal thickness of the barrier dielectric 814" is maintained in a range of approximately 20 Å to 50 Å or other thicknesses.The oxide thinning process allows the barrier dielectric 814" to be kept within its operating thickness, while reducing the overall height difference between the non-volatile dielectric layers (810, 812, 814") of the NVM transistor 326 and the HV gate dielectric layer 816 of the selection transistor 327 or the HV MOS 312. Alternatively, the barrier dielectric 814" can be thinned by plasma etching, chemical etching, or other etching processes known in the art. The HV dielectric layers 816 in the selection transistor 327 or the HV MOS 312 can be structured such that the HV dielectric layer 816 deposited in the CMOS region 318 can be completely or partially removed.

[0065] Next, with reference to Fig. 9 and Fig. 10D The gate dielectric of the I / O_MOS and the LV-MOS is formed and structured in step 952 in the CMOS region 318. In embodiments, an I / O dielectric 820 and an LV dielectric 818 can be silicon dioxide, silicon oxynitride, or a combination thereof, and can be produced by a thermal oxidation process by ISSG or radical oxidation, ALD, or conventional deposition processes known from the prior art by growth. In embodiments, the thicknesses of the LV gate oxide layer 818, the I / O gate oxide layer 820, and the HV gate oxide layer 816 have an ascending order; and all transistor oxide layer types can be formed simultaneously or individually. Subsequently, in step 954, as is best described in Fig. Figure 10D shows the structured LV gate oxide layer 818, the I / O gate oxide layer 820, and the HV gate oxide layer 816. Although only one of each transistor type (SONOS NVM transistor, switching transistor, HV MOS transistor, I / O MOS transistor, LV MOS transistor) is shown, it is understood that multiple transistors of each type (in ) can be produced using the aforementioned procedures and process steps. Fig. 10D not shown) can be produced simultaneously or subsequently. How best to do this in Fig. As can be seen in Figure 10D, the I / O dielectric 820 and the LV dielectric 818 are formed outside the NVM array recess 552 or the HV recess 553 (if present) such that the total gate height difference 850 under all devices is kept to a minimum of less than 50 Å. When the NVM gate stack 850 is formed in the SONOS trench 550, as is best done in Fig. 6 can be seen (in Fig. (10D not shown), it can further compensate for the gate height with other devices, including the selection transistor 327 and the devices (312, 314, 316) in the CMOS region 318, or reduce the total gate height difference 850.

[0066] With further reference to Fig. 9A and Fig. In step 10D, a high dielectric constant dielectric or a high-k dielectric layer 835 is formed or deposited in the first region 308 and in the second region 318 on or over the blocking dielectric 814" of the NVM transistor 326 and the HV gate oxide 816 of the selection transistor 327 (step 956). The high-k dielectric layer 835 can comprise, among other materials, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, hafnium zirconium oxide, and lanthanum oxide, deposited to a physical thickness between about 3.0 nm and about 8.0 nm or other thicknesses, e.g., by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), or a plasma-enhanced CVD process. (PECVD).

[0067] How best to Fig. As shown in Figure 10D, a polysilicon or poly-gate layer 840 is deposited or formed over substantially the entire surface of the substrate 504, or at least in both the first and second regions 308 and 318, and all layers and structures formed thereon (step 956). In one embodiment, the polysilicon-gate layer 840 can be formed by chemical vapor deposition (CVD) to a thickness of about 30 nm to about 100 nm, or other suitable thicknesses. In other embodiments, the polysilicon or poly-gate layer 840 can be formed by other deposition or manufacturing processes known in the prior art. In an alternative embodiment, a thin layer of titanium nitride (not shown in this figure) is deposited prior to the deposition of the poly-gate layer 840, and the poly-gate layer 840 can be deposited over the thin titanium nitride layer.Titanium nitride deposition is optional and can facilitate subsequent structuring or removal of the poly-gate layer. In one embodiment, the poly-gate layer 840 can be conformally deposited and then structured to form sacrificial or dummy polysilicon gates 840' for all devices in memory region 308 and CMOS region 318 in step 958.

[0068] Next, with reference to Fig. 9 and Fig. 10E deposited and etched a spacer layer to form sidewall spacers or offset spacers 828 adjacent to the dummy or sacrificial polysilicon gates 840' of the MOS transistors 312, 314, 316, the selection transistor 327, and the NVM transistor 326 (step 958). In one embodiment, the spacer layer may comprise silicon oxide or silicon nitride deposited to a thickness of about 5 nm to about 20 nm using any known CVD technique as described herein. In another embodiment, the sidewall spacers 828 may comprise multiple layers of different dielectric materials.

[0069] With reference to Fig. 9 and Fig. 10E further comprises the process of forming a stress-inducing lining or layer 830, such as a stress-inducing nitride layer, and depositing an interplane dielectric layer (ILD layer) 860 over substantially the entire surface 520, 522 and 524 of the substrate 504 and any layers and structures formed thereon, wherein the ILD layer 860 is planarized, for example, by using a chemical-mechanical polishing (CMP) process (step 958).The stress-inducing layer 830 can comprise a compression or tension nitride layer formed using plasma-enhanced chemical vapor deposition (PECVD) or a bis-tert-butylaminosilane nitride layer (BTBAS nitride layer), deposited to a thickness of about 30 nm to about 70 nm or other thicknesses using any known technique, including chemical vapor deposition, or produced by growth. The ILD layer 860 can, for example, comprise silicon nitride or silicon oxide deposited to a thickness of about 0.5 µm to about 1.0 µm or other thicknesses using any known CVD technique, as described above, or produced by growth.

[0070] Next, with reference to Fig. 10F, a chemical-mechanical planarization (CMP) process is performed to expose the sacrificial polysilicon gates 840 in the NVM transistor 326 and the selector transistor 327 in the first region 308, and the MOS transistors 312 (not shown), 314, and 316 in the second region 318. As best described in Fig. As illustrated in Figure 10F, a single CMP process is performed to expose all targeted dummy polysilicon gates 840'. As previously explained, the gate height of various transistors, or the height differences of the top surfaces of various transistors, e.g., the NVM 326, the selection transistor 327, and the HV-MOS 312, or the I / O_MOS 314 and the LV-MOS 316, can be compensated for or greatly reduced by the presence of the SONOS trench 550 and / or the NVM array recess 552 and / or the HV recess 553, as best illustrated in Figure 10F. Fig. 10D. Therefore, ILD material and SiN residue problems and their corresponding effects during the CMP process step can be reduced or minimized. Due to the possible difference in gate heights, different transistors may exhibit different thicknesses of the remaining dummy polygates 840' after the CMP process step. In another embodiment, due to the potential difference in the total gate heights of different transistors, multiple CMP processes can be employed, so that all targeted dummy polysilicon gates 840' are exposed.

[0071] With reference to Fig. 9 and Fig. In step 960, dummy polysilicon gates 840' are removed. In one embodiment, the dummy polysilicon gates 840' can be removed to create gate openings 870 using standard polysilicon etching chemistries, such as CHF3 or C2H2 or HBr / O2, and prior art methods that are highly selective for the material of the ILD layer 860, the voltage-inducing lining 830, and the sidewall spacers 828. In an alternative embodiment, one or more dummy polysilicon gates 840' in the NVM transistor 326, the selection transistor 327, and / or the MOS transistors 312, 314, and 316 can remain in place in cases where a polysilicon gate is preferred over a metal gate. In the embodiment in which the thin titanium nitride is present, the polysilicon etching can instead terminate at the thin titanium nitride layer (not shown).In one embodiment, the polysilicon etching process can terminate at the high-k dielectric layer 835, as best shown in . Fig. 10F can be seen.

[0072] Next, with reference to Fig. 9 and Fig. 10G first metal layers 832 of multilayer metal gates are formed (step 962). In one embodiment, the multilayer metal gates can replace the removed dummy polysilicon gates 840 in the gate openings 870. The first metal layer 832 is deposited over substantially the entire surface of the substrate 504 and all layers and structures formed thereon, with a structured photoresist layer (not shown) being formed using standard lithography techniques to remove the first metal layer 832 outside the gate openings 870 in the first and second regions 308 and 318. As best as in Fig. As can be seen in Figure 10G, the first metal layer 832 can be formed over the high-k dielectric layers 835 and optionally on the sidewalls of the gate openings 870, which were previously covered by the dummy polysilicon gates 840'. In embodiments, the first metal layers 832 can be a P+ metal layer (high work function metal) comprising aluminum, titanium, or compounds or alloys thereof, deposited to a thickness of about 20 nm to about 100 nm or other thicknesses using physical or chemical vapor deposition. The P+ metal can form a high work function gate for one or more P-type NVM transistors and one or more P-type MOS transistors.In other embodiments, the first metal layers 832 can comprise an N+ metal layer that is deposited and etched to form a non-high or low work function metal gate for one or more N-type transistors in the first and second regions 308 and 318. The N+ metal can comprise titanium, lanthanum, aluminum, or compounds or alloys thereof, deposited to a thickness of about 20 nm to about 100 nm or other thicknesses using physical or chemical vapor deposition. The inclusion of the high work function metal layer in the N-type NVM transistor 326 can lead to improved quenching performance of the device, as quenching saturation can be avoided. In the embodiment in which the thin titanium nitride layer is present, the first P+ or N+ metal layer can be deposited over the thin titanium nitride layer.Since the titanium nitride layer is very thin, it may not significantly impair the properties of the finished metal gates. In an alternative embodiment, a layer of tantalum nitride is deposited over the thin layer of titanium nitride (if present) before the formation of the first P+ or N+ metal layer 832. The thin layer of titanium nitride and tantalum nitride forms a lower metal barrier layer. As discussed, the lower metal barrier layer, which is arranged between the first P+ or N+ metal layer 832 and the high-k dielectric layer 835, is optional.

[0073] With further reference to Fig. In step 10G, a thick gate metal layer is deposited and etched, and planarization can be performed using one or more CMP processes to form thick metal gates 834, thereby completing the formation of multilayer metal gates for the NVM transistor 326, the selection transistor 327, and all MOS transistors 312, 314, and 316 (step 962). In one embodiment, the thick gate metal layer can comprise a conformal layer of aluminum, titanium, titanium nitride, tungsten, or compounds or alloys thereof, superimposed on its respective first P+ or N+ metal layer 832. The thick gate metal layer 834 can be deposited to a thickness of about 0.1 µm to about 0.5 µm, or other thicknesses, using physical or chemical vapor deposition or other deposition methods known in the art.In one embodiment, the NVM transistor 326 can also be referred to as a metal-oxide-nitride-oxide-semiconductor (MONOS) transistor due to the presence of a multilayer metal gate (the first metal layer 832 and the thick gate metal layer 834). It is understood that NVM, MONOS, and MONOS are used synonymously throughout the patent document. Optionally, a metal polishing process can be applied to level or planarize the upper surfaces 852 of the thick gate metal layer 834 of the NVM transistor 326, the selection transistor 327, and the MOS transistors 312, 314, and 316 (step 964). In an alternative embodiment, an upper metal barrier layer (not shown in this figure), comprising titanium nitride and titanium, can be formed before the formation of the thick gate metal layer 834, such that it lies above the first P+ or N+ metal layer 832. In one embodiment, the upper metal barrier layer is optional.

[0074] How best to Fig. As can be seen in Figure 10G, the SONOS-based NVM device 1000, comprising the NVM transistor 326, the selector transistor 327, the HV transistor, the I / O transistor, and the LV transistors 316, 314, and 312, can have a planarized top surface 852 after the CMP process mentioned above. In one embodiment, the planarized top surface 852 is essentially coplanar or flat, although it incorporates devices with different gate oxide thicknesses. In embodiments, as mentioned previously, the NVM transistor 326 can be formed within the SONOS trench 550, as best illustrated in Figure 10G. Fig. 10G can be seen. In other embodiments, the SONOS trench 550 may not be formed, and the NVM transistor 326 is formed in the NVM array recess 552 with the select transistor 327, as best shown in Fig. 10D can be seen. In other embodiments, the HV recess 553 may or may not be present. It is understood that the process flow described in the Fig. 9A- Fig. 10G is illustrated and shown in detail, and can be used in all of the above-mentioned embodiments.

[0075] Finally, the standard or basic CMOS process flow is continued to substantially complete the fabrication of the front-end device (step 966). The process flow may include the formation of high-frequency manifolds, spacers, channels, source / drain regions, etc., for each transistor type. In one embodiment, the completed NVM transistor 326 and the high-voltage transistor, I / O transistor, or LV MOS transistor 312, 314, 316 may be configured to form an embodiment of an NVM cell 600 within the NVM array recess 552. In alternative embodiments, the switching transistor 327 may also have a structure, such as a gate oxide thickness, that differs from that of the high-voltage transistor, I / O transistor, or LV MOS transistor 312, 314, 316. In another alternative embodiment, the memory cell 600 may contain only the NVM transistor 326 in a single-transistor configuration.

[0076] Thus, embodiments of a SONOS-based non-volatile memory with HKMG and manufacturing processes, including balanced gate heights, and methods for integration into a basic CMOS process flow are presented. Although the present disclosure has been described with reference to specific embodiments, it is obvious that various modifications and changes to these embodiments can be made without deviating from the intent and scope of the disclosure. Therefore, the description and the drawings are to be considered exemplary and not limiting.

[0077] The summary of disclosure is provided to comply with the requirements of Section 1.72(b) of Title 37 of the Code of Federal Regulations, which mandates a summary that enables the reader to quickly ascertain the nature of one or more embodiments of the technical disclosure. It is submitted on the condition that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, it is clear from the foregoing detailed description that various features are grouped together in a single embodiment to streamline the disclosure. This method of disclosure is not to be construed as reflecting the intention that the claimed embodiments require more features than are expressly stated in each claim.As reflected in the following claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, each claim representing a distinct embodiment on its own.

[0078] References in the description to an embodiment or exemplary embodiment mean that a specific feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the circuit or method. Expressions such as "an embodiment" appearing at various points in the description do not necessarily all refer to the same embodiment. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 658,027

[0001]

Claims

[1] A method for manufacturing a semiconductor device comprising: Dividing a substrate into a first and a second region; Forming an initial recess to a first depth in the first region; Forming an NVM transistor (NVM = non-volatile memory) and a selection transistor at least partially within the first recess, further comprising: Forming a non-volatile (NV) dielectric stack in the first recess, wherein the non-volatile dielectric stack comprises a barrier oxide arranged above a charge-trapping layer and a tunnel oxide; Performing at least one silicon oxide deposition process in an atomic layer deposition (ALD) tool to form a gate dielectric layer of the selection transistor adjacent to the non-volatile dielectric stack in the first recess; Performing an oxide removal process step to thin the thickness of the barrier oxide of the non-volatile dielectric stack; Forming a high-k dielectric layer that lies above the blocking oxide or gate dielectric layer; Formation of a sacrificial polysilicon gate over the high-k dielectric layers of the non-volatile dielectric stack or gate dielectric layer; and Replacing the sacrificial polysilicon gates with metal gates. [2] Method according to claim 1, wherein the NVM transistor and the selection transistor are configured to form a two-transistor (2T) NVM cell. [3] Method according to claim 1, wherein forming the first recess further comprises: Structuring a photoresist to expose the first region; Performing an oxidation process, wherein in the oxidation process an upper section of the substrate in the first region is consumed to form an initial recess oxide layer down to the first depth within the substrate; and Perform an oxide cleaning process to completely remove the first recession oxide layer in the first region. [4] Method according to claim 1, wherein the oxide removal process step of the non-volatile dielectric stack further comprises: Structuring a photoresist to expose the non-volatile dielectric stack; Performing an oxide purification process on the barrier oxide; and Calibrating the oxide purification process to control the thickness of the barrier oxide. [5] Method according to claim 4, wherein the gate dielectric layer formed by the at least one silicon oxide deposition process is deposited substantially over an upper surface of the substrate in the first recess. [6] Method according to claim 1, wherein the increase of the upper surfaces of the sacrificial polysilicon gates of the NVM transistor and the selection transistor has a height difference of less than 50 Å. [7] Method according to claim 1, wherein replacing the sacrificial polysilicon gates further comprises: Forming a voltage-inducing silicon nitride layer and an interplane dielectric layer (ILD) that lie above the substrate in the first region; Performing an initial chemical-mechanical polishing (CMP) process until at least one of the sacrificial polysilicon gates of the NVM transistor and the selection transistor is exposed; Performing polysilicon etching to remove the sacrificial polysilicon gates in the NVM transistor and the selection transistor to create gate openings; Forming a metal gate that lies over each of the high-k dielectric layers; and Perform a second CMP process to equalize the gate heights of the NVM transistor and the selection transistor. [8] Method according to claim 1, wherein the increase of the upper surfaces of the metal gates of the NVM transistor and the selection transistor is substantially coplanar. [9] Method according to claim 1, further comprising: Forming an I / O transistor (I / A = Input / Output), an LV transistor (LV = Low Voltage), and an HV transistor (HV = High Voltage) outside the first recess in the second region, wherein a gate dielectric layer of the HV transistor is thicker than a gate dielectric layer of the I / O transistor, the gate dielectric of the I / O transistor is thicker than a gate dielectric layer of the LV transistor, each of the HV transistor, the I / O transistor, and the LV transistor includes a high-k metal gate, and wherein the elevation of the upper surfaces of the high-k metal gates of the NVM transistor and the select transistor located within the first recess, and of the upper surfaces of the high-k metal gates of the HV transistor, the I / O transistor, and the LV transistor located outside the first recess, in the It is essentially coplanar. [10] Method according to claim 9, further comprising: Forming a second recess to the first depth in the second region simultaneously with the first recess, wherein the selection transistor and the HV transistor have the same structural features and wherein the HV transistor is formed within the second recess. [11] Method according to claim 1, further comprising: Forming a second recess to a second depth within the first recess in the first region; and Forming the NVM transistor inside the second recess, where the second depth is greater than the first depth, and the selection transistor is formed outside the second recess. [12] A method for manufacturing a semiconductor device comprising: Dividing a substrate into a first and a second region; Forming an initial recess to a first depth in the first region; Forming a second recess to a second depth in the first recess, the second depth being greater than the first depth; Forming an NVM transistor (NVM = non-volatile memory) and a selection transistor in the first recess, further comprising: Forming a non-volatile (NV) dielectric stack at least partially in the second recess, the non-volatile dielectric stack comprising a barrier oxide arranged above a charge-trapping layer and a tunnel oxide; and Forming a gate dielectric layer of the selection transistor next to the non-volatile dielectric stack and outside the second recess; Forming an HV transistor (HV = high voltage), an I / O transistor (I / A = input / output) and an LV transistor (LV = low voltage), each containing a gate dielectric layer, in the second region outside the first recess; Forming a high-k dielectric layer that lies over each of the non-volatile dielectric stack and gate dielectric layer of the selection transistor, HV transistor, I / O transistor or LV transistor; Formation of sacrificial polysilicon gates that lie above the high-k dielectric layers; and Replacing the sacrificial polysilicon gates with metal gates, wherein the increase in the upper surface area of ​​the metal gates of the NVM transistor and the select transistor in the first region and the upper surface area of ​​the metal gates of the HV transistor, the I / O transistor and the LV transistor in the second region is essentially the same. [13] Method according to claim 12, wherein the NVM transistor and the selection transistor are configured to form a two-transistor (2T) NVM cell. [14] Method according to claim 12, wherein forming the first recess further comprises: Structuring a photoresist to expose the first region; Performing an oxidation process, wherein in the oxidation process an upper section of the substrate in the first region is consumed to form an initial recess oxide layer down to the first depth within the substrate; and Perform an oxide cleaning process to completely remove the first recession oxide layer in the first region. [15] Method according to claim 12, wherein forming the second recess further comprises: Formation of a recession nitride layer that lies above a sacrificial oxide layer in the first region; Structuring a photoresist to expose an NVM region in which the NVM transistor is to be formed; Removal of the recession nitride layer in the NVM area; Performing a first oxidation process in the NVM region, wherein in the first oxidation process an upper section of the substrate in the NVM region is consumed to form a second recess oxide layer within the substrate; Removal of the recession nitride layer in the first region; Performing a second oxidation process in the first region, wherein in the second oxidation process the second recess oxide layer further grows to the second depth in the substrate; and Performing an oxide cleaning process to completely remove the second recess oxide layer in the NVM area. [16] Method according to claim 12, wherein forming the gate dielectric layer of the selection transistor further comprises: Performing at least one silicon oxide deposition process in an atomic layer deposition (ALD) tool to form the gate dielectric layer of the selection transistor alongside the non-volatile dielectric stack in the first recess; and Performing an oxide removal process step to reduce the thickness of the barrier oxide of the non-volatile dielectric stack. [17] Method according to claim 12, wherein replacing the sacrificial polysilicon gates further comprises: Forming a voltage-inducing silicon nitride layer and an interplane dielectric layer (ILD) that lie above the substrate in the first region; Performing an initial chemical-mechanical polishing (CMP) process until at least one of the sacrificial polysilicon gates of the NVM transistor and the selection transistor is exposed; Performing polysilicon etching to remove the sacrificial polysilicon gates in the NVM transistor and the selection transistor to create gate openings; Forming a metal gate that lies over each of the high-k dielectric layers; and Perform a second CMP process to equalize the gate heights of the NVM transistor and the selection transistor. [18] A method for manufacturing a semiconductor storage device comprising: Dividing a substrate into a first and a second region; Forming an initial recess to a first depth in the first region; Forming a second recess to a second depth in the first recess, the second depth being greater than the first depth; Forming a third recess down to the first depth in the second region; Forming an NVM transistor (NVM = non-volatile memory) comprising a non-volatile (NV) dielectric stack in the second recess, wherein the non-volatile dielectric stack comprises a barrier oxide arranged above a charge-trapping layer and a tunnel oxide; Forming a selection transistor next to the NVM transistor, comprising a selection gate dielectric located in the first recess and outside the second recess; Forming an HV transistor (HV = high voltage), an I / O transistor (I / A = input / output) and an LV transistor (LV = low voltage), each containing a gate dielectric layer, in the second region outside the first recess, with the HV transistor being located inside the third recess; Forming a high-k dielectric layer that lies over each of the blocking oxide of the NVM transistor, the select gate dielectric, and the gate dielectric layers of the HV transistor, the I / O transistor, and the LV transistor; and Forming a sacrificial polysilicon gate that lies over each of the high-k dielectric layers. [19] Method according to claim 18, wherein the elevation of the upper surfaces of the sacrificial polysilicon gates of the NVM transistor and the selection transistor in the first region and of the upper surfaces of the sacrificial polysilicon gates of the HV transistor, the I / O transistor and the LV transistor in the first and second regions has a height difference of less than 50 Å. [20] Method according to claim 18, further comprising: Replacing the sacrificial polysilicon gates with metal gates, wherein the increase in the upper surface area of ​​the metal gates of the NVM transistor and the select transistor in the first region and the upper surface area of ​​the high-k metal gates of the HV transistor, the I / O transistor and the LV transistor in the second region is essentially the same.