VLAN-aware clock hierarchy

Abstract

Network device, including: a port; a clock; one or more computer processors; and a computer-readable storage medium containing instructions for controlling one or more processors to: Synchronizing the clock in the network device with a clock in a first participating device in a first logical network, including exchanging initial synchronization messages between the port of the network device and a port of the first participating device, wherein the exchange of the initial synchronization messages includes providing an identifier in the initial synchronization messages that identifies the first logical network; and Synchronizing the clock in the network device with a clock in a second participating device in a second logical network different from the first logical network, including exchanging second synchronization messages between the port of the network device and a port of the second participating device, wherein the exchange of the second synchronization messages includes providing an identifier in the second synchronization messages that identifies the second logical network.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority from US patent application No. 16 / 752,280, filed on January 24, 2020, which claims the filing date of US provisional application No. 62 / 888,370, filed on August 16, 2019.

[0002] This application is related to the simultaneously filed US application No. 16 / 752,314, filed on January 24, 2020, entitled “VLAN-Aware Clock Synchronization”. BACKGROUND

[0003] This disclosure relates to the synchronization of clocks in computer-based devices connected in a network (e.g., computers, industrial automation equipment, and the like) to compensate for latency and delay variations in the network. Synchronization becomes relevant when devices operating at a distance from one another must also cooperate. In such scenarios, a local clock synchronizes with the device clocks networked within the same system. However, even when two clocks are synchronized, there is no guarantee that they will remain synchronized. Temperature differences, the age of the clocks themselves, and similar factors can affect the quality of the synchronization.

[0004] Further background information can be found in “Keeping clock accuracy on a master clock failure in substation network” by Yasuyuki Kozakai et al., which describes how communication between Grandmaster Clocks (GMCs) can be restricted so that the failure of one GMC has only a limited impact on other GMCs, and in US 2013 / 121351 A1, which describes part of the process for PTP message transmission between devices in different VLANs. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] With regard to the following discussion and, in particular, the drawings, it should be noted that the details shown are examples for illustrative purposes and serve to provide a description of the principles and conceptual aspects of this disclosure. No attempt is made to present implementation details beyond what is necessary for a basic understanding of this disclosure. The following discussion, in conjunction with the drawings, will make clear to those skilled in the art how embodiments according to this disclosure can be implemented. Similar or identical reference numerals may be used to refer to or denote similar or identical elements in the various drawings and related descriptions. In the accompanying drawings: Fig. Figure 1 represents a system block diagram according to some embodiments. The Fig. 2A, Fig. 2B, Fig. 2C provide examples of a master / slave timing tree according to some embodiments. Fig. Figure 3 shows a specific configuration for illustrative purposes. Fig. Figure 4 shows operations for setting port status for ports in a computer device according to the present disclosure. The Fig. 5A, Fig. 5B, Fig. 5C provides examples of data that can be used according to the operations for setting port status. The Fig. 6A and Fig. 6B shows operations for comparing clock data. Fig. Figure 7 provides an example of data that can be used according to the operations for setting port status. Fig. Figure 8 shows operations for setting the port status for a port according to the present disclosure. Fig. 9 represents a synchronization sequence. The Fig. 10A and Fig. 10B describes operations for synchronizing between a clock in a device and a clock in a participating device according to the present disclosure. The Fig. 11A and Fig. Section 11B provides examples of Ethernet frames according to the present disclosure. Fig. Figure 12 shows an example of a computer device according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0006] This disclosure relates to the synchronization of clocks in devices connected in a network (e.g., computers, industrial automation equipment, and the like) to compensate for latency and delay variations in the network. According to aspects of this disclosure, the effects of network latency can be reduced by using an exemplary method in which pairs of nodes in the network, operating in a master / slave relationship, communicate with each other to compensate for the delay between the two nodes. For illustrative purposes only, the Precision Time Protocol (PTP), defined in the IEEE 1588-2008 specification and incorporated herein in its entirety by reference, is used as an illustrative example of clock synchronization.

[0007] Some network topologies include network devices (e.g., computers, switches, etc.) configured in different VLANs (Virtual Local Area Networks). Traditional PTP processing does not synchronize clocks located in different VLANs. The clock synchronization described in this disclosure takes into account devices in different VLANs, such as those configured by an administrator.

[0008] Consider, for example, the host machines Host1 through Host100 in a company, all connected to a single switch port. Some host machines might belong to the human resources department, others to the engineering department, still others to the sales department, and so on. Although all host machines are connected to the same switch port, the host machines of the different groups and departments can still be isolated from each other by defining separate VLANs for each. Furthermore, it is desirable to synchronize the clocks of all 100 host machines so that they are all synchronized to the same clock.

[0009] Traditional synchronization techniques allow the synchronization of machines within a specific VLAN, but do not allow the synchronization of machines in different VLANs with each other. In our example, all 100 hosts connected to the same (trunk) port would therefore need to be in the same VLAN to be synchronized. In contrast, the synchronization according to the present disclosure takes into account that a trunk port can be configured for multiple VLANs.

[0010] The following description includes numerous examples and specific details to provide a comprehensive understanding of the present revelation.

[0011] Fig. Figure 1 is a general representation of a networked communication system (network system) 100 configured to synchronize the clocks in the associated network devices in accordance with the present disclosure. The network system 100 includes a communication network 102 comprising a group of interconnected, cooperating switches and routers, designated N1-N5 in the figure and collectively referred to as communication network devices 104, to provide communication between computer devices 108 (designated D1-D7 in the figure). Computer devices 108 may include computers, computer-based machines, and computer-based systems in general. In some embodiments, the communication network 102 may be a local area network (LAN).

[0012] System 100 can be configured with one or more logical networks 106. In some implementations, the logical networks can be, for example, virtual local area networks (VLANs). For illustrative purposes only, the following is shown: Fig. 1. Devices D1 and D2 are configured in VLAN A. Devices D5, D6, and D7 are configured in VLAN B. Fig. Figure 1 further shows that devices can be part of two or more VLANs; for example, devices D2 and D5 are also configured in VLAN C. Not all devices need to be part of a VLAN. For example, devices D3 and D4 could be systems that do not communicate over a VLAN.

[0013] The network devices 104 and computer devices 108 can be configured to synchronize their respective clocks. According to the present disclosure, clock synchronization between the network devices 104 and the computer devices 108 is performed taking into account the presence of VLANs 106 in the system 100. In some embodiments, the clock synchronization according to the present disclosure can, for example, be based on the Precision Time Protocol (PTP) standard defined in the IEEE 1588-2008 specification. Accordingly, and solely as a means of disclosing aspects of the present disclosure, embodiments according to the present disclosure are explained in the context of PTP processing and the PTP terminology defined in IEEE 1588-2008. However, those skilled in the art will understand that the present disclosure can also be adapted to other exemplary methods for clock synchronization.

[0014] Fig. Figure 1 shows that VLAN-aware clock synchronization can be performed in each of the devices 104 and 108. According to some embodiments, the clock synchronization comprises two components: (1) representing the devices 104 and 108 in a master / slave clock time tree; and (2) synchronizing the clocks in the devices 104 and 108 according to the master / slave relationship defined in the time tree.

[0015] Each device 104 and 108 is assigned a clock. Clock synchronization serves to synchronize the clocks in devices 104 and 108 so that the devices have a common time reference. Devices 104 and 108 can be considered clocks and can therefore simply be referred to as "clocks". As in Fig. As shown in Figure 1, clock synchronization operations involve sending messages between two clocks. In accordance with IEEE 1588-2008, synchronization-related messages include, for example, Announce, Sync, Delay_Req, Follow_Up, and Delay_Resp. The figure illustrates, for example, the exchange of synchronization-related messages between device D1 and device N2, between devices D3 and N2, between devices D5 and N3, and so on. Synchronization can occur between devices that form the communication network 102; as shown in Figure 102. Fig. 1 For example, the exchange of synchronization-related messages between network devices N1 and N3, N4 and N5, and so on.

[0016] Clock synchronization operations are performed via a communication path between two clocks. A "communication path" is a data path without any intervening ordinary clocks or boundary clocks. A device can be called an "ordinary clock" if it has only one port (interface) through which it can perform clock synchronization operations. For example, computer devices communicate via a single port and can therefore be called ordinary clocks. A device can be called a "boundary clock" if it has multiple ports and performs clock synchronization operations over two or more of them. For example, network devices, such as multi-port switches, can be called boundary clocks.

[0017] Fig. Figure 2A shows an example of a master / slave clock time tree 200. The time tree 200 has a root node 202, one or more intermediate nodes 204, and one or more leaf nodes 206, arranged in a hierarchy. The in Fig. The time tree 200 shown in Figure 2A, for example, has four hierarchy levels. Each node represents a network device or a computer device in a network system. The root node 202 can be called the Grandmaster (GM) clock and can be a normal clock or a boundary clock.

[0018] All clocks in Time Tree 200 are either directly synchronized with the Grandmaster clock (i.e., clocks at level 2 of the hierarchy) or indirectly synchronized with the Grandmaster clock, as in the case of clocks below level 2 in the hierarchy. For example, clocks at level 2, acting as slave clocks, synchronize with the Grandmaster clock. Clocks at level 3, acting as slave clocks, synchronize with clocks at level 2, which now act as master clocks, and so on, down the hierarchy.

[0019] The designation MASTER / SLAVE for a clock refers to the status of that clock's ports. For example, a standard clock's port can be in MASTER or SLAVE status. A border clock's port can be in MASTER, SLAVE, or PASSIVE status. In the case of a border clock, one port will be in SLAVE status, while the other ports can be in MASTER or PASSIVE status.

[0020] A time tree according to the present disclosure can represent devices across different logical networks (e.g., VLANs) on the same (trunk) port. According to the present disclosure, such a trunk port can be in SLAVE status relative to a clock higher up in the hierarchy, and in MASTER status relative to a clock lower down in the hierarchy. Fig. Figure 2B illustrates this with a simplified configuration, showing a boundary clock with two Ethernet ports, eth1 and eth2. Ethernet port eth1 is a master port to a slave port (not shown) in device D1 on VLAN 10. Similarly, Ethernet port eth2 is a master port to device D3 on VLAN 30. Simultaneously, Ethernet port eth2 is also a slave port to device D2 on VLAN 20. The time tree 200a in Fig. 2C represents the in Fig. Configuration shown in 2B.

[0021] The description now turns to the discussion of the generation of a master / slave clock time tree according to some embodiments of the present disclosure. Fig. Figure 3 shows a simplified network 300, which can serve as an example to facilitate discussion. The figure shows a switch 302 with ports (interfaces) eth1, eth2, eth3, eth4, eth5, a hub 304 with ports eth10, eth20, eth30, and a hub 36 with ports eth40, eth50, eth60. Computers D1, D2, and D4 are connected to switch 302 at their respective ports eth1, eth2, and eth4. Hub 304 is connected to port eth3 of switch 302. Computers D3 and D5 are connected to ports eth20 and eth30 of hub 304, respectively. Hub 306 is connected to port eth5 of switch 302. The computer devices D6 and D7 are connected to the respective ports eth40 and eth60 of the hub 306.

[0022] Network 300 is configured with three logical networks: VLAN 10, VLAN 20, and VLAN 30. Devices D1 and D2 are in VLAN 10, and devices D4 and D5 are in VLAN 30. Device D2 is also in VLAN 20, along with device D3. Consider the different ports of switch 302. The eth2 port of switch 302 can carry traffic for VLAN 10 and VLAN 20. Similarly, the eth3 port of switch 302 can carry traffic for VLAN 20 and VLAN 30. Ports eth2 and eth3 are referred to as "root ports" and "trunk ports," respectively, because they are assigned to or otherwise configured for two or more logical networks, such as VLANs. Ports eth1 and eth4 are also referred to as trunk ports because they are located in a single VLAN. However, ports eth1 and eth4 are sometimes referred to as "access" and "access" ports, respectively.These are referred to as "access" ports because each is configured for a single VLAN; port eth1 is in VLAN 10 and port eth4 is in VLAN 30. The eth5 port of switch 302 can be referred to as a "non-trunk" port because this port is not assigned to any logical network or otherwise configured for that purpose. The ports of switches 304 and 306 are similarly referred to as trunk ports, access ports, or non-trunk ports.

[0023] Generally, a time tree is created by setting the port states (status variables) of the ports of every device in a network; the network topology defines the connectivity of the nodes in the time tree. The time tree is port-based; a port on a device can have the MASTER state, while another port on the same device can have the SLAVE state. Every device in a network, whether a regular clock or a boundary clock, sets a state for each of its ports. The 302 switch in Fig. Device 3, for example, is a boundary clock, while devices D1 through D7 are normal clocks. Some devices are referred to as transparent clocks; hubs 304 and 306, for example, can be considered transparent clocks. No port status is determined for transparent clocks.

[0024] With reference to Fig. 4. The discussion now turns to a high-level description of the processing in a clock (a network device) to determine the port status of each of its ports in accordance with the present disclosure. Note that the processing according to the in Fig. The 4 operations shown are performed by each boundary clock and each normal clock in the network. The clock is used for the purpose of describing Fig. 4 is referred to as "the local clock". To illustrate its operation, the switch 302 (a border clock) in Fig. 3. Referenced. In some embodiments, the local clock may contain computer-executable program code which, when executed by a processor (e.g., 1202, Fig. 12) is executed in the local clock, which can cause the processor to perform processing according to Fig. 4. The sequence of operations performed by the processor is not necessarily limited to the sequence of operations shown. Furthermore, operations can be combined in various ways or subdivided into smaller operations.

[0025] The processing is generally performed for each port (trunk and non-trunk ports) in the local clock (outer loop), regardless of the activity in the other ports. In some embodiments, a non-trunk port can receive clock data from ports of clocks connected to the communication path served by that port. Recall that a communication path between a port P1 on one clock and a port P2 on another clock is a path on which there are no intermediate ordinary clocks or boundary clocks between P1 and P2. With reference to Fig. For example, the path between devices D6 and D7 represents a communication path. On the other hand, the path between the port (not shown) on device D1 and device D5 is not a communication path due to the intervening switch 302 (a boundary clock).

[0026] According to the present disclosure, a trunk port can receive clock data received from the clock ports in each logical network assigned to the trunk port. For example, a trunk port assigned to VLAN A and VLAN B receives clock data from clocks in VLAN A and clock data from clocks in VLAN B. As explained below, the clock data received on one VLAN (e.g., VLAN A) is processed separately from the clock data received on another VLAN (e.g., VLAN B).

[0027] In some embodiments according to IEEE 1588-2008, the clock data can be a "data set" sent in an announce message from one clock to another. Clock data includes, among other things, data specifying a clock's accuracy. For clock data received on a trunk port, processing occurs according to inner loop 402. In the case of clock data received on a non-trunk port, processing continues according to operation 404. Trunk port processing

[0028] In inner loop 402, in the case of a trunk port, the local clock can process each logical network associated with the trunk port. As explained above, each port receives clock data (e.g., via announce messages) from clocks on the communication path served by that port. In the case of a trunk port, the port receives clock data from clocks in its logical networks. According to the present disclosure, the local clock can process received clock data based on each individual logical network.

[0029] Accordingly, in Operation 412, the local clock can identify clock data received from clocks located on a specific logical network associated with the trunk port. For example, the received Announce message might be encapsulated in an Ethernet frame tagged according to the IEEE 802.1Q standard for VLANs. The logical network (i.e., the VLAN) can be identified by the VLAN identifier (VID) included in the received Ethernet frame (see, for example, Fig. 11A). With reference to Fig. For example, port eth2 (a trunk port) of switch 302 can receive clock data from devices D1 and D2 in VLAN 10, as well as clock data from devices D2 and D3 in VLAN 20. Similarly, trunk port eth3 can receive clock data from device D3 in VLAN 20 and clock data from device D5 in VLAN 30, and so on.

[0030] In Operation 414, the local clock can provide the best clock data (E pvbest) calculate or otherwise determine from all clock data received on a given logic network. Here, the "best" clock data corresponds to the clock that, among the clocks in the given logic network, is considered to provide the most accurate time. The E pvbest Clock data can be determined for each logical network connected to the trunk port. Referring to Fig. 3 can be, for example, E pvbest -Clock data for VLAN10 can be determined using clock data received from device D1 and clock data received from device D2. Similarly, the E pvbest -Clock data for VLAN20 is determined using the clock data received from device D2 and the clock data received from device D3, etc.

[0031] In some embodiments, a comparison algorithm ( Fig. 6A, Fig. 6B) can be used to compare a pair of clock data and determine which of the two clock data represents the more accurate clock. Consider, for example, the following clock data: C1, C2, C3, C4, C5. The comparison algorithm can be called repeatedly to compare pairs of clock data and determine the best clock data from the set C1, C2, C3, C4, C5. For example, clock data C1 and C2 can be compared to determine the better of the two clock data. The clock data resulting from the comparison can be compared with clock data C3 to determine the better clock data, and so on, to determine the clock data of the clock that is considered to have the most accurate time among the other clock data, namely the "best" clock data.

[0032] Referring to Fig. 3 can, for example, be the inner loop E pvbest -Calculate clock data for the following (trunk port, VLAN) pairs: E pvbest -Clock data sources for clock data (eth1, VLAN10) D1 (eth2, VLAN10) D1, D2 (eth2, VLAN20) D2, D3 (eth3, VLAN20) D3 (eth3, VLAN30) D5 (eth4, VLAN30) D4, D5

[0033] For example, for port eth2 in a first logical network VLAN10, device D2 can be considered the device with the most accurate clock (in other words, the clock data for D2 is the "best" among the clock data for D1 and the clock data for D2). For the same port eth2, but in a second logical network VLAN20, device D3 can be considered the device with the most accurate clock (in other words, the clock data for D3 is the "best" among the clock data for D2 and the clock data for D3), and so on.

[0034] The example above shows that in some configurations, a trunk port / VLAN pair may only have one device. In these cases, the E pvbestClock data refers to the clock data received by this one device, e.g., (eth1, VLAN10), (eth3, VLAN20), (eth3, VLAN30). For example, device D1 is considered the most accurate clock for port eth1 in the logical network VLAN10. As mentioned above, trunk ports eth1 and eth4 can also be referred to as "access" ports, since each port is in a separate VLAN. In some implementations, access ports may be treated as non-trunk ports, and thus references to non-trunk ports may also be understood as referring to access ports. Non-trunk port processing

[0035] In Operation 404, in the case of a non-trunk port, the local clock can determine the best clock data from the clock data received at the non-trunk port. Here, the "best" clock data corresponds to the clock that, among the clocks connected to the communication path served by that non-trunk port, is considered to provide the most accurate time. In some embodiments, for example, the local clock can determine the best clock data (E phest ) from the clock data received from each clock connected to this non-trunk port. The clock data comparison algorithm discussed below can be used to determine the E from the clock data received at the non-trunk port. pbest -to determine clock data. With reference to, for example, Fig. 3. eth5 is a non-trunk port, and devices D6 and D7 are connected to this port via the 306 hub. Accordingly, the E pbest-Clock data for port eth5 based on a comparison (see e.g. the Fig. 6A, Fig. 6B) of clock data received by device D6 and device D7. As mentioned above, ports eth1 and eth4, which serve as access ports, can be treated as non-trunk ports in some embodiments. Accordingly, in some embodiments the respective E pbest -Clock data instead of the E pvbest -Clock data is calculated for ports eth1 and eth4.

[0036] In operation 406, the local clock can provide the best clock data (E best ) based on the E determined for each non-trunk / access port pbest -Clock data and the E determined for each logical network at each trunk port pvbest -Determine clock data. The E best -Clock data represents the best clock data from all calculated E pbest - and E pvbestThese represent clock data and can be determined using the clock data comparison algorithm described below. Here, the "best" clock data corresponds to the clock considered most accurate among all clocks connected to the non-trunk ports of the local clock and to each logical network connected to each trunk port of the local clock.

[0037] In operation 408, the local clock can determine the port status for each non-trunk / access port based on the E best -clock data, the E pbest -Set the clock data corresponding to the respective non-trunk / access port, as well as the device clock data (D0) of the local clock itself. This operation is performed for each non-trunk port for which E pbest Clock data was calculated. A separate port status is determined for each non-trunk port. Details on how the port status is determined are discussed below.

[0038] In operation 410, the local clock can determine the port status for each trunk port and each logical network pair based on the E best -clock data, the E pvbest -Set clock data corresponding to the local network on this trunk port and the device clock data (D0) of the local clock itself. Multiple port states can be defined for a trunk port; for each logical network on this trunk port, for which E pvbest Once the clock data has been calculated, a port status is determined. In the example of Fig. For example, a single port status is determined for eth5 (non-trunk port), while two port statuses are determined for eth2: one port status for the eth2 / VLAN10 pair and another port status for the eth2 / VLAN20 pair. Details on determining the port status are discussed below.

[0039] As explained above, the operations can be made from Fig. Four operations are performed for each clock in the network to determine the MASTER / SLAVE status of the ports on the clocks. This results in a master / slave clock time tree, as shown, for example, in Fig. Figure 2A is shown. The physical connections between the devices in the network determine the connectivity between the nodes in the time tree, while the MASTER / SLAVE status determines the master / slave hierarchy.

[0040] The discussion now turns to a brief description of the clock data used to determine the best clock, according to some embodiments. In some embodiments in accordance with IEEE 1588-2008, for example, one clock is compared with another to determine which is the better clock (with respect to timekeeping accuracy) by comparing the respective clock data (“data sets”) that these clocks represent; see, for example, operations 414 and 404 in Fig. 4. In some embodiments, a clock can transmit its data set in an IEEE-1588-2008 Announce message.

[0041] Fig. Figure 5A shows an example of clock data 502, which in some embodiments according to IEEE 1588-2008 may be assigned to each clock. The clock data 502 for a clock may have the following data fields: • priority - a user-configurable label indicating that the watch belongs to an ordered set of watches from which a master is selected. • uhrKlasse - an attribute that denotes the traceability of the time or frequency distributed by the Grandmaster clock • Clock accuracy - an attribute that indicates the expected accuracy of a watch if it becomes a Grandmaster watch • offsetScaleLogVariance - an attribute that defines the stability of a clock • priority2 - a user-configurable label that allows for a finer ranking among otherwise equivalent watches • uhrIdentity - a unique identifier that serves as a tie-breaker • stepsAway - the number of communication paths traversed between the watch and the Grandmaster watch; in Fig. For example, clock 206a is three steps away from Grandmaster clock 202.

[0042] Fig. Figure 5B shows an example of a transmitted Announce message 504, which each clock transmits to other clocks as part of the time tree definition process. The clock data 502 is contained in corresponding data fields within the transmitted Announce message 504. An additional data field can be included in the transmitted Announce message 504: • sourcePortIdentity - an identifier of the port on the clock that transmitted the Announce message.

[0043] Fig. Figure 5C shows an example of a received Announce 506 message being processed by the receiving watch. The received Announce 506 message contains additional data fields, including: • Port identity of the receiving port - Identifier of the port on the clock that receives the announcement message • Port number of the receiving port - Port number of the port on the clock that receives the announcement message

[0044] The best clock is determined using a comparison algorithm that compares the clock data of two clocks to determine which clock data describes the better clock in terms of providing more accurate time. This is used to determine which of the clocks described in several announcement messages received from a local clock port is the best clock. The comparison algorithm involves comparing the clock data in received announcement messages to determine E pvbest-Clock data, E pbest -Clock data and E best -to calculate or otherwise obtain clock data.

[0045] The Fig. 6A and Fig. Figure 6B shows an example of a comparison algorithm based on IEEE 1588-2008 according to some embodiments that can be used to compare the in Fig. to perform the best clock determinations as described in the 4 sections. The comparison algorithm is described in Fig. 4 is called to compare two sets of clock data, clock data A and clock data B. Fig. 7 shows how the in the Fig. 6A and Fig. The terms used in the algorithm shown in Figure 6B are assigned to the corresponding data fields in the received announcement message 506. The comparison algorithm includes a series of decision points at which data fields from clock A are compared with corresponding data fields in clock B. The algorithm contains several return points at different decision points, at which it is determined that one clock is better than the other. The algorithm returns an indication of which of the two clocks, A and B, is better.

[0046] With reference to Fig. 8 The discussion now turns to the description of setting port status in a clock according to the present disclosure. Recall from Operation 408 that the port status for a non-trunk port is based on the E best -Clock data, the corresponding E pbestThe port's clock data and the device clock data (D0) are set. Operation 410 sets or specifies a port status for each logical network (e.g., VLAN) assigned to a trunk port, based on the E best -clock data, the E pvbest -Clock data corresponding to the trunk port / VLAN pair and the device clock data (D0).

[0047] Fig. Figure 8 shows a status decision algorithm for determining a port state according to the present disclosure. The status decision algorithm sets a port to one of four port states: MASTER, SLAVE, PASSIVE, LISTENING. The PASSIVE state is used to disable a port for clock synchronization to avoid loops in the timing tree. The LISTENING state is the initial state in which the ports of a device are when the device is powered on. Fig. Figure 8 shows two conditions (at 812, 814) under which a port or a port / VLAN can be set as a Grandmaster clock.

[0048] The state decision algorithm represents the logic that a state machine executes on each port. In the case of a non-trunk port, the algorithm is called to execute a state machine on that non-trunk port. In the case of a trunk port, the algorithm is called for each logical network connected to the trunk port to execute a state machine for each logical network. Although the state machines are the E best -Use clock data derived from the E pvbest - and E pbest While clock data is determined, the state machines otherwise run independently of each other, so that the status of a non-trunk port and the status of each trunk port / VLAN pair are set independently of each other.

[0049] Decision points 802, 804, 806, and 808 in the status decision algorithm refer to a term called "C-data." This term refers to the clock data used to call the status decision algorithm. For a non-trunk port, for example, the algorithm is called with the E pbest -Clock data is called that corresponds to the non-trunk port; accordingly, the C data for a non-trunk port refers to the corresponding E pbest -Clock data. The status decision algorithm uses E pbest -Clock data at decision points 802, 804, 806, 808. In the case of a trunk port, the algorithm for a specific logical network on this trunk is used with the E pvbest -Clock data is called up that corresponds to the specific logical network; the C data refers to E pvbest -Clock data. The status decision algorithm uses E pvbest-Clock data at decision points 802, 804, 806, 808.

[0050] Decision point 810 refers to "Port / VLAN". In the case of a non-trunk port, "Port / VLAN" refers only to the non-trunk port itself. "VLAN" is irrelevant because a non-trunk port is not configured for VLANs. The same applies to access ports, as an access port is in a single VLAN. Accordingly, decision point 810 determines, for both a non-trunk port and an access port, whether the E best -Clock data originates from a clock on a communication path served by this non-trunk or access port. In the case of a trunk port, "port / VLAN" refers to both the trunk port and a specific logical network (e.g., VLAN) associated with that trunk port. The decision is made based on the logical network, i.e., whether the E best-Clock data originates from a clock in this logical network.

[0051] Decision points 804 and 806 call the comparison algorithm ( Fig. 6A, Fig. 6B) to connect the device clock data (D0) with the E pbest -clock data or the E pvbest -to compare clock data. Fig. Figure 7 shows data fields in the device clock data (D0) that correspond to the terms used in the comparison algorithm.

[0052] The discussion now turns to the description of clock synchronization in accordance with the present disclosure. In general, the idea of ​​synchronizing clocks on devices connected via a network involves sending messages over the network between the devices. For the purposes of the following discussion, the IEEE 1588-2008 PTP protocol will be used to illustrate some embodiments according to the present disclosure.

[0053] Referring to Fig. Figure 1 describes the synchronization of clocks (e.g., devices 104, 108) in a system 100, which, according to some embodiments, involves the exchange of synchronization messages. Announcement messages were discussed above in connection with establishing the master / slave relationship between the clocks in the system, which can be represented, for example, in a master / slave time tree, as described in Fig. 2A is shown. More precisely, the master / slave relationship is established with respect to ports (interfaces) on the clocks and, according to the present disclosure, with respect to logical networks for those ports that are trunk ports.

[0054] Now, with reference to Fig. Figure 9 shows a synchronization sequence according to some embodiments. For illustration, the synchronization sequence according to IEEE 1588-2008 is used as an example. The synchronization sequence between a master clock and a slave clock can be initiated at a port of the master clock (here referred to as the "master port"), followed by an exchange of messages between the master port and a port on the slave clock (here referred to as the "slave port"). According to the present disclosure, the synchronization sequence can be performed multiple times at a trunk port, once for each logical network associated with the trunk port. Furthermore, according to the present disclosure, the trunk port can be a master port in one logical network and a slave port in another logical network.

[0055] The sequence is described using the sequence numbers, which are represented by circled numbers in the figure. In sequence 1, the master port sends a sync message to the slave port. The master port records the time t1 at which the sync message was sent, while the slave port records the time t2 when the sync message was received. In sequence 2, the master port transmits the timestamp t1 to the slave port by embedding the timestamp in a follow-up message sent to the slave port (two-step limit clock). The slave port receives the follow-up message and records the timestamp. In other embodiments using a one-step limit clock, the timestamp t1 can be embedded in the sync message. In sequence 3, the slave port sends a Delay_Req message to the master port and records the time t3 at which it was sent. The master port receives the Delay_Req message and records the reception time t4.In sequence 4, the master port transmits the timestamp t4 to the slave port by embedding it in a Delay_Resp message that is sent to the slave port. The slave port receives the Delay_Resp message and records the timestamp.

[0056] At the end of this message exchange, the slave clock recorded all four timestamps. These timestamps can be used to calculate the offset between the slave clock and the master clock, although the details of this calculation would exceed the scope of this disclosure.

[0057] The discussion now turns to a description of the operations in both the master clock and the slave clock for processing the exchange of messages to perform synchronization according to the present disclosure. For the purposes of this discussion, the message exchange between the master and the slave clock is described using Ethernet frames. However, it is understood that other embodiments may use different data transmission protocols or include additional encapsulation, etc.

[0058] Fig. Figure 10A shows a general description of the processing in a network device (clock) to perform synchronization with the clocks connected to the network device, according to the present disclosure. In some embodiments, the clock may have computer-executable program code which, when executed by a processor (e.g., 1202, Fig. 12) is executed in the clock, which can cause the processor to perform processing according to Fig. 10A. The sequence of operations performed by the processor is not necessarily limited to the sequence of operations shown. Furthermore, operations can be combined in various ways or subdivided into smaller operations.

[0059] The processing is generally performed for each port in the clock (outer loop). A port can be a trunk port or a non-trunk port. According to the present disclosure, in the case of a trunk port, the processing continues according to inner loop 1002. In the case of a non-trunk / access port, the processing continues according to operation 1008.

[0060] In the inner loop 1002, the clock can perform a synchronization sequence with a participating clock over any logical network in the case of a trunk port.

[0061] In operation 1004, the clock can identify the logical network connected to the trunk port. In some implementations, for example, each logical network connected to a trunk port can be identified by a VLAN identifier (VID). As discussed below, the VID can be used to send synchronization messages.

[0062] In Operation 1006, the clock can perform a synchronization sequence with a participating clock over the identified logical network. According to the present disclosure, the trunk port can be a master port (MASTER status) with respect to a participating clock in a logical network. In this case, the clock can initiate a synchronization sequence by sending a sync message and otherwise participate as a master port, as shown in Fig. Figure 9 illustrates this. According to the present disclosure, the trunk port can simultaneously also be a slave port (SLAVE status) with respect to another participating clock in a different logical network. In this case, the clock can participate as a slave port, as shown in Fig. 9 shown. Fig. 2C illustrates, for example, an example where the port eth2 of the border clock BC is a master port with respect to the port ethC on the device D3 over VLAN30, and at the same time eth2 is a slave port with respect to the port ethB on the device D2 over VLAN20.

[0063] In Operation 1008, if a non-trunk / access port is involved, the clock can perform a synchronization sequence with a participating clock on a communication path served by the non-trunk port. Unlike a trunk port, which can function as both a master and a slave port, a non-trunk port is either in the MASTER state with respect to the participating clock or in the SLAVE state.

[0064] Fig. Figure 10B shows a high-level description of processing in a clock for synchronization with a participating clock according to the present disclosure. In particular, the processing is performed with respect to a port (here referred to for the purposes of discussion as the given port) on the clock. Note that the in Fig. The operations shown in Figure 10B can be performed by the clock on any of the clock's ports, regardless of whether the port is a master or slave port. In some embodiments, the clock may contain computer-executable program code which, when executed by a processor (e.g., 1202, Fig. 12) is executed in the clock, which can cause the processor to perform processing according to Fig. 10B. The sequence of operations performed by the processor is not necessarily limited to the sequence of operations shown. Furthermore, operations can be combined in various ways or subdivided into smaller operations.

[0065] For the purpose of discussion, the operations related to synchronization are explained in accordance with IEEE 1588-2008. It is understood that the operations can be adapted to other synchronization techniques. Also for the purpose of discussion, VLANs are used as examples of logical networks, and those described in the Fig. 2B and Fig. The configuration shown in 2C serves as a clear example.

[0066] Operation 1022 allows the clock to generate a synchronization message that is transmitted to the specified port. In the case of a master port, the synchronization message can be a sync message containing a synchronization sequence (see, for example, ...). Fig. 9) initiated with another clock, a Follow_Up message, and a Delay_Resp message that completes the synchronization sequence. In the case of a slave port, the synchronization message can be a Delay_Req message. If the specified port is a trunk port, processing can continue with operation 1024. If the specified port is a non-trunk / access port, processing can continue with operation 1026.

[0067] In operation 1024, if the specified port is a trunk port, the clock can transmit the synchronization message in a tagged Ethernet frame. Because the specified port is a trunk port, the synchronization sequence is performed over a VLAN associated with that trunk port. For example: • Sync message - If a master clock (e.g., D2, Fig. 2C) a synchronization sequence with a slave clock (e.g. BC, Fig. 2C) initiated on one of the VLANs assigned to the trunk port, the master clock can use the VLAN (e.g. VLAN20, Fig. 2C) by their VLAN identifier (VID). The VID can be used to tag the Ethernet frame encapsulating the sync message according to the IEEE 802.1Q standard for VLAN tagging of Ethernet frames. Fig. Figure 11A illustrates details of a tagged Ethernet frame. • Follow_Up message - Similarly, if the master clock sends a Follow_Up message to a slave clock, the encapsulating Ethernet frame can be tagged with the VID of the VLAN in which the slave clock is located. • Delay_Req message - When the slave clock sends a Delay_Req message to the master clock, the slave clock can identify the VLAN in which the master clock resides based on its VID. The Ethernet frame encapsulating the Delay_Req message can be tagged with this VID. • Delay_Resp message - When the master clock sends a Delay_Resp message to a slave clock, the encapsulating Ethernet frame can be tagged with the VID of the VLAN in which the slave clock is located.

[0068] In some implementations, messages can be transmitted in an untagged 802.1Q Ethernet frame on the native VLAN. When an untagged message is received, the message refers to a specific VLAN, namely the native VLAN, which can be configured port by port.

[0069] The synchronization message forms the payload of the tagged Ethernet frame. The source MAC address of the Ethernet frame can be the MAC address of the specified port. Note that both unicast and multicast transmission modes are possible. In unicast mode, the destination MAC address of the Ethernet frame can be the MAC address of the port of the remote clock participating in the synchronization sequence. In the case of multicast transmissions, for example, according to IEEE 1588-2008, the destination MAC address can be the multicast MAC address of the PTP protocol, namely 01-1B-19-00-00-00. The tagged Ethernet frame can then be transmitted from the specified port of the identified VLAN.

[0070] In operation 1026, if the specified port is a non-trunk / access port, the clock can transmit the synchronization message in an untagged Ethernet frame. The payload of the Ethernet frame can be the synchronization message (Sync, Follow_Up, Delay_Req, Delay_Resp). Fig. Item 11B shows details of an untagged Ethernet frame. The untagged Ethernet frame can be transmitted from the specified port.

[0071] Fig. Figure 12 shows a simplified block diagram of an exemplary computer system 1200 according to certain embodiments. The computer system 1200 can be used to implement a computer device (e.g., D1, Fig. 1) or a network device (e.g., N1). As described in Fig.As shown in Figure 12, the computer system 1200 has one or more processors 1202 that communicate with a number of peripheral devices via a bus subsystem 1204. These peripheral devices include the memory subsystem 1206 (consisting of the main memory subsystem 1208 and the file storage subsystem 1210), user interface input devices 1212, user interface output devices 1214, and the network interface subsystem 1216.

[0072] The 1204 bus subsystem can provide a mechanism by which the various components and subsystems of the 1200 computer system can communicate with each other as intended. Although the 1204 bus subsystem is schematically represented as a single bus, alternative embodiments of the bus subsystem can use multiple buses.

[0073] The network interface subsystem 1216 can serve as an interface for data communication between the computer system 1200 and other computer systems. Embodiments of the network interface subsystem 1216 may, for example, include an Ethernet card, a WLAN adapter, and the like. The network interface subsystem 1216 may include non-volatile, machine-readable storage media capable of storing program code and / or data which, when executed by the logic in the interface, can cause the logic to perform operations according to embodiments of the present disclosure.

[0074] User interface input devices 1212 can include a keyboard, pointing devices (e.g., mouse, trackball, touchpad, etc.), a touchscreen integrated into a display, audio input devices (e.g., speech recognition systems, microphones, etc.), and other types of input devices. In general, the use of the term "input device" is intended to cover all possible types of devices and mechanisms for inputting information into the computer system 1200.

[0075] The output devices of the user interface (1214) can include a display subsystem, a printer, or non-visual displays such as audio output devices, etc. The display subsystem, for example, can be a flat panel display, such as a liquid crystal display (LCD) or an organic light-emitting diode (OLED) display. In general, the use of the term "output device" is intended to cover all possible types of devices and mechanisms for outputting information from the computer system (1200).

[0076] The memory subsystem 1206 comprises the main memory subsystem 1208 and the file / disk storage subsystem 1210, which represent non-volatile, computer-readable storage media capable of storing program code and / or data which, when executed by the processor 1202, can cause the processor 1202 to perform operations according to embodiments of the present disclosure.

[0077] The 1208 main memory subsystem comprises several storage devices, including the 1218 main random access memory (RAM) for storing instructions and data during program execution, and the 1220 read-only memory (ROM) for storing fixed instructions. The 1210 file storage subsystem can provide persistent (i.e., non-volatile) storage for program and data files and may include a magnetic or solid-state hard disk drive, an optical drive along with associated removable media (e.g., CD-ROM, DVD, Blu-ray, etc.), a removable flash memory-based drive or card, and / or other types of storage media known in the art.

[0078] It is understood that the Computer System 1200 is exemplary and many other configurations with more or fewer components than the System 1200 are possible. Virtual ports

[0079] The foregoing embodiments describe physical ports on physical devices (computers, switches, etc.). However, it is understood that the present disclosure can be implemented in a virtual environment. For example, a virtual environment can be configured with virtual machines configured as computer devices and / or network devices with corresponding virtual ports. In some embodiments, a network can comprise a combination of physical devices and virtual devices (virtual machines). Embodiments according to the present disclosure can be adapted to virtual ports on virtual devices. Configurations featuring a virtual environment can be useful for simulation purposes, for example, to assess whether the process converges properly in a network of switches. Further examples

[0080] The following information serves only as examples. The invention is defined by the attached set of claims.

[0081] An exemplary method may include determining first clock data associated with a first logical network configured on a first port of a network device, including receiving on the first port, and a first plurality of clock data associated with one or more first devices, with the first clock data being determined based on the first plurality of clock data. The exemplary method may further include determining second clock data associated with a second logical network, distinct from the first logical network and also configured on the first port of the network device, including receiving on the first port, and a second plurality of clock data associated with one or more second devices, with the second clock data being determined based on the second plurality of clock data.The exemplary method can further include setting a first status variable assigned to the first logical network on the first port, based at least on the device clock data of the network device and the first clock data. The exemplary method can further include setting a second status variable assigned to the second logical network on the first port, based at least on the device clock data and the second clock data.

[0082] In some embodiments of the exemplary method, receiving the first plurality of clock data at the first port may include receiving first data frames encapsulating the first plurality of clock data, wherein the first data frames are tagged with information designating the first logical network, and receiving the second plurality of clock data at the first port may include receiving second data frames encapsulating the second plurality of clock data, wherein the second data frames are tagged with information designating the second logical network.

[0083] In some embodiments of the exemplary method, the one or more first devices communicate via the first logical network, while the one or more second devices communicate via the second logical network.

[0084] In some embodiments, the exemplary method may further include selecting the first clock data or the second clock data as selected clock data, wherein the first and second status variables are furthermore based at least on the selected clock data.

[0085] In some embodiments of the exemplary method, the first clock data correspond to a device in the first logical network which is regarded as providing the most accurate time among the majority of first devices, wherein the second clock data correspond to a device in the second logical network which is regarded as providing the most accurate time among the majority of second devices.

[0086] In some embodiments, the exemplary method may further include determining third clock data associated with a second port of the network device, including receiving a third plurality of clock data from one or more third devices connected to the second port of the network device, wherein the third clock data is determined based on the third plurality of clock data, wherein the second port is not assigned to any logical network, and wherein the setting of the first and second status variables associated with the first port is further based at least on the third clock data.The exemplary method may further include selecting the first, second, or third clock data as selected clock data, wherein the first and second status variables assigned to the first port are furthermore based at least on the selected clock data, wherein the selected clock data correspond to a device which, among the devices corresponding to the first, second, and third clock data respectively, is regarded as having the most accurate clock.

[0087] In some embodiments of the exemplary method, the first logical network is a first VLAN enabled on the first port, and the second logical network is a second VLAN enabled on the first port.

[0088] In some embodiments of the exemplary method, the first port is a virtual port on a virtual machine.

[0089] A non-volatile, computer-readable storage medium according to the present disclosure may contain computer-executable instructions which, when executed by a processor in a network, may cause the processor to: determine first clock data associated with a first logical network configured on a first port of the network device, including receiving on the first port; determine a first plurality of clock data associated with one or more first devices, with the first clock data being determined based on the first plurality of clock data;Determining second clock data associated with a second logical network, distinct from the first logical network and also configured on the first port of the network device, including receiving, on the first port, a second plurality of clock data associated with one or more second devices, the second clock data being determined based on the second plurality of clock data; setting a first status variable associated with the first logical network on the first port, based at least on device clock data from the network device and the first clock data; and setting a second status variable associated with the second logical network on the first port, based at least on the device clock data and the second clock data.

[0090] In some embodiments, receiving the first plurality of clock data at the first port may include receiving first data frames that encapsulate the first plurality of clock data, wherein the first data frames are tagged with information that designates the first logical network, and receiving the second plurality of clock data at the first port may include receiving second data frames that encapsulate the second plurality of clock data, wherein the second data frames are tagged with information that designates the second logical network.

[0091] In some embodiments, the computer-executable instructions, when executed by the processor, can further cause the processor to select the first clock data or the second clock data as selected clock data, wherein the first and second status variables are furthermore based on at least the selected clock data.

[0092] In some embodiments, the first clock data corresponds to a device in the first logical network that is considered among the majority of first devices to provide the most accurate time, wherein the second clock data corresponds to a device in the second logical network that is considered among the majority of second devices to provide the most accurate time.

[0093] In some embodiments, the computer-executable instructions, when executed by the processor, can further cause the processor to determine third clock data associated with a second port of the network device, including receiving a third plurality of clock data from one or more third devices connected to the second port of the network device, wherein the third clock data is determined based on the third plurality of clock data, wherein the second port is not assigned to any logical network, and wherein the setting of the first and second status variables associated with the first port is further based at least on the third clock data.

[0094] In some embodiments, the computer-executable instructions, when executed by the processor, can further cause the processor to select the first, second, or third clock data as selected clock data, wherein the first and second status variables are furthermore based on at least the selected clock data.

[0095] A network device according to the present disclosure may comprise a first port; one or more computer processors; and a computer-readable storage medium containing instructions for controlling the one or more computer processors, such that they can be operated to: determine first clock data associated with a first logical network configured at the first port of the network device, including receiving at the first port; determine a first plurality of clock data associated with one or more first devices, with the first clock data being determined based on the first plurality of clock data;Determining second clock data associated with a second logical network, distinct from the first logical network and also configured on the first port of the network device, including receiving, on the first port, a second plurality of clock data associated with one or more second devices, the second clock data being determined based on the second plurality of clock data; setting a first status variable associated with the first logical network on the first port, based at least on the device clock data of the network device and the first clock data; and setting a second status variable associated with the second logical network on the first port, based at least on the device clock data and the second clock data.

[0096] In some embodiments of the network device, receiving the first plurality of clock data at the first port may include receiving first data frames encapsulating the first plurality of clock data, wherein the first data frames are tagged with information designating the first logical network, and receiving the second plurality of clock data at the first port may include receiving second data frames encapsulating the second plurality of clock data, wherein the second data frames are tagged with information designating the second logical network.

[0097] In some embodiments of the network device, the computer-readable storage medium may further include instructions to control the one or more computer processors to select the first clock data or the second clock data as selected clock data, wherein the first and second status variables are furthermore based on at least the selected clock data.

[0098] In some embodiments of the network device, the first clock data corresponds to a device in the first logical network that is considered among the majority of first devices to provide the most accurate time, wherein the second clock data corresponds to a device in the second logical network that is considered among the majority of second devices to provide the most accurate time.

[0099] In some embodiments of the network device, the computer-readable storage medium may further include instructions to control the one or more computer processors, to determine third clock data associated with a second port of the network device, including receiving a third plurality of clock data from one or more third devices connected to the second port of the network device, wherein the third clock data is determined based on the third plurality of clock data, wherein the second port is not assigned to any logical network, and wherein the setting of the first and second status variables associated with the first port is further based at least on the third clock data.

[0100] In some embodiments of the network device, the computer-readable storage medium may further include instructions to control the one or more computer processors to select the first, second, or third clock data as selected clock data, wherein the first and second status variables are furthermore based on at least the selected clock data.

[0101] An exemplary procedure may include synchronizing a clock in a network device with a clock in a first participating device in a first logical network, including exchanging first synchronization messages between a port of the network device and a port of the first participating device, wherein the exchange of first synchronization messages may include providing an identifier with the first synchronization messages that identifies the first logical network.The exemplary method may further include synchronizing the clock in the network device with a clock in a second participating device in a second logical network that is different from the first logical network, including exchanging second synchronization messages between the port of the network device and a port of the second participating device, wherein the exchange of second synchronization messages may include providing an identifier with the second synchronization messages that identifies the second logical network.

[0102] In some embodiments of the exemplary method, the port on the network device can be a master port with respect to the port of the first device involved and a slave port with respect to the port of the second device involved.

[0103] In some embodiments, the exemplary method may further include the port on the network device initiating a first synchronization sequence with the port of the first participating device and performing a second synchronization sequence with the port of the second participating device in response to the second participating device initiating the second synchronization sequence.

[0104] In some embodiments of the exemplary method, the exchange of first synchronization messages with the first participating device may include encapsulating the first synchronization messages in corresponding data frames and tagging the data frames with the identifier that identifies the first logical network, wherein the exchange of second synchronization messages with the second participating device may include encapsulating the second synchronization messages in corresponding data frames and tagging the data frames with the identifier that identifies the second logical network.

[0105] In some embodiments of the exemplary method, the first logical network can be a first VLAN enabled on the port, and the second logical network can be a second VLAN enabled on the port.

[0106] A non-volatile, computer-readable storage medium according to the present disclosure may contain computer-executable instructions which, when executed by a processor in a network device, may cause the processor to: synchronize a clock in the network device with a clock in a first participating device in a first logical network, including exchanging first synchronization messages between the port of the network device and a port of the first participating device, wherein the exchange of first synchronization messages may include providing an identifier with the first synchronization messages that identifies the first logical network;and synchronizing the clock in the network device with a clock in a second participating device in a second logical network that is different from the first logical network, including exchanging second synchronization messages between the port of the network device and a port of the second participating device, wherein the exchange of second synchronization messages may include providing an identifier with the second synchronization messages that identifies the second logical network.

[0107] In some embodiments, the port on the network device can be a master port with respect to the port of the first device involved and a slave port with respect to the port of the second device involved.

[0108] In some embodiments, the computer-executable instructions, when executed by the processor, may further cause the processor to initiate a first synchronization sequence with the port of the first participating device and to perform a second synchronization sequence with the port of the second participating device in response to the second participating device initiating the second synchronization sequence.

[0109] In some embodiments, the exchange of first synchronization messages with the first participating device may include encapsulating the first synchronization messages in corresponding data frames and tagging the data frames with the identifier that identifies the first logical network, wherein the exchange of second synchronization messages with the second participating device may include encapsulating the second synchronization messages in corresponding data frames and tagging the data frames with the identifier that identifies the second logical network.

[0110] In some implementations, the first logical network is a first VLAN that is enabled on the port, and the second logical network is a second VLAN that is enabled on the port.

[0111] A network device according to the present disclosure may comprise a port; a clock; one or more computer processors; and a computer-readable storage medium containing instructions for controlling the one or more computer processors, such that they can be operated to: synchronize the clock in the network device with a clock in a first participating device in a first logical network, including exchanging first synchronization messages between the port of the network device and a port of the first participating device, wherein the exchange of first synchronization messages may include providing an identifier with the first synchronization messages that identifies the first logical network;and synchronizing the clock in the network device with a clock in a second participating device in a second logical network that is different from the first logical network, including exchanging second synchronization messages between the port of the network device and a port of the second participating device, wherein the exchange of second synchronization messages may include providing an identifier with the second synchronization messages that identifies the second logical network.

[0112] In some embodiments of the network device, the port on the network device can be a master port with respect to the port of the first participating device and a slave port with respect to the port of the second participating device.

[0113] In some embodiments of the network device, the computer-readable storage medium may further contain instructions to control the one or more computer processors to initiate a first synchronization sequence with the port of the first participating device and to perform a second synchronization sequence with the port of the second participating device in response to the second participating device initiating the second synchronization sequence.

[0114] In some embodiments of the network device, the exchange of first synchronization messages with the first participating device may include encapsulating the first synchronization messages in corresponding data frames and tagging the data frames with the identifier that identifies the first logical network, wherein the exchange of second synchronization messages with the second participating device may include encapsulating the second synchronization messages in corresponding data frames and tagging the data frames with the identifier that identifies the second logical network.

[0115] In some embodiments of the network device, the first logical network is a first VLAN enabled on the port, and the second logical network is a second VLAN enabled on the port.

[0116] The above description illustrates various embodiments of the present disclosure as well as examples of how aspects of the respective embodiments can be implemented. The above examples should not be considered the only embodiments and serve to illustrate the flexibility and advantages of the respective embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations, and equivalents may be used without deviating from the scope of the present disclosure as defined in the claims.

[0117] The following is a series of numbered features that describe specific embodiments of the invention. If one feature refers to another numbered feature, these features can be considered in combination. 1. Non-volatile, computer-readable storage medium on which computer-executable instructions are stored which, when executed by a processor in a network, cause the processor to: Determining first clock data associated with a first logical network configured on a first port of a network device, including receiving, on the first port, a first plurality of clock data associated with one or more first devices, wherein the first clock data is determined based on the first plurality of clock data; Determining second clock data associated with a second logical network that is different from the first logical network and is also configured on the first port of the network device, including receiving on the first port, a second plurality of clock data associated with one or more second devices, wherein the second clock data is determined based on the second plurality of clock data; Setting a first status variable assigned to the first logical network on the first port, based at least on device clock data from the network device and the first clock data; and setting a second status variable assigned to the second logical network on the first port, based at least on the device clock data and the second clock data; 2. Non-transitory, computer-readable storage medium according to embodiment 1, wherein the reception of the first plurality of clock data at the first port comprises receiving first data frames encapsulating the first plurality of clock data, wherein the first data frames are characterized with information designating the first logical network, and wherein the reception of the second plurality of clock data at the first port comprises receiving second data frames encapsulating the second plurality of clock data, wherein the second data frames are characterized with information designating the second logical network. 3. Non-transitory, computer-readable storage medium according to embodiment 1, wherein the computer-executable instructions, when executed by the processor, further cause the processor to select the first clock data or the second clock data as selected clock data, wherein the first and the second status variables are furthermore based at least on the selected clock data. 4. Non-transitory, computer-readable storage medium according to embodiment 1, wherein the first clock data corresponds to a device in the first logical network which is regarded among the majority of the first devices as providing the most accurate time, and wherein the second clock data corresponds to a device in the second logical network which is regarded among the majority of the second devices as providing the most accurate time. 5. Non-transitory, computer-readable storage medium according to embodiment 1, wherein the computer-executable instructions, when executed by the processor, further cause the processor to determine third clock data associated with a second port of the network device, including receiving a third plurality of clock data associated with one or more third devices connected to the second port of the network device, wherein the third clock data is determined based on the third plurality of clock data, wherein the second port is not assigned to any logical network, and wherein the setting of the first and second status variables at the first port is further based at least on the third clock data. 6. Non-transitory, computer-readable storage medium according to embodiment 5, wherein the computer-executable instructions, when executed by the processor, further cause the processor to select the first, second or third clock data as selected clock data, wherein the first and second status variables are furthermore based on at least the selected clock data. 7. Network device, including: a first port; one or more computer processors; and a computer-readable storage medium containing instructions for controlling one or more computer processors so that they can perform the following: Determining first clock data associated with a first logical network configured on the first port of the network device, including receiving, on the first port, a first plurality of clock data associated with one or more first devices, wherein the first clock data is determined based on the first plurality of clock data; Determining second clock data associated with a second logical network that is different from the first logical network and is also configured on the first port of the network device, including receiving on the first port, a second plurality of clock data associated with one or more second devices, wherein the second clock data is determined based on the second plurality of clock data; Setting an initial status variable associated with the first logical network on the first port, based at least on device clock data from the network device and the initial clock data; and Setting a second status variable assigned to the second logical network on the first port, based at least on the device clock data and the second clock data. 8. Network device according to embodiment 7, wherein the reception of the first plurality of clock data at the first port comprises receiving first data frames encapsulating the first plurality of clock data, wherein the first data frames are characterized with information designating the first logical network, and wherein the reception of the second plurality of clock data at the first port comprises receiving second data frames encapsulating the second plurality of clock data, wherein the second data frames are characterized with information designating the second logical network. 9. Network device according to embodiment 7, wherein the computer-readable storage medium further comprises instructions for controlling one or more computer processors to select the first clock data or the second clock data as selected clock data, wherein the first and second status variables are furthermore based on at least the selected clock data. 10. Network device according to embodiment 7, wherein the first clock data corresponds to a device in the first logical network which is regarded among the majority of the first devices as providing the most accurate time, and wherein the second clock data corresponds to a device in the second logical network which is regarded among the majority of the second devices as providing the most accurate time. 11. Network device according to embodiment 7, wherein the computer-readable storage medium further comprises instructions for controlling one or more computer processors to determine third clock data assigned to a second port of the network device, including receiving a third plurality of clock data from one or more third devices connected to the second port of the network device, wherein the third clock data is determined based on the third plurality of clock data, wherein the second port is not assigned to any logical networks, and wherein the setting of the first and second status variables assigned to the first port is further based at least on the third clock data. 12. Network device according to embodiment 11, wherein the computer-readable storage medium further comprises instructions for controlling one or more computer processors to select the first, second or third clock data as selected clock data, wherein the first and second status variables are furthermore based on at least the selected clock data. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 16 / 752,314

[0002] US 2013 / 121351 A1

[0004] Cited non-patent literature

[0000] IEEE-1588-2008

[0006]

Claims

[1] Network device, comprising: a port; a clock; one or more computer processors; and a computer-readable storage medium containing instructions for controlling one or more processors to: Synchronizing the clock in the network device with a clock in a first participating device in a first logical network, including exchanging initial synchronization messages between the port of the network device and a port of the first participating device, wherein the exchange of the initial synchronization messages includes providing an identifier in the initial synchronization messages that identifies the first logical network; and Synchronizing the clock in the network device with a clock in a second participating device in a second logical network different from the first logical network, including exchanging second synchronization messages between the port of the network device and a port of the second participating device, wherein the exchange of the second synchronization messages includes providing an identifier in the second synchronization messages that identifies the second logical network. [2] Network device according to claim 1, wherein the first and second synchronization messages are exchanged in a unicast transmission. [3] Network device according to claim 1, wherein the first and second synchronization messages are exchanged in a multicast transmission. [4] Network device according to claim 1, wherein the port on the network device is a master port with respect to the port of the first participating device and a slave port with respect to the port of the second participating device. [5] Network device according to claim 1, wherein the port on the network device is a master port with respect to both the port of the first participating device and the port of the second participating device. [6] Network device according to claim 1, wherein the computer-readable storage medium further comprises instructions for controlling one or more processors to: Performing an initial synchronization sequence with the port of the first participating device to synchronize the clock in the network device with the clock of the first participating device in the first logical network; and Perform a second synchronization sequence with the port of the second participating device to synchronize the clock in the network device with the clock of the second participating device in the second logical network. [7] Network device according to claim 6, wherein the first synchronization sequence is performed according to IEEE 1588-2008, wherein the second synchronization sequence is performed according to IEEE 1588-2008. [8] Network device according to claim 6, wherein the first synchronization sequence is performed with the port of the first participating device as the slave port, wherein the second synchronization sequence is performed with the port of the second participating device as the master port. [9] Network device according to claim 1, wherein the computer-readable storage medium further comprises instructions for controlling one or more processors to: Initiating an initial synchronization sequence with the port of the first participating device; and Performing a second synchronization sequence with the port of the second participating device in response to the second participating device initiating the second synchronization sequence. [10] Network device according to claim 9, wherein the first synchronization sequence is initiated with the port of the first participating device as the slave port, wherein the second synchronization sequence is initiated with the port of the second participating device as the master port. [11] Network device according to claim 1, wherein the exchange of first synchronization messages with the first participating device comprises encapsulating the first synchronization messages in corresponding data frames and tagging the data frames with the identifier that identifies the first logical network, and wherein the exchange of second synchronization messages with the second participating device comprises encapsulating the second synchronization messages in corresponding data frames and tagging the data frames with the identifier that identifies the second logical network. [12] Network device according to claim 1, wherein the first logical network is a first VLAN that is enabled on the port and the second logical network is a second VLAN that is enabled on the port. [13] Non-volatile, computer-readable storage medium on which computer-executable instructions are stored which, when executed by a processor in a network, cause the processor to: Synchronizing the clock in the network device with a clock in a first participating device in a first logical network, including exchanging initial synchronization messages between the port of the network device and a port of the first participating device, wherein the exchange of the initial synchronization messages includes providing an identifier in the initial synchronization messages that identifies the first logical network; and Synchronizing the clock in the network device with a clock in a second participating device in a second logical network different from the first logical network, including exchanging second synchronization messages between the port of the network device and a port of the second participating device, wherein the exchange of the second synchronization messages includes providing an identifier in the second synchronization messages that identifies the second logical network. [14] Non-volatile computer-readable storage medium according to claim 13, wherein the first and second synchronization messages are exchanged in a unicast transmission. [15] Non-volatile computer-readable storage medium according to claim 13, wherein the first and second synchronization messages are exchanged in a multicast transmission. [16] Non-volatile computer-readable storage medium according to claim 13, wherein the port on the network device is a master port with respect to the port of the first participating device and a slave port with respect to the port of the second participating device. [17] Non-volatile computer-readable storage medium according to claim 13, wherein the port on the network device is a master port with respect to both the port of the first participating device and the port of the second participating device. [18] Non-volatile computer-readable storage medium according to claim 13, wherein the computer-executable instructions, when executed by the processor, further cause the processor to: Performing an initial synchronization sequence with the port of the first participating device to synchronize the clock in the network device with the clock of the first participating device in the first logical network; and Perform a second synchronization sequence with the port of the second participating device to synchronize the clock in the network device with the clock of the second participating device in the second logical network. [19] Non-volatile computer-readable storage medium according to claim 18, wherein the first synchronization sequence is performed in accordance with IEEE 1588-2008, and wherein the second synchronization sequence is also performed in accordance with IEEE 1588-2008. [20] Non-volatile computer-readable storage medium according to claim 18, wherein the first synchronization sequence is performed with the port of the first participating device as the slave port, wherein the second synchronization sequence is performed with the port of the second participating device as the master port. [21] Non-volatile computer-readable storage medium according to claim 13, wherein the computer-executable instructions, when executed by the processor, further cause the processor to: Initiating an initial synchronization sequence with the port of the first participating device; and Performing a second synchronization sequence with the port of the second participating device in response to the second participating device initiating the second synchronization sequence. [22] Non-volatile computer-readable storage medium according to claim 21, wherein the first synchronization sequence is initiated with the port of the first participating device as the slave port, wherein the second synchronization sequence is initiated with the port of the second participating device as the master port. [23] Non-volatile computer-readable storage medium according to claim 13, wherein the exchange of first synchronization messages with the first participating device comprises encapsulating the first synchronization messages in corresponding data frames and tagging the data frames with the identifier that identifies the first logical network; and wherein the exchange of second synchronization messages with the second participating device comprises encapsulating the second synchronization messages in corresponding data frames and tagging the data frames with the identifier that identifies the second logical network. [24] Non-volatile computer-readable storage medium according to claim 13, wherein the first logical network is a first VLAN that is enabled on the port and the second logical network is a second VLAN that is enabled on the port.

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