Neuron circuit
By encoding data in pulse width and utilizing FPGA configuration data, the challenges of computational effort and power consumption in neural networks are addressed, enabling efficient and flexible implementation in integrated circuits.
Patent Information
- Application Number
- DE202023001731
- Authority / Receiving Office
- DE · DE
- Patent Type
- Utility models
- Current Assignee / Owner
- Filing Date
- 2023-08-16
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2033-08-31
AI Technical Summary
Existing neural networks, particularly convolutional neural networks (CNNs), face challenges in computational effort, memory access bottlenecks, and high power consumption, while spiking neural networks (SNNs) are difficult to implement in highly integrated circuits due to their analog nature.
Implementing neurons that represent data using pulses of varying lengths, where data values are encoded in pulse width, utilizing tristate buffers to convert current into voltage for processing, and leveraging FPGA configuration data for weight data and connectivity, with configurable neuron inputs.
This approach enables faster processing with lower power consumption, facilitating implementation in highly integrated chips and providing flexibility and efficiency in signal transmission.
Smart Images
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Abstract
Description
[0001] The state of the art in artificial intelligence (AI) is dominated by so-called neural networks (NNs). These are circuit representations of real neurons in the brain. The goal is to emulate these parts of the brain as closely as possible in order to achieve human-like intelligence in a circuit implementation.
[0002] The main challenges are the speed of signal processing of the neurons, their size and the energy consumption required to operate such an artificial brain.
[0003] For the state of the art in artificial intelligence, it is important to know the basic concepts of the various neural networks.
[0004] The most widespread type is the so-called "convolutional neural network" (CNN). Such neural networks are used for so-called "deep learning," that is, for a learning process similar to that of the brain. In biology, this is comparable to a child learning.
[0005] CNNs have the widest application in image processing and image recognition. The advantage of CNNs lies in the fact that they can be fully described mathematically. This makes it possible to implement them digitally on digital computers or, even better, in field-programmable gate arrays (FPGAs).
[0006] CNNs are easy to implement in digital environments, but have the major disadvantage of significant computational overhead due to the multiplication and addition (MAC) circuits. Furthermore, they suffer from memory access bottlenecks and have high specific power consumption.
[0007] There is another class of neural networks that can extend the concept of neural networks to include the factor of time or simultaneity. These spiking neural networks (SNNs) are more closely related to their real-world biological counterparts.
[0008] As the name suggests, the information is not represented by digital numbers, but by pulses of varying amplitude and duration. Because the spikes can be very short, the SNN can operate significantly faster than a CNN. Furthermore, its power consumption is much lower compared to CNNs.
[0009] In summary, CNNs require massive digital computing power for their implementation; SNNs require analog circuits that are difficult or impossible to implement in highly integrated circuits with feature sizes of less than 10 nm.
[0010] The present invention aims to propose advanced neurons that can be implemented in highly integrated chips.
[0011] This problem is solved according to the invention by the features listed in the claims.
[0012] In principle, in the present invention, the data (signals) to be processed are represented neither by a binary word, as is usual in CNNs, nor by spikes of different amplitudes, as is usual in SNNs.
[0013] The analog data is represented by pulses of varying lengths. The data value is encoded in the length of the pulse.
[0014] This method of representation offers significant advantages for data processing, as the pulses can be transmitted purely digitally. Furthermore, they use only one signal line, regardless of the analog value range.
[0015] Therefore, as a fundamental feature of the invention, integrated electronic neurons whose input and output signals are pulse-width modulated are used.
[0016] The weight data used for the evaluation, ie multiplication of the pulse-width modulated input data, are digitally applied to the neuron and converted into a current by an arrangement of tristate buffers staggered according to driver strength.
[0017] The current generated by the tristate buffers is used to charge and / or discharge a capacitor and the resulting voltage is converted into a pulse of varying length by a buffer with or without hysteresis.
[0018] It is particularly advantageous if the neurons are implemented in an FPGA and are configurably connected using routing structures commonly used for FPGAs.
[0019] The FPGA configuration data can also be used, at least partially.
[0020] Thus, the weight data of the neurons is at least partially derived from the configuration data of a configurable logic block of an FPGA.
[0021] In particular, the weight data of the neurons from the configuration data for LUTs of a configurable logic block of an FPGA are used.
[0022] Flexibility is also improved if the number of inputs to the neurons is configurable.
[0023] In a chip implementation, the use of a configurable logic block or a neuron can be configured at any point.
[0024] "Configurable" means that the setting can be adjusted via a configuration data stream. Fig. 1: Exemplary implementation of a neuron according to the invention (only one input shown)
Claims
[1] Neuron circuit characterized by that integrated electronic neurons whose input and output signals are pulse-width modulated are used. [2] Neuron circuit according to claim 1 characterized by that the weight data for the evaluation of the pulse-width modulated input data are applied digitally to the neuron and are converted into a current by an arrangement of tristate buffers staggered according to driver strength. [3] Neuron circuit according to one or more of the preceding claims characterized by that the current generated by the tristate buffers charges and / or discharges a capacitor and the resulting voltage is converted into a pulse of varying length by a buffer with or without hysteresis. [4] Neuron circuit according to one or more of the preceding claims characterized by that the neurons are configurably connected via routing structures commonly used for FPGAs. [5] Neuron circuit according to one or more of the preceding claims characterized by that the weight data of the neurons are at least partially used from the configuration data of a configurable logic block of an FPGA. [6] Neuron circuit according to one or more of the preceding claims characterized by that the weight data of the neurons from the configuration data for LUTs of a configurable logic block of an FPGA are used. [7] Neuron circuit according to one or more of the preceding claims characterized by that the number of inputs of the neurons is configurable. [8] Neuron circuit according to one or more of the preceding claims characterized by that the use of a configurable logic block or a neuron is configurable.