Digital signal processing for coherent optical packet detection in burst mode

Abstract

Hub node of a passive optical network, wherein the hub node includes a DSP (Digital Signal Processing) chain configured to: Receiving a signal burst from a leaf node in the passive optical network, wherein the signal burst comprises a frame including a payload and a frame header, the frame header comprising a clock and gain control section, a frame detection section and an equalizer section; Retrieving a clock phase of the leaf node from the clock-and-gain control section of the frame header; Estimation of the signal strength of a signal burst from the leaf node in the passive optical network; Compensation for differences in the signal power of the signal burst from the leaf node; Detecting a frame alignment sequence that indicates the arrival of the signal burst; Determination of MIMO (Multiple Input, Multiple Output) polarization filter coefficients from the frame alignment sequence; Aligning the phase between the X-polarization and Y-polarization of the signal burst using the MIMO polarization filter coefficients; and Determine the frequency offset estimate (FOE) of a local oscillator signal.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This application claims priority to provisional patent application identified by U.S. Serial No. 63 / 607,671, entitled DIGITAL SIGNAL PROCESSING FOR BURST-MODE COHERENT OPTICAL PACKET DETECTION, filed August 12, 2023, which is hereby expressly incorporated by reference into this patent application. AREA OF REVELATION

[0002] The disclosure generally relates to methods and apparatus for passive optical networks and coherent passive optical networks. BACKGROUND

[0003] Optical access networks have evolved to meet the high bandwidth demands driven by emerging services such as 5G mobile internet, cloud networks, high-quality 8K / 16K video streaming applications, and virtual / augmented reality. Passive optical network (PON) technologies are widely deployed as cost-effective solutions to meet such high capacity requirements for end users. Standard PON solutions are based on intensity-modulated direct detection (IMDD) schemes. PONs based on a TDM (time-division multiplexing) mechanism are of particular interest, as they not only conserve wavelength resources but also reduce the associated costs and the number of required optical components. However, standard passive fiber optic networks almost reach their limits at 50 Gbps, considering the required power budget.With the ever-increasing demand for higher transmission capacity, it is therefore expected that passive optical networks with 100 Gbit / s or even more will be required, and that these can use coherent detection.

[0004] In a typical passive optical network using Digital Subcarrier Multiplexing (DSCM), each subcarrier of an N-subcarrier DSCM signal can be divided into M timeslots by the hub optical line terminal (OLT) to enable flexible bandwidth allocation for up to N × M access leaf optical network unit (ONU) subscribers.

[0005] Due to its technological maturity and superior receiver sensitivity, coherent optics, traditionally used for long-haul, metro, and data center transmissions, have attracted significant interest in access networks. It can be used as an attractive solution to the challenges faced by intensity-modulated direct detection (IMDD) techniques, which are limited by chromatic dispersion and spectral efficiency (typically electrical bandwidth efficiency). By utilizing advanced modulation formats, digital dispersion compensation, and equalization enabled by digital signal processing (DSP), coherent PON can provide much greater reach and network capacity.

[0006] However, Coherent PON still faces several challenges, and many efforts have been made to overcome the cost and complexity barrier of coherent optics in access networks.

[0007] Apart from cost and complexity, another key challenge for coherent optics is effective and robust detection in the upstream burst mode direction.

[0008] In the downstream direction, signals are transmitted continuously to all users, while the upstream of TDM-PON is in burst mode. Here, the user-facing leaf ONUs are time-synchronized so they can interleave burst packets with the hub's centralized OLT. The received upstream signals typically have different signal powers, are interleaved in time, have different clock times, carrier phases, carrier frequency offsets, and polarization states (SOPs). For reliable upstream efficiency, the hub OLT must respond quickly to the burst signal, complete the acquisition within a short time, and reset for the next incoming upstream burst.

[0009] This burst-mode detection is more difficult for coherent PONs compared to IMDD-PONs because the information is modulated and multiplexed in phase, polarization, and amplitude dimensions. Traditional coherent continuous-mode detection cannot be used for burst-mode detection because it requires a longer time to complete the acquisition. This makes the coherent PON DSP more challenging, as all subsystems must act very quickly to detect and acquire the short optical packet along with a reliable frequency offset estimate (FOE). The convergence time of the IMDD DSP in the ITU-T standard for 50G-PON has been defined on the timescale of 100 ns. For 100 Gbit / s coherent PON, acquisition times are on the order of several hundred nanoseconds.

[0010] Systems and methods that enable the rapid capture of a TDM (Time Division Multiplexing) burst are needed. With the inclusion of "coherent" frames for PON networks, faster and more reliable frame capture methods are required. SUMMARY

[0011] Systems, nodes, and methods are disclosed, including systems, nodes, and methods for fast retrieval of the clock phase; estimation and compensation for varying signal powers of bursts arriving from different leaf nodes (ONUs); robust detection of the frame alignment sequence indicating the arrival of a signal burst; determination of the polarization MIMO filter coefficients from the frame alignment sequence and alignment of the phase between X-pole and Y-pole; determination of a reliable local oscillator signal frequency offset estimate (FOE); and / or applying / correcting the FOE. The disclosed systems, nodes, and methods provide fast and reliable frame acquisition for coherent passive optical networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments described herein and, together with the description, explain those embodiments. In the drawings: Fig. 1 is a schematic of an exemplary passive optical network according to the present disclosure. Fig. 1A is a schematic of an exemplary DSP chain according to the present disclosure. Fig. 2 is a schematic of an exemplary frame according to the present disclosure. Fig. 3 is a schematic of an exemplary passive optical network overlay method according to the present disclosure. Fig. 4 is a schematic of an exemplary clock recovery loop according to the present disclosure. Fig. 5 is a schematic of an exemplary phase detector according to the present disclosure. Fig. 6 is a diagram illustrating the lower and upper frequencies of a clock tone according to the present disclosure. Fig. 7 is a diagram illustrating the correlating lower and upper frequencies of a clock tone according to the present disclosure. Fig. 8 is a schematic of an exemplary state machine of a clock recovery step according to the present disclosure. Fig. 9A is a diagram illustrating hypothetical received data regarding the timing of fast tracking mode and slow tracking mode by a hub node according to the present disclosure. Fig. 9B is a diagram illustrating the hypothetical position of the clock lock and the detected burst within the clock and gain control portion of an exemplary frame according to the present disclosure. Fig. 9C is a diagram illustrating the hypothetical clock output phase relative to the timing of fast tracking mode and slow tracking mode by a hub node according to the present disclosure. Fig. 9D is a diagram illustrating a hypothetical clock lock value and a false lock with respect to the timing of fast tracking mode and slow tracking mode by a hub node according to the present disclosure. Fig. 9E is a diagram illustrating a hypothetical estimation of clock tone performance relative to the timing of fast tracking mode and slow tracking mode by a hub node according to the present disclosure. Fig. 9F is a diagram illustrating the hypothetical estimation of received signal power with respect to the timing of fast tracking mode and slow tracking mode by a hub node according to the present disclosure. Fig. 10A is a diagram illustrating an example finite state machine (FSM) according to the present disclosure. Fig. 10B is a diagram illustrating an input waveform according to the present disclosure. Fig. 10C is a graph illustrating the gain calculated and applied at various points of the FSM in accordance with the present disclosure. Fig. 10D is a diagram illustrating a clock lock value according to the present disclosure. Fig. 10E is a diagram illustrating a clock output phase according to the present disclosure. Fig. 10F is a graph illustrating clock tone performance using an IIR filter according to the present disclosure. Fig. 10G is a graph illustrating received signal power using an IIR filter according to the present disclosure. Fig. 10H is a diagram illustrating an output waveform according to the present disclosure. Fig. 11 is a schematic of an exemplary gain adjustment state machine according to the present disclosure. Fig. 12 is a schematic of an exemplary frame detector method according to the present disclosure. Fig. 13 is a diagram of Monte Carlo simulations at different decision thresholds according to the present disclosure. Fig. 13A is an exemplary probability diagram for false image detection according to the present disclosure. Fig. 13B is an exemplary graph showing the probability of false detection for various symbol lengths according to the present disclosure. Fig. 14 is a schematic of an exemplary frame detection method using hard decisions and soft decisions according to the present disclosure. Fig. 15 is a table of exemplary frequency offsets translated into a rotation in degrees between consecutive symbols according to the present disclosure. Fig. 16A illustrates diagrams of an example of a cross-correlation (XCorr) of received data for QPSK XPol and YPol (true detection) according to the present disclosure. Fig. 16B illustrates diagrams of an example of received data cross-correlation (XCorr) for QPSK XPol and YPol (error detection) according to the present disclosure. Fig. 17 is a graph of exemplary numerical frame detection probability according to the present disclosure. Fig. 18A illustrates diagrams of an example of different rotations on X-pole and Y-pole after starting equalizer taps for 16QAM according to the present disclosure. Fig. 18B illustrates diagrams of the same spin on X-pole and Y-pole after phase matching according to the present disclosure. Fig. 19A is a diagram of an exemplary frequency offset estimation on X-Pol according to the present disclosure. Fig. 19B is a diagram of an exemplary frequency offset estimation on Y-pole according to the present disclosure. DETAILED DESCRIPTION

[0013] The following detailed description refers to the attached drawings. The same reference numbers in different drawings may indicate the same or similar elements.

[0014] The mechanisms proposed in this disclosure circumvent the problems described above.

[0015] When used in the description and drawings, the following short terms have the following meanings unless otherwise specified:

[0016] Rx stands for receiver, which typically refers to receivers via optical channels, but can also refer to circuit receivers.

[0017] Tx stands for transmitter, which typically refers to optical channel transmitters, but can also refer to circuit transmitters.

[0018] CDest stands for Chromatic Dispersion Estimate.

[0019] The terms "comprises," "includes," "includes," "comprises," "includes," "including," "including," "has," "has," or any other variation thereof are intended to cover non-exclusive inclusion. For example, a method, process, article, or device comprising a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed or inherent in such method, process, article, or device. Further, unless expressly stated otherwise, "or" refers to an inclusive or, not an exclusive or. For example, a condition A or B is satisfied by one of the following: A is true (or present) and B is false (or absent), A is false (or absent) and B is true (or present), and both A and B are true (or present).

[0020] Furthermore, the use of "a" or "an" is used to describe elements and components of the embodiments herein. This is done solely for clarity and to convey a general understanding of the inventive concept. This description should be understood to encompass one or more, and the singular includes the plural unless it is clearly intended otherwise.

[0021] Furthermore, the use of the term “majority” is intended to mean “more than one” unless expressly stated otherwise.

[0022] Furthermore, the phrase “based on” shall mean “at least in part on” unless explicitly stated otherwise.

[0023] Additionally, certain portions of the embodiments have been described as "components" or "circuits" that perform one or more functions. The term "component" or "circuit" may include hardware, such as a processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA), or a combination of hardware and software. Software includes one or more executable computer instructions that, when executed by one or more components, cause the component or circuit to perform a particular function. It is understood that the algorithms described herein are stored on one or more non-transient memories. An example non-transient memory includes random access memory, read-only memory, flash memory, or the like. Such non-transient memory may be electrically or optically based.Furthermore, the messages described herein may be generated by the components and may result in various physical transformations.

[0024] As used herein, any reference to "an embodiment" or "an embodiment" means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment.

[0025] According to the present disclosure, messages transmitted between the nodes AK may be processed by circuitry within the input interface(s) and / or the output interface(s) and / or the control module. Circuitry may be analog and / or digital, components, or one or more appropriately programmed microprocessors and associated hardware and software, or hard-wired logic. Furthermore, certain portions of the embodiments have been described as "components" that perform one or more functions. The term "component" may include hardware, such as a processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA), or a combination of hardware and software.

[0026] Software includes one or more executable computer instructions that, when executed by one or more components, cause the component to perform a particular function. It is understood that the algorithms described herein are stored on one or more non-transient memories. An example non-transient memory includes random access memory, read-only memory, flash memory, or the like. Such non-transient memory may be electrically or optically based. Further, the messages described herein may be generated by the components and result in various physical transformations.

[0027] Additionally, certain portions of the embodiments may be described as "components" or "circuits" that perform one or more functions. The term "component" or "circuit" may include hardware, such as a processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA), or a combination of hardware and software.

[0028] Furthermore, the phrase “based on” shall mean “at least in part on” unless explicitly stated otherwise.

[0029] With reference to the drawings, Fig. 1 is a schematic of an exemplary passive optical network (PON) 10. The passive optical network 10 may include one or more leaf nodes 12a, 12b, 12c, 12n (which may be referred to generally as leaf nodes 12 or as ONUs 12) and one or more hub nodes 14 (which may be referred to as OLTs 14) connected to the one or more leaf nodes 12 via one or more optical fibers. In the exemplary passive optical network (PON) 10, for explanatory purposes, the leaf nodes 12 are referred to as "downstream" of the hub node 14 and the hub node 14 is referred to as "upstream" of the leaf node 12. In some embodiments, the PON 10 may include one or more splitters 16 disposed between the hub node 14 and the one or more leaf nodes 12. The PON 10 may include other components that are not shown for clarity.

[0030] The hub node 14 may include one or more transmitters (Tx) 17 for receiving signals from one or more leaf nodes 12 and may include one or more receivers (Rx) 18 for transmitting signals to the one or more leaf nodes. The hub node 14 may include a digital signal processing (DSP) chain 19 for the subsequent analog-to-digital conversion (ADC) of a received signal at the hub node 14. The digital signal processing chain 19 may be executed in the receiver 18 of the hub node 14. An exemplary DSP chain 19 is shown in Fig. 1A as applied to the nodes and methods described herein; however, since standard DSPs are well known to persons of ordinary skill in the art, the general structure of a standard DSP will not be further described here.

[0031] The hub node 14 may include one or more processors 21. The processor 21 may be implemented as a single processor or multiple processors operating cooperatively or independently to execute program logic and / or configured to perform steps as described herein. It should be understood that in certain embodiments employing more than one processor 21, the processors 21 may be remotely located, co-located, or comprise a unitary multi-core processor. The processors 21 may be capable of reading and / or executing executable processor code and / or be capable of creating, manipulating, retrieving, modifying, and / or storing data structures in non-transitory memory.

[0032] Example embodiments of the processor 21 may include, but are not limited to, a digital signal processor (DSP), a central processing unit (CPU), a field programmable gate array (FPGA), a microprocessor, a multi-core processor, combinations thereof, and / or the like, for example.

[0033] It should be understood that the hub node 14 and the one or more leaf nodes 12 may be implemented in a variety of ways, including those shown and discussed in U.S. Patent Application No. 20090245289 entitled "Programmable Time Division Multiplexed Switching," the entire contents of which are hereby incorporated by reference.

[0034] The passive optical network (PON) 10 has continuous downstream signals from the hub node 14 to one or more leaf nodes 12, while upstream signals are sent from the leaf nodes 12 to the hub node 14 in bursts (which may be referred to herein as signal bursts). The bursts are synchronized so as not to interfere with each other. (Conventionally, the upstream signals were sent upstream over a single channel on the same wavelength.) The leaf nodes 12 each send data signals in the signal burst to the hub node 14 via a frame 20 (which may also be referred to as a packet 20). The hub node 14 receives the frame 20.

[0035] The processor 21 of the hub node 14 can process the frame 20 using the DSP chain 19 after the arrival of the signal burst.

[0036] Fig. Figure 2 illustrates an example frame 20, such as may be sent from an example leaf node 12 to the hub node 14. The frame 20 includes the payload 22 (which includes the transmitted data traffic) and a frame header 24. The frame header 24 is typically approximately 480 ns. The payload 22 is typically approximately three microseconds.

[0037] The frames 20 may be transmitted in signal bursts from the downstream leaf nodes 12 to the upstream hub node 14. That is, a first leaf node 12a may transmit a first frame 20a as the first signal burst, then a second leaf node 12b may transmit a second frame 20b as the second signal burst, then the third leaf node 12c may transmit a third frame 20c as the third signal burst, and the "n" leaf node 12n may transmit an N frame 20n as an N signal burst, and so on, sequentially in a time-ordered sequence. The sequential order of the leaf nodes 12 each transmitting a corresponding frame 20 in a signal burst to the hub node 14 may be repeated.

[0038] The frame header 24 contains information for frame alignment. The frame header 24 may include a clock and gain control section 30, a frame detection section 32, and an equalizer section 34. The frame header 24 may have a length of 1920 characters, which may correspond to an acquisition time of approximately 480 ns for 4 GBaud systems (1920 / 4e9).

[0039] Each frame 20 may have different powers (errors), which is indicated in the clock and gain control section 30 of frame 20. Hub node 14 may compensate for an error, as indicated in the clock and gain control section 30 of frame 20. In some embodiments, the clock and gain control section 30 may contain up to 1024 symbols. The clock and gain control section 30 of frame 20 may be reserved for automatic gain control (AGC) and clock lock.

[0040] The frame detection section 32 of the frame 20 contains information for the hub node 14 to determine the existence of the frame 20 (the beginning of the frame 20) arriving at the hub node 14. Furthermore, the frame detection section may contain "jump-start" information that aids in estimating the tap weights of the polarization MIMO, which leads into the equalizer section 34 of the frame 20. In some embodiments, the frame detection section 32 may contain up to 512 symbols.

[0041] The equalizer section 34 may include subsections, including a phase correction subsection 40 for aligning the phase rotation between the X pole and the Y pole; an equalizer training phase and a frequency offset estimation subsection 42; and a carrier phase estimator (CPE) frequency convergence subsection 44. In some embodiments, the equalizer section 34 may include up to 384 symbols. The phase correction subsection 40 may include up to 64 symbols. The equalizer training phase subsection and the frequency offset estimation subsection 42 may include up to 256 symbols. The CPE frequency convergence subsection 44 may include up to 64 symbols.

[0042] An exemplary PON overlay method 100 is shown in Fig. 3. The PON overlay method 100 may assign a specific wavelength (ie, a specific subcarrier) to a specific leaf node 12 for upstream communication with the hub node 14.

[0043] The PON overlay method 100 utilizes the acquisition of a frame 20 at the hub node 14 from a corresponding leaf node 12. In general, the PON overlay method 100 may include a step 102 for quickly acquiring the clock phase; a step 104 for estimating and compensating for different signal powers of bursts coming from different bursts of the leaf nodes 12 (which may be referred to as ONUs); a step 106 for robustly detecting the frame alignment sequence indicating the arrival of a signal burst; a step 108 for determining the polarization MIMO filter coefficients from the frame alignment sequence and aligning the phase between X-pole and Y-pole; and a step 110 for determining a reliable local oscillator signal Frequency Offset Estimate (FOE) and / or applying the FOE correction.

[0044] In some embodiments, the PON overlay method 100 can be implemented within 480ns.

[0045] In some embodiments, step 102 of detecting the clock cycle may last from eighteen nanoseconds to twenty nanoseconds. In step 102, clock recovery may be a method for a coherent burst-mode receiver 18 in which the clock frequency offset has been resolved to a few parts per million (ppm) by locking the clock of the upstream signal from leaf node 12 to the downstream signal from hub node 14. Locking the signal may be accomplished, for example, by directly tuning a VCO of leaf node 12 and hub node 14 or by preprogramming the numerically controlled oscillator (NCO) in an Rx DSP of leaf node 12 and hub node 14.

[0046] The clock phase and the small frequency difference can be captured during the first part of the frame alignment sequence (FAS) from packet 20 in hub node 14. The clock phase can be captured in the frequency domain by correlating the upper and lower sideband frequencies at a frequency offset of the baud rate for each polarization and then summing the resulting signals.

[0047] The clock and gain control section 30 may include clock symbols comprising a series of alternating -1 and +1 symbols for strong tone detection, or a similar sequence for 16QAM / QPSK transmission.

[0048] An example of a clock recovery loop 50 is shown in Fig. 4, including FFT 52, Rx CDEQ 54, a trace phase detector 56, a loop fitter 58, a phase adjuster 60, and an IFFT 62. An exemplary trace phase detector 56 is shown in more detail in FIG. 5. Phase detection can be performed in the frequency domain after CD compensation (Rx CDEQ 54). The trace phase detector 56 correlates upper and lower sideband frequencies, spaced by the baud rate.

[0049] In the case of a +1,-1 sequence, the energy of the clock tone is very high and is ideal for the initial clock lock, as in the Fig. 6 and Fig. 7 shown. Fig. Figure 6 illustrates the correlation of lower and upper frequencies. Fig. Figure 7 shows strong beat tones from +1,-1 patterns. A strong beat increases the probability that the hub node will lock on the beat tone.

[0050] A "determinant" version of the phase detector does not work with some input polarization states (SOP) when using a preamble (such as frame header 24). The trace-type phase detector 56 used in the clock recovery loop 50 is effective as long as the DGD in the link is negligible (as is the case with the PON 10). For fast locking, clock frequency locking is used by adjusting the ONU's VCO to lock to the OLT or by storing the clock frequency offset from the last burst.

[0051] Fig. Figure 8 is a state machine diagram of the clock recovery step 102. In a step 150, the hub node 14 waits for a signal from the leaf node 12 while observing the input power and the strength of the clock tone. The receiver's clock frequency may be preprogrammed with the observations of the burst clock frequency from a particular ONU 12. In one embodiment, the ONU clock of the leaf node 12 may be tuned to be identical to, or a fixed offset from, the continuous downstream signal from the hub node 14.

[0052] If hub node 14 detects a signal burst from leaf node 12 in step 152, such as after both the input power and the clock have exceeded a predetermined threshold, hub node 14 enters fast-tracking mode in step 154. In fast-tracking mode, the clock loop filter is programmed for fast clock convergence, and the clock loop is closed.

[0053] If hub node 14 detects that the clock is locked, the hub node transitions to step 156 of the slow monitoring mode. Hub node 14 may remain in fast tracking for a predetermined number (N) of clock cycles (also referred to as the "hold-off time") to allow convergence and then transition to slow tracking mode after the clock phase has converged. Slow tracking mode uses clock loop filter coefficients programmed for slow changes, thus better suppressing phase detector noise.

[0054] Once the burst has disappeared (i.e., the signal is completed), the hub node 14 waits again for another signal (step 150).

[0055] Fig. 9A-9F illustrate hypothetical examples of different clock recovery outputs related to fast tracking mode and slow tracking mode during processing of the clock and gain control section 30 of frame 20 by hub node 14. The hold time also gives the clock recovery time to stabilize, ignoring false lock points (shown) while the clock recovery performs a "pull-in." The power of the clock tone can also be used for gain control. In fast tracking mode, hub node 14 quickly pulls in the clock to correctly determine the phase. In fast tracking mode, hub node 14 turns on clock recovery. Then, once the clock is locked, hub node 14 enters a slow tracking mode with coefficients that are less noisy than coefficients used in fast tracking mode.

[0056] Fig. 9A illustrates received data regarding the timing of the fast tracking mode and the slow tracking mode by the hub node 14. Fig. Figure 9B illustrates the position of the clock lock and the detected burst within the clock and gain control section 30 of frame 20. Fig. Figure 9C illustrates the clock output phase with respect to the timing of the fast tracking mode and the slow tracking mode by the hub node 14. Fig. Figure 9D illustrates the value of the clock lock (which also shows a false lock) with respect to the timing of the fast tracking mode and the slow tracking mode by the hub node 14. Fig. Figure 9E illustrates the estimation of clock tone power (which can be used for AGC) with respect to the timing of the fast tracking mode and the slow tracking mode by hub node 14. Fig. Figure 9F illustrates the estimation of received signal power (which can be used for AGC) with respect to the timing of the fast tracking mode and the slow tracking mode by the hub node 14.

[0057] The clock and gain control section 30 can be used by the hub node 14 for automatic gain control (AGC) for coherent optical burst-mode receivers 18. The initial gain value can be set according to the power of the last packet payload from a single leaf node 12, which can be referred to as the last known good gain value. The appropriate gain can be determined within the initial portion of the frame header 24 by measuring the power of the clock tone from the clock phase detector.

[0058] The appropriate gain can be adjusted within the payload portion 22 of the packet 20 using a signal power estimate. The last known good gain value from a particular leaf node 12 can be updated and stored for future packets from that leaf node 12. The clock and gain control portion 30 of the frame header 24 of frame 20, as well as the payload portion 22 of frame 20, can be used for automatic gain control (AGC).

[0059] Fig. 10A-10G illustrate a hypothetical example where the gain of the incoming signal is very low. Fig. Figure 10A shows a finite state machine (FSM). Fig. Figure 10B illustrates an input waveform. Fig. Figure 10C illustrates the calculated and applied gain at different points of the FSM. Fig. 10D illustrates a clock lock value. Fig. 10E shows a clock output phase. Fig. Figure 10F illustrates clock tone performance using an IIR filter that may be used for AGC within the clock and gain control section 30 of the frame header 24 of frame 20. Fig. Figure 10G illustrates the received signal power using an IIR filter, which may be used for continuous gain control within the payload 22 of the frame 20 until the end of the burst (i.e., until the end of the received signal). Fig. 10H illustrates an output waveform.

[0060] As previously mentioned, clock recovery may switch to fast tracking mode upon detection of a signal burst. In some embodiments, hub node 14 switches to slow tracking mode after holding back for N clock cycles for convergence. AGC does not change any coefficients for fast tracking mode or slow tracking mode. In some embodiments, the gain is not adjusted during fast tracking mode and is only adjusted using the power estimate from either the average power of the clock tone or the signal in slow tracking mode ( Fig. 10C).

[0061] Fig. 10F and Fig. 10G illustrates a graph of the average clock tone and signal power using an IIR filter. During the payload, the signal power and gain are continuously estimated and updated, respectively. The last known good (LKG) gain value can be stored as a reference for adjusting the gain of the next incoming burst from a specific ONU 12. This process is independent and records different gain values ​​for each ONU 12.

[0062] Fig. Figure 11 shows an example of a gain adjustment state machine, illustrating step 104, for estimating and compensating for different signal power of bursts arriving from different leaf nodes (ONUs) 12. The gain is calculated to yield the desired power (depending on the modulation format). Power measurements can be calculated by the hub node 14 from the clock tone / signal power within the clock and gain control section 30 of the frame header 24 of the frame 20 or from RMS power measurements from the payload 22. The sequence of events is as follows.

[0063] As shown, step 170 is a "discovery" bring-up phase. The discovery bring-up phase may be used, for example, when the hub node 14 is first plugged in and / or powered on. Processing of signal bursts may not begin immediately. The hub node 14 may go through a "transient" phase once it is activated when signal bursts are received, for example, using a firmware state machine, before the hub node 14 begins processing, that is, before the hub node 14 begins detecting packets 20 and processing the frame header 24 and payload 22 of the packets 20. The discovery bring-up phase may not be used in some cases, for example, when the hub node 14 is already in use.

[0064] Starting in the detection application phase, the hub node 14 sets the gain to the LKG gain value in a step 172. The LKG gain value originates from a specific leaf node 12 and is calculated separately for each leaf node 12. In a step 174, a burst from leaf node 12 is detected by the hub node 14.

[0065] In a step 176, the hub node 14 measures the power during the fast clock recovery mode after burst detection.

[0066] In a step 178, the hub node 14 sets the gain from the clock tone or signal power when the clock is locked and goes into slow tracking mode.

[0067] In a step 180, the hub node 14 may continuously measure the performance after IIR convergence during the payload 22 of the burst and update the gain value. The hub node 14 may store the LKG gain value for a particular leaf node 12 to be used for the next burst from that particular leaf node 12.

[0068] Let us return to Fig. 3, step 106 in the PON overlay method 100 includes a frame detector of the hub node 14 for coherent optical burst-mode receivers 18, where the hub node 14 robustly detects the frame alignment sequence (FAS) indicating the arrival of a burst from a particular leaf node 12. If the hub node 14 does not detect the packet 20, the packet 20 is discarded. The frame alignment sequence (FAS) comprises interleaved symbols of a known pattern and the encrypted version of the known pattern in the frame detection section 32 of the frame header 24 of the frame 20. The frame detector deinterleaves and decrypts the received sequence and then correlates the two received sequences (i.e., the known pattern with the "decrypted" version). The sum of the correlation can be used as a soft decision to indicate the presence of the frame alignment sequence (FAS).A hard decision can then be used to make a more reliable decision to indicate the presence of the frame alignment sequence (FAS), as opposed to soft decision-based frame detectors that are commonly used.

[0069] The total FAS length in the frame detection section 32 of the frame header 24 of the frame 20 is 512 symbols and includes a pattern on one polarization followed by the second polarization (i.e., one after the other, as shown in Figure 2 in the frame detection section 32). The frame alignment sequence can be used to obtain an initial estimate of the MIMO tap weights. In fact, there are 128 known original symbols on each polarization. These symbols are encrypted and interleaved to form 256 FAS symbols (simultaneously, as shown in Figure 2 in the frame detection section 32) for each polarization.

[0070] As in Fig. As shown in Figure 12, as part of step 106, the frame detector at receiver 18 of hub node 14 deinterleaves odd and even symbols representing the original symbols S1 and scrambled symbols S2 (not all of which are labeled in the figure for clarity). The scrambled symbols are decoded by multiplying them with a scrambler sequence yielding D_syms. This data is further correlated with the original deinterleaved symbols (S_syms). The sum of the correlation (peak) can be used as a soft decision to indicate the presence of the FAS. This soft detection method is independent of state of polarization (SOP) and occurs without separating the X-pole and Y-pole.

[0071] Frame detection for access networks is the same as cross-correlating the incoming signal with the known frame alignment sequence (FAS) and detecting the correlation peak. However, these soft decisions become very unreliable when the incoming signal has some gain variation (e.g., ±1 dB). Transmitter power control and receiver automatic gain control (AGC) can minimize the power variations, although good gain tolerance improves the robustness of packet detection from geographically diverse leaf nodes 12. The strength of the correlation peak depends on the scale / power of the input signal. A packet 20 can be falsely detected simply by increasing the signal power so that noise or random correlations become large enough to trigger "packet detection" by increasing the correlation peak power beyond the detection threshold.This is called a false positive result. On the other hand, if the scale / power of the input signal becomes too small due to gain fluctuations, the correlation peak power becomes too low to exceed the detection threshold. "Packet detect" is not triggered. This is called a false negative result.

[0072] Fig. Figure 13 shows an example of Monte Carlo simulations for QPSK for the probability of detecting false / untrue frames at different decision thresholds. Left curves indicate a false negative result (no frame detected when the frame is present) and right curves indicate a false positive result (frame detected when no frame is present). The results for the gain variation of -1 dB were extrapolated to show that the probability of detecting false images is quite high (> 1e-3). More than 10 million simulations were performed for an SNR = 6 dB (FEC threshold for QPSK), phase noise (PN) = 600 kHz, frequency offset (FO) = 150 MHz, and polarization mixing (Pol. Red) = 45 degrees between X-Pol. & Y-Pol. It is worth noting that in a PON scenario, there can be 256,000 to 1 million packets in a single second, so packet detection must be extremely reliable.

[0073] Fig. Figure 13A shows an example of the probability of false image detection for a frame detection section length of 32 out of 512 symbols (2x2x128 encrypted and interleaved symbols on two polarizations). Numerical curves are obtained from analytical equations, and simulative curves are obtained by performing more than 35M Monte Carlo simulations with SOP, SNR of 6 dB, phase noise of 600 kHz, and laser frequency offset of 150 MHz. The experimental analysis was performed on more than 100 images, each with different polarization rotations.

[0074] For numerical analysis, the false positive probability can be calculated as the probability that the expected pattern appears randomly in the received data: Pfalse+ive=∑r=0nerr(Nr)Per(1−Pe)N−r where N and nerr = 128 (the original symbols in the frame detection section 32) and = 0.5 (equally probable). Please note that this is independent of any depreciation. e

[0075] A false negative probability would be: Pfalse+ive=∑r=0nerr(Nr)Per(1−P′e)N−r P′e For false negatives, the noise (6 dB SNR) and the polarization mix would be dependent. In particular, SOP rotations of 0 degrees represent the base case and 45 degrees the worst case, which determines the detection threshold. Fig. Figure 13A shows the two limits, with the experimental results lying in between. At a threshold of 105 symbols, a false detection occurs with a probability of about 10 -11 or about once every six days.

[0076] Fig. Figure 13B shows the probability of false detection for different lengths of symbols in the frame detection section 32 of frame 20. The “soft decisions” detection scheme (i.e., a gain variation of -1 dB, represented by a diamond point and a gain variation of 0 dB, represented by a square point in the diagram of Fig. 13B) misses frames every five ms or ten seconds. The "Hard Decisions" detection scheme is several orders of magnitude more robust, delivering a missing frame approximately every six days for the same length of the synchronization pattern. The use of the hard decision detector results in a high tolerance to gain variations, such as those observed in PON systems operating in burst mode 10. The frequency offset is within the tolerable range for frequency variations between bursts. To achieve reliable frame detection, the PON overlay method 100 uses frequency offset-tolerant hard decisions in addition to soft decisions, as in Fig. 14 shown.

[0077] The effect of a frequency offset is to rotate the correlated symbols by one phase. The tolerance to the frequency offset is a result of using consecutive correlated symbols for hard decisions, as shown in the table in Fig. 15. The table in Fig. Figure 15 shows the frequency offset (in MHz) translated into a rotation in degrees between consecutive symbols for 4GBaud.

[0078] Fig. 16A and Fig. 16B gives an example of a cross-correlation (XCorr) of received data with known FAS for an FO = 150MHz for QPSK. Fig. Figure 16A shows an example of XCorr between FAS symbols (true detection). The rotation can be seen for the correlated symbols, as shown in the table of Fig. 15. By setting a threshold for hard decisions at 'x>0' (see Fig. 14) and by making hard decisions symbol by symbol and summing them, reliable frame detection can be obtained. Varying signal power does not change the number of difficult decisions that are right / wrong. Fig. Figure 16B shows an example of XCorr for non-FAS data with known FAS. Hard decisions: The probability of a correct / false detection is about 50% for false detections.

[0079] Fig. Figure 17 gives an example of a numerical frame detection probability for a FAS length of 128 symbols (i.e., the original symbols in the frame detection section 32, Fig. 2) for both false positives and false negatives for a 16QAM system. By properly adjusting the threshold for hard decisions, the probability of detecting false frames can be reduced to approximately 1e-15.

[0080] In order to Fig. 3, step 108 of the PON overlay method 100 includes determining the polarization MIMO filter coefficients from the frame alignment sequence and aligning the phase between X-pole and Y-pole. Step 106 of the PON overlay method 100 may include equalizer startup and phase adjustment. To start the polarization MIMO filter for a coherent burst-mode receiver 18 of the hub node 14, a training sequence may be used that includes a pattern of a first polarization followed by a second polarization (i.e., one after the other, as in the frame detection section 32 of the frame header 24 of the frame header 20 in Fig. 2 shown).

[0081] This can be used for an initial estimate of the MIMO tap weights, between which any phase rotation can occur.

[0082] The training sequence can be followed by another known training sequence on both polarizations. This can resolve the phase shift between two polarizations (as in the equalizer section 34 of the frame header 24 of frame 20 in Fig. 2 shown).

[0083] By using the training sequences, the phase difference between the polarizations is resolved, allowing a single carrier phase estimator (CPE) to be used for both polarizations. This reduces the complexity of the CPE and improves tolerance to phase noise.

[0084] Due to the rapid acquisition required for burst mode detection, the equalizer taps must converge very quickly. This can be achieved by estimating the channel's Inverse Jones Matrix. After the inverse Jones matrix estimation (IJME) using the equalizer section 34 of frame header 24 of frame 20, as shown in Fig. 2, equalizer taps can be "jumped in" for faster convergence. However, these "jump-start" taps may cause different phase shifts in X-polarization and Y-polarization and would require a separate carrier phase estimation (CPE). To improve the accuracy of the phase noise estimation and enable the use of a single CPE estimator, additional training symbols (the first 64 symbols of the equalizer section 34 of the frame header 24 of frame 20, as shown in Fig. 2). The relative phase difference between X-pole and Y-pole can be calculated by multiplying X-pole and Y-pole symbols by the conjugate of known Y-pole symbols. rxvec=xr[n]∗conj(yr[n]) txvec=xt[n]∗conj(yt[n]) where rxvec and txvec are received and transmitted FAS on X-Pol (xr, x t ) or Y-Pol (yr, y t ) can be calculated.

[0085] The phase difference between the two polarizations can be calculated using: diff=angle∑n=063rxvec[n]∗conj(txvec[n])

[0086] After calculating the phase difference, the Y-pole taps of the LMS2x2 equalizer can be rotated to have the same rotation for both polarizations:

[0087] Since x t and y t known transmitted symbols, the conjugate of tx vec stored as a look-up table (LUT) to save power and complexity. Otherwise, the relative phase difference between X-pole and Y-pole can also be calculated by multiplying X-pole and Y-pole symbols by the conjugate of known X-pole and Y-pole symbols, respectively. rxvec=xr[n]∗conj(yr[n]) txvec=xt[n]∗conj(yt[n]) diff=angle∑n=063rxvec∗conj(txvec[n])=angle∑n=063xr[n]∗conj(yr[n])∗conj( xt[n]∗conj(yt[n]))=angle∑n=063xr[n]∗conj(xt[n])∗conj(yr[n]∗conj(yt[n]))

[0088] Fig. Figure 18A shows an example of a different rotation of X-pole and Y-pole after starting the equalizer taps for 16QAM. The phase is adjusted between the two polarizations (as in Fig. 18B) using the first 64 symbols of the equalizer section 34 of the frame header 24 of the frame 20 (as shown in 18B) (as shown in Fig. 2). This allows the estimated phase to be averaged between the two polarizations, improving the accuracy of the phase noise estimation and enabling the use of a single CPE estimator. The next symbols 256 and 64 of the equalizer section 34 of the frame header 24 can be used for more accurate convergence of equalizer taps and CPE frequency convergence, respectively.

[0089] Let us return to Fig. 3, step 110 of the PON overlay method 100 involves determining a reliable local oscillator signal Frequency Offset Estimate (FOE) using a local oscillator signal frequency recovery circuit (Lo-Sig). The phase vector between the received signal and the known FAS is calculated. The instantaneous frequency is calculated from the phase difference between consecutive phase vectors. The average frequency offset is calculated by averaging the instantaneous frequency offset over the FAS. Since the received symbols are already equalized after the IJME jump start, the frequency offset (FO) can be reliably estimated using the second part (256 symbols) of the equalizer section 34 of the frame header 24 of frame 20 (as in Fig. 2 shown): phs_vec[n]=rx[n]∗conj(tx[n]) FO=(BaudRate2π)angle(1N∑n=1Nphs_vec[n]∗conj(phs_vec[n−1])) where N = 256 and rx and tx are the received and known transmitted FAS symbols, respectively.

[0090] In addition, various FOE methods are available, such as detecting the frequency tone and / or performing FOE with maximum likelihood, which can be used.

[0091] Step 110 uses the FAS to determine the frequency offset of the signal burst from leaf node 12. This allows the FOE to be reliably estimated within the frequency offset range of ±Fs / 2 (Fs is the sampling rate). For example, Fig. 19A and Fig. Figure 19B shows the FOE accuracy for a 16QAM, 4 GBaud system with SNR = 12.5 dB (FEC threshold), PN = 600 kHz, and 45 degrees of polarization mixing between X-pole and Y-pole. Figure 19A illustrates the X-pole FO estimation, and Figure 19B the Y-pole FO estimation. Once the FOE is determined, it can be applied for correction. For example, as in Fig.As shown in Figure 1A, the FOE can be fed back to a matched filter for use in correction.

[0092] The following is a numbered list of non-limiting example illustrative sentences: Clause 1. A method comprising: receiving a signal burst from a leaf node in the passive optical network with a hub node of a passive optical network, the signal burst comprising a frame including a payload and a frame header, the frame header comprising a clock and gain control section, a frame detection section, and an equalizer section; retrieving a clock phase of the leaf node with the hub node from the clock and gain control section of the frame header; estimating the signal power of a signal burst from the leaf node in the passive optical network with the hub node; compensating for differences in the signal power of the signal burst from the leaf node with the hub node; detecting a frame alignment sequence indicating the arrival of the signal burst with the hub node;Determining MIMO (multiple input, multiple output) polarization filter coefficients from the frame alignment sequence with the hub node; aligning a phase between X-polarization and Y-polarization of the signal burst with the hub node using the MIMO polarization filter coefficients; and determining a local oscillator signal with the hub node Frequency Offset Estimate (FOE). Clause 2. The method according to Clause 1, comprising: applying the determined frequency offset estimate. Clause 2a. The method of Clause 2, wherein a matched filter is used when applying the determined frequency offset estimate. Clause 3. The method of any of clauses 1, 2, and 2a, where the frame header has a length of up to 480ns. Paragraph 3a. Methods in any of sentences 1, 2, 2a and 3, wherein the payload of the frame has a length of up to three microseconds. Clause 4. The method of any of clauses 1, 2, 2a, 3, and 3a, wherein the clock and gain control section is configured to contain up to 1024 symbols. Clause 5. The method of any of clauses 1 to 4, wherein the frame detection portion of the frame header is configured to contain up to 512 symbols. Clause 6. The method of any of clauses 1 to 5, wherein the frame detection portion of the frame includes information for the hub node to determine an existence of the frame coming to the hub node. Clause 7. The method of any of clauses 1 to 6, wherein the equalizer section of the frame header is configured to contain up to 384 symbols. Clause 8. The method according to any one of sentences 1 to 7, wherein the equalizer portion of the frame comprises a phase correction subsection; a subsection for the equalizer training phase and the frequency offset estimation; and a subsection for frequency convergence of the carrier phase estimator (CPE). Clause 9. The method of Clause 8, wherein the phase correction subsection is configured to contain up to sixty-four symbols, while the equalizer training phase subsection is configured to contain up to 256 symbols; and / or the frequency offset estimation and CPE frequency convergence subsection is configured to contain up to sixty-four symbols. Clause 10. The method of any one of clauses 1 to 9, wherein detecting the clock phase of the leaf node from the clock and gain control portion of the frame header with the hub node comprises a trace phase detector in the hub node that performs the following: locking the clock of the signal burst to a downstream signal from the hub node; and correlating the upper and lower sideband frequencies at a frequency offset of one baud rate for each polarization, then summing the resulting signals. Clause 11. The method of any one of clauses 1 to 10, wherein detecting the clock phase of the leaf node from the clock and gain control portion of the frame header with the hub node comprises a trace phase detector in the hub node that, upon detecting the signal burst, performs the following: entering fast tracking mode in which a clock loop filter is programmed for fast clock convergence and a clock loop is closed; detecting that the clock is locked; entering slow tracking mode in which the clock loop filter coefficients programmed for slow changes are used; and once the signal burst is complete, waiting for a second signal burst. Clause 12. The method of any one of clauses 1 to 11, wherein estimating the signal power of the signal burst from the leaf node with the hub node and compensating for differences in the signal power of the signal burst with the hub node comprises: setting the gain to a last known good gain value for the leaf node; measuring the signal power during a fast clock recovery mode after detecting the signal burst; adjusting the gain; switching to the slow tracking mode; measuring the signal power during the payload of the frame; and updating the gain value. Clause 13. The method of any of clauses 1 to 12, wherein detecting the frame alignment sequence indicating the arrival of the signal burst with the hub node comprises applying a frame detector comprising: deinterleaving and decoding a sequence of symbols in the frame detection section of the frame header; cross-correlating the symbol sequence with a known pattern of symbols; and using a sum of the cross-correlation as a soft decision to indicate the presence of a frame alignment sequence. Clause 14. The method of clauses 1 to 13, wherein determining the frequency offset estimate (FOE) of the local oscillator signal with the hub node uses a frequency recovery (Lo-Sig) circuit of the local oscillator signal configured to: calculate a phase vector between the signal burst and a known frame alignment sequence; calculate an instantaneous frequency from a phase difference between consecutive phase vectors; and calculate an average frequency offset by averaging the instantaneous frequency offset over the frame alignment sequence. Clause 15. A hub node of a passive optical network, the hub node comprising a Digital Signal Processing (DSP) chain configured to receive a signal burst from a leaf node in the passive optical network, the signal burst comprising a frame including a payload and a frame header, the frame header comprising a clock and gain control section and a frame detection section, and an equalizer section; retrieving a clock phase of the leaf node from the clock and gain control section of the frame header; estimating the signal strength of a signal burst from the leaf node in the passive optical network; compensating for differences in the signal power of the signal burst from the leaf node; detecting a frame alignment sequence indicating the arrival of the signal burst; determining multiple input, multiple output (MIMO) polarization filter coefficients from the frame alignment sequence;Align a phase between X-polarization and Y-polarization of the signal burst using the MIMO polarization filter coefficients; and determine the frequency offset estimate (FOE) of a local oscillator signal. Clause 15a. The hub node referred to in Clause 15, the hub node comprising a digital signal processing (DSP) chain configured to apply the determined frequency offset estimate. Clause 15b. A hub node as defined in Clause 15, wherein the DSP chain comprises a matched filter, and wherein the matched filter is used when applying the determined frequency offset estimate. Clause 16. The hub node of any of clauses 15, 15a, and 15b, wherein the equalizer portion of the frame comprises a phase correction subsection; a subsection for the equalizer training phase and frequency offset estimation; and a subsection for frequency convergence of the carrier phase estimator (CPE). Clause 16a. The hub node of Clause 16, wherein the phase correction subsection is configured to contain up to sixty-four symbols, while the equalizer training phase subsection is configured to contain up to 256 symbols; and / or the frequency offset estimation and CPE frequency convergence subsection is configured to contain up to sixty-four symbols. Clause 17. The hub node of any one of clauses 15 to 16, wherein the clock phase of the leaf node from the clock and gain control portion of the frame header comprises a trace phase detector configured to perform the following: locking the clock of the signal burst to a downstream signal from the hub node; and correlating the upper and lower sideband frequencies at a frequency offset of one baud rate for each polarization, then summing the resulting signals. Clause 18. The hub node of any of clauses 15 to 17, wherein the hub node comprises a trace phase detector configured to, for acquiring the clock phase of the leaf node from the clock and gain control portion of the frame header, upon detecting the signal burst: enter fast tracking mode, in which a clock loop filter is programmed for fast clock convergence and a clock loop is closed; detect that the clock is locked; enter slow tracking mode, in which the clock loop filter coefficients programmed for slow changes are used; and once the signal burst is complete, wait for a second signal burst. Clause 19. The hub node of any of clauses 15 to 18, wherein estimating the signal power of the signal burst from the leaf node and compensating for differences in the signal power of the signal burst comprises: setting the gain to a last known good gain value for the leaf node; measuring the signal power during a fast clock recovery mode after detecting the signal burst; adjusting the gain; switching to the slow tracking mode; measuring the signal power during the payload of the frame; and updating the gain value. Clause 20. The hub node of any of clauses 15 to 19, wherein the local oscillator signal Frequency Offset Estimate (FOE) determination uses a hub node local oscillator signal (Lo-Sig) frequency recovery circuit configured to: calculate a phase vector between the signal burst and a known frame alignment sequence; calculate an instantaneous frequency from a phase difference between consecutive phase vectors; and calculate an average frequency offset by averaging the instantaneous frequency offset over the frame alignment sequence. Clause 21. The hub node of any of clauses 15 to 20, where the frame header has a length of up to 480ns. Clause 22. The hub node of any of Clauses 15 to 21, where the frame payload has a length of up to three microseconds. Clause 23. The hub node of any of clauses 15 to 22, wherein the clock and gain control section is configured to contain up to 1024 symbols. Clause 24. The hub node of any of clauses 15 to 23, wherein the frame detection portion of the frame header is configured to contain up to 512 symbols. Clause 25. The hub node of any of clauses 15 to 24, wherein the frame detection portion of the frame includes information for the hub node to determine an existence of the frame coming to the hub node. Clause 26. The hub node of any of clauses 15 to 25, wherein the equalizer section of the frame header is configured to contain up to 384 symbols. Clause 27. A hub node of any of clauses 15 to 26, wherein detecting the frame alignment sequence indicating the arrival of the signal burst comprises applying a frame detector: deinterleaving and decoding a sequence of symbols in the frame detection section of the frame header; cross-correlating the symbol sequence with a known pattern of symbols; and using a sum of the cross-correlation as a soft decision to indicate the presence of a frame alignment sequence. CONCLUSION

[0093] Traditionally, there are problems in achieving coherent detection in the upstream burst-mode direction in passive optical networks. In accordance with the present disclosure, nodes and methods are disclosed that are configured to address the rapidly growing market of coherent passive optical networks (CPONs) for access networks to handle a significant increase in bandwidth demand. The disclosed systems, nodes, and methods provide fast and reliable frame detection for coherent passive optical networks.

[0094] The foregoing description is intended to be illustrative and descriptive, but is not exhaustive, and is intended to limit the inventive concepts to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be learned from practice of the methods presented in this disclosure.

[0095] Furthermore, while this has been described in the context of an optical network, this need not be the case. These embodiments can be applied to an electronic network using copper cables or even a wireless network.

[0096] Although certain combinations of features are listed in the claims and / or disclosed in the description, these combinations are not intended to limit the disclosure. Indeed, many of these features may be combined in ways not expressly listed in the claims and / or disclosed in the description. Although each dependent claim listed below may directly depend on only one other claim, the disclosure encompasses each dependent claim in combination with every other claim in the claim set and in the example clauses listed above.

[0097] No element, act, or instruction used in the present application should be construed as critical or essential to the invention unless it is expressly described as such outside the preferred embodiment. List of reference symbols 10 passive optical network (PON) 12 leaf nodes (ONU) 14 lifting nodes (OLT) 16 splinters 17 transmitters (Tx) 18 receivers (Rx) 19 digital signal processing chain (DSP) 20 frames 21 processor 22 payload 24 frame headers 30 Clock and gain control 32 frame capture 34 equalizers 40 X / Y phase correction 42 Frequency offset estimation 44 CPE Frequency Convergence 50 Clock recovery loop 52 FFT 54 Rx-CDEQ 56 Phase detector 58 loop fitters 60 Phase adjustment 62 IFFT 100 PON overlay methods 102 Detecting the clock phase 104 Estimation / compensation of leaf node signal power 106 Detect frame alignment sequence indicating the arrival of bursts 108 Determination of polarization MIMO filter coefficients from the frame alignment sequence and alignment of the phase between X-Pol & Y-Pol 110 Determining / Applying the Local Oscillator Signal Estimating the Frequency Offset 150 Waiting for signal 152 Burst detected 154 Fast Follow-up 156 Slow Tracking 170 Call up exploration 172 Setting the gain on LKG 174 bursts recorded 176 Start of performance measurement 178 Adjusting the gain of the clock tone or signal strength 180 Adjusting the payload signal power gain QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 20090245289

[0033]

Claims

[1] Hub node of a passive optical network, wherein the hub node comprises a DSP (Digital Signal Processing) chain configured to: Receiving a signal burst from a leaf node in the passive optical network, the signal burst comprising a frame including a payload and a frame header, the frame header comprising a clock and gain control section, a frame detection section, and an equalizer section; Retrieving a leaf node clock phase from the clock and gain control section of the frame header; Estimation of the signal strength of a signal burst from the leaf node in the passive optical network; Compensation for differences in the signal power of the signal burst from the leaf node; Detecting a frame alignment sequence indicating the arrival of the signal burst; Determination of MIMO (multiple input, multiple output) polarization filter coefficients from the frame alignment sequence; Aligning a phase between X-polarization and Y-polarization of the signal burst using the MIMO polarization filter coefficients; and Determine the frequency offset estimate (FOE) of a local oscillator signal. [2] The hub node of claim 1, wherein the hub node comprises a digital signal processing (DSP) chain configured to apply the determined frequency offset estimate. [3] The hub node of claim 1 or 2, wherein the DSP chain comprises a matched filter, and wherein applying the determined frequency offset estimate uses the matched filter. [4] Hub node according to one of the preceding claims, wherein the frame header has a length of up to 480ns. [5] Hub node according to one of the preceding claims, wherein the payload of the frame has a length of up to three microseconds. [6] A hub node according to any preceding claim, wherein the clock and gain control section is configured to contain up to 1024 symbols. [7] A hub node according to any preceding claim, wherein the frame detection portion of the frame header is configured to contain up to 512 symbols. [8] A hub node according to any preceding claim, wherein the frame detection portion of the frame includes information for the hub node to determine an existence of the frame coming to the hub node. [9] A hub node according to any preceding claim, wherein the equalizer portion of the frame header is configured to contain up to 384 symbols. [10] A hub node according to any preceding claim, wherein the equalizer portion of the frame comprises a phase correction subsection; a subsection for the equalizer training phase and the estimation of the frequency offset; and a subsection for frequency convergence of the carrier phase estimator (CPE). [11] The hub node of claims 1 to 9, wherein the equalizer portion of the frame comprises a phase correction subsection; a subsection for the equalizer training phase and the frequency offset estimation; and a subsection for the frequency convergence of the carrier phase estimator (CPE), wherein the phase correction subsection is configured to contain up to sixty-four symbols, the equalizer training phase subsection is configured to contain up to 256 symbols, and the frequency offset estimation and CPE frequency convergence subsection is configured to contain up to sixty-four symbols. [12] A hub node according to any preceding claim, wherein the clock phase of the leaf node from the clock and gain control section of the frame header comprises a trace phase detector configured to perform the following: Locking the timing of the signal burst to a downstream signal from the hub node; and Correlating the upper and lower sideband frequencies with a frequency offset of one baud rate for each polarization and then summing the resulting signals. [13] The hub node of any preceding claim, wherein the hub node comprises a trace phase detector configured to detect the clock phase of the leaf node from the clock and gain control portion of the frame header after detecting the signal burst: Switch to Fast Tracking mode, in which a clock loop filter is programmed for fast clock convergence and a clock loop is closed; Detect that the watch is locked; Switch to slow-tracking mode, which uses the clock loop filter coefficients programmed for slow changes; and Once the signal burst is complete, wait for a second signal burst. [14] A hub node according to any preceding claim, wherein estimating the signal power of the signal burst from the leaf node and compensating for differences in the signal power of the signal burst comprises: Setting the gain to a last known good gain value for the leaf node; Measuring the signal power during a fast clock recovery mode after signal break detection; Adjusting the gain; switch to slow tracking mode; Measuring the signal power during the payload of the frame; and Updating the gain value. [15] A hub node according to any preceding claim, wherein detecting the frame alignment sequence indicating the arrival of the signal burst with the hub node comprises using a frame detector to: De-interleaving and decoding a symbol sequence in the frame detection section of the frame header; Cross-correlation of the symbol sequence with a known pattern of symbols; and Use the sum of the cross-correlation as a soft decision to indicate the presence of a frame alignment sequence. [16] Hub node according to one of the preceding claims, wherein a frequency recovery circuit of the hub node for a local oscillator signal (Lo-Sig) is used to determine the local oscillator signal Frequency Offset Estimate (FOE), which is configured for: Calculating a phase vector between the signal burst and a known frame alignment sequence; Calculating an instantaneous frequency from a phase difference between successive phase vectors; and Calculate an average frequency offset by averaging the instantaneous frequency offset over the frame alignment sequence.

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