Automatic test system for an actuator

Abstract

Automatic testing system for an actuator, characterized in that it comprises a first unit and a second unit; wherein the first unit comprises a D / MA function block, an OR function block, an RSFLP function block and a DI function block and is used to perform a pre-test reset to initialize and reset the system state before starting the test; wherein the second unit comprises a TIMER function block, an AND function block, a NOT function block and a DO function block, wherein the second unit contains three types of branches including opening a sampling valve, opening a flushing water valve and opening a blowdown valve, wherein the second unit serves to automatically check the state of an actuator; and wherein the first unit can be connected to a plurality of branches of the second unit and can realize the control by setting a delay mode for the TIMER function block.

Description

TECHNICAL FIELDThe present invention relates to the technical field of automatic testing of an actuator, and more specifically to an automatic testing system for an actuator.PRIOR ARTIn modern thermal power plants, the control of the technological process is usually implemented by electrical, pneumatic or hydraulic actuators which serve to regulate the direction and the flow rate of various media in technological processes. Electric, pneumatic and hydraulic actuators differ only in their energy sources, which are respectively electric drive, compressed air drive and hydraulic drive. However, with regard to their mode of operation, they fulfil the same task: they act on valves in order to open or close them, thus making it possible to pass through or shut off the process medium on both sides of the valve.In practical application, it frequently happens that actuators cannot be opened or closed properly due to energy loss, malfunctions of the control elements or jamming in the valve body. If such errors are not detected in time, this may result in the process medium on both sides of the valve becoming out of control. Once the process medium is out of control, the entire technological process may be disturbed, which in the worst case leads to a standstill of the entire production process and causes considerable economic losses and risks for personal safety.CONTENT OF THE PRESENT INVENTIONIn view of the above problem, the present invention is proposed.Therefore, the object of the present invention is to propose an automatic test program for an actuator, wherein an automatic check of the opening and closing functions can be carried out via the automatic test program before or during the use of an actuator. When an abnormality is detected in the opening or closing function, the automatic check program issues an alarm to notify the operator to correct the fault in time and restore the normal control function of the actuator.Compared to traditional manual checking by the operator, the actuator automatic checking program provided in this patent allows button press checking. It is sufficient that the operator in the control system instructs the automatic test program to perform the operation and test of the actuator according to the preset steps. Only when all test parts pass does the automatic test program issue a signal confirming the normal state of the actuator. If a test part fails, the automatic test program issues an alarm.The automatic test program for an actuator can carry out a functional self-check of the actuator, as a result of which faults can be detected and corrected at an early stage. This prevents damage to the entire production process system caused by actuator failures and ensures safety and reliability of the continuous production system operation.According to the present invention, the object is achieved by the following technical solution: an automatic test system for an actuator comprises a first unit and a second unit. The first unit includes a D / MA function block, an OR function block, an RSFLP function block, and a DI function block, and is for performing a reset before a test to initialize and reset the system state before the test starts.The second unit includes a TIMER function block, an AND function block, an NOT function block, and a DO function block. The second unit includes three types of branches including opening a sampling valve, opening a flushing water valve, and opening a sludge valve. The second unit serves for automatically checking the state of an actuator.The first unit may be connected to a plurality of branches of the second unit and may realize control by setting a delay mode for the TIMER function block.As a preferred embodiment of the automatic test system for an actuator according to the invention, it is provided that the first unit comprises: receiving an external operating instruction from DCS via the D / MA function block, monitoring the state of a digital input signal via the DI function block, logically assessing a plurality of input signals via the OR function block in order to determine whether a reset is to be triggered, and implementing a reset logic via the RSFLP function block in order to reset the system state and ensure that the system is in the initialization state after the reset.The second unit includes transmitting a start signal from the first unit, transmitting a control signal via the TIMER function block to drive a target actuator to operate, and judging the state of the actuator via the logical function blocks AND and NOT to ensure correctness of an action being performed. As a preferred embodiment of the automatic test system for an actuator according to the invention, it is provided that the first unit comprises the following: the function blocks of the first unit fulfil the following tasks: the D / MA function block serves as a starting point for the human-machine interaction, receives a command signal for starting the test from the operator, receives an external operating instruction via DCS and outputs the operating instruction as a signal to a subsequent module.The DI function block monitors important switching signals in the system to determine whether the system is currently to be reset, receives and outputs an external digital signal, where 0 means no signal and 1 means the presence of a signal.The OR function block performs an OR logic judgment of an input signal, triggers a reset when one of the input signals is 1, inputs two signals output from the DI function block and the D / MA function block, respectively, and outputs the result of the OR logic judgment to a set terminal S of the RSFLP function block.The RSFLP function block resets the system based on a set and a reset signal, maintains the state after the reset, and inputs the reset signal R and the set signal S, the reset signal R is triggered by an external reset command of the system to forcibly clear all the output signals, and the set signal S is triggered by the output of the OR function block, the set signal triggers a reset when a condition is satisfied, and an output signal indicating the reset state of the system is output, the output of 1 indicating a completed reset.As a preferred embodiment of the automatic test system for an actuator according to the invention, it is provided that the second unit comprises the following: the function blocks of the second unit fulfil the following tasks: the DO function block transmits a signal to the actuator in order to trigger its execution of a corresponding action and, upon signal triggering, outputs the signal D=1; a hardware device starts to execute the action after receiving the signal.The TIMER function block is used for time-related processing of the input signal and outputs a control signal including pulse mode, delay mode and timer mode based on a set time function.The AND function block performs an AND logic operation on two input signals Z 1 and Z 2, outputs the signal D=1 only when both the first signal Z 1 and the second signal Z 2 are 1, and outputs the signal 0 when one of the input signals is 0.The NOT function block performs a NOT logic operation on the input signal Z, outputs the signal D=0 when the input signal Z=1 and outputs the signal D=1 when the input signal Z=0.As a preferred embodiment of the automatic test system for an actuator according to the invention, it is provided that the opening of the sampling valve comprises the following: in the first unit, an instruction for starting the test is input via the DCS system, the D / MA function block receives the instruction and then outputs on its right side the signal D, which is transmitted to the OR function block and an S input terminal of RSFLP.At the same time, the DI function block monitors the external digital input signal. If the digital signal is valid, the DI function block outputs the signal D=1 and transmits it to a Z2 input terminal of the OR function block.The OR function block performs a logical operation on the signal Z1 from the D / MA function block and the signal Z2 from the DI function block. If one of the signals is 1, the OR function block outputs the signal D=1 and transmits it to an S input terminal of the RSFLP function block.The RSFLP function block receives a signal from the OR function block and thereafter outputs a signal to a D-pin. A signal of 1 at the D pin indicates that the test system is started. The D signal is transmitted to the TIMER function block of the second unit to start the automatic sampling valve check process.In the second unit, an S input terminal of the TIMER function block of the second unit receives the signal D=1 from the D pin of the RSFLP function block of the first unit, and the TIMER function block is set to the delay mode upon receiving the S signal. The output signal D=1 is triggered and continues for a duration of 3 seconds. The output signal is communicated to the sampling valve to drive the sampling valve to open.The state of the sampling valve is monitored in real time by the DI function block. If the sampling valve is successfully opened, the DI function block outputs the signal D=1 and transmits it to the AND function block.Simultaneously, the AND function block receives a sampling valve action completion signal. If both signals are 1, the AND function block outputs the signal D=1 to indicate that the sampling valve is normally open.If the sampling valve is not opened successfully, the DI function block outputs the signal D=0 and transmits this to the NOT function block. The NOT function block inverts D=0 to D=1 to indicate that the valve is not normally open.A computer device comprises a memory and a processor, wherein a computer program is stored on the memory, wherein the processor realizes the steps of the system described above when executing the computer program.A computer readable storage medium having stored thereon a computer program that, when executed by a processor, implements the steps of the above-described system.Advantageous effects of the invention: The automatic test program for an actuator is distinguished by the following advantages:The entire test process does not require manual intervention. The operator only needs to start the program, whereupon the entire checking process from opening to closing can be automatically executed to check whether the actuator is in a normal working state.In the event of an unexpected incident, the operating personnel can manually intervene in the checking process and stop this emergency in order to prevent the incident from spreading.The test process can automatically check multiple actuators simultaneously, without limiting the number or type of actuators and whether they are shift or regulation actuators. This allows wide applicability and good adaptability in numerous sectors.This greatly reduces the workload of the personnel and increases the work efficiency.In important production phases, the actuator automatic test program proposed in this patent can be used to prevent production interruptions due to actuator errors and to increase the safety and reliability of the production system.Therefore, this patent is suitable for large area use in all producing companies that use actuators.BRIEF DESCRIPTION OF THE DRAWINGSIn order to better explain the technical solutions in the embodiments according to the present invention, the accompanying drawings used in the embodiments will be briefly described below, it being understood that the following drawings represent only some embodiments of the invention and it is possible for those skilled in the art to obtain further drawings without inventive operations from such drawings. Shown therein are: FIG. 1 is an overall diagram of an automatic test program for an actuator for an automatic test system for an actuator according to a first embodiment of the present invention; FIG. 2 is a diagram showing the D / MA function block of the actuator automatic test system according to the first embodiment of the present invention; FIG. 3 is a diagram showing the DI function block of the actuator automatic test system according to the first embodiment of the present invention; FIG. 4 is a diagram showing the DO function block of the actuator automatic test system according to the first embodiment of the present invention; FIG. 5 is a diagram showing the OR function block of the automatic test system for an actuator according to the first embodiment of the present invention; FIG. 6 is a diagram showing the RSFLP function block of the actuator automatic test system according to the first embodiment of the present invention; FIG. 7 is a diagram showing the TIMER function block of the actuator automatic test system according to the first embodiment of the present invention; FIG. 8 is a diagram showing the AND function block of the automatic test system for an actuator according to the first embodiment of the present invention; FIG. 9 is a diagram showing the NOT function block of the actuator automatic test system according to the first embodiment of the present invention.DETAILED DESCRIPTIONIn order to provide a better understanding of the above objects, features and advantages of the present invention, specific embodiments of the invention will be described in more detail below with reference to the accompanying drawings of the specification. It is understood that the described embodiments represent only some of the embodiments instead of all embodiments of the invention. All other embodiments obtained by persons skilled in the art from the embodiments of the invention without inventive activity should also be included within the scope of protection of the invention.First Embodiment: Reference is made to Figures 1-9, which shows an embodiment of the present invention that provides an automatic test system for an actuator, comprising:The present patent discloses an automatic test program for an actuator, which is based mainly on a DCS (distributed control system) as shown in FIG. 1, and uses some of the functional blocks of the DCS system to realize the automatic test function by combining them. The individual function blocks fulfil the following tasks:The D / MA function block as shown in FIG. 2 serves for human-machine interaction. The left input side provides two functions, namely TR (force trace value) and TS (force trace switch), which are not used in this example, however, and therefore will not be explained further. The right output side is used for the output of instructions. In this example, the D / MA function block issues an instruction when the operator issues an operation instruction on a DCS (Distributed Control System) display interface. It does not have any further additional functions.The DI function block as shown in FIG. 3 stands for digital input, namely digital (switching) input. Its symbol is a regular hexagon. If there is a connection on the right, this is a DI function block; if there is a connection on the left, this is a DO function block. For the DCS system, the received and controlled signals are mainly divided into two types: analog signals and switching signals. Analog signals are any number (which may include decimal places), e.g. 3, 2 or 120. Switching signals (digital signals) have only two states: 0 and 1. If there is no signal or instruction, the state is 0; if there is a signal or instruction, the state is 1. In this example, the DI function block outputs the state 1 when the required switching signal is triggered, i.e., there is an output. Otherwise, the DI function block does not output.The DO function block as shown in FIG. 4 stands for digital output, namely digital (switching) output. Its symbol is identical to that of the DI function block, but the link is on the left to transmit signals to the outside. When an instruction is issued on the left side, the DO function block causes a hardware device to execute an appropriate action, thus realizing the control function. The OR function block as shown in Fig. 5 corresponds to the "OR" function. This function block has two inputs, Z1 and Z2, on the left and one output, D, on the right. Its algorithm is: D=Z1+Z2. The OR function block can only accept switching inputs. That is, each input of the OR function block has only two states, namely 0 (no signal) and 1 (signal present). The output is also a switching signal. When either Z1 or Z2 is triggered, the output D outputs the value 1. When neither Z1 nor Z2 is triggered, the output D outputs the value 0.The RSFLP function block as shown in Fig. 6 is an RS trigger. The RS trigger has two inputs, namely R and S. Here, R is reset and S is set. Furthermore, the RS trigger has two outputs, namely D and D1 (D1 is the inverted signal of D, i.e., when D outputs an output, D1 does not output an output. When D does not output, D1 outputs an output. Since D1 is not used in this example, it will not be explained further). The specific functions of the RS trigger are as follows: If a signal is present at the input S, then the output D triggers a signal output. When a signal is applied to the input terminal R, all the signals are reset and the output terminal D forcibly outputs 0. That is, no signal is outputted. For input S and input R, input R has a higher priority. That is, when a signal is applied to R, the output D does not output regardless of the presence of the signal S. That is, the state of D corresponds to 0. When no signal is present at R, the output of D depends on the state of S. It should also be noted that in the RS trigger D a signal is output once the input S appears. The output signal of D still remains activated even if the signal at S disappears later. Only when the input R is triggered does D stop outputting. When the signal at the input R disappears, the state of D again depends on the state of S.The TIMER function block as shown in FIG. 7 is a time function block. This function block has three inputs on the left side, namely S, R and DT, and two outputs on the right side, namely dt and D. The input S is used for connection to an input signal. When a signal is present, it is processed according to the selected time function and output via the D-pin on the right side. The input R serves to reset the signal at the input S. Since this function is not used in this example, a more detailed explanation is omitted. The input DT serves to set the signal processing time. The output D serves to output the processing result. The output dt serves for the counting function. Since the function dt is not used in this example, a detailed explanation will be omitted. Three time processing techniques are available for the input function block, all of which are used in this example: the first processing technique is a pulse function. That is, pulses are displayed under the TIMER function block. The pulse function serves to trigger the output D when the input S is triggered. However, the input D is only triggered for one pulse cycle (the value of the input DT). After this cycle, the output D is deactivated. The second processing method is a delay function. That is, under the TIMER function block, TD_ON is displayed. In the delay function, it is provided that when S is triggered, the output D is not triggered immediately, but only after a delay cycle (the value of the input DT). Thereafter, the output D depends on the state of S. The third processing method is a timer function. That is, "Timing" is displayed under TIMER. In the timer function, it is provided that when the input S is triggered, the output D is triggered only for one timer cycle (the value of the input DT). After this cycle, the output D is deactivated. (It should be further noted that the difference between the pulse function and the timer function is the judgment of the signal of the input S. For the pulse function, when the duration of the S signal is longer than the set pulse cycle, the output D is maintained within the pulse cycle. If the duration of the S signal is shorter than the set pulse cycle, the output D disappears immediately as soon as the S signal disappears without being retained for the entire pulse cycle. The timer function, on the other hand, does not evaluate the duration of the input signal S. As soon as the input signal S occurs briefly, the output D outputs an output during the timer cycle, regardless of the state in which the S signal is located thereafter.The AND function block as shown in Fig. 8 is an "AND" function. This function block has two inputs, Z1 and Z2, on the left and one output, D, on the right. Its algorithm is: D=Z1*Z2. The AND function block accepts only switching inputs, i.e., each input has only two states: 0 (no signal) and 1 (signal present). The output is also a switching signal. The output is only output when both Z1 and Z2 are 1 (i.e., when both Z1 and Z2 are enabled). If one of the signals is not triggered, the output is not triggered.The NOT function block as shown in FIG. 9 is a "NOT" function. This function block has an input, Z, on the left and an output, D, on the right. When the input Z is triggered, the output D is not triggered, which corresponds to 0. If the input Z is not triggered, the output D is triggered, which corresponds to 1.The complete sequence of the automatic test program is as follows (executed from left to right): First, the operating personnel issue an instruction for automatic testing, which is transmitted to the DCS system. Then, a D pin of function block 1:10 in the upper left corner of FIG. 1 outputs an output which is provided to an input S terminal of 77:770. During normal operation, no signal is present at the R pin of 77:770 (the RS trigger), so no signals are reset. As soon as the S signal occurs, the D signal is triggered. (When the D signal is triggered, the signal is passed to 9 function blocks. In this example, 3 actuators are simultaneously checked, so the D signal is passed on to 9 function blocks. If only one actuator is checked, the D signal only needs to be passed on to 3 function blocks. In this example, only the automatic sampling valve test program will be explained. The programs for the flushing water valve and the sludge valve are identical and will therefore not be described in more detail. Therefore, after the output of the D pin of the function block 77:770 in this example, only the three connections 5:50, 10:100, and 23:230 among the nine connected function blocks will be explained. Other compounds will not be explained further). Once the D pin of function block 77:770 outputs a signal, the three function blocks 5:50, 10:100, and 23:230 receive the signal and begin signal processing. Upon receipt of the signal, function block 5:50 outputs a three second pulse signal (since the pulse function is set for function block 5:50 as previously described in the explanation of the TIMER function block). This signal is passed directly to the sampling valve, so that the sampling valve opens. Thus, the entire flow of this branch is completed.In function block 10:100, its Z1 pin has already received a signal when function block 77:770 has output a signal. Since function block 10:100 is an AND function block, both inputs, Z1 and Z2, must simultaneously receive a signal to allow an output to be output. Therefore, the function block 10:100 waits for the arrival of the Z2 signal. After the instruction for opening the sampling valve has been issued in the first step, the sampling valve opens if it functions correctly. Once the valve is open, it sends a signal to the Z2 pin of function block 10:100 to indicate that the sampling valve is open. When the Z2 pin receives this signal indicating that the sampling valve is open, the conditions for triggering function block 10:100 are met and it outputs a signal on its D pin. The output signal of the D pin of the function block 10:100 is simultaneously forwarded to two further function blocks. First, function block 9:90 receives the signal, after which it outputs a continuous signal at its D pin (since the TD_ON function is set for function block 9:90, as described previously in the explanation of the TIMER function block). This signal is passed to function block 6:60 whereupon a three second pulse signal is output at the D pin of function block 6:60 (since the pulse function is set for function block 6:60 as previously described in the explanation of the TIMER function block). After the outputs by the D pin of function block 6:60, an instruction to close the sampling valve is issued. If the sampling valve is functioning properly, it performs the closing operation as soon as it receives the instruction. Thus, this flow is completed.Further, after the signal is output, the D-pin of the function block 10:100 simultaneously sends signals to two function blocks. One of the two function blocks that receive the signals is 9:90 (this process has already been explained above) and the other is 16:160. When function block 16:160 receives the signal, it outputs a continuous signal at its D pin for 60 seconds (since the TD_ON function is set for function block 16:160 as previously described in the explanation of the TIMER function block). After the expiration of the duration of 60 seconds, the D pin no longer outputs a signal regardless of the initial state of the S pin of the function block 16:160. The output of function block 16:160 is sent to function block 19:190. Function block 19:190 is an AND function block that outputs an output on its D-pin only when both Z1 and Z2 are triggered simultaneously. Therefore, function block 19:190 does not immediately output when the D pin of function block 16:160 outputs an output to the Z1 pin of function block 19:190. Instead, it waits for the arrival of the Z2 signal. In the previous process, the instruction to close the sampling valve has been issued. If the sampling valve is properly closing, a signal is sent to the Z2 pin of function block 19:190 to indicate that the valve is closed. Once the Z2 pin receives this signal, the conditions for the initiation of function block 19:190 are met and its D pin outputs a signal to the S pin of function block 20:200. If the S pin of function block 20:200 receives the signal and no signal is present at the R pin, the D pin of function block 20:200 outputs a continuous signal (function block 20:200 has already been explained above). The output of the D pin of function block 20:200 is passed to function block 74:740. The function block 74:740 is operable to send the result of the entire test process to a display interface. This notifies the operating personnel that the test process has been completed and the result is normal.It should be noted that two aspects have not yet been explained throughout the program flow. One of these relates to function blocks 78:780, 80:800 and 82:820. These three blocks are used to reset the test program. If unexpected or uncontrollable events occur during the test program, the operator can manually end the test program by operating the function block 80:800 on the display interface (the operation of this function block has already been explained above). When function block 80:800 receives the operator's operating instruction, it outputs a signal on its D pin which is passed to function block 82:820. Function block 82:820 is an OR function block. When one of its inputs, Z1 or Z2, receives the signal, a signal is output at its D pin. This signal is sent to an R terminal of function block 77:770 to reset the entire test program (function block 77:770 has been discussed above). This ends the automatic test program. Furthermore, it is provided that even when executing other programs (e.g. when a signal for starting a measurement process is triggered), the automatic test process can be reset via the function block 82:820 in order to prevent the automatic test process from interfering with the measurement process.A further aspect, not explained, relates to the function block 23:230. During execution of the automatic test program, the D-pin of function block 77:770 continuously outputs a signal. Therefore, the Z pin of function block 23:230 continuously receives a signal. If the automatic test program is interrupted or a new automatic test operation is started manually, the D pin of function block 77:770 ceases to output a signal. In this case, the Z pin of the function block 23:230 no longer receives a signal and its D pin outputs a signal (the function block 23:230 has already been explained above). This signal, after being output, is sent to an R terminal of function block 20:200 to reset it. This resets the result of the current test operation and prepares the system for the next automatic test operation.The entire test program can be divided into four parts. The first part comprises the area for start and interrupt actions and consists of the function blocks 1:10, 77:770, 78:780, 80:800 and 82:820 on the left-hand side of Fig. 1.The second part is provided for automatic sampling valve testing and consists of function blocks 5:50, 68:680, 62:620, 10:100, 9:90, 6:60, 69:690, 23:230, 64:640, 16:160, 19:190, 20:200 and 74:740 in the upper right corner of Figure 1.The third part is provided for automatic check of the flushing water valve and consists of the function blocks 24:240, 70:700, 63:630, 29:290, 28:280, 25:250, 71:710, 42:420, 65:650, 35:350, 38:380, 39:390 and 75:750 in the middle of the right-hand side of FIG. 1. (Since the flushing water valve and the sampling valve are both actuators and the test process is identical, explanation about the flushing water valve is omitted herein.)The fourth part is provided for automatic inspection of the sludge valve and consists of the function blocks 43:430, 72:720, 67:670, 48:480, 47:470, 44:440, 73:730, 61:610, 66:660, 54:540, 57:570, 58:580 and 76:760 on the lower right side of FIG. 1. (The entire automatic test program simultaneously performs the test of the three actuators, namely, sampling valve, flushing water valve and sludge valve. Since the test programs for all three actuators are identical, only the test of the sampling valve will be described in detail.)The actuator automatic test program described in this patent can be summarized as follows: First, an instruction is given to start the automatic test. Then, the automatic test program starts running. In the first step, the actuator is automatically opened. After opening, the actuator is automatically closed. If the actuator is properly closing, this indicates that the actuator can properly open and close and function properly. Subsequently, a signal confirming the normal state of the actuator is outputted. The entire process is automatically performed. Should a step fail, no positive result is output. In this way, the automatic test function for the actuators is realized.The computing device may be a server. This computing device includes a processor, a memory, an input / output (I / O) interface, and a communication interface. Here, the processor, the memory, and the input / output interface are connected via a system bus. The communication interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computing device includes a non-volatile storage medium and an internal memory. The non-transitory storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the execution of the operating system and the computer programs from the non-volatile storage medium. The database of the computer device is used for storing data cluster data of a stream monitoring system. The input / output interface of the computing device is for exchanging information between the processor and external devices. The communication interface of the computing device is for communication with external terminals via a network connection. The computer program, when executed by the processor, implements an automatic test system for an actuator.One of ordinary skill in the art can understand that all or some of the processes in the method according to the above embodiments can be realized under control of a computer program by the related hardware, and the computer program can be stored in a non-transitory computer readable storage medium. When executed, the computer program may include the processes of the above method examples. Herein, any reference to a memory, database, or other medium in each embodiment of the present application may include at least one of the memories of nonvolatile and volatile memories. The nonvolatile memory may include a read-only memory (ROM), a magnetic tape, a floppy disk, a flash memory, an optical memory, a high-density embedded nonvolatile memory, a resistive random access memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a graphene memory, etc. The volatile memory may include, among other things, random access memory (RAM) or an external cache. By way of illustration and not limitation, RAM may be in various forms. For example, a static random access memory (SRAM) or a dynamic random access memory (DRAM), etc. are conceivable. The databases mentioned in the various embodiments of the present application may include at least one of the types of relational databases and non-relational databases. Non-relational databases may include, but are not limited to, blockchain-based distributed databases, among others. The processors mentioned in the individual embodiments of the present application may include, but are not limited to, general processors, central processing units, graphics processors, digital signal processors, programmable logic devices, and quantum computing logic devices.Second Embodiment: This embodiment of the present invention provides an automatic test system for an actuator. In order to verify the advantageous effects of the invention, scientific verification was carried out by simulation experiments.In order to verify the effectiveness of an automatic test system for an actuator in practical use, an automatic test experiment was carried out on actuators of a thermal power plant in the present exemplary embodiment. The results were compared with a conventional manual test method.Actuator type: Electric actuator (for controlling the closing and opening of valves).Experimental environment: Simulated operating environment of a thermal power plant comprising three kinds of valves, namely sampling valve, flushing water valve and sludge valve.The experimental equipment comprises:an automatic test system: an automatic test system is used for this purpose for an actuator, which comprises a first unit and a second unit, which are respectively responsible for resetting and testing.A conventional test system is provided which manually monitors the opening and closing of the valves by the operator and records each execution and the time for the error recovery.Implementation Process of the Test System According to the Invention:(1) inputting an instruction for starting the test through the D / MA function block, starting the automatic test program, and completing a reset before the test by the system.(2) Monitoring the valve state by the first unit, determining by the DI function block whether reset is required, determining the reset conditions by the OR function block, and generating a reset signal by the RSFLP function block.(3) Start of the test program of the second unit after the system resets and controls the sampling valve, the flushing water valve and the sludge valve one after another.Sampling Valve Check: The system outputs a 3 second pulse signal via the TIMER function block to control the sampling valve to open, and the AND function block asserts the completed action signal.Check of the flush water valve: Control by the TIMER function block in the 5 second delay mode to ensure proper delay of the action of the valve.Check of the sludge removal valve: Time-controlled control by the TIMER function block in the timer mode for 10 seconds and confirmation of the completed closing process by status feedback.(4) The entire test process records state feedback and execution times in real time and automatically generates a report.Implementation Process in the Related Art:(1) The operator manually sends opening and closing instructions via the distributed control system (DCS) to successively control the sampling valve, the flushing water valve and the sludge valve.(2) The operator monitors the action state of the actuators to confirm whether the action is complete.(3) If an action fails or anomalies occur, the operator manually searches for the cause and makes new attempts.(4) The entire process is recorded manually and no real time feedback or automatic fault analysis function is available.The result of the test is shown in Table 1. Table 1. Table 1.First TestAutomatic Test System3,25,110,300Manual Check6,57,215,41510Second TestAutomatic Test System3,04,910,000Manual Check6,77,014,81812Third TestAutomatic Test System3,15,010,100Manual Check7,06,815,0128Fourth TestAutomatic Test System3,35,210,400Manual Check6,97,314,91614Average increase rate of the test efficiency nz-54%30%40%--From the above experimental data, it can be clearly seen that the automatic test system according to the invention has considerable advantages in relation to the test efficiency of the actuators and the error recovery capability compared to the prior art. Detailed analysis is performed below:The time required for the automatic test system to test a single actuator (e.g., 3.2 seconds for the sampling valve) is significantly shorter than for manual testing (6.5 seconds). This corresponds to a time saving of about 54%. The test efficiency for the flushing water valve and the sludge valve was increased by 30% and 40%, respectively, which enables a quick and reliable action test.The automatic test system detects state signals in real time during the test process and detects errors immediately. For example, in several attempts, a fault within 0 seconds was detected by the system and an alarm was triggered, while the manual check required 12-18 seconds to detect the fault. The recovery time is 0 seconds, indicating that the automatic system enables seamless transition through reset logic and real-time feedback. On the other hand, manual checking takes an additional 8-14 seconds for manual debugging and re-trial.In manual checking, inaccurate assessments or recording errors by the operator may result in variations in results. The automatic system, on the other hand, ensures automated assessment of actions and states by function blocks, which ensures the accuracy of the test results.In the tests, the automatic system exhibits stable performance even when a plurality of actuators are simultaneously tested. In manual testing, the increased complexity results in longer test times (e.g., up to 15.4 seconds for the mud valve). The automatic system may meet the real-time test requirements of various actuators, which increases the generality of the system.The experimental data clearly show that the automatic test system for an actuator according to the invention solves the problems in the prior art, namely slow test speed, time-consuming error correction and susceptibility to human errors. It provides a more efficient, reliable and more intelligent solution for testing an actuator and has broad application possibilities and considerable technical advantages in the field of industrial automation.It should be noted that the above embodiments are merely for explaining the technical configurations of the invention, without limiting the same. Although the invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions of the technical forms of the invention are possible without departing from the spirit and scope of the technical forms of the invention and should be included in the scope of the claims of the invention.

Claims

An automatic test system for an actuator, characterized in that it comprises a first unit and a second unit; wherein the first unit comprises a D / MA function block, an OR function block, an RSFLP function block and a DI function block and is for performing a reset before a test to initialize and reset the system state before the start of the test; wherein the second unit comprises a TIMER function block, an AND function block, an NOT function block and a DO function block, wherein the second unit includes three types of branches including opening a sampling valve, opening a flushing water valve and opening a desludging valve, wherein the second unit is for automatically checking the state of an actuator; and wherein the first unit is connected to a plurality of branches of the second unit, and can realize control by setting a delay mode for the TIMER function block.The automatic test system for an actuator of claim 1, characterized in that the first unit comprises: receiving an external operating instruction from DCS via the D / MA function block; monitoring the state of a digital input signal via the DI function block; logically judging multiple input signals via the OR function block to determine whether to trigger a reset; and implementing reset logic via the RSFLP function block to reset the system state and ensure that the system is in the initialization state after the reset; wherein the second unit comprises transmitting a start signal from the first unit, transmitting a control signal via the TIMER function block to drive a target actuator to operate, and judging the state of the actuator via the logical function blocks AND and NOT to ensure correctness of an action being performed.The automatic test system for an actuator according to claim 2, characterized in that the first unit comprises: the function blocks of the first unit perform the following tasks: the D / MA function block serves as a starting point for the human-machine interaction, receives a command signal for starting the test from the operator, receives an external operation command via DCS, and outputs the operation command as a signal to a subsequent module; wherein the DI function block monitors important switching signals in the system to determine whether the system needs to be reset currently, receives an external digital signal, and outputs it, where 0 denotes no signal and 1 denotes the presence of a signal; wherein the OR function block performs an OR logic judgment of an input signal, triggers a reset when one of the input signals is 1, inputs two signals output from the DI function block and the D / MA function block, respectively, and outputs the result of the OR logic judgment to a set terminal S of the RSFLP function block; wherein the RSFLP function block resets the system based on a set and a reset signal, maintains the state after the reset, and inputs the reset signal R and the set signal S, the reset signal R is triggered by an external reset command of the system to forcibly clear all the output signals, and the set signal S is triggered by the output of the OR function block, the set signal triggers a reset when a condition is satisfied, and an output signal indicating the reset state of the system is output, the output of 1 indicating a completed reset.The automatic test system for an actuator according to claim 3, characterized in that the second unit comprises: the function blocks of the second unit perform the following tasks: the DO function block transmits a signal to the actuator to trigger its execution of a corresponding action, and outputs the signal D=1 upon signal triggering, wherein a hardware device starts to execute the action upon receipt of the signal; wherein the TIMER function block is for time-related processing of the input signal, and outputs a control signal including pulse mode, delay mode, and timer mode based on a set time function; wherein the AND function block performs an AND logic operation on two input signals Z1 and Z2, outputs the signal D=1 only when both the first signal Z1 and the second signal Z2 are 1, and outputs the signal 0 when one of the input signals is 0; wherein the NOT function block performs a NOT logic operation on the input signal Z, outputs the signal D=0 when the input signal Z=1 and outputs the signal D=1 when the input signal Z=0.The automatic test system for an actuator according to claim 4, characterized in that the opening of the sampling valve comprises: in the first unit, an instruction to start the test is input via the DCS system, the D / MA function block receives the instruction and thereafter outputs on its right side the signal D, which is transmitted to the OR function block and an S input terminal of RSFLP; wherein simultaneously the DI function block monitors the external digital input signal and, when the digital signal is valid, the DI function block outputs the signal D=1 and transmits it to a Z2 input terminal of the OR function block; wherein the OR function block performs a logical operation on the signal Z1 from the D / MA function block and the signal Z2 from the DI function block, and when one of the signals is 1, the OR function block outputs the signal D=1 and transmits it to an S input terminal of the RSFLP function block; wherein the RSFLP function block receives a signal from the OR function block and thereafter outputs a signal to a D pin, wherein a signal of 1 at the D pin indicates that the test system is started, and wherein the D signal is transmitted to the TIMER function block of the second unit to start the automatic test process of the sampling valve; wherein in the second unit, an S input terminal of the TIMER function block of the second unit receives the signal D=1 from the D pin of the RSFLP function block of the first unit, and the TIMER function block is set to the delay mode upon receiving the S signal, triggering the output signal D=1 that continues for a duration of 3 seconds; wherein the output signal is transmitted to the sampling valve to drive the sampling valve to open; wherein the state of the sampling valve is monitored by the DI function block in real time, and when the sampling valve is successfully opened, the DI function block outputs the signal D=1 and transmits it to the AND function block; wherein the AND function block simultaneously receives a sampling valve action completion signal and, when both signals are 1, the AND function block outputs the signal D=1 to indicate that the sampling valve is normally open; wherein, when the sampling valve is not successfully opened, the DI function block outputs the signal D=0 and transmits it to the NOT function block, and wherein the NOT function block inverts D=0 to D=1 to indicate that the valve is not normally open.A computer device comprising a memory and a processor, on which memory a computer program is stored, characterized in that the processor, when executing the computer program, implements the steps of the system according to any one of claims 1 to 5.Computer-readable storage medium on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements the steps of the system according to any one of claims 1 to 5.

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