Device for condition testing of chip substrates

Abstract

Device for condition testing of chip substrates, comprising a carrier platform (1); a receiving carrier (2) which is arranged on the carrier platform (1) and serves to receive a plurality of chip substrates (9) stacked at intervals; a carrier door (21) which can be opened and is arranged on one side of the receiving carrier (2); a door opening device (3) which is movably arranged on one side of the support platform (1) and serves to open the support door (21); at least one flash element (4) arranged on the door opening device (3) to illuminate the front sides of the chip substrates (9) and to create a light-reflecting contour (41) corresponding to the side surfaces of the chip substrates (9); at least one image recording device (5) which is arranged on the door opening device (3) and is informationally connected to the flash element (4) in order to take an image of the light-reflecting contour (41) when the flash element (4) is activated and thus obtain a substrate contour image (51); a storage element (6) for storing the standard state information (61) of the chip substrates (9); and an identification module (7) that is informationally connected to the image acquisition device (5) and the storage element (6) to determine, based on the substrate contour image (51) and the standard state information (61), whether the thickness and deformation of the chip substrates (9) are abnormal.

Description

Technical field

[0001] The invention relates to a device for checking the condition of chip substrates, which can simultaneously detect the substrate bearing condition and substrate body defects before the chip substrates are removed from the receiving carrier, thereby increasing overall work efficiency and reducing the risk of transport collisions. State of the art

[0002] In semiconductor, display, and advanced packaging manufacturing, thin materials such as wafers and panels are frequently stored and transported using specialized carriers. The most common structures include the front-opening unit container (FOUP), the front-opening common box (FOSB), open cassette, and panel box. These carriers isolate the wafers from the external environment and are compatible with automated machine operation. Despite their widespread use, these carriers often exhibit storage anomalies or material defects. These include missing, overlapping, or tilted wafers or panels, and other misalignments. They can also have shape defects such as chipped corners, cracks, warping, and uneven wafer thickness.If these anomalies are not detected early, they can lead to wafer removal errors, transport damage, and even equipment damage and product rejects during subsequent automated processes, impacting production capacity and yield.

[0003] To address these issues, several automated inspection devices and processes have already been implemented in existing production lines. For example, regarding bearing condition, existing research and commercial systems utilize technologies such as infrared light curtains, raster scans, laser beam sensors, and image identification modules to perform preliminary assessments of the presence, position, and tilt of objects within the cassette. This allows for the detection of conditions such as absence, overlap, and tilt. Some systems also employ lateral light sources in combination with camera angle adjustments to reconstruct the contours of objects within the cassette, thereby increasing assessment accuracy. However, these technologies primarily focus on presence and correct positioning and struggle to detect shape defects in the objects.

[0004] Currently, laser triangulation, confocal displacement measurement, interferometers, 3D profiling, and thickness measurement modules are commonly used to detect shape defects, enabling partial or complete shape measurement of individual wafers or panels. Some high-end devices also integrate AI image recognition to classify and evaluate wafer edge damage, microcracks, chipped corners, warping, and other anomalies. However, for this type of shape detection, the wafers or panels often need to be individually removed from their supports or at least rotated, flipped, or angled to ensure that the sensor or optical module is aligned with the inspection surface for accurate measurement. While these devices offer high accuracy, the process is cumbersome and does not allow for real-time screening.

[0005] In current testing technologies, storage anomalies and shape defects are generally treated separately. A mechanism that integrates these two testing functions and enables a complete evaluation while the material is still in the tray is lacking. Although some systems promise comprehensive testing, in reality, each wafer or panel must be individually removed, measured, and identified. This cannot be done simultaneously with opening the cassette door or automatic wafer removal, thus preventing an increase in the overall efficiency of the production line.

[0006] Furthermore, existing devices often require multiple sensor modules and precision displacement platforms for complete shape inspection. This makes them bulky, expensive, and presents high integration barriers, hindering their use in standard chip substrate removal modules or existing wafer cassette door opening mechanisms. Consequently, most inspection operations are independent steps and cannot be integrated with continuous processes such as cassette door opening, wafer relocation, and loading. This leads to bottlenecks in the production line, causes additional labor and operational risks, and simultaneously increases the risk of operator error and wafer breakage during removal, which in turn disrupts advanced processes and automated transport systems. Object of the invention

[0007] The object of the invention is as follows: An image acquisition device and a flash element are attached to the door opening device to determine, based on the light-reflecting contour of the chip substrates, whether the storage condition of the chip substrates is abnormal. The identification module determines whether the thickness and deformation of the chip substrates are abnormal, thereby achieving rapid identification and integration of storage condition and substrate defect detection, thus increasing overall work efficiency and reducing the risk of transport collisions.

[0008] This object is achieved by the invention, which comprises: a carrier platform, a receiving carrier, several chip substrates, a carrier door, a door opening device, at least one flash element, at least one image acquisition device, a storage element, and an identification module. The receiving carrier is arranged on the carrier platform and serves to receive the chip substrates stacked at intervals. The receiving door can be opened and is arranged on one side of the receiving carrier. The door opening device is movably arranged on one side of the carrier platform and serves to open the receiving door. The flash element is arranged on the door opening device to illuminate the front of the chip substrates and to generate a light-reflecting contour corresponding to the side surfaces of the chip substrates.The image capture device is located on the door opening device and is informationally connected to the flash element in order to capture an image of the light-reflecting contour when the flash element is activated, thus obtaining a substrate contour image. The identification module is informationally connected to the image capture device and the storage element.

[0009] When the user performs condition testing of chip substrates using the present invention, several chip substrates are placed in the holder and positioned on the carrier platform. The carrier door of the holder is opened by a door opening device. As the door opening device moves up and down in front of the holder, a flash element illuminates the front faces of the chip substrates, creating a light-reflecting contour that corresponds to the side faces of the chip substrates. Upon activation of the flash element, the image acquisition device captures an image of the light-reflecting contour to obtain a substrate contour image. Finally, the identification module reads the substrate contour image and the standard condition information stored in the memory element to determine whether the thickness and deformation of the chip substrates are abnormal.This integrates the detection of bearing condition anomalies and shape defects with the door opening function, increasing overall work efficiency and reducing the risk of transport collisions.

[0010] The aforementioned technique can solve the problems of conventional wafer or panel inspection technologies, such as the inability to simultaneously detect storage condition and body shape, the inspection cannot be completed in a single carrier, additional transport and separation are required, and integration with the door opening or wafer removal process is not possible. Therefore, the invention can achieve the aforementioned practical advancements. Brief description of the drawings Fig. 1 a perspective view of the first preferred embodiment of the invention, Fig. 2 an exploded view of the first preferred embodiment of the invention, Fig. 3 a representation of the standard state of the first preferred embodiment of the invention, Fig. 4 a description of the examination of the first preferred embodiment of the invention, Fig. 5 a representation of the abnormal state of the first preferred embodiment of the invention (1), Fig. 6 a representation of the abnormal state of the first preferred embodiment of the invention (2), Fig. 7 a perspective view of the second preferred embodiment of the invention, Fig. 8 a representation of the thickness measurement of the second preferred embodiment of the invention, Fig. 9 a representation of the deformation measurement of the second preferred embodiment of the invention, Fig. 10 a flowchart of the determination during substrate extraction of the second preferred embodiment of the invention. Ways to implement the invention

[0011] Fig. Figures 1 to 3 show a perspective view up to a representation of the standard state of the first preferred embodiment of the invention. As shown in the figures, the invention comprises: a support platform 1; a receiving carrier 2, which is arranged on the carrier platform 1 and serves to receive a plurality of chip substrates 9 stacked at intervals; a carrier door 21 which can be opened and is arranged on one side of the receiving carrier 2; a door opening device 3, which is movably arranged on one side of the support platform 1 and serves to open the support door 21; at least one flash element 4 arranged on the door opening device 3 to illuminate the front sides of the chip substrates 9 and to create a light-reflecting contour 41 corresponding to the side surfaces of the chip substrates 9; at least one image recording device 5, which is arranged on the door opening device 3 and is informationally connected to the flash element 4 in order to take an image of the light-reflecting contour 41 when the flash element 4 is actuated and thus obtain a substrate contour image 51; a memory element 6, which serves to store the standard state information 61 of the chip substrates 9; and an identification module 7, which is informationally connected to the image acquisition device 5 and the storage element 6, to determine, based on the substrate contour image 51 and the standard state information 61, whether the thickness and deformation of the chip substrates 9 are abnormal.

[0012] The receiving carrier 2 is a forward-opening unit container (FOUP), a forward-opening common box (FOSB), an open cassette, or a panel box. In this embodiment, an FOUP is used as an example, so the chip substrates 9 stored therein are, for example, wafers. The carrier platform 1 is a platform for securing or moving the receiving carrier 2 forward and backward. The carrier door 21 is a cover for closing the receiving carrier 2. The door opening device 3 is an interface (FOUP charging port) installed on the front of the device. The flash element 4 is, for example, an infrared flash. The image acquisition device 5 is, for example, a camera. The storage element 6 is a storage device, such as computer memory or network storage, e.g., Google Cloud storage.In this embodiment, for example, a memory is used that is arranged together with a processor or IC on a printed circuit board and is represented in the figure by a dashed frame. The identification module 7 is, for example, a processor in the carrier platform 1 and is also represented in the figure by a dashed frame. However, the component types described above are merely examples of preferred embodiments. All types with the same functionality fall within the scope of this invention and are not limited to the examples described above.

[0013] The above description already outlines the structure of this technology. By appropriately configuring this structure, the detection of the substrate bearing condition and substrate defects can be completed before the chip substrates 9 are removed from the mounting carrier 2. This increases overall work efficiency and reduces the risk of transport collisions. A detailed description follows.

[0014] The Fig. Figures 1 to 6 show a perspective view up to a representation of the abnormal state of the first preferred embodiment of the invention. When assembling the aforementioned components, as clearly shown in the figures, only the image capture device 5 and the flash element 4 need to be attached to the door opening device 3, and the image capture device 5 needs to be connected to the identification module 7 and the storage element 6. The assembly is simple, and the installation costs are low. In addition to direct mounting on the door opening device 3, the image capture device 5 and the flash element 4 can also be attached to an outer frame 31, which is deflected at the image capture device 5. This not only simplifies assembly but also facilitates the adjustment of the lighting and image capture position.In this embodiment, three flash elements 4 and two image capture devices 5 are used as an example, which are arranged offset on the outer frame 31. Since the image capture device 5 and the flash element 4 are arranged indirectly on the door opening device 3 and their image capture direction and illumination direction are both directed towards the opening of the mounting carrier 2, the image capture direction and the illumination direction are always the same.

[0015] Since the image capture device 5 and the flash element 4 are arranged at the same height, the entire light-reflecting contour 41 can be captured more accurately.

[0016] Before the substrate removal device performs the gripping action, several chip substrates 9 are stored. It is verified that they have no abnormal storage condition or body defects, so that the comparison data of the standard storage condition can be pre-stored in the memory element 6. During actual operation, the door opening device 3 opens the carrier door 21 and then begins to lower, gradually exposing the chip substrates 9 in the receiving carrier 2. Simultaneously, the flash element 4 emits light onto the chip substrates 9, causing them to create a light-reflecting contour 41. At the same time, the image acquisition device 5 is activated to capture an image of the light-reflecting contour 41.

[0017] For example, the left side of the screen shows the image acquisition area of ​​the image acquisition device 5, which captures images of the chip substrates 9 in the illumination area of ​​the flash element 4. Since the chip substrates 9 are housed in the image carrier 2, the light-reflecting contour 41 is formed according to the side faces of the chip substrates 9. The image acquisition device 5 captures the image of the light-reflecting contour 41 and generates a substrate contour image 51 (as shown by the dashed frame). Finally, the identification module 7 compares the substrate contour image 51 with the stored default state reference data to determine the state of the chip substrates 9. However, the light-reflecting contour 41, the substrate contour image 51, or the default state information 61 are only displayed on the screen for the user's viewing or recording purposes.They can also be processed directly in identification module 7 to simply provide feedback on the identification result.

[0018] Therefore, all conditions of the chip substrates 9, including abnormal storage conditions such as absence, tilting and overlapping of the chip substrates, and body defects such as thickness, warping and deformation, can be quickly identified. Fig. Figure 3 shows a representation of the standard storage condition, Fig. Figure 5 shows a representation of the abnormal thickness and Fig. Figure 6 shows a representation of the deformation. Abnormal bearing conditions occur relatively frequently and are not discussed in detail here.

[0019] In contrast to the prior art, where the memory state and shape anomalies are treated separately, the present invention thus enables simultaneous dual testing while the chip substrates 9 are still in the holder 2 and during the execution of the door opening or substrate removal process, thereby significantly reducing the frequency of transport and the need for mechanical changes. Integrating the image acquisition device 5 and the flash element 4 into the door opening device 3 effectively reduces the operating time and costs for device integration, thus improving the efficiency of automated production. Furthermore, since the inspection is performed simultaneously with the door opening and substrate removal process, the risk of human error and additional breakage is reduced, which is particularly valuable for high-value or fragile workpieces.The present invention also has modularity potential and enables easy integration into existing mounting carriers 2 in order to realize low-interference, highly compatible inline testing functions.

[0020] Fig.Figures 7 to 10 show a perspective view up to a flow diagram of the determination during substrate removal in the second preferred embodiment of the invention. As can be clearly seen from the figures, the main difference between this embodiment and the previous embodiment is that the evaluation of thickness and deformation is improved and the substrate removal process is adapted accordingly. Therefore, the identification module 7 includes a centerline equation 71 for defining the thickness information of the standard state information and a curve fitting module 72 for calculating the deformation. In addition, a substrate removal device 8, which is informationally connected to the identification module 7, is provided on one side of the door opening device 3 in order to eliminate or compensate for the substrate removal process based on the identification results.

[0021] The thickness information of the standard state information is determined by providing the chip substrate with a known thickness and no deformation and calculating the pixel count T in the thickness direction of the light-reflecting contour 41 of the chip substrate with known thickness and no deformation. After calculating the pixel count T, the deformation information of the standard state information is determined by obtaining the centerline 711 on the substrate contour image 51 using the centerline equation 71. If the identification module 7 determines whether the thickness is anomalous (step A), the pixel count T in the thickness direction of the light-reflecting contour 41 is calculated and compared with the thickness information of the standard state information (step B). A larger pixel count T is interpreted as thicker, and a smaller pixel count T is interpreted as thinner.Regarding deformation, the identification module 7 determines whether the centerline 711 of the chip substrate matches the deformation information from the standard state information (step C). If they match, there is no deformation, and the deformation determination is terminated (step I). If they do not match, the degree of deformation is calculated using the curve-fitting module 72. The curve-fitting module 72 is a chip or software with curve-fitting technology. Curve-fitting refers to the process of fitting a set of data points to a curve using mathematical methods (such as the method of least squares) to further analyze the bending trend and calculate the offset or degree of deformation.

[0022] For example, the curve fitting module 72 can calculate the difference between individual data points and the centerline 711. The centerline 711 is defined as the zero point. If the curve slopes upwards, the difference is greater than 0, and if the curve slopes downwards, the difference is less than 0. The maximum difference between all upward-sloping data points is called the height compensation value y. i of lifting the substrate removal device 8 used (y i is a representative symbol and in practice i is a natural number, for example the highest value of y1 and y3 is y 1) Similarly, the maximum difference between all downward-curved data points (such as y2) is called the height compensation value y. i the lowering of the substrate extraction device 8 is used. Of course, before each chip substrate is extracted by a substrate extraction device 8, the height compensation value y is first determined. iThe degree of deformation is calculated (step D), and the deformation height and the position of the chip substrate are recorded (step E). If the height compensation value y i If the value exceeds a safety threshold, the substrate removal process is canceled (i.e., the wafer is not removed) (steps F and H) and the deformation determination process (step I) is terminated. If the height compensation value y i If the substrate extraction device 8 is smaller than the safety value, it adjusts the substrate extraction height based on the height compensation value y. i and records them (steps F and G).

[0023] The invention uses the algorithm in the curve-fitting module 72 to adapt the contour curve of the chip substrate and thus accurately determine the degree of deformation. It offers higher resolution and flexibility than conventional, threshold-based assessment methods. If the calculated deformation is within the system's preset safety value, the system records the defect information and automatically performs height compensation and displacement correction during the subsequent substrate removal process to ensure stable transport and the integrity of the chip substrate. If the deformation exceeds the safety value, the abnormal location is automatically marked, and the substrate removal process is canceled to avoid the risk of mechanical blockages or breakage.This staged response strategy, based on quantified deformation results, simultaneously considers the accuracy and efficiency of the production line, facilitates subsequent quality traceability and data analysis, and increases the level of intelligence of the entire processing workflow.

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