Apparatus for using a low reference voltage with a MEMS device

Abstract

Sensor component, including: a case; an electrical interface located on the outside of the housing; a capacitive transducer arranged in the housing, the capacitive transducer comprising a first electrode and a second electrode; and an electrical circuit arranged in the housing and electrically connected to the capacitive transducer and the electrical interface, wherein the electrical circuit comprises a bias source connected to the first electrode, the bias source comprising: a charge pump that includes a clock input; a reference voltage source that provides a reference voltage; a clock circuit that outputs a clock signal with a clock voltage; and A voltage amplifier circuit coupled to the charge pump and the reference voltage source, wherein the voltage amplifier circuit receives the reference voltage and the clock signal, increases the reference voltage, and increases a voltage of the clock signal supplied to the clock input of the charge pump based on the increased reference voltage.

Description

BACKGROUND

[0001] The present disclosure relates to a microelectromechanical system (MEMS) device. In particular, the present disclosure relates to an apparatus for using a low reference voltage with a MEMS device. BACKGROUND

[0002] Currently, consumer electronics devices such as mobile phones, PCs, smart speakers, hearing aids, and true wireless stereo (TWS) headphones, as well as other host devices, typically contain one or more small sensors, such as microphones, actuators, and / or other sensors. Advances in micro- and nanofabrication technology have led to the development of MEMS device-level sensors that exhibit increasingly smaller dimensions and diverse form factors.

[0003] Due to the small dimensions of sensor packages, MEMS devices are often used with small power supplies that output low voltages. However, the capacitive element of MEMS devices requires higher voltages than those provided by small power supplies. Therefore, a charge pump is used to bias the capacitive element with a voltage much higher than that supplied by the power supply. The bias voltage range is often between 10 V and 40 V, depending on the MEMS converter, and may need to be wider depending on the converter. This bias voltage is typically generated using a reference voltage and a series of cross-coupled inverter pump stages, where the reference voltage multiplier is proportional to the number of pump stages.Due to the requirements for the small size of the sensor package, there is a need to reduce the number of charge pump stages while simultaneously providing the required voltage for a specific MEMS converter.

[0004] The approaches described in this section are those that could be pursued, but not necessarily those that have been previously conceived or followed. Therefore, unless otherwise stated, the approaches described in this section should not be considered background information simply because they are included here. Furthermore, the approaches described in this section should not be assumed to be well understood, routine, or conventional simply because they are included here. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To describe how the advantages and features of the disclosure can be achieved, the disclosure is described with reference to specific embodiments illustrated in the accompanying drawings. These drawings show only illustrative embodiments of the disclosure and are therefore not to be considered as limiting its scope. The drawings may have been simplified for clarity and are not necessarily drawn to scale. Fig. Figure 1A is an exploded view of a representative sensor according to an exemplary embodiment. Fig. Figure 1B is a side cross-sectional view of the representative sensor according to an exemplary embodiment. Fig. Figure 2 is a schematic diagram of a converter according to an exemplary embodiment. Fig. Figure 3 is a schematic diagram of a charge pump stage according to an exemplary embodiment. Fig. Figure 4 shows two charge pump stages of a charge pump according to an exemplary embodiment. Fig. Figure 5 is an exemplary block diagram of a bias source according to an exemplary embodiment. Fig. Figure 6 is a representation of a voltage amplifier stage according to an exemplary embodiment. Fig. Figure 7 is a representation of a first switching control circuit according to an exemplary embodiment. Fig. Figure 8 is a representation of a second switching control circuit according to an exemplary embodiment. Fig. Figure 9 is an exemplary diagram of signals applied to the voltage amplifier stage according to an exemplary embodiment. Fig. Figure 10 is an illustrative representation of a bootstrap circuit according to an exemplary embodiment. Fig. Figure 11 is an illustrative representation of a bias source according to an exemplary embodiment. Fig. Figure 12 is an illustrative representation of a bias source according to an exemplary embodiment. DETAILED DESCRIPTION

[0006] The following description provides numerous specific details for explanatory purposes, in order to convey a comprehensive understanding of the present invention. However, it is obvious that the present invention can also be implemented without these specific details. In other cases, known structures and devices are represented in block diagrams to avoid unnecessarily obscuring the present invention. The drawings illustrate aspects of the disclosed embodiments, omitting elements that are known to those skilled in the art for implementing the disclosed embodiments.

[0007] At least some embodiments can provide a device and a method for using a low reference voltage with a MEMS device. In one embodiment, a sensor component comprises a housing and an electrical interface located on an outer surface of the housing. The sensor component includes a capacitive transducer located within the housing, the capacitive transducer comprising a first electrode and a second electrode. The sensor component includes an electrical circuit located within the housing and electrically coupled to the transducer and the electrical interface, the electrical circuit comprising a bias voltage source coupled to the first electrode.

[0008] The bias source comprises a charge pump with a clock input. In one embodiment, the charge pump can comprise a plurality of charge pump stages, each charge pump stage having a charge pump stage clock input. Each charge pump stage clock input can comprise two clock inputs, one receiving a clock signal that is phase-shifted relative to a clock signal received at the other clock input. The bias source also comprises a reference voltage source that provides a reference voltage. The bias source further comprises a clock circuit that outputs a clock signal with a clock voltage.

[0009] The bias supply comprises a voltage amplifier circuit coupled to the charge pump and the reference voltage source. The voltage amplifier circuit receives the reference voltage and the clock signal, boosts the reference voltage, and then amplifies the clock signal, which is fed to the clock input of the charge pump, based on the increased reference voltage. The charge pump may include a charge pump input, and the voltage amplifier circuit supplies the increased reference voltage to this input.

[0010] In one embodiment, the voltage amplifier circuit comprises a plurality of voltage amplifier stages, wherein a first voltage amplifier stage amplifies a clock voltage supplied to a second voltage amplifier stage. The first voltage amplifier stage can also amplify the reference voltage and supply the amplified reference voltage to the second voltage amplifier stage.

[0011] In one embodiment, the voltage amplifier circuit includes a voltage level shifter coupled to an output of the first voltage amplifier stage and to a clock input of the second voltage amplifier stage. The voltage level shifter increases the clock voltage supplied to the second voltage amplifier stage based on an increased reference voltage output by the first voltage amplifier stage.

[0012] In one embodiment, the electrical circuit comprises a multiplexer that selectively releases a voltage amplifier output signal, provided by at least one voltage amplifier stage of the plurality of voltage amplifier stages, to the charge pump. The voltage amplifier output signal can be a multiplied reference voltage signal and / or an increased voltage clock signal.

[0013] In one embodiment, the voltage amplifier circuit comprises at least two transistors, each having a gate and a source. Each of the at least two transistors can be part of a separate inverter. The voltage amplifier circuit includes a switching control circuit coupled between the gates of the at least two transistors, wherein the switching control circuit controls the at least two transistors independently of the reference voltage. The switching control circuit is considered a switching control circuit because the transistors function as switches and the switching control circuit controls the switching function of the transistors. In particular, the switching control circuit makes the gate-source voltage of the transistors independent of the reference voltage. For example, the switching control circuit sets Vgs based on a voltage derived from a source voltage that differs from the reference voltage.The switching control circuit turns the transistors on and off based on a gate voltage Vg, which makes the gate control independent of a reference voltage applied to the source.

[0014] In one embodiment, the at least two transistors comprise a first PMOS transistor with a gate, a first NMOS transistor with a gate, a second PMOS transistor with a gate, and a second NMOS transistor with a gate. The switching control circuit can control a voltage applied to the gate of a PMOS transistor separately from a voltage applied to the gate of an NMOS transistor. In one embodiment, the switching control circuit comprises a first switching circuit coupled between the gate of the first PMOS transistor and the gate of the second PMOS transistor, and a second switching circuit coupled between the gate of the first NMOS transistor and the gate of the second NMOS transistor.

[0015] In one embodiment, the first switching circuit comprises an inverting clock amplifier that supplies an inverted, amplified clock signal to the gate of the first PMOS transistor and the gate of the second PMOS transistor. The second switching circuit comprises a clock amplifier that supplies an amplified clock signal to the gate of the first NMOS transistor and the gate of the second NMOS transistor. In an exemplary embodiment, the voltage amplifier circuit comprises a first voltage amplifier capacitor and a second voltage amplifier capacitor, which are driven by corresponding complementary clock generators. The complementary clock generators control the charging and discharging of the respective capacitors.

[0016] In one embodiment, the charge pump includes a charge pump output. The bias source includes a low-pass filter coupled between the charge pump output and the capacitive transducer. In another embodiment, the electrical circuit may include a non-inverting amplifier having an input coupled to the capacitive transducer, wherein the non-inverting amplifier has an input impedance greater than 1 TΩ. The minimum input impedance can be determined by the capacitance of the MEMS component, for example, a MEMS motor. Some microphones may have an input impedance of GΩ when the MEMS capacitance is large and is determined by the desired acoustic lower bandwidth.

[0017] As described above, a charge pump is used to bias the capacitive MEMS element with a voltage much higher than the supply voltage. The bias voltage range is commonly between 10 V and 40 V, depending on the motor design, and other motor designs and applications may require different values, a wider range, or a narrower range. This bias can be developed using a reference voltage and a series of cross-coupled inverter pump stages, with a multiplication factor of the reference voltage proportional to the number of pump stages. Furthermore, due to the small size of the sensor package, it is advantageous to reduce the number of charge pump stages while still providing the required voltage for a given MEMS transducer.

[0018] In 0.9 V battery applications, the charge pump multiplication factor is typically very high, and several multiplier stages can be used, so the reference voltage is pre-multiplied before driving a multi-stage charge pump. Thus, instead of a 0.75 V reference voltage, the reference can be pre-multiplied, for example, by a factor of 2, to drive the remaining charge pump stages with 1.5 V, thereby reducing the total number of pump stages.

[0019] Different MEMS motors require different bias voltages. The wide final bias range required for various MEMS motors, combined with a high multiplication pump factor, results in high and low reference voltages, depending on the specific MEMS motor used. In other words, to achieve a 44 V charge pump output with a charge pump multiplication factor of 59, the required reference voltage might be 0.75 V, while for a 20 V output, the required reference voltage might be approximately 0.34 V. Such a low reference voltage is difficult to use with a standard charge pump where the cross-coupled inverter switches are driven by the reference voltage.This is especially true at startup when series doublers are used to pre-multiply the reference voltage for use with the charge pump stages, since a higher load current requirement at startup necessitates a lower on-resistance for the switches.

[0020] In some embodiments, the requirement for low on-resistance at startup can be met by using very low reference voltages. This is achieved by decoupling the transistors / switches from the reference voltage and driving the switches with suitable bootstrap signals using a higher voltage, such as a VDD source voltage. In this way, a more robust pump doubler can be designed to pre-multiply the reference voltage, thus maintaining a low on-resistance for the initial phases. A low initial reference voltage may be less critical in subsequent phases, as the reference voltage is increased for later phases.

[0021] At least some embodiments can decouple the reference voltage from the control of the switches in the charge pump core by using switching control circuits, such as separate bootstrap switching control circuits, with higher voltages, such as VDD. This decoupling of the switch control from the reference voltage increases the gate-source voltage Vgs of the switches, resulting in a lower on-resistance of the switches, while the reference multiplication factor of the overall charge pump transfer function remains unchanged, assuming parasitic losses can be neglected. The switching control voltage can also be increased / doubled to further reduce the on-resistance of the switches.Furthermore, the separate control of PMOS switches compared to NMOS switches in the amplifier / doubler allows for improved break-before-make control, so that the forward current from the output of the amplifier / doubler stage to the input of the amplifier / doubler stage can be minimized to increase the efficiency of the charge pump.

[0022] At least some embodiments can provide different charge pump output voltages for different applications. For example, some sensor circuits may require different voltages than others, and the charge pump output voltage can be adjusted, for example, programmed or trimmed, for different applications without problems caused by low reference voltages. For example, the charge pump range can be ~20 V to 40 V with a Vref of ~400 mV to 750 mV. Different ranges can also be used for different applications. Embodiments can provide a wide range of useful charge pump voltages by allowing lower reference voltages. For example, a multiplexer can be used to set different charge pump voltages, provide trimmable reference voltages, short-circuit charge pump stages, and for other purposes.

[0023] Fig. Figure 1A is an exploded view of a representative sensor component 100 according to an exemplary embodiment. Fig. Figure 1B is a side cross-sectional view of the representative sensor component 100 according to an exemplary embodiment. A sensor component generally comprises a capacitive transducer and an electrical circuit arranged in a housing with an external electrical interface. In a general embodiment, a sensor component comprises a housing and an electrical interface located on the outside of the housing. The sensor component includes a capacitive transducer arranged within the housing, the capacitive transducer comprising a first electrode and a second electrode. The sensor component includes an electrical circuit arranged within the housing and electrically coupled to the transducer and the electrical interface, the electrical circuit comprising a bias source coupled to the first electrode.

[0024] For example, a representative sensor component 100 comprises a housing with a cover 102 mounted on a base 104. Optionally, a protective ring 106 is located between the cover and the base 104, for example, a substrate. The cover 102, the protective ring 106, and the base 104 can comprise conductive materials to electrically shield parts of the sensor within the housing. The cover 102 can consist of a metal housing or metallized PCB materials. The base 104 can also be a PCB comprising one or more layers.

[0025] In general, a transducer 110 is electrically connected to an electrical circuit 112, and the electrical circuit is electrically connected to the external electrical interface of the housing. The transducer generally comprises at least one movable electrode (e.g., a membrane or diaphragm) and one fixed electrode. The displacement of the movable electrode relative to the fixed electrode in response to a detected state forms the basis for generating an electrical signal representing the detected state. Representative transducers include capacitive microelectromechanical systems (MEMS), also known as the MEMS die or MEMS motor. Other suitable transducers include electret, piezoelectric, and photocell devices, which have fixed and movable electrodes. The electrical circuit can be implemented as one or more integrated circuits (ICs) or ASICs.

[0026] In one possible embodiment, the representative sensor component 100 is implemented as a microphone comprising a transducer 110, for example an acoustic transducer such as a MEMS transducer, which is arranged above a sound opening 114 in the base 104. The transducer 110 divides the housing into a front volume 122, which is acoustically coupled to the sound opening 114, and a rear volume 124 on the side of the transducer 110 opposite the sound opening 114.

[0027] In one embodiment, the transducer 110 comprises the first electrode in the form of a diaphragm 111 and the second electrode in the form of a perforated backplate 113. The diaphragm 111 is movable relative to the perforated backplate 113 to respond to changes in the sound pressure entering the interior of the housing through the sound port 114. Instead of being arranged above an acoustic port at the base 104, the transducer 110 can be arranged above an acoustic port in the cover. In other implementations, the sensor is a vibration sensor or accelerometer without an acoustic port in the housing. The transducer of a vibration sensor or accelerometer can be configured as a test mass.

[0028] The electrical circuit, for example an IC, 112 is arranged in the housing and electrically connected to contacts 108 on the base 104. The MEMS transducer 110 is wired to the electrical circuit 112, and the electrical circuit 112 is wired to the contacts 108 on the base 104. Alternatively, the electrical circuit 112 can be surface-mounted on the contacts 108. The contacts 108 on the base 104 can be electrically connected to an electrical interface 120 on the outside of the housing via vias extending through the base 104. Alternatively, the electrical circuit 112 can be mounted on another surface inside the housing, such as the cover 102, and connected to an electrical interface via conductors extending through the side walls or another structure of the housing.

[0029] Fig. Figure 2 is a schematic diagram of a converter circuit 200 according to an exemplary embodiment. The converter circuit 200 generally comprises features of the electrical circuit 112, which may, for example, include a bias source 201 coupled to an electrode of a capacitive converter 110. The bias source 201 includes a charge pump 210. The bias source 201 includes a low-pass filter 211 coupled between an output of the charge pump and the capacitive converter 110. The converter circuit 200 may also include a non-inverting amplifier 220 with an input coupled to the capacitive converter 110, wherein the non-inverting amplifier 220 has an input impedance of more than 1 TΩ, the impedance being related to the motor capacitance and the signal path bandwidth.

[0030] For clarification: Electrical components of the converter circuit 200 can be part of the electrical circuit 112. The converter circuit 200 generally comprises the bias source 201, the converter 102, and an amplification circuit 203. The bias source 201 can be a DC bias circuit. In some embodiments, the bias source 201 and the amplification circuit 203 are integrated into the electrical circuit 112. In some embodiments, the amplification circuit 203 can be part of a host device. In some embodiments, the amplification circuit 203 can be a signal conditioning circuit that includes a buffer, a high-pass filter, and / or an analog-to-digital converter (e.g., in digital microphones).The amplification circuit 203 can be a non-inverting amplifier comprising an input coupled to the capacitive converter 110, wherein the non-inverting amplifier has an input impedance of more than 1 TΩ.

[0031] The bias source 201 is arranged to supply a DC bias signal to the converter 110. In some embodiments, the bias source 201 includes a charge pump, for example a multi-stage charge pump circuit 210, and a low-pass filter (LPF) circuit 211. In some embodiments, the bias source 201 further includes an electrostatic discharge (ESD) circuit 212, which is coupled to an output of the bias source 201, to ground or another useful voltage, and is configured to discharge electrostatic charges.

[0032] In some embodiments, the bias source 201 may include other types of DC amplifier circuits as an alternative to, or in addition to, the multi-stage charge pump circuit 210. The multi-stage charge pump 210 is configured to convert an input DC voltage into an output DC voltage that is higher than the input DC voltage. For example, the multi-stage charge pump circuit 210 may have an input from a battery or other power source of approximately 5 volts, and the output of the multi-stage charge pump circuit 210 may be 50 volts or more. In some embodiments, the increase in DC voltage from the input to the output of the multi-stage charge pump circuit 210 is based on the number of charge pump stages CP. 1-Nor other DC gain circuits within the multi-stage charging pump circuit 210. The LPF 211 is arranged to receive a signal from the output of the multi-stage charging pump circuit 210 and output the DC bias signal to a first terminal of the transducer 110. In some embodiments where the mechanical compliance of the transducer 102 is low, the output voltage of the bias source 201 can be increased so that the sensor component has increased sensitivity and signal-to-noise ratio (SNR).

[0033] The transducer 102 is arranged to receive the DC bias signal from the bias source 201 and generate an electrical signal indicating the detected acoustic energy. The electrical signal is generated using the DC bias signal as a reference voltage. For example, the DC bias signal can be 55 volts (V), and the electrical signal generated by the transducer 102 can range from a few millivolts (mV) to several hundred millivolts (e.g., 0.001 mV to 100 mV). The electrical signal is then passed to the amplification circuit 203. As an example, the electrical signal can be amplified by the amplification circuit 203 and further processed by an analog-to-digital converter to generate a digital representation of the electrical signal and the acoustic activity that the electrical signal represents.

[0034] Fig. Figure 3 is a schematic diagram of a charge pump stage 300 according to an exemplary embodiment. In some embodiments, the charge pump stage 300 can be one of the number of charge pump stages CP. 1-N the bias source 201 from Fig. 2. It should be noted that other embodiments may implement different types, images, or configurations of charge pump stages. For example, in some embodiments, a charge pump stage may be implemented with one or more capacitors and one or more semiconductor devices. In some embodiments, the one or more semiconductor devices may include one or more diodes and / or one or more transistors.

[0035] The charge pump stage 300 includes an input V in , several transistors M 1-6 , a first capacitor C1, a second capacitor C1 and an output V outIn one particular implementation, transistors M5 and M6 can be omitted. The charge pump stage 300 is configured to be connected to a clock circuit via a first terminal φ1 and a second terminal φ2. The clock circuit is used to drive the charge pump stage 300. In some embodiments, the clock circuit generates a two-phase, non-overlapping signal, with one phase configured to be applied to the first terminal φ1 and a second phase configured to be applied to the second terminal φ2. In other embodiments, more than two phases can be implemented. The charge pump stage 300 receives a DC input voltage at input V. in and outputs a DC voltage whose magnitude is higher than the input DC voltage at output V out In some implementations, the output V outThe charge pump stage 300 is connected to an input of a second charge pump stage 300, so that the charge pump stages are cascaded and an output DC voltage of the multitude of charge pump stages can reach higher voltages.

[0036] Fig. Figure 4 shows two charge pump stages 402 and 404 of a charge pump 400 according to an exemplary embodiment. Each stage is sometimes referred to by those skilled in the art as a voltage doubler, each stage being constructed with cross-coupled inverters I1 and I2 driven by capacitors C1 and C2 by an overlapping clock generator 406. A high F1 in this simplified representation discharges the charged capacitor C1, while a low F2 charges the discharged capacitor C2. When F1 goes high (0->Vref), I1 connects Vin to the top plate of C2, thereby charging C2 from the output of the previous stage (Vin), if there are previous stages. Conversely, when F2 goes low (Vref->0), I2 connects Vout to C1, thereby transferring charge from C1 to the next stage 404.The final output voltage of a charge pump is approximately equal to the number of stages multiplied by Vref, where the voltage Vin supplied to the first stage 402 is Vref and the clock voltage is Vref.

[0037] Fig. Figure 5 is an example block diagram of a bias source 500 according to an exemplary embodiment. In general, the bias source 500 comprises a charge pump with a clock input. In one embodiment, the charge pump can comprise a plurality of charge pump stages, each charge pump stage having a charge pump stage clock input. Each charge pump stage clock input can comprise two clock inputs, one input receiving a clock signal that is phase-shifted relative to the clock signal received at the other input. The bias source 500 includes a reference voltage source that provides a reference voltage.

[0038] The bias source 500 also includes a clock circuit that outputs a clock signal with a clock voltage. The bias source 500 further includes a voltage amplifier circuit coupled to the charge pump and the reference voltage source. The voltage amplifier circuit receives the reference voltage and the clock signal, increases the reference voltage, and then amplifies a portion of the clock signal, based on the increased reference voltage, which is then fed to the clock input of the charge pump. The charge pump may have a charge pump input, and the voltage amplifier circuit supplies the increased reference voltage to this input.

[0039] The voltage amplifier circuit can comprise multiple voltage amplifier stages, with a first voltage amplifier stage amplifying a clock voltage supplied to a second voltage amplifier stage. The first voltage amplifier stage can also amplify the reference voltage and supply the amplified reference voltage to the second voltage amplifier stage.

[0040] In one embodiment, the voltage amplifier circuit includes a voltage level shifter coupled to an output of the first voltage amplifier stage and to a clock input of the second voltage amplifier stage. The voltage level shifter increases the clock voltage supplied to the second voltage amplifier stage based on an increased reference voltage output by the first voltage amplifier stage.

[0041] For example, the bias source 500 comprises a reference voltage circuit 502, a voltage amplifier circuit 504, and a multi-stage charge pump 506. The bias source 500 is coupled to a capacitive MEMS converter CMEMS. The voltage amplifier circuit 504 comprises at least one voltage amplifier stage 508 and 510, and a clock generator 512. The clock generator comprises a non-overlapping clock circuit 514 and at least one voltage level shifter 516 and 518. An overlapping clock circuit can also be used instead of a non-overlapping one. The voltage level shifters 516 and 518 can be charge pumps or other level shifters. Each voltage level shifter can be considered part of the respective voltage amplifier stages, and additional voltage amplifier stages and level shifters can also be present.

[0042] In operation, the non-overlapping clock circuit 514 generates two-phase, non-overlapping clocks that either have a period in which both clocks are high before one changes to low, or both are low before one changes to high. It generates clocks that drive the switched capacitors of the first voltage amplifier stage 508. The first voltage amplifier stage 508 receives a reference voltage Vref from the reference voltage circuit 502 and generates the 2 x Vref (double Vref) supply for the next voltage amplifier stage 510, or for the input of the charge pump 506 if the second voltage amplifier stage 510 is not present. It also generates the 2 x Vref voltage for the first voltage level shifter 516.

[0043] The level shifter 516 is a clock generator that receives Vref and converts the clock signals to 2 x Vref, so that the clock generator is powered by the 2 x Vref supply generated by the first amplifier stage. If additional amplifiers are present, the level shifter 516 also drives the inputs to the following level shifter 518 and controls the switched capacitors of the next voltage amplifier stage 510. If no additional amplifiers are present, the level shifter 516 drives, for example, successive core cells of the charge pump 506 via driver 520.

[0044] The voltage amplifier stages 508 and 510 can be voltage amplifiers, voltage multipliers, voltage doublers, and may include switching control circuits, such as bootstrap pump capacitor transistors, which are described in later embodiments. Each voltage amplifier increases a voltage supplied at an input of the amplifier. For example, the first voltage amplifier stage 508 generates a 2 x Vref output voltage from a Vref input voltage when its pump capacitors (not shown) are also driven by Vref-referenced clock signals from the clock circuit 514.

[0045] The multi-stage charge pump 506 comprises a variety of charge pump core stages, such as a number N of charge pump doubling stages, with the pump capacitors of each stage driven by drivers supplied by the final reference voltage. For example, drivers 520 can use the voltage Vrefx4 (four times Vref) from the second voltage amplifier stage 510 to boost the clock signal up to 4 times Vref and supply the boosted clock signal to the charge pump stages of the charge pump 506. The final reference voltage Vrefx4 can also be used as an input for the charge pump 506. The charge pump 506 boosts the final reference voltage Vrefx4 based on the boosted clock signal and the number of stages.

[0046] For example, an initial clock signal (0 to VDD) generates non-overlapping inputs for both the voltage level shifter 516 from Vref to 2Vref and the first voltage amplifier stage 508. The first voltage amplifier stage 508 generates the supply voltage Vrefx2 for the first voltage level shifter 516 from 2Vref to 4Vref. The output of the first voltage amplifier stage 508 is buffered to generate non-overlapping clock signals for the second voltage amplifier stage 510, which provides the supply Vrefx4 for the 2Vref-to-4Vref level shifter 518. It should be noted again that overlapping clock signals can also be used for the clock signals in the disclosed embodiments. The output of the second level shifter 518 is buffered and drives the multi-stage charge pump 506 via the drivers 520.

[0047] Each stage of the voltage amplifier circuit 504 and the charge pump 506 adds the clock voltage to the reference voltage. In the present embodiment, the voltage amplifier circuit 504 quadruples the reference voltage input to the charge pump 506 and also quadruples the clock signals. This effectively multiplies the charge pump stages by four, as if there were four times as many stages. The voltage amplifier circuit 504 is useful in many applications, but especially in small devices to save space, as it reduces the number of charge pumps required to boost low supply voltages to a desired voltage.

[0048] It should be noted that the bias source 500 may exhibit a starting problem where the second amplifier stage 510 and the charge pump 506 load the first amplifier stage 508, and the bias source 500 may not start properly if the reference voltage is too low relative to Vth (resulting in high on-resistance for the switches) when conventional cross-coupled inverter stages are used for the voltage amplifier stages 508 and 510. The embodiments of the switching control circuit described below decouple the inverter switching control for the voltage amplifier stages 508 and 510 and use the supply voltage to improve the on-resistance Ron for a given transistor / switch size. This allows the use of very low reference voltages.Furthermore, the switch control of the amplifier stages and / or their increase, for example, a quadrupling, of the reference voltage allows subsequent stages of the 506 charge pump to be standard cross-coupled inverters that do not require a switch control circuit, such as a bootstrap circuit. Decoupling the reference voltage from the switch control also enables improvements, such as the implementation of a break-before-make function for the switches or other suitable switching controls, to increase the efficiency of the amplifier stages.

[0049] As described below, switching control circuits, such as bootstrap switches, enable Vgs = Vref + Vdd for NMOS and 2Vref - Vdd for PMOS. Furthermore, separate switching control for high-side and low-side transistors / switches enables true break-before-make operation to reduce discharge current and increase efficiency.

[0050] Fig. Figure 6 is a representation of a voltage amplifier stage 600, such as the first voltage amplifier stage 508, according to an exemplary embodiment. Fig. Figure 7 shows a representation of a first switching control circuit 700 according to an exemplary embodiment. The first switching control circuit 700 can be coupled to a voltage source-based clock generator 710. The first switching control circuit 700 can be integrated into the voltage amplifier stage 600, as described below. Fig. Figure 8 shows a representation of a second switching control circuit 800 according to an exemplary embodiment. The second switching control circuit 800 can be coupled to the voltage source-based clock generator 710. The second switching control circuit 800 can be integrated into the voltage amplifier stage 600, as described below. Fig. Figure 9 is an example diagram of signals 900 applied to the voltage amplifier stage 600 according to an exemplary embodiment. The voltage designations 0 V and VREF represent a specific state and change due to the phase-shifted clock signals. While the designations 0 V and VREF are used for the voltages across capacitors C1 and C2 of the voltage amplifier stage 600, other voltages, such as CLK, may be used in other embodiments. REF_A and CLK REF_B .

[0051] In general, the voltage amplifier stage 600 comprises at least two transistors, each with a gate and a source. Each transistor can be part of an inverter, such as inverters I1 and I2 described above. The transistors / inverters are typically cross-coupled. However, the voltage amplifier stage 600 also includes a switching control circuit, such as the switching control circuit 700 and / or 800, which is coupled between the gates of the at least two transistors. The switching control circuit controls at least two transistors independently of the reference voltage. The switching control circuit is considered a switching control circuit because the transistors function as switches, and the switching control circuit controls the switching function of the transistors.

[0052] In one embodiment, the transistors comprise a first PMOS transistor with a gate, a first NMOS transistor with a gate, a second PMOS transistor with a gate, and a second NMOS transistor with a gate. The switching control circuit comprises a first switching control circuit 700 coupled between the gate of the first PMOS transistor and the gate of the second PMOS transistor, and a second switching control circuit 800 coupled between the gate of the first NMOS transistor and the gate of the second NMOS transistor. The first switching control circuit 700 can be an inverting clock amplifier that provides an inverted amplified clock voltage signal to the gate of the first PMOS transistor and the gate of the second PMOS transistor. The second switching control circuit 800 can be a clock amplifier that provides an amplified clock voltage signal to the gate of the first NMOS transistor and the gate of the second NMOS transistor.

[0053] In an exemplary embodiment, the amplifier stage 600 comprises a first voltage amplifier capacitor C1 and a second voltage amplifier capacitor C2, which are controlled by corresponding complementary clock generators F1 and F2. The complementary clock generators control the charging and discharging of the respective capacitors.

[0054] The switching control circuits make the gate-source voltage of the transistors independent of the reference voltage. For example, a transistor switches on when Vgs is higher than a threshold voltage. The switching control circuits turn the transistors on and off based on a gate voltage Vg, which makes the gate control independent of a reference voltage applied to the source. The switching control circuit sets the Vgs independently of the reference voltage because the reference voltage at the transistor source is inverted from the transistor gate voltage.

[0055] More precisely, the switching control circuit sets Vgs based on a voltage derived from a source voltage that differs from the reference voltage. For example, in an NMOS transistor: If the source voltage Vs=Vref and the gate voltage Vg=Vdd+Vref If it is, then the gate-source voltage is Vgs=(Vref+Vdd)−Vref, Vdd turns on the gate when it is higher than the required threshold voltage Vth. Therefore, Vgs is independent of the reference voltage Vref relative to the gate voltage. In particular, Vgs is equal to Vdd regardless of the value of Vref.

[0056] Here too, the switching control circuit adjusts a gate-source voltage based on the reference voltage and a voltage different from the reference voltage. In an NMOS transistor, for example, the switching control circuit increases a gate-source voltage Vgs based on the reference voltage and another voltage different from the reference voltage, which charges the capacitors of the voltage amplifier stage 600. The switching control circuit decouples the control of the transistor's on / off function from the reference voltage and controls the switching using a voltage source with a different voltage than the reference voltage. The switching voltage control circuit can set a gate-off voltage based on the reference voltage and a gate-on voltage based on the combination of the reference voltage and the source voltage.It decouples the voltage amplifier switching control from the reference voltage and controls the switching circuitry using a voltage source with a different voltage than the reference voltage. The switching control circuit can also control a voltage applied to the gate of a PMOS transistor separately from a voltage applied to the gate of an NMOS transistor.

[0057] According to one possible embodiment, the first switching control circuit 700 can be an inverted clock amplifier, for example, a type of voltage inverter switching control circuit, which can also be considered a bootstrap switching control circuit for the PMOS. The first switching control circuit 700 is connected to 2Vref to lower it by Vdd. The first switching control circuit 700 supplies the signals F1HP and F2HP to the gates PMOS1 and PMOS2.

[0058] The second switching control circuit 800 can be a clock amplifier, which can be a type of voltage doubler or adder switching control, and can also be considered a bootstrap switching control for the NMOS. The second switching control circuit 800 adds a clocked source voltage Vdd to the reference voltage Vref. This makes Vdd Vgs for the NMOS. The second switching circuit supplies the signals F1H and F2H to the gates NMOS1 and NMOS2.

[0059] Referring to signals 900 in Fig. Figure 9 represents F1 and F2 as pump capacitor inputs, which are clocked Vref signals supplied by a clock generator to capacitors C1 and C2. F1 and F2 provide the main clock signal at the reference voltage to the voltage amplifier stage 600. For example, overlapping clock signals are fed into inverters that operate at Vref. In subsequent voltage amplifier stages, the voltages F1 and F2 can be higher, for example, 2 x Vref, and even higher depending on the number of stages.

[0060] F2_VDD and F1_VDD represent clock signals for switching control circuits, which are clocked source voltages supplied to the first and second switching control circuits 700 and 800. These signals supply Vdd as reference signals, for example, source signals with different phases that are in phase with F1 and F2, to the first and second switching control circuits 700 and 800. They are driven by a VDD-based clock.

[0061] F1H and F2H represent voltages from the second switching control circuit 800, applied to the NMOS1 and NMOS2 gates. In one possible implementation, F1H and F2H can be considered NMOS bootstrap switching control signals. F1HP and F2HP represent voltages from the first switching control circuit 700 applied to the PMOS1 and PMOS2 gates. For the PMOS gates, one cycle increases by 2 Vref and decreases by 2 Vref minus Vdd, resulting in a fluctuation range from 2 Vref to 2 Vref minus Vdd. For the NMOS gates, one cycle increases by Vref plus Vdd and decreases by Vref, resulting in a fluctuation range from Vref + Vdd to Vref.

[0062] Fig. Figure 10 is an illustrative representation of a bootstrap circuit 1000 according to an exemplary embodiment. The transistor M 11 functions as a switched capacitor circuit, with the gate of transistor M 11 It is bootstrapped. In the first cycle, C bCharged from VDD to ground, then C b in the other cycle of V in with the gate of M 11 connected. In this case, when the switch is in the sampling cycle, Vgs of M 11 regardless of the value of V in equal V DD +V in This results in a constant on-resistance R. on of the switch regardless of V in Would the gate of M be used instead? 11 in each cycle of V DD If switched to ground, Vgs of M would be 11 equal V DD -V in , and R on would be caused by the relative voltage difference between V DD and V IN certainly.

[0063] Fig. Figure 11 is an exemplary representation of a bias source 1100 according to an exemplary embodiment. The bias source 1100 comprises elements of the bias source 500 as well as switching control circuits SCP and SCN. In particular, the bias source 1100 comprises the multi-stage charge pump 506, the voltage amplifier stages 508 and 510, a clock generator 1002, and the switching control circuits SCP and SCN. The voltage amplifier stages 508 and 510 comprise PMOS switching control circuits SCP and NMOS switching control circuits SCN, which perform functions of the switching control circuits 700 and 800 described above. A clock signal provided by the clock generator 1002 is fed into the respective voltage amplifier stages 508 and 510 by the 1x CLK drivers and the 2x CLK drivers.The clock signal supplied to the charge pump stages of the multi-stage charge pump 506 is routed by 4 x CLK drivers, which receive the 4 x Vref output from the voltage amplifier stages 508 and 510.

[0064] Fig.Figure 12 is an exemplary representation of a bias source 1200 comprising a multiplexer according to an exemplary embodiment. The bias source 1100 comprises elements of the bias sources 500 and 1100, as well as a multiplexer 1202. The multiplexer 1202 selectively activates a voltage amplifier output signal supplied to the charge pump by at least one voltage amplifier stage of the plurality of voltage amplifier stages. The voltage amplifier output signal can be a multiplied reference voltage signal and / or an amplified clock signal. For example, the multiplexer 1202 can select Vref, Vrefx2, or Vrefx4 as the voltage supplied to the clock generators 520 and / or the input of the multi-stage charge pump 506.

[0065] At least some of the procedures of this disclosure can be implemented on a programmed processor. However, the controls, blocks, and modules can also be implemented on a general-purpose or specialized computer, a programmed microprocessor or microcontroller and peripheral integrated circuit elements, an integrated circuit, an electronic hardware or logic circuit such as a circuit with discrete elements, a programmable logic device, software, firmware, or the like. In general, any device on which a finite state machine is located that is capable of implementing the flowcharts shown in the figures can be used to implement the functions of this disclosure.

[0066] Although this disclosure has been described with reference to specific embodiments, it is obvious to those skilled in the art that many alternatives, modifications, and variations are possible. For example, various components of the embodiments can be exchanged, added, or replaced in the other embodiments. Furthermore, not all elements of each figure are necessary for the operation of the disclosed embodiments. For instance, a person skilled in the art of the disclosed embodiments would be able to create and utilize the teachings of the disclosure simply by using the elements of the independent claims. Accordingly, the embodiments of the disclosure set forth herein are to be understood as illustrative and not as limiting. Various modifications can be made without departing from the spirit and scope of the disclosure.

[0067] In this document, relational terms such as "first," "second," and the like may be used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between such entities or actions. The expressions "at least one of," "at least one selected from the group of," or "at least one selected from," followed by a list, are defined to mean one, some, or all, but not necessarily all, of the items in the list.The terms "comprises," "comprehensive," "including," or other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements may contain not only those elements but also other elements not expressly listed or inherent in that process, method, article, or apparatus. An element preceded by "a," "an," or similar prefix does not, without further limitations, preclude the existence of additional identical elements in the process, method, article, or apparatus comprising that element. Furthermore, the term "another" is defined as at least one second or more. The terms "including," "with," and similar prefixes, as used herein, are defined as "comprehensive."Approximation terms such as "approximately," "close," "essentially," and / or other related terms are, unless otherwise defined, defined as a range within + / - 5% of the approximate element, a range within + / - 10% of the approximate element, and / or a range close enough to the approximate element to achieve an intended result. All elements of the disclosed embodiments may be modified by such terms. Furthermore, the background section is not recognized as prior art but corresponds to the inventor's understanding of the context of some embodiments at the time of filing and includes the inventor's own knowledge of any problems with existing technologies and / or problems encountered in the inventor's own work.

Claims

[1] Sensor component, comprising: a case; an electrical interface located on the outside of the housing; a capacitive transducer arranged in the housing, the capacitive transducer comprising a first electrode and a second electrode; and an electrical circuit arranged in the housing and electrically connected to the capacitive transducer and the electrical interface, wherein the electrical circuit comprises a bias source connected to the first electrode, the bias source comprising: a charge pump that includes a clock input; a reference voltage source that provides a reference voltage; a clock circuit that outputs a clock signal with a clock voltage; and A voltage amplifier circuit coupled to the charge pump and the reference voltage source, wherein the voltage amplifier circuit receives the reference voltage and the clock signal, increases the reference voltage, and increases a voltage of the clock signal supplied to the clock input of the charge pump based on the increased reference voltage. [2] Sensor component according to claim 1, wherein the charge pump comprises a charge pump input and the voltage amplifier circuit supplies the increased reference voltage to the charge pump input. [3] Sensor component according to claim 1 or 2, wherein the voltage amplifier circuit comprises a plurality of voltage amplifier stages, wherein a first voltage amplifier stage increases a clock voltage supplied to a second voltage amplifier stage. [4] Sensor component according to claim 3, wherein the first voltage amplifier stage increases the reference voltage and supplies the increased reference voltage to the second voltage amplifier stage. [5] Sensor component according to claim 4, wherein The voltage amplifier circuit includes a voltage level shifter that is coupled to an output of the first voltage amplifier stage and to a clock input of the second voltage amplifier stage, and The voltage level shifter increases the clock voltage supplied to the second voltage amplifier stage based on an increased reference voltage output by the first voltage amplifier stage. [6] Sensor component according to claim 3, wherein the electrical circuit comprises a multiplexer which selectively releases a voltage amplifier output signal, provided by at least one voltage amplifier stage of the plurality of voltage amplifier stages, to the charge pump. [7] Sensor component according to one of claims 1-6, wherein the voltage amplifier circuit comprises: at least two transistors, each transistor comprising a gate and a source; and a switching control circuit that is connected between the gates of the at least two transistors, wherein the switching control circuit controls the at least two transistors independently of the reference voltage. [8] Sensor component according to claim 7, wherein the switching control circuit controls the at least two transistors independently of the reference voltage by making a gate-source voltage of the at least two transistors independent of the reference voltage. [9] Sensor component according to claim 7, wherein at least two transistors comprise a PMOS transistor and an NMOS transistor, and wherein the switching control circuit separately controls a voltage applied to a gate of the PMOS transistor from a voltage applied to a gate of the NMOS transistor. [10] Sensor component according to claim 7, including at least two transistors: a first PMOS transistor with a gate; a first NMOS transistor with a gate; a second PMOS transistor with a gate; and a second NMOS transistor with a gate, and the switching control circuit includes: a first switching circuit coupled between the gate of the first PMOS transistor and the gate of the second PMOS transistor; and a second switching circuit coupled between the gate of the first NMOS transistor and the gate of the second NMOS transistor. [11] Sensor component according to claim 10, wherein the first switching circuit comprises an inverted clock amplifier which supplies an inverted amplified clock voltage as a voltage source to the gate of the first PMOS transistor and the gate of the second PMOS transistor, and wherein the second switching circuit includes a clock amplifier which supplies an amplified clocked voltage signal to the gate of the first NMOS transistor and the gate of the second NMOS transistor. [12] Sensor component according to any one of claims 1 to 11, wherein the voltage amplifier circuit comprises a first voltage amplifier capacitor and a second voltage amplifier capacitor which are controlled by corresponding complementary clock generators, wherein the complementary clock generators control the charging and discharging of each respective capacitor. [13] Sensor component according to any one of claims 1 to 11, wherein the charge pump includes an output and wherein the bias source includes a low-pass filter coupled between the charge pump output and the capacitive transducer. [14] Sensor component according to any one of claims 1 to 11, wherein the electrical circuit comprises a non-inverting amplifier having an input coupled to the capacitive transducer, wherein the non-inverting amplifier has an input impedance of more than 1 TΩ. [15] Sensor component, comprising: a housing with a sound opening; an electrical interface located on the outside of the housing; a microelectromechanical system (MEMS) transducer arranged above the sound opening, wherein the MEMS transducer divides the housing into a front volume acoustically coupled to the sound opening and a rear volume on one side of the MEMS transducer opposite the sound opening; and an electrical circuit arranged in the housing and electrically connected to the MEMS transducer and the electrical interface, wherein the electrical circuit comprises a bias source connected to a first electrode of the MEMS transducer, the bias source comprising: a charge pump comprising a plurality of charge pump stages, each charge pump stage comprising a charge pump stage clock input; a reference voltage source that provides a reference voltage; a clock circuit that outputs a clock signal with a clock voltage; and a voltage amplifier circuit coupled to the charge pump and the reference voltage source, wherein the voltage amplifier circuit receives the clock signal and increases a voltage of the clock signal provided to each charge pump stage clock input, based on the reference voltage.

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