METHOD FOR SWITCHING A CYCLE IN A POWER TRANSISTOR CIRCUIT

Description

[0001] Power transistors are used in electronic ballasts and transformers, among other applications. They are designed to switch and / or control large currents. If currents exceed the capacity of a single power transistor, the current is typically distributed across multiple transistors in a circuit. Due to the design of power transistors, asymmetrical heating of one of them can occur, as the individual transistors typically exhibit at least slightly different characteristics, resulting in varying levels of switching and conduction losses. Switching a power transistor into a conducting state incurs switching losses, causing it to heat up.Such heating of the power transistor leads, on the one hand, to an increase in conduction losses and, on the other hand, to a decrease in the threshold voltage at which the power transistor conducts current.

[0002] In a parallel circuit of several power transistors, one of the transistors typically exhibits the lowest threshold voltage due to component variations. As a result, this transistor carries almost all of the switching losses of the circuit. This leads to an asymmetrical distribution of switching losses and thus to asymmetrical heating across the circuit.

[0003] Known solutions to the problem of asymmetric heating include fast switching of the power transistors, whereby the parasitic inductive properties lead to a certain symmetrization of the switching losses.

[0004] Alternatively, power transistors are used which are selected for a high degree of uniformity in their properties or characteristics and which therefore exhibit a low variation in their characteristics, but are expensive due to the necessary selection effort.

[0005] DE 10 2013 220 842 A1 discloses a method for switching a cycle in a power transistor circuit, in particular in a parallel circuit of power transistors. The method involves specifying a switching time difference and switching the power transistors at two switching times, which are separated from each other by the switching time difference.

[0006] EP 2 587 670 A1 discloses a method for switching a cycle in a power transistor circuit according to the preamble of claim 1.

[0007] The object of the present invention is to provide an improved method for switching a cycle in a power transistor circuit.

[0008] The problem is solved according to the invention by a method having the features of claim 1.

[0009] Beneficial further training is subject to dependent claims.

[0010] In a method according to the invention for switching a cycle in a power transistor circuit, which has at least two, for example three, power transistors connected in parallel, for example MOSFETs or IGBTs, wherein the power transistors each have a gate, the gates are driven with at least three control values ​​that are different from each other and from zero. In a switch-on sequence of the parallel-connected power transistors, a first of the power transistors is initially driven with a higher control value than the other power transistor or the other power transistors, so that a gate voltage of the first power transistor exceeds a threshold voltage first, that is, before the gate voltage of the other power transistor or the other power transistors reaches the threshold voltage.

[0011] In one embodiment, the other power transistor(s) is / are controlled by means of the control value used in such a way that its / their gate voltage remains below the threshold voltage at least until the gate voltage of the first power transistor has reached a Miller plateau.

[0012] In one embodiment, during a switch-off sequence of the parallel-connected power transistors, a first of the power transistors is initially driven with a lower control value than the other power transistor or the other power transistors, so that a gate voltage of the first power transistor reaches a Miller plateau last, that is, after the gate voltage of the other power transistor or the other power transistors has reached or fallen below the Miller plateau.

[0013] In one embodiment, a gate current or a gate voltage change rate is used as the control value.

[0014] In one embodiment, the parallel-connected power transistors are alternately driven with a higher control value as the first power transistor in the switch-on sequence and / or alternately driven with a lower control value as the first power transistor in the switch-off sequence via successive pulse width modulation clock periods.

[0015] In one embodiment, within each of the pulse width modulation clock periods, one of the power transistors is initially controlled with a higher control value as the first power transistor in the switch-on sequence, and also is initially controlled with a lower control value as the first power transistor in the switch-off sequence.

[0016] In one embodiment, within each of the pulse width modulation clock periods, one of the power transistors is initially controlled with a higher control value as the first power transistor in the switch-on sequence, and in the switch-off sequence another of the power transistors is initially controlled with a lower control value as the first power transistor.

[0017] In one embodiment, during the power-on sequence, when a predetermined value is exceeded and until the Miller plateau is reached by the gate voltage of the first power transistor, the first power transistor is driven with a lower control value than the other power transistor or the other power transistors, whereby the control values ​​of all parallel-connected power transistors are subsequently increased.

[0018] In one embodiment, during the turn-off sequence, at or shortly before the gate voltage of the other power transistor(s) drops to zero, the gate voltage of the first power transistor is reduced to a lower control value and the gate voltage of the other power transistor(s) is reduced to zero.

[0019] In one embodiment, the gates are controlled by means of an ASIC. For example, the ASIC contains driver circuits according to the control device and method described in WO 2014 / 173969 A1, in particular according to the Figure 1 and 3 to 18 and the description on pages 8 to 26. WO 2014 / 173969 A1 is hereby incorporated in its entirety by reference into the present patent application.

[0020] The method according to the invention makes it possible to symmetrize the switching losses between parallel-connected power transistors and simultaneously reduce switching times. The uniform distribution of power losses across the parallel-connected power transistors reduces the maximum power loss for each of the power transistors.

[0021] Exemplary embodiments of the invention are explained in more detail with reference to the drawings. These show: Fig. 1 a schematic view of a bridge circuit made of power transistors with a control circuit, Fig. 2 a schematic view of a half-bridge made of Figure 1Fig. 3 a diagram with signal waveforms for a power transistor during a switch-on sequence, Fig. 4 a diagram with signal waveforms for a power transistor during a switch-off sequence, Fig. 5 a diagram with signal waveforms for three parallel-connected power transistors during a switch-on sequence, and Fig. 6 a diagram with signal waveforms for three parallel-connected power transistors during a switch-off sequence.

[0022] Corresponding parts are provided with the same reference numerals in all figures.

[0023] Figure 1Figure 1 shows a schematic view of a bridge circuit 1, for example, for a power inverter. The bridge circuit 1 comprises three half-bridges HB1, HB2, HB3, each connected between a battery potential Vbatt and a ground potential PGND, and each having an output signal PH1, PH2, PH3. Each of the half-bridges HB1, HB2, HB3 is driven by a driver circuit GD1, GD2, GD3, which is controlled by a control unit 2.

[0024] Figure 2 shows a schematic view of one of the half-bridges HB1 and the associated driver circuit GD1. Figure 1 The half-bridge HB1 has three parallel external branches 3, each of which is subdivided into sub-branches 3.1 and 3.2. Each sub-branch 3.1 and 3.2 of each external branch 3 contains an electronic component M1, M2, M3, M4, M5, or M6, configured to output a signal PH1 and equipped with a control connection GL1, GL2, GL3, GH1, GH2, or GH3.

[0025] Each of the electronic components M1, M2, M3, M4, M5, M6 is located in the Figure 2 The illustrated embodiment is designed as a MOSFET (metal-oxide-semiconductor field-effect transistor). In this case, the control signal S controls a gate current Ig in the gate of the MOSFET or, alternatively, a gate voltage change rate Vg' (time derivative) of a gate voltage Vg between gate and source or of a gate potential at the gate of the MOSFET.

[0026] In this case, the output signal PH1 is a drain-source voltage between the drain and source of the MOSFET.

[0027] Alternatively, instead of a MOSFET, an IGBT (bipolar transistor with insulated gate electrode) can be used as an electronic component with a corresponding control signal and output signal PH1.

[0028] The output signals PH1 of the electronic components M1, M2, M3, M4, M5, M6 control an electric current through an electrical load and / or an electrical voltage applied to the electrical load. For this purpose, the electronic components M1, M2, M3, M4, M5, M6 are switched on and off using pulse width modulation (PWM).

[0029] Each of the electronic components M1, M2, M3, M4, M5, M6 is connected to the driver circuit GD1, which can be configured as an ASIC. Within the driver circuit GD1, driver units GD1.1, GD1.2, GD1.3 are provided for controlling one of the external branches 3 each. A control logic 4 controls the driver units GD1.1, GD1.2, GD1.3. The driver circuits GD1, GD2, GD3 can each be configured to include six configurable constant current sources, by means of which at least three different constant current levels can be set for each of the electronic components M1, M2, M3, M4, M5, M6. For example, the driver circuits GD1, GD2, GD3 are configured according to the control device and method described in WO 2014 / 173969 A1, in particular according to the Figure 1 and 3 to 18 and the description on pages 8 to 26.

[0030] When switching three electronic components M1, M2, M3, M4, M5, M6 connected in parallel, for example MOSFETs or IGBTs, a uniform power distribution across the parallel electronic components M1, M2, M3, M4, M5, M6 is desired. Due to component tolerances, the electronic components M1, M2, M3, M4, M5, M6 do not switch simultaneously. One of the three electronic components M1, M2, M3, M4, M5, M6 always switches faster than the others and must therefore bear the switching losses alone, resulting in a non-uniform power distribution across the parallel electronic components M1, M2, M3, M4, M5, M6.

[0031] Figure 3 is a diagram with signal waveforms for an electronic component M1, M2, M3, M4, M5, M6, for example a power transistor, in particular a MOSFET or IGBT during a power-on sequence.

[0032] In a first implementation variant, a control signal S controls the gate current Ig. To switch on the electronic component M1, M2, M3, M4, M5, M6, a first control value Ig1, a second control value Ig2, and a third control value Ig3 are specified for the gate current Ig. After a level change time t0, the gate current Ig is initially driven from zero to the first control value Ig1. The gate current Ig is then held at the first control value Ig1 until a first switching time t1. At the first switching time t1, the gate current Ig is driven to the second control value Ig2. The gate current Ig is then held at the second control value Ig2 until a second switching time t2. At the second switching time t2, the gate current Ig is driven to the third control value Ig3. After that, the gate current Ig is held at the third control value Ig3 until the gate voltage Vg reaches a gate voltage end value at an end value time t3.After that, the gate current Ig drops to zero.

[0033] The control values ​​Ig1, Ig2, and Ig3 can be suitably preset depending on the properties of bridge circuit 1, so that they enable a reduction in the oscillations of the output signal. For example, they are chosen such that Ig2 < Ig1 < Ig3.

[0034] In a second implementation variant, the control signal S controls the gate voltage change rate Vg'. Analogous to the first implementation variant, a first control value Vg1', a second control value Vg2', and a third control value Vg3' of the gate voltage change rate Vg' are specified. These three control values ​​Vg1', Vg2', Vg3' are used analogously to the control values ​​Ig1, Ig2, Ig3 of the first implementation variant to control the electronic component M1, M2, M3, M4, M5, M6, i.e., the gate voltage Vg is changed between the level change time t0 and a first switching time t1 by the first control value Vg1', between the first switching time t1 and a second switching time t2 by the second control value Vg2', and from the second switching time t2 until a final gate voltage value is reached by the third control value Vg3'.

[0035] In both implementation variants, the switching times t1 and t2 can be determined based on a measured amplitude value in such a way as to limit the oscillation amplitudes of the output signal PH1. To determine the first switching time tl, the oscillation amplitudes during a first time window, extending from the level change time t0 to the second switching time t2, are evaluated. To determine the second switching time t2, the oscillation amplitudes during a second time window, extending from the second switching time t2 to the final value time t3, are evaluated for a single amplitude value. The respective amplitude values ​​are measured during each PWM clock cycle and used to determine the switching times t1 and t2 of the following clock cycle in order to limit the oscillation amplitudes.For the switching times t1 and t2, two limit values ​​can be specified, and the switching times t1 and t2 can be determined such that the first switching time t1 does not fall below the first limit value and the second switching time t2 does not exceed the second limit value. The first limit value thus specifies a lower limit for the first switching time t1, and the second limit value specifies an upper limit for the second switching time t2. The limit values ​​can be specified such that switching on the electronic component M1, M2, M3, M4, M5, M6 is not prevented by a first switching time t1 that is too low or a second switching time t2 that is too high.

[0036] In one embodiment, during a first pulse-width modulation (PWM) cycle, when switching on the electronic components M1, M2, M3 of sub-branches 3.1 connected to ground potential (PGND), electronic component M1 is configured to have a larger control value Vg1', Vg2', Vg3' or Ig1, lg2, Ig3 during the period from t0 to t1 than electronic components M2 and M3. This ensures that electronic component M1 absorbs all switching losses. In a subsequent PWM cycle, when switching on the electronic components M1, M2, M3 connected to ground potential (PGND), electronic component M2 is configured to have a larger control value Vg1', Vg2', Vg3' or Ig1, lg2, Ig3 during the period from t0 to t1 than electronic components M1 and M3. This ensures that the electronic component M2 bears all switching losses.In a subsequent pulse-width modulation (PWM) cycle, when the electronic components M1, M2, and M3 connected to ground potential (PGND) are switched on, electronic component M3 is configured to have a larger control value (Vg1', Vg2', Vg3' or Ig1, Ig2, Ig3) than electronic components M1 and M2 during the period from t0 to t1. This ensures that electronic component M3 absorbs all switching losses. The same procedure is applied when the electronic components M4, M5, and M6 connected to battery potential (Vbatt) are switched on in sub-branches 3.2. In each PWM cycle, the electronic component M1, M2, M3, M4, M5, or M6 that is switched on first changes as a result of the described control by the driver circuits GD1, GD2, and GD3.

[0037] In order to keep the total load current I_LOAD in the first electronic component switched on M1, M2, M3, M4, M5, M6 of sub-branches 3.1 or 3.2, the respective two other electronic components M1, M2, M3, M4, M5, M6 are kept below their threshold voltage V_TH until the first electronic component switched on M1, M2, M3, M4, M5, M6 reaches its Miller plateau Vg_PLAT.

[0038] Figure 4 shows a diagram with signal waveforms for an electronic component M1, M2, M3, M4, M5, M6, for example a power transistor, in particular a MOSFET or IGBT during a switch-off sequence.

[0039] In a first implementation variant, a control signal S controls the gate current Ig. To switch off the electronic component M1, M2, M3, M4, M5, M6, a first control value Ig1, a second control value Ig2, and a third control value Ig3 are specified for the gate current Ig. After a level change time t0, the gate current Ig is initially driven from zero to the first control value Ig1. The gate current Ig is then held at the first control value Ig1 until a first switching time t1. At the first switching time t1, the gate current Ig is driven to the second control value Ig2. The gate current Ig is then held at the second control value Ig2 until a second switching time t2. At the second switching time t2, the gate current Ig is driven to the third control value Ig3. After that, the gate current Ig is held at the third control value Ig3 until the gate voltage Vg reaches a gate voltage end value at an end value time t3.After that, the gate current Ig drops to zero.

[0040] The control values ​​Ig1, Ig2, and Ig3 can be suitably preset depending on the properties of bridge circuit 1, so that they enable a reduction in the oscillations of the output signal. For example, they are chosen such that Ig2 < Ig1 < Ig3.

[0041] In a second implementation variant, the control signal S controls the gate voltage change rate Vg'. Analogous to the first implementation variant, a first control value Vg1', a second control value Vg2', and a third control value Vg3' of the gate voltage change rate Vg' are specified. These three control values ​​Vg1', Vg2', Vg3' are used analogously to the control values ​​Ig1, Ig2, Ig3 of the first implementation variant to control the electronic component M1, M2, M3, M4, M5, M6; that is, the gate voltage Vg is changed between the level change time t0 and a first switching time t1 by the first control value Vg1', between the first switching time t1 and a second switching time t2 by the second control value Vg2', and from the second switching time t2 until a final gate voltage value is reached by the third control value Vg3'.

[0042] In both implementation variants, the switching times t1 and t2 can be determined based on a measured amplitude value in such a way as to limit the oscillation amplitudes of the output signal PH1. To determine the first switching time t1, the oscillation amplitudes during a first time window, extending from the level change time t0 to the second switching time t2, are evaluated. To determine the second switching time t2, the oscillation amplitudes during a second time window, extending from the second switching time t2 to the final value time t3, are evaluated for each amplitude value. The respective amplitude values ​​are measured during each PWM clock cycle and used to determine the switching times t1 and t2 of the following clock cycle in order to limit the oscillation amplitudes.For the switching times t1 and t2, two limit values ​​can be specified, and the switching times t1 and t2 can be determined such that the first switching time t1 does not fall below the first limit value and the second switching time t2 does not exceed the second limit value. The first limit value thus specifies a lower limit for the first switching time t1, and the second limit value specifies an upper limit for the second switching time t2. The limit values ​​can be specified such that switching on the electronic component M1, M2, M3, M4, M5, M6 is not prevented by a first switching time t1 that is too low or a second switching time t2 that is too high.

[0043] When switching off the parallel connected electronic components M1, M2, M3, M4, M5, M6, the switching-off sequence is reversed compared to the switching-on sequence.

[0044] For example, in the first pulse-width modulation (PWM) cycle, when the electronic components M1, M2, and M3 of sub-branches 3.1 connected to ground potential (PGND) are switched off, electronic component M1 is configured to switch off after electronic components M2 and M3. This ensures that electronic component M1 absorbs all switching losses. In a subsequent PWM cycle, when the electronic components M1, M2, and M3 connected to ground potential (PGND) are switched off, electronic component M2 is configured to switch off after electronic components M1 and M3. This ensures that electronic component M2 absorbs all switching losses.In a subsequent pulse-width modulation (PWM) cycle, when the electronic components M1, M2, and M3 connected to ground potential (PGND) are switched off, electronic component M3 is configured to switch off after electronic components M1 and M2. This ensures that electronic component M3 absorbs all switching losses. The same procedure is applied when the electronic components M4, M5, and M6 connected to battery potential (Vbatt) are switched off in sub-branches 3.2. In each PWM cycle, the electronic component M1, M2, M3, M4, M5, or M6 that is switched off last changes as a result of the described control by the driver circuits GD1, GD2, and GD3.

[0045] Figure 5shows a diagram with signal waveforms for three parallel-connected electronic components M1, M2, M3, M4, M5, M6, for example power transistors, in particular MOSFET or IGBT power transistors during a power-on sequence.

[0046] After a level change time t0, the gate current Ig_M1 of electronic component M1 is switched from zero to the third control value Ig3, while the gate currents lg_M2 and lg_M3 of electronic components M2 and M3 are each switched from zero to the second control value Ig2, which is lower than the third control value Ig3. The gate currents Ig_M1, Ig_M2, and Ig_M3 are held at their respective values ​​until a first switching time t1. Consequently, the gate voltage Vg_M1 of electronic component M1 rises more sharply than the gate voltages Vg_M2 and Vg_M3 of electronic components M2 and M3 until the first switching time t1. The gate voltage Vg_M1 initially exceeds the threshold voltage V_TH of electronic component M1, causing a drain current ID_M1 to begin flowing through electronic component M1 and to increase.At the first switching time t1, the gate voltage Vg_M1 of the electronic component M1 reaches a value Vg_PLAT_2ND, while the gate voltages Vg_M2, Vg_M3 of the electronic components M2, M3 remain below the threshold voltage V_TH.

[0047] At the first switching time t1, the gate current Ig_M1 of electronic component M1 is reduced to the first control value Ig1, while the gate currents lg_M2, Ig_M3 of electronic components M2 and M3 are held at the second control value Ig2. The gate currents Ig_M1, Ig_M2, Ig_M3 are held at their respective values ​​until a second switching time t2. Consequently, the gate voltages Vg_M1, Vg_M2, Vg_M3 of electronic components M1, M2, M3 continue to rise until the second switching time t2, causing the drain current ID_M1 across electronic component M1 to increase further. At the second switching time t2, the gate voltage Vg_M1 of the electronic component M1 reaches the Miller plateau Vg_PLAT and the gate voltages Vg_M2, Vg_M3 of the electronic components M2 and M3 reach the threshold voltage V_TH, so that a drain current ID_M2, ID_M3 begins to flow through the electronic components M2 and M3.

[0048] At the second switching point t2, the gate current Ig_M1, Ig_M2, Ig_M3 of the electronic components M1 is increased to the third control value Ig3 or slightly below. Consequently, the drain currents ID_M2, ID_M3 of the electronic components M2 and M3 rise sharply, relieving the electronic component M1, whose drain current ID_M1 then drops, until each of the drain currents ID_M1, ID_M2, ID_M3 is one-third of the load current I_LOAD.

[0049] Figure 6 shows a diagram with signal waveforms for three parallel-connected electronic components M1, M2, M3, M4, M5, M6, for example power transistors, in particular MOSFET or IGBT power transistors during a switch-off sequence.

[0050] At a level change time t0, the gate current Ig_M1 of electronic component M1 is reduced from the third control value Ig3 to the first control value Ig1, while the gate currents lg_M2, Ig_M3 of electronic components M2 and M3 are each reduced from the third control value Ig3 to the second control value Ig2, which is higher than the first control value Ig1. As a result, the gate voltages Vg_M1, Vg_M2, Vg_M3 of electronic components M1, M2, M3 decrease until they reach the Miller plateau Vg_PLAT, with the gate voltage Vg_M1 reaching the Miller plateau Vg_PLAT slightly later than the gate voltages Vg_M2, Vg_M3. After falling below the Miller plateau Vg_PLAT, the gate voltages Vg_M2, Vg_M3 continue to drop to the threshold voltage V_TH until the first switching time t1, causing the drain currents ID_M2, ID_M3 of the electronic components M2, M3 to drop to zero.The gate voltage Vg_M1 of the electronic component M1, however, remains on the Miller plateau Vg_PLAT, so that the electronic component M1 remains switched on and the drain current ID_M1 increases as a result of the falling drain currents ID_M2, ID_M3 until the load current I_LOAD is reached.

[0051] Until the second switching time t2, the gate currents Ig_M1, Ig_M2, Ig_M3 remain at their values ​​and the gate voltages Vg_M2 and Vg_M3 of the electronic components M2 and M3 consequently drop to zero, while the gate voltage Vg_M1 of the electronic component M1 remains on the Miller plateau Vg_PLAT.

[0052] At the second switching time t2, the gate currents Ig_M2 and Ig_M3 are reduced to zero, and the gate current Ig_M1 is reduced, possibly shortly before reaching the second switching time t2, to a control value Ig0 that is greater than zero but less than the first control value Ig1. As a result, the gate voltage Vg_M1 falls below the Miller plateau Vg_PLAT, and the drain current ID_M1 also decreases. At the third switching time t3, the gate current Ig_M1 is raised back to the control value Ig1. Consequently, the gate voltage Vg_M1 and the drain current ID_M1 fall more steeply to zero.

[0053] The described method can be applied such that, in the first pulse-width modulation (PWM) cycle, when switching on the electronic components M1, M2, and M3 of sub-branches 3.1 connected to ground potential (PGND), electronic component M1 is configured to switch on before electronic components M2 and M3. This ensures that electronic component M1 absorbs all switching losses. In a subsequent PWM cycle, when switching on the electronic components M1, M2, and M3 connected to ground potential (PGND), electronic component M2 is configured to switch on before electronic components M1 and M3. This ensures that electronic component M2 absorbs all switching losses.In a subsequent pulse-width modulation (PWM) cycle, when the electronic components M1, M2, and M3 connected to ground potential (PGND) are switched on, electronic component M3 is configured to switch on before electronic components M1 and M2. This ensures that electronic component M3 absorbs all switching losses. The same procedure is applied when the electronic components M4, M5, and M6 connected to battery potential (Vbatt) are switched on in sub-branches 3.2. In each PWM cycle, the electronic component M1, M2, M3, M4, M5, or M6 that is switched on first changes as a result of the described control by the driver circuits GD1, GD2, and GD3. Similarly, when switching off, electronic components M1, M2, M3, M4, M5, and M6 are alternately switched off last.In each pulse-width modulation (PWM) cycle, the same electronic component M1, M2, M3, M4, M5, M6 can be switched on first and switched off last. Alternatively, in each PWM cycle, one of the electronic components M1, M2, M3, M4, M5, M6 can be switched on first and another of the electronic components M1, M2, M3, M4, M5, M6 can be switched off last. Reference symbol list

[0054] 1 Bridge circuit 2 Control unit 3 External branch 3.1, 3.2 Sub-branch 4 Control logic GD1, GD2, GD3 Driver circuit GD1.1, GD1.2, GD1.3 Driver unit GH1, GH2, GH3 Control connection GL1, GL2, GL3 Control connection HB1, HB2, HB3 Half-bridge, power transistor circuit ID_M1, ID_M2, ID_M3 Drain current Ig Gate current Ig0 Control value Ig1 First control value Ig2 Second control value Ig3 Third control value lg_M1, lg_M2, Ig_M3 Gate current I_LOAD Load current M1 - M6 Electronic component, power transistor PGND Ground potential PH1, PH2, PH3 Output signal PWM Pulse width modulation S Control signal t Time t0 Level change time t1 First switching time t2 second switching time t3 third switching time, final value time Vbatt battery potential Vg gate voltage Vg' gate voltage change rate Vg1' first control value Vg2' second control value Vg3' third control value Vg_M1, Vg_M2, Vg_M3 gate voltage Vg_PLAT Miller plateau Vg_PLAT_2 ND value V_TH threshold voltage

Claims

1. Method for switching a cycle in a power transistor circuit (HB1, HB2, HB3) comprising at least two power transistors (M1, M2, M3, M4, M5, M6) connected in parallel with one another, wherein the power transistors (M1, M2, M3, M4, M5, M6) each comprise a gate, which during the method are driven with at least three control values (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') which are different from one another and different from zero, characterized in that during a switch-on sequence of the power transistors (M1, M2, M3, M4, M5, M6) connected in parallel, a first of the power transistors (M1, M2, M3, M4, M5, M6) is firstly driven with a higher control value (Ig1, Ig2, Ig3, Vgl `, Vg2', Vg3') than the other power transistor (M1, M2, M3, M4, M5, M6) or the other power transistors (M1, M2, M3, M4, M5, M6), such that a gate voltage (Vg) of the first power transistor (M1, M2, M3, M4, M5, M6) is the first to exceed a threshold voltage (V_TH), and in that the power transistors (M1, M2, M3, M4, M5, M6) connected in parallel with one another are firstly driven with a higher control value (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') alternately as first power transistor (M1, M2, M3, M4, M5, M6) over successive pulse width modulation clock periods in the switch-on sequence.

2. Method according to Claim 1, wherein the other power transistor (M1, M2, M3, M4, M5, M6) or the other power transistors (M1, M2, M3, M4, M5, M6) is / are driven by means of the control value (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') used such that its / their gate voltage (Vg) remains below the threshold voltage (V_TH) at least until the gate voltage (Vg) of the first power transistor (M1, M2, M3, M4, M5, M6) has reached a Miller plateau (Vg_PLAT).

3. Method according to Claim 1 or 2, wherein during a switch-off sequence of the power transistors (M1, M2, M3, M4, M5, M6) connected in parallel, a first of the power transistors (M1, M2, M3, M4, M5, M6) is firstly driven with a lower control value (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') than the other power transistor (M1, M2, M3, M4, M5, M6) or the other power transistors (M1, M2, M3, M4, M5, M6), such that a gate voltage (Vg) of the first power transistor (M1, M2, M3, M4, M5, M6) is the last to reach a Miller plateau (Vg_PLAT), wherein the power transistors (M1, M2, M3, M4, M5, M6) connected in parallel with one another are firstly driven with a lower control value (Ig1, Ig2, Ig3, Vgl `, Vg2', Vg3') alternately as first power transistor (M1, M2, M3, M4, M5, M6) over successive pulse width modulation clock periods in the switch-off sequence.

4. Method according to any of the preceding claims, wherein a gate current (Ig) or a gate voltage change rate (Vg`) is used as control value (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3').

5. Method according to Claim 3 or 4, wherein within a respective one of the pulse width modulation clock periods one of the power transistors (M1, M2, M3, M4, M5, M6) both in the switch-on sequence is firstly driven with a higher control value (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') as first power transistor (M1, M2, M3, M4, M5, M6) and in the switch-off sequence is firstly driven with a lower control value (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') as first power transistor (M1, M2, M3, M4, M5, M6).

6. Method according to Claim 3 or 4, wherein within a respective one of the pulse width modulation clock periods one of the power transistors (M1, M2, M3, M4, M5, M6) is firstly driven with a higher control value (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') as first power transistor (M1, M2, M3, M4, M5, M6) in the switch-on sequence and another of the power transistors (M1, M2, M3, M4, M5, M6) is firstly driven with a lower control value (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') as first power transistor (M1, M2, M3, M4, M5, M6) in the switch-off sequence.

7. Method according to any of Claims 2 to 6, wherein in the switch-on sequence, when a predefined value (Vg_PLAT_2ND) is exceeded and until the Miller plateau (Vg_PLAT) is reached by the gate voltage (Vg) of the first power transistor (M1, M2, M3, M4, M5, M6), the first power transistor (M1, M2, M3, M4, M5, M6) is driven with a lower control value (Ig1, Ig2, Ig3, Vgl `, Vg2', Vg3') than the other power transistor (M1, M2, M3, M4, M5, M6) or the other power transistors (M1, M2, M3, M4, M5, M6), wherein the control values (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3`) of all the power transistors (M1, M2, M3, M4, M5, M6) connected in parallel with one another are subsequently increased.

8. Method according to any of Claims 3 to 7, wherein in the switch-off sequence, when or shortly before the gate voltage (Vg) of the other power transistor (M1, M2, M3, M4, M5, M6) or of the other power transistors (M1, M2, M3, M4, M5, M6) falls to zero, the gate voltage (Vg) of the first power transistor (M1, M2, M3, M4, M5, M6) is decreased to a lower control value (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') and the gate voltage (Vg) of the other power transistor (M1, M2, M3, M4, M5, M6) or of the other power transistors (M1, M2, M3, M4, M5, M6) is decreased to zero.

9. Method according to any of the preceding claims, wherein the gates are driven by means of an ASIC.