Circuit for checking an analog input circuit of an A / D converter

Description

AREA

[0001] The present invention relates to a circuit for testing an analog input circuit of an A / D converter. BACKGROUND

[0002] Fail-safe input / output modules (FE / O modules) that fall into Category 4 of DIN EN ISO 13849 or have risk mitigation according to DIN EN 61508 and DIN EN 61511 typically have redundant transmission channels. Therefore, the inputs and outputs, as well as the microcontrollers, in such FE / O modules are often duplicated. Faulty transmission channels can be detected on the module side through monitoring circuits and by comparing the signals transmitted over the transmission channels.

[0003] Fail-safe analog inputs are designed for the fail-safe acquisition of analog input variables. Typically, each input variable is preprocessed in analog form, and the resulting voltage, which may be proportional to the input variable, is then digitized and forwarded to a microprocessor. The microprocessor can then perform further processing, such as applying calibration data to the digitized input variable, and generate a process value, which is then transmitted to a higher-level controller. The controller can then use the process value to control an application-specific process.

[0004] It may be necessary to transfer a defined process value to the controller even if the function of an analog input is no longer fulfilled. To ensure this, however, it may be necessary to monitor the function of the components of the fail-safe I / O module during operation so that the I / O module can assume a defined state in the event of a malfunction.

[0005] US Pat. No. 5,412,385 A discloses an A / D converter device with error correction. An analog input signal is converted using an A / D converter, and the resulting digital signal is converted into an analog signal using a D / A converter, which is subtracted from the analog input signal. The difference signal is then amplified, converted again, and used to improve the accuracy of the digital signal generated by the A / D converter.

[0006] DE 103 20 717 A1 discloses a circuit arrangement and a method for verifying the proper functioning of an A / D converter designed for safety-relevant applications. The circuit arrangement includes an A / D converter that provides a digital signal from an analog input signal, a control unit that provides a reference signal from the analog input signal, a comparison unit with a comparator that compares the analog input signal with the reference signal and outputs a comparison signal based on the comparison signal, and an evaluation unit that determines a difference signal by comparing the digital signal and the comparison signal and outputs an error signal if the difference signal exceeds a predetermined threshold.

[0007] US Pat. No. 8,947,276 B1 discloses a method for testing A / D converters. A converted signal is compared with a reference signal, and the deviation between the signals is analyzed.

[0008] From DE 10 2010 029 497 A1 a method for detecting errors in an A / D converter is known, which is designed to convert an analogue input signal into a digital output signal, wherein it is provided that the digital output signal represents a number z which results from an input value Uin of the analogue input signal during an A / D conversion, wherein in the method a value range for all possible numbers z is divided into sub-ranges and a value range for all possible input values ​​Uin is divided into sub-ranges and an input value Uin and a number z corresponding thereto are each assigned to mutually corresponding sub-ranges.The method checks to which sub-range an input value Uin to be converted is assigned, and to which sub-range a number z determined by the A / D converter is assigned, whereby an error is detected if the number z and the input value Uin are assigned to sub-ranges that do not correspond to each other.

[0009] In a vehicle electronic control system known from DE 10 2008 027591 A1, a constant-voltage power supply generates a 5V low-capacity output voltage Vad, a 0V high-capacity low-precision output voltage Vif, a 3.3V high-capacity low-precision output voltage Vcp, and at least one of a 2.8V low-precision low-capacity output voltage Vup and a 3.3V high-precision high-precision output voltage Vsb. A judgment signal input circuit logically combines comparison results of divided voltages of the above output voltages Vif, Vcp, Vup, and Vsb with a divided voltage of the output voltage Vad as a reference voltage, and inputs relative voltage information ER2, ER3, ER4, and ER5 to a microprocessor. The microprocessor judges the output voltages including the comparison reference voltage and reports an abnormality. SUMMARY

[0010] The invention enriches the state of the art in this regard, as a circuit according to the invention is configured to derive two signals from an analog input variable for testing an analog input circuit of an A / D converter and to process both signals spatially separated from each other, so that they are independent of each other with regard to interference (such as potential differences or EMC interference) and with regard to processing errors triggered by faulty elements. Following preprocessing, both signals can then be compared to verify the preprocessing.

[0011] A circuit according to the invention for checking an analog input circuit of an A / D converter comprises the analog input circuit and a comparison circuit, wherein the analog input circuit is configured to generate a first derived signal and a second derived signal from an analog input signal of the analog input circuit, only the first derived signal is an input signal for the A / D converter, which digitizes the first derived signal, the first derived signal and the second derived signal are input signals for the comparison circuit, the comparison circuit is configured to check whether a deviation of the derived signals from one another lies within a tolerance range and to output an output signal dependent on the check, which can be further evaluated.

[0012] The terms "circuit" and "circuitry," as used in the description and claims, are understood to mean, in particular, a combination of electrical and / or electronic components to form a functional arrangement. Furthermore, the comparison in the comparison circuit can be hardware- or software-based, and based on analog or digital signals. For example, the comparison can be performed using a comparator or a microcontroller, and the microcontroller or an analog-to-digital converter connected upstream of the microcontroller can digitize the first derived signal and the second derived signal before the comparison. Furthermore, the verification of whether the deviation of the derived signals from each other lies within a tolerance range can be performed by calculating the difference, but also by other mathematical operations, such as summation, percentage division, or similar, which allow a comparison of the derived signals.

[0013] Furthermore, the term "signal," as used in the description and claims, refers in particular to an electrical signal, e.g., a voltage, a defined voltage range, or a specific voltage curve. Furthermore, the term "derived signal," as used in the description and claims, refers in particular to a signal that can be calculated from the signal from which it is derived using a calculation rule (e.g., a continuous function).

[0014] Preferably, the circuit comprises a switching element, wherein by closing or opening the switching element the second signal can be specifically changed or switched off in order to generate a defined error state.

[0015] The term "switching element," as used in the description and claims, refers in particular to a component configured to interrupt an electrical connection over which a signal can or will be transmitted (e.g., a transistor). Furthermore, the term "fault state," as used in the description and claims, refers in particular to a state that, if not actively generated, suggests a malfunction of the circuit or a malfunction of circuit elements. Furthermore, the term "defined fault state," as used in the description and claims, refers in particular to a state that can be actively generated and allows for verification of whether the state suggesting a malfunction is detected.

[0016] Preferably, the comparison circuit is configured to derive a difference signal from the first derived signal and the second derived signal, wherein the tolerance range specifies a value range for the difference signal.

[0017] The term "differential signal" as used in the description and claims is to be understood in particular as a voltage difference.

[0018] Preferably, the analog input circuit is configured to derive the first derived signal from a voltage drop across a first resistor and to derive the second derived signal from a voltage drop across a second resistor, wherein the first resistor and the second resistor are connected in series to an analog input of the input circuit.

[0019] Preferably, the analog input circuit comprises a first amplifier and a second amplifier, the first derived signal is an output signal of the first amplifier and the second derived signal is an output signal of the second amplifier.

[0020] Preferably, a system comprises two of said circuits, a first circuit and a second circuit, wherein the first circuit comprises a first selection circuit and the second circuit comprises a second selection circuit, wherein the first selection circuit is configured to transmit the first derived signal of the first circuit or the first derived signal of the second circuit to the A / D converter of the first circuit, wherein the second selection circuit is configured to transmit the first derived signal of the first circuit or the first derived signal of the second circuit to the A / D converter of the second circuit, wherein the system is further configured to check whether the signals digitized by the A / D converters are identical or whether a deviation of the digitized signals from one another lies within an acceptance range,when the selection circuits transmit the first derived signal of the first circuit or the first derived signal of the second circuit to the A / D converters.

[0021] A method according to the invention for digitizing a signal received at an analog input comprises deriving a first signal from the signal received at the analog input, deriving a second signal from the signal received at the analog input, amplifying the first signal, amplifying the second signal, digitizing the amplified first signal, checking whether an expected dependency of the amplified signals resulting from the derivation of the first signal and the derivation of the second signal from the received signal exists, taking into account a tolerance range, and, if the dependency of the amplified signals does not exist, generating an error signal.

[0022] The term "error signal" as used in the description and the claims is to be understood in particular as an electrical signal (e.g. a two-value signal) which signals an error and either leads to the display of the error or triggers a routine to overcome the error.

[0023] Preferably, the method further comprises amplifying a third signal which is independent of the signal received at the analog input or is generated by means of a targeted modification of the derivative of the second signal and checking whether a deviation between the amplified first signal and the amplified third signal lies outside the tolerance range.

[0024] Preferably, the method further comprises generating the error signal when the deviation between the amplified first signal and the amplified third signal is within the tolerance range.

[0025] Preferably, the method further comprises deriving a difference signal from the amplified first signal and the amplified second signal, wherein the tolerance range specifies a value range for the difference signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The invention is explained below in the detailed description using exemplary embodiments, with reference to drawings in which: Fig. 1 an exemplary circuit with a circuit for testing an analog input circuit of an A / D converter; Fig. 1a exemplary voltage curves in the Fig. 1 circuit shown; Fig. 2 a variation of the Fig. 1 shown circuit for generating a defined error condition; Fig. 3 a possible design of the analog input circuit of the Fig. 1 circuit shown; Fig. 4 another possible design of the analog input circuit of the Fig. 1 circuit shown; Fig. 5 another possible design of the analog input circuit of the Fig. 1 circuit shown; Fig. 6 another possible design of the analog input circuit of the Fig. 1 circuit shown; Fig. 7 another possible design of the analog input circuit of the Fig. 1 circuit shown; Fig. 8 a possible design of the Fig. 1 circuit shown; Fig. 9 a possible design of the Fig. 2 circuit shown; Fig. 10 a modification of the Fig. 9 shown design; Fig. 11 a system with two of the Fig. 1 shown circuits and additional selection circuits for testing the A / D converters; and Fig. 12 shows a flowchart of a process for digitizing a signal received at an analog input.

[0027] In the drawings, identical or functionally similar elements are identified by the same reference symbols. DETAILED DESCRIPTION

[0028] Fig. 1 shows a circuit 10 with a circuit 12 for testing an analog input circuit 14 of an analog / digital converter 16 (A / D converter), which may be provided in a fail-safe I / O module for controlling a process or system. As shown in Fig. 1 As shown, the analog input circuit 14 derives a first signal S1 and a second signal S2 from the input signal SE. The first signal S1 is digitized by the A / D converter 16 and read by a microcontroller 18.

[0029] To test the analog input circuit 14, the first signal S1 and the second signal S2 are processed by a comparison circuit 20, which monitors whether the deviation of the derived signals S1, S2 from each other lies within a tolerance range TOL. Based on the result of the test, an output signal SA can be generated, which can be further evaluated, for example, by the microcontroller 18 or a higher-level controller (not shown).

[0030] Fig. 1a shows example waveforms of the voltages representing the signals. The voltages representing the first signal S1 and the second signal S2 are approximately equal up to time t1, so that the differential voltage DIFF initially lies within the tolerance range TOL (delimited by the dotted lines). From time t1, the voltage representing the second signal S2 is no longer parallel to the voltage representing the first signal S1. As a result, the differential voltage DIFF lies outside the tolerance range TOL from time t2. Since the differential voltage DIFF lies outside the tolerance range TOL from time t2, the level of the output signal SA changes (e.g. as in Fig. 1a from "Low" to "High" or alternatively from "High" to "Low").

[0031] The output signal SA can be sampled by the microcontroller 18, which, based on the deviation of the signals S1, S2 from each other (i.e., if the differential voltage DIFF lies outside the tolerance range TOL), concludes that there is a defect or malfunction in the analog input circuit 14. The output signal SA indicating the defect or malfunction can then trigger a processing routine in the microcontroller 18 and cause an error signal SF to be output at an output of the microcontroller 18 (e.g., via a bus).

[0032] For example, the microcontroller 18 can switch to a predetermined (safe) operating state or bring a process controlled by the microcontroller 18 or a system controlled by the microcontroller 18 into a (safe) stable state. It is understood that the check as to whether the deviation of the derived signals S1, S2 from one another lies within the tolerance range TOL can also be performed by the microcontroller 18 if, for example, the comparison circuit 20 outputs the differential voltage DIFF instead of the output signal SA or the microcontroller 18 (as part of the comparison circuit 20) reads in the first signal S1 and the second signal S2 (or a digitized first signal and a digitized second signal) and compares them using software.

[0033] Fig. 2 shows a modification of the Fig. 1 shown circuit 12 for generating a defined error state. For this purpose, the signal path via which the second signal S2 is transmitted to the comparison circuit 20 is provided with a switching element 22 (e.g., a semiconductor switch such as a transistor) that allows the transmission of the second signal S2 to the comparison circuit 20 to be interrupted. This makes it possible to Fig. 1a shown case (by targeted control of the switching element 22).

[0034] By opening the switching element 22, instead of the second signal S2, a third signal S3, which is independent of the input signal SE (e.g., a constant voltage that lies outside the value range expected for the voltage representing the second signal 2), is transmitted to the comparison circuit 20, and the comparison circuit 20 or the error detection by the microcontroller 18 is checked. Of course, it goes without saying that instead of interrupting the transmission of the second signal S2 to the comparison circuit 20, a targeted modification of the derivation of the second signal S2 can also be carried out, so that the third signal S3, although not independent of the input signal SE, does not exhibit the dependency (on the input signal SE) expected of the second signal S2.

[0035] If, for example, the transmission of the second signal S2 to the comparison circuit 20 is interrupted by a corresponding control signal during ongoing operation, or if the derivation of the second signal S2 is deliberately disrupted / modified, it can be checked whether the comparison circuit 20 detects the error or whether the output signal SA indicates the artificially generated error. If the artificially generated error is not indicated, the generation of the error signal can be triggered, for example, by a check circuit (not shown), to indicate that the circuit 10 is not functioning correctly.

[0036] Fig. 3 shows a possible embodiment of the analog input circuit 14 of the circuit 12. The analog input circuit 14 comprises a first resistor 24a and a second resistor 24b, across which an input voltage representing the input signal SE is dropped. The voltages dropped across the resistors 24a, 24b are tapped and each fed to an amplifier 26a, 26b, which amplifies the tapped voltage and outputs the first signal S1 or the second signal S2. The ratio of the resistors 24a, 24b (R1 / R2) and the ratio of the amplification factors (V1 / V2) can be used to generate both (approximately) identical signals S1, S2 and different signals S1, S2.

[0037] For example, (approximately) identical signals S1, S2 can be generated by (approximately) equal resistors 24a, 24b and (approximately) equal amplification factors. Likewise, (approximately) identical signals S1, S2 can be generated by (approximately) different resistors 24a, 24b and correspondingly unequal amplification factors (e.g., R1 / R2=V2 / V1). If the voltages representing the signals S1, S2 differ by a certain factor, this can be taken into account by appropriately designing the comparison circuit 20 or by defining the tolerance range TOL.

[0038] Fig. 4 shows a further possible embodiment of the analog input circuit 14 of the circuit 12, which differs from that shown in Fig. 3 differs from the embodiment shown in that, in addition to the voltage drop across the first resistor 24a, the input voltage drop across both resistors 24a, 24b is tapped and fed to an amplifier 26a, 26b, which amplifies the tapped voltage and outputs the first signal S1 and the second signal S2, respectively. (Almost) identical signals S1, S2 can then be achieved by appropriately dimensioning the amplification factors of the amplifiers 26a, 26b, such as V2 / V1=(R1+R2) / R2. If the resistors 24a, 24b are, for example, identical in construction, (almost) identical signals S1, S2 can be achieved by amplifying the second signal S2 by an amplification factor that is half as large as the amplification factor of the first amplifier 26a.

[0039] Fig. 5 shows a further possible embodiment of the analog input circuit 14 of the circuit 12, which differs from that shown in Fig. 3 The second resistor 24b differs from the embodiment shown in that a third resistor 24c is connected in parallel with the second resistor 24b. This allows (almost) identical signals S1, S2 to be generated even when resistors 24a, 24b are of unequal size and have the same gain factors, or when resistors 24a, 24b are of equal size and have unequal gain factors. Furthermore, the second resistor 24b connected in parallel provides safety advantages because the resistors 24a and 24b / c are loaded differently, for example, in the event of an overcurrent, and the error signal is generated due to the different behavior of the resistors 24a, 24b, 24c in the event of an overcurrent.

[0040] Fig. 6 shows a further possible embodiment of the analog input circuit 14 of the Fig. 1 shown circuit 12, which differs from the one shown in Fig. 3 shown embodiment in that the first signal S1 and the second signal S2 are tapped at resistors in parallel current paths, wherein the parallel current paths are connected to a current mirror, so that the currents flowing through the current paths are in a fixed ratio (e.g. 1:1) to each other. Furthermore, as in Fig. 6 As shown, a fourth signal S4 is generated to detect differences between the resistances in the current paths. If the voltage representing the fourth signal S4 is outside an acceptable range, this can indicate a fault or error in the resistors 24a-24c or in the lines between the resistors 24a-24c.

[0041] In addition, the Fig. 6 The analog input circuit 14 shown includes a switching element 22, which can output a third signal S3 instead of the second signal S2. Although this third signal S3 is not independent of the input signal SE, it differs from the second signal S2. Thus, one of the parallel current paths comprises several resistors, with the second signal S2 and the third signal S3 being tapped via a different number of resistors. As a result, the voltage representing the third signal S3 differs from the voltage representing the second signal S2 by a certain factor (e.g., 0.5 or 2).

[0042] Fig. 7 shows a further possible embodiment of the analog input circuit 14 of the circuit 12, which differs from that shown in Fig. 6 The circuit shown differs in that the parallel current paths are designed in the form of a bridge circuit, each with two equally sized resistors 24d, 24f and 24e, 24g. The voltage drop across the resistor 24h arranged in the bridge branch (after optional amplification by the amplifier 26) is output as the fourth signal S4, and the voltage representing the fourth signal S4 can be used to detect differences between the resistances in the current paths. If the voltage representing the fourth signal S4 lies outside an acceptable range, this can be used to conclude that there is a fault or error in the resistors 24d-24g or in the lines between the resistors 24d-24g.

[0043] Fig. 8 shows a possible design of the Fig. 1 shown circuit 12, which is shown in Fig. 3 shown input circuit 14. The comparison circuit 20 generates, for example, an output signal SA which corresponds to the difference DIFF between the voltage representing the first signal 1 and the voltage representing the second signal, or, as in Fig. 1a shown, indicates whether the differential voltage DIFF is within or outside the tolerance range TOL.

[0044] Fig. 9 shows a possible design of the Fig. 2 shown circuit 12, which is shown in Fig. 3 The switching element 22 is integrated into the input circuit 14 such that, when the switching element 22 is open, the second signal S2 is no longer derived from the input voltage. This eliminates the dependence existing between the first signal S1 and the second signal S2 when the switching element 22 is closed, resulting in correspondingly high differential voltages DIFF occurring at high input voltages, and the deviation between the derived signals S1, S2 being outside the tolerance range TOL.

[0045] Fig. 10 shows a modification of the Fig. 9 shown circuit 12, wherein instead of generating a third signal S3 independent of the input signal, the third signal S3 is generated by a targeted change in the derivative of the second signal S2, so that the third signal S3 is not independent of the input signal SE, but does not have the dependency (on the input signal SE) expected from the second signal S2. As in Fig. 10 shown, is closed by closing the switching element 22 (analogous to the design in Fig. 5 ) a third resistor 24c is connected in parallel with the second resistor 24b, thereby changing the voltage tapped at the second resistor 24b.

[0046] Fig. 11 shows a system 28 with two of the Fig. 1 shown circuits 10 for creating redundant transmission channels, wherein in each of the circuits 10, an additional selection circuit 30a / 30b is connected upstream of the A / D converter 16a / 16b. The selection circuits 30a / 30b receive the first signals S1 of both circuits 10 on the input side and input a selected one of the first signals S1 to the respective A / D converter 16a / 16b on the output side. By inputting the same first signal S1 to both A / D converters 16a / 16b, as in Fig. 10 As illustrated by the highlighted signal paths, the A / D converters 16a / 16b are checked by comparing the digitized signals.

[0047] For this purpose, both A / D converters 16a / 16b are connected on the output side to both microcontrollers 18a / 18b, so that the microcontrollers 18a / 18b can read the output digitized data from both A / D converters 16a / 16b. The read digitized data can then be checked to determine whether any deviation between the digitized data lies within a tolerance range.

[0048] Fig. 12shows a flowchart of a process for digitizing a signal received at an analog input. The process begins with steps 32, 34 of deriving the first signal S1 from the signal SE received at the analog input and of deriving the second signal S2 from the signal SE received at the analog input, as well as the step of amplifying the first signal S1 and amplifying the second signal S2. The process then continues with step 38 of checking whether the expected dependence of the amplified signals resulting from the derivation of the first signal S1 and the derivation of the second signal S2 from the received signal SE, taking into account the tolerance range TOL. If the dependence of the amplified signals is not present, an error signal can be generated as described above.

[0049] It is understood that all features of the circuits described above can also be features of preferred embodiments of the process relating to the use of the circuit 12 for testing an analog input circuit 14 of an A / D converter 16, wherein the circuit 12 comprises the analog input circuit 14 and a comparison circuit 20 and the analog input circuit 14 is configured to generate a first derived signal S1 and a second derived signal S2 from the analog input signal SE of the analog input circuit 14.

[0050] As described above, the first derived signal S1 and the second derived signal S2 are input signals for the comparison circuit 20; but only the first derived signal S1 is an input signal for the A / D converter 16. The comparison circuit 20 can then check whether a deviation of the derived signals S1, S2 from each other lies within the tolerance range TOL and output an output signal SA dependent on the check, which can be further evaluated (e.g., by a microcontroller 18 or a higher-level control system). LIST OF REFERENCE SYMBOLS

[0051] 10Circuit 12Circuit 14Input circuit 16A / D converter 18Microcontroller 20Comparison circuit 22Switching element 24Resistance 26Amplifier 28System 30Selection circuit 32-38Process steps DIFFDifferential voltage S1First signal S2Second signal S3Third signal S4Fourth signal SEInput signal SAOutput signal TOLTolerance range

Claims

1. Switching circuit (12) for checking an analog input circuit (14) of an A / D converter (16), comprising: the analog input circuit (14); and a comparator circuit (20); wherein the analog input circuit (14) is configured to generate a first derived signal (S1) and a second derived signal (S2) from an analog input signal (SE) of the analog input circuit (14); only the first derived signal (S1) is an input signal for the A / D converter (16), which digitizes the first derived signal (S1); the first derived signal (S1) and the second derived signal (S2) are input signals for the comparator circuit (20); the comparator circuit (20) is configured to check whether a deviation of the derived signals (S1, S2) from each other lies within a tolerance range (TOL) and to output an output signal (SA) which is dependent on the check and which can be further evaluated.

2. Switching circuit (12) according to claim 1, wherein the switching circuit (12) has a switching element (22), wherein the second derived signal (S2) can be changed or deactivated in a targeted manner by closing or opening the switching element (22) in order to generate a defined error state.

3. Switching circuit (12) according to claim 1 or 2, wherein the comparator circuit (20) is configured to derive a difference signal (DIFF) from the first derived signal (S1) and the second derived signal (S2), and the tolerance range (TOL) specifies a value range for the difference signal (DIFF).

4. Switching circuit (12) according to any of claims 1 to 3, wherein the analog input circuit (14) is configured to derive the first derived signal (S1) from a voltage drop at a first resistor (24a); and to derive the second derived signal (S2) from a voltage drop at a second resistor (24b); wherein the first resistor (24a) and the second resistor (24b) are connected in series to an analog input of the input circuit (14).

5. Switching circuit (12) according to any of claims 1 to 4, wherein the analog input circuit (14) comprises a first amplifier (26a) and a second amplifier (26b); the first derived signal (S1) is an output signal of the first amplifier (26a); and the second derived signal (S2) is an output signal of the second amplifier (26b).

6. System (28), comprising: a first switching circuit (12a) according to any of claims 1 to 5; and a second switching circuit (12b) according to any of claims 1 to 5; wherein the first switching circuit (12a) comprises a first selection circuit (30a) and the second switching circuit (12b) comprises a second selection circuit (30b); wherein the first selection circuit (30a) is configured to transmit the first derived signal (S1) of the first switching circuit (12a) or the first derived signal (S1) of the second switching circuit (12b) to the A / D converter (16a) of the first switching circuit (12a); wherein the second selection circuit (30b) is configured to transmit the first derived signal (S1) of the first switching circuit (12a) or the first derived signal (S1) of the second switching circuit (12b) to the A / D converter (16b) of the second switching circuit (12b); wherein the system (28) is further configured to check whether the signals digitized by the A / D converters (16a, 16b) are identical or whether a deviation of the digitized signals from each other lies within an acceptance range when the selection circuits (30a, 30b) transmit the first derived signal (S1) of the first switching circuit (12a) or the first derived signal (S1) of the second switching circuit (12b) to the A / D converters (16a, 16b).

7. Method for digitizing a signal (SE) received at an analog input, the method comprising: deriving (32) a first signal (S1) from the signal (SE) received at the analog input; deriving (34) a second signal (S2) from the signal (SE) received at the analog input; amplifying (36) the first signal (S1); amplifying (36) the second signal (S2); digitizing the amplified first signal; checking (38) whether an expected dependency of the amplified signals resulting from the derivation of the first signal (S1) and the derivation of the second signal (S2) from the received signal (SE) is present, taking into account a tolerance range (TOL); and generating an error signal if the dependency of the amplified signals is not present.

8. Method according to claim 7, further comprising: amplifying a third signal (S3) which is independent of the signal (SE) received at the analog input or is generated by means of a targeted modification of the derivation of the second signal (S2); and checking whether a deviation between the amplified first signal (S1) and the amplified third signal (S3) lies outside the tolerance range (TOL).

9. Method according to claim 8, further comprising: generating the error signal if the deviation between the amplified first signal (S1) and the amplified third signal (S3) lies within the tolerance range (TOL).

10. Method according to any of claims 7 to 9, further comprising: deriving a difference signal (DIFF) from the amplified first signal (S1) and the amplified second signal (S2), wherein the tolerance range (TOL) specifies a value range for the difference signal (DIFF).