METHOD FOR ACCESSING A MEMORY OF AN INTEGRATED CIRCUIT, PROGRAM, DATA PROCESSING DEVICE AND NETWORK

Description

[0001] The invention relates to a method for accessing a memory of an integrated circuit by another computing device, a program, a data processing device and a network.

[0002] Known from the prior art is a system for programming a configurable semiconductor device comprising a programmable controller, a programmable computer, a connecting link, a configurable hardware device with configurable analog elements, and a memory having multiple memory locations and coupled to a programmable controller via the connecting link. This is described, for example, in EP 1 376 416 B1.

[0003] It is also known to use integrated circuits (ICs), particularly in the form of so-called FPGAs (field programmable gate arrays), to implement control functions, particularly motion control. For example, such an integrated circuit can be used to control the motion of moving elements of a coordinate measuring machine.

[0004] Also known is the use of CPU-based computing devices, in particular microcontrollers, to perform additional functions, for example to communicate with other systems or devices, to interpret commands generated and transmitted by other systems or to perform additional functions.

[0005] It is also known that for the operation of a system, for example the coordinate measuring machine explained above, both an IC-based computing device, i.e. a computing device comprising one or more integrated circuits, and a CPU-based computing device are used, whereby these communicate with each other during operation, i.e. carry out a data transmission, in particular according to a so-called SPI protocol.

[0006] The document "Masnicki Romuald: The fluency of data flow in the instrument for measurement and registration of parameters of the electrical power network, 2015 IEEE 15th Int. Conf. on Environment and Electrical Engineering (EEEIC), IEEE, June 10, 2015, pages 2040-2044, DOI: 10.1109 / EEEIC.2015.7165489" discloses data measurement and registration as well as synchronization operations in the communication between different functional blocks.

[0007] US 7,340,727 B2 discloses a method for translating hardware structure design language into a general programming language.

[0008] The document "One Technology Way: 250 kSPS, 12-Bit Impedance Converter, Network Analyzer AD5934", January 1, 2005, pages 1-32, found at http: / / www.avrfreaks.net / sites / default / files / AD5934.pdf" discloses a description of an impedance converter system.

[0009] The document "Anonymous: 6. Recommended HDL Coding Styles, January 1, 2009, found online at http: / / www.gstitt.ece.ufl.edu / courses / spring 10 / eel4712 / lectures / vhdl / gts gii51007.pdf" reveals recommendations for HDL programming.

[0010] The technical problem arises of improving communication between an IC computing device and another computing device, in particular in order to reduce the time required to execute certain functions during which the memory of the integrated circuit is accessed, as well as the effort required for memory access management.

[0011] The solution to the technical problem is achieved by the subject matter having the features of the independent claims. Further advantageous embodiments of the invention are set forth in the subclaims.

[0012] A method is proposed for accessing a memory of an integrated circuit by a further computing device. The integrated circuit can, in particular, form an IC-based computing device or a part of such an IC-based computing device. As explained in more detail below, the integrated circuit is, in particular, designed as an FPGA or forms part of an FPGA. The further computing device can, in particular, be a CPU computing device, i.e., a computing device that comprises a CPU. As also explained in more detail below, the further computing device can, in particular, be a microcontroller.

[0013] The integrated circuit and the further computing device can form a network or part of such a network. For this purpose, the integrated circuit and the further computing device can be connected to each other via data and / or signaling, in particular via suitable interfaces. This enables data transmission between these units.

[0014] Furthermore, the additional computing device accesses the memory of the integrated circuit depending on computing device-specific information.

[0015] The computing device-specific access information for accessing the integrated circuit's memory is generated from predetermined IC-specific memory information. This may mean that the computing device-specific access information is generated at runtime of the method.

[0016] Access can be either read or write, for example. This generation can also be referred to as translation.

[0017] Memory information can be information about a memory configuration, a memory structure, and / or information about addresses, in particular address values, of the memory locations. Furthermore, the memory information can include information about a variable or constant and the address assigned to that variable.

[0018] The generation of the computing device-specific access information from the predetermined IC-specific memory information can be carried out, in particular, by a so-called parsing process. In other words, IC-specific memory information, which is particularly encoded or described in an IC-specific programming language, can be translated into a computing device-specific programming language.

[0019] In particular, the generated information can be used by the additional computing device to generate a command, in particular a read command or a write command, and transmit it to the integrated circuit, which then performs the desired access depending on the transmitted information, which may be encoded in the command. The transmission can be carried out according to a desired protocol, in particular according to the previously mentioned SPI protocol. Thus, the additional computing device can generate an SPI-based command with the computing device-specific access information and transmit it to the integrated circuit, which then performs a memory access according to the command.

[0020] For example, memory information can be encoded in a command, e.g., an address value of a memory location. For example, an address value of a memory location can be encoded in a read command. When the command is executed, particularly by the circuit, a read access to the memory location can then be performed and the value stored there can be read out, for example. Alternatively, an address value of a memory location can be encoded in a write command, in which case a write access to the corresponding memory location takes place, e.g., to store a value in the memory location. The value to be stored can also be encoded in the command.

[0021] In the method, the further computing device uses the memory information to generate access commands, which are then transmitted to the integrated circuit, which can then access the memory directly, i.e. without further data processing operations for command interpretation.

[0022] If the memory information contains address values, i.e., values ​​that represent the address or position of a specific memory location, a pointer functionality is advantageously enabled by the described method. Thus, the IC-specific memory information and thus also the computing device-specific access information can include these address values, allowing the further computing device to access the corresponding memory location using the address value, in particular by encoding the address value in a corresponding access command.

[0023] This can significantly accelerate the execution of certain functions, especially those that involve accessing the integrated circuit's memory. For example, it is no longer necessary for the integrated circuit itself to determine the address or memory location to be accessed for reading or writing when a corresponding access command is transmitted from the additional computing device to the integrated circuit.

[0024] A further advantage is the automatic synchronization of the integrated circuit's memory addresses with other computing devices, which reduces the effort required for memory access management.

[0025] Also described is a method for operating a network comprising the integrated circuit and the additional computing device. In a first step, the IC-specific memory information is provided. This can be provided, for example, by a programmer. In a further step, the computing device-specific access information is generated from this IC-specific memory information. In a third step, the additional computing device accesses the memory of the integrated circuit depending on the computing device-specific access information.

[0026] In a further embodiment, the integrated circuit is embodied as an FPGA or forms part of such an FPGA. This advantageously enables rapid execution of desired functions.

[0027] Alternatively, but preferably cumulatively, the additional computing device is designed as a CPU computing device, in particular as a microcontroller. This advantageously expands the functionality and consequently the area of ​​application of a network consisting of such computing devices.

[0028] According to the invention, the IC memory information and the computing device-specific access information are each encoded in a file. The file encoding the computing device-specific access information is stored in a memory device. This memory device is accessed during compilation to generate code or code means that can be executed by the additional computing device. The memory device can be, for example, a memory device of a so-called development computing device, which can be an external computing device. The memory device can also be a memory device of the additional computing device or a memory device that the additional computing device can access. The file encoding the IC-specific memory information can, in particular, be a file used for the circuit design of the integrated circuit.This can be used, for example, to convert it into a programming file for loading the integrated circuit, whereby the programming file can be created by a so-called compilation.

[0029] The file encoding the IC-specific storage information is then used to generate the file encoding the computing device-specific access information, which is then used by the other computing device for access. This advantageously results in easily implemented generation of the desired information and efficient management of this information.

[0030] In a further embodiment, the IC-specific memory information is described using VHDL. Alternatively, but preferably cumulatively, the computing device-specific information is described using C or C++. The abbreviation VHDL refers to a hardware description language, namely the so-called Very High Speed ​​Integrated Circuit Hardware Description Language.

[0031] In particular, the file encoding the IC-specific memory information can be VHDL-based, and / or the file encoding the computing device-specific information can be C-based or C++-based. This advantageously results in a computationally simple provision and use of the desired information.

[0032] In a further embodiment, a second further computing device accesses the memory of the integrated circuit depending on further access information, wherein the further access information is or is generated from the computing device-specific access information.

[0033] Thus, further access information can be generated from the computing device-specific access information. Furthermore, the computing device-specific access information and the further access information can be described in different programming languages.

[0034] Depending on the further access information, in particular further systems or further computing devices that are different from the integrated circuit and the first further computing device can access the memory.

[0035] In particular, from the computing device-specific access information described in C or C++, further access information described in C# can be generated. This can be done, for example, by translating the previously explained file that encodes the computing device-specific access information into another file that encodes the additional access information.

[0036] In this case, the computing device that uses the additional access information can also be part of the previously explained network. Such a second additional computing device can be connected to the first additional computing device via signal and / or data technology. The second additional computing device can, in particular, also be a CPU-based computing device, in particular a further microcontroller. It is possible for the second additional computing device to be connected to the integrated circuit via data and / or signal technology, not directly, but only via the first additional computing device.

[0037] This advantageously enables other computing devices, for example computing devices of PCs, in particular in the form of portable devices, to access the memory of the integrated circuit and the information stored therein.

[0038] The translation of the access information of the additional computing device into the access information for the second additional computing device can take place during the runtime of the method. For example, a function executed by the second additional computing device, such as a diagnostic function, can access the memory of the integrated circuit via the first additional computing device based on this translation performed during runtime.

[0039] Thus, a user, such as service personnel, can connect a PC containing the second additional computing device to the network described above and access the integrated circuit's memory quickly and easily. This can then advantageously reduce the time required for the second additional computing device to execute functions, such as diagnostic functions.

[0040] Further according to the invention, the computing device-specific access information is generated by executing a predetermined translation algorithm. This can be performed, for example, such that predetermined characters or character strings contained in the IC-specific memory information description correspond to characters or character strings assigned to them according to the computing device-specific access information description. The further access information can also be generated from the computing device-specific access information in a corresponding manner.

[0041] In particular, the translation algorithm can be a search-and-replace algorithm, where predetermined characters or character sequences are searched for and replaced with other predetermined characters or character sequences, as previously explained. This advantageously results in a uniform, fast, and accurate generation of the required information, which in turn enables reliable memory access.

[0042] In a further embodiment, the IC-specific memory information comprises information about a memory size of the memory. This memory can comprise one or more memory areas, in particular an enum area and / or a so-called buffer memory area and / or a so-called constant memory area. A memory area can comprise one or more memory blocks, wherein a memory block in turn can comprise one or more memory locations. For example, it is possible for a constant memory area to comprise 8 memory blocks. Furthermore, it is possible for a memory block to comprise 8 memory locations (address memory locations). Furthermore, it is possible for a size of the buffer memory area or a size of the buffer and enum memory area to comprise 2 13< memory locations.

[0043] Alternatively, but preferably cumulatively, the memory information includes information about a number and size of memory areas and / or about a number and size of memory blocks of the memory or a memory area. Further alternatively, but preferably cumulatively, the information includes information about a size of a constant memory area and / or about a size of a buffer memory area.

[0044] Different access rights can exist for different memory areas. For example, it is possible for memory locations in a constant memory area to be accessible during all functions executed by the integrated circuit. Furthermore, it is possible for an enum memory area to be accessible only during the execution of certain functions.

[0045] The constant memory area can provide a hardware address space. In particular, the previously explained address values ​​of memory locations can be stored in the constant memory area.

[0046] For example, the size of a memory area can be encoded in bits. Information about the number of memory areas and / or memory blocks can also be encoded in bits.

[0047] Individual, several, or all of the above-mentioned information advantageously enables simple and reliable translation and thus the generation of computing device-specific access information. Thus, based on this information, an address value for a specific memory location can be determined and, as previously explained, used to access the value stored at that memory location.

[0048] According to the invention, the IC-specific memory information comprises information about memory locations of a memory block of a first memory area, in particular the constant memory area. These memory locations can be address memory locations for the previously explained address values. According to the invention, this memory information comprises or forms these address values ​​or a value for calculating an address value, e.g., by means of a predetermined calculation rule. Using the calculation rule, the desired address value can be calculated, for example, from the stored value and, if applicable, other values, e.g., from internal memory variables, such as constants and / or further stored values. This advantageously results in simple access to address values ​​and thus also to the values ​​stored at the corresponding addressed memory location.As explained previously, this reduces the overhead of memory access management.

[0049] In a further embodiment, the information about memory locations of the memory block comprises information about a first memory location of a first memory block, wherein the first memory location of the first memory block is determined as a function of information about a first memory location of a first memory area, in particular the constant memory area. It is possible for a memory block to comprise multiple memory locations that are arranged sequentially, i.e., one after the other, in the memory. Thus, each memory location of a memory block can be assigned an ordinal number according to this sequence. Furthermore, it is possible for the previously explained memory areas to comprise different memory locations that are also arranged sequentially in the memory.In this case, a memory area generally comprises related memory locations, i.e., memory locations that have at least one immediate neighboring memory location assigned to the same memory area. A neighboring memory location of a memory location with an ordinal number is, in particular, a memory location with the next higher or next lower ordinal number.

[0050] For example, the address value of the first memory location of the first memory block is the value corresponding to the size of the buffer memory area or the sum of the size of the buffer memory area and the enum memory area.

[0051] This advantageously results in a simple translation of the memory information into access information for the further computing device, especially in the case of dynamically expandable or reconfigurable memory information. The proposed information advantageously enables, for example, for a new application, existing memory locations to be deleted, used to store other values, or new memory locations to be added for use. This reconfiguration can be carried out easily, in particular by providing new IC-specific memory information.

[0052] In a further embodiment, the information about memory locations of a further memory block comprises information about a first memory location of the further memory block, wherein the first memory location of the further memory block is determined as a function of the information about the first memory location of the first memory block and as a function of the information about the size of the memory blocks. For example, the address value of the first memory location of a second memory block results from the sum of the address value of the first memory location of the first memory block and the size of a memory block.

[0053] In a further embodiment, information about a further memory location of a memory block is determined depending on the information about the first memory location of the memory block and a predetermined memory cell counting constant. For example, the address value of a second memory location of a memory block can be the sum of the address value of the first memory location of this memory block and the constant 1. Furthermore, the address value of a third memory location of a memory block can be the sum of the address value of the first memory location of this memory block and the constant 2.

[0054] The described information advantageously allows for optimal utilization of the integrated circuit's memory. In particular, it allows memory locations or memory blocks in the integrated circuit's memory to be contiguous to one another without gaps, even if the size of a memory block is increased or decreased, or memory blocks are added or removed.

[0055] The embodiments relating to the IC-specific memory information, in particular their content and structure, as well as their sub-aspects, can constitute an independent invention. Thus, a method, in particular a computer-implemented method, for accessing a memory of an integrated circuit depending on IC-specific memory information is described, wherein the IC-specific memory information contains information about a memory size and / or information about a number and size of memory areas and / or about a number and size of memory blocks of the memory or memory area and / or about a size of a constant memory area and / or about a size of a

[0056] Buffer memory area. Furthermore, the IC-specific memory information can include information about memory locations of a memory block of a first memory area, in particular the constant memory area. Furthermore, the information about memory locations of a memory block can include information about a first memory location of a first memory block, wherein the first memory location of a first memory block is determined as a function of information about a first memory location of a first memory area, in particular the constant memory area.Furthermore, the information about memory locations of a further memory block can comprise information about a first memory location of the further memory block, wherein the first memory location of the further memory block is determined as a function of the information about the first memory location of the first memory block and as a function of the information about the size of the memory blocks and / or that information about a further memory location of a memory block is determined as a function of the information about the first memory location of the memory block and a predetermined memory location counting constant.

[0057] Also described is a program which, when executed on or by a computer, causes the computer to perform one, several or all of the steps of such a method for accessing a memory.

[0058] Furthermore, an integrated circuit with a memory as well as a memory and a network with the integrated circuit or memory are described, which is designed or organized according to the storage information.

[0059] Such IC-specific memory information and the corresponding design / organization of the memory advantageously enable the previously described better utilization of the memory of the integrated circuit, in particular the seamless adjoining of the memory locations or memory blocks in the memory of the integrated circuit, even if the size of a memory block is increased or reduced or memory blocks are added or removed.

[0060] In a further embodiment, the access information is or will be stored in a memory device of the further computing device or in a memory device accessible by the latter. Furthermore, the IC-specific memory information, as previously explained, can be used to implement the integrated circuit. Of course, the further access information can also be or will be stored in a memory device of the second further computing device or in a memory device accessible by the latter.

[0061] In a further embodiment, the integrated circuit and the further computing device are part of a coordinate measuring device. In this case, the integrated circuit can be used, in particular, to control or regulate moving parts of the coordinate measuring device. Furthermore, the integrated circuit can read sensor values, for example, values ​​from position, speed, and / or force sensors, in particular for implementing the aforementioned motion control or regulation. For this purpose, the integrated circuit can be connected to the corresponding sensors via data and / or signals.

[0062] The additional computing device can be used for communication with other devices or systems, for example via a suitable bus system, in particular a CAN bus system, an EtherCAT bus system, an Ethernet bus system, a ModBus system, and a parallel bus system. Furthermore, the additional computing device can be used for communication with the second additional computing device explained above.

[0063] This advantageously results in improved operation of a coordinate measuring machine, in particular through faster memory access.

[0064] In another embodiment, the method is a computer-implemented method. This will be explained in more detail below.

[0065] Further proposed is a program which, when executed on or by a computer, causes the computer to perform one, several or all steps of a method for accessing a memory of an integrated circuit according to an embodiment explained in this disclosure.

[0066] A computer can be any type of data processing device, but in particular one of the previously explained computing devices or a device for data processing, in particular a programmable computing device or device for data processing.

[0067] Alternatively or cumulatively, a program storage medium or computer program product is described on or in which the program is stored, in particular in a non-temporary, e.g., in a permanent, form. The previously explained files, for example, can be stored in such a medium or product. Alternatively or cumulatively, a computer is described which comprises this program storage medium. Further alternatively or cumulatively, a signal is described, for example, a digital signal which encodes information representing the program and which comprises code means adapted to carry out one, several or all steps of the method presented in this disclosure for accessing a memory of an integrated circuit. The signal can be a physical signal, e.g., an electrical signal, which is generated in particular technically or mechanically.

[0068] Furthermore, the method for accessing a memory of an integrated circuit can be a computer-implemented method. For example, one, several, or all steps of the method can be carried out by a computer. One embodiment of the computer-implemented method is the use of the computer to carry out a data processing method. The computer can, for example, comprise at least one computing device, in particular a processor, and, for example, at least one storage device, in order to process the data, in particular technically, e.g., electronically and / or optically. A processor can be a semiconductor-based processor.

[0069] Further described is a computer program or a computer program product comprising instructions which, when executed by a computer, cause the computer to perform one, several, or all steps of the method presented in this disclosure for accessing a memory of an integrated circuit. Further described is a computer-readable (storage) medium comprising such instructions. Further described is a computer-readable data carrier on which the computer program (product) is stored.

[0070] Further proposed is a data processing device, comprising means for performing the steps of a method for accessing a memory of an integrated circuit according to one of the embodiments described in this disclosure. In particular, the data processing device may comprise means for executing the steps of the described method. Furthermore, the data processing device may comprise a processor adapted / configured to execute said method.

[0071] Furthermore, a network is proposed comprising at least one integrated circuit and at least one further computing device, wherein the further computing device accesses the memory of the integrated circuit depending on the computing device-specific access information.

[0072] A coordinate measuring machine with such a network is described further.

[0073] This coordinate measuring machine can comprise at least one movable element. The movable element can be used, in particular, to position a sensor of the coordinate measuring machine, in particular for measuring a measurement object. For example, the movable element can be a movable column of a gantry of a gantry-type coordinate measuring machine. The movable element can also be a spindle of the coordinate measuring machine. The movable element can also be a carriage that can be moved along a crossbeam of the coordinate measuring machine.

[0074] Furthermore, the coordinate measuring machine can comprise at least one drive device for generating a driving force / torque for the movable element. The drive device can be controlled or regulated by means of the integrated circuit. Furthermore, the coordinate measuring machine can comprise at least one sensor for generating measured values. The sensor can be a position sensor for detecting a position of the movable part. In this case, the integrated circuit can retrieve and store the measured values ​​of this sensor, in particular in one or more memory locations. Furthermore, a sensor can be a current sensor, wherein current measured values ​​of the current sensor can be stored in one or more memory locations. Accordingly, the sensor can also be a voltage sensor, wherein voltage measured values ​​of the voltage sensor can be stored in one or more memory locations.A sensor can also be a speed sensor, whereby speed measurements from the sensor can be stored in one or more memory locations.

[0075] A method for operating a coordinate measuring machine is also described, in particular for controlling / regulating the movement of at least one movable element of the coordinate measuring machine, wherein the integrated circuit of a previously explained network generates the corresponding control signals or regulating signals.

[0076] The invention is explained in more detail using exemplary embodiments. The figures show: Fig. 1 is a schematic block diagram of a network according to the invention, Fig. 2a is a schematic flow diagram of a method according to the invention, Fig. 2b is a schematic flow diagram of a method according to the invention in a further embodiment, Fig. 3a is a schematic flow diagram of a method according to the invention in a further embodiment, Fig. 3b is a schematic flow diagram of a method according to the invention in a further embodiment, Fig. 4a is an exemplary representation of IC-specific memory information and Fig. 4b is a schematic view of an IC memory.

[0077] In the following, the same reference symbols designate elements with the same or similar technical features.

[0078] Fig. 1 shows a schematic block diagram of a network 1 according to the invention with an integrated circuit 2 designed as an FPGA and a CPU computing device 3 designed as a microcontroller. Also shown is a memory 4 of the FPGA.

[0079] The CPU-based computing device 3 is connected to the integrated circuit 2 via signals and / or data.

[0080] Also shown is a further storage device 5, which can be designed, for example, as a hard disk memory of a mainboard.

[0081] The integrated circuit 2, the CPU computing device 3 and the further memory device 5 can be components of a coordinate measuring machine 6.

[0082] Also shown is a third computing device 7, which can be designed, for example, as a PC, in particular as a laptop, and thus as a further CPU-based computing device.

[0083] The memory 4 of the integrated circuit 2 has a certain memory configuration and a certain memory structure, which can be described by IC-specific memory information. In particular, the memory information can encode address values ​​of memory locations in the memory 4 where values ​​of predetermined variables are / are to be stored. This IC-specific memory information can be specified before the integrated circuit 2 or the network 1 is put into operation as intended, for example, by a programmer.

[0084] This specification can be specified by a file, which can in particular be a VHDL-based file. This file can then serve as the basis for a compilation, whereby the structure of the integrated circuit 2 and in particular also the memory structure of the integrated circuit 2 is then defined in terms of circuitry.

[0085] Furthermore, depending on this IC-specific memory information, computing device-specific access information of the CPU-based computing device 3 to the memory 4 of the integrated circuit 2 can be generated. This can be done by executing a predetermined translation algorithm. This can, in particular, generate a C- or C++-based / coded file from the VHDL-based / coded file. This can, in particular, be done using a so-called search-and-replace algorithm. This C- or C++-based / coded file then describes the memory information in a form readable by the CPU-based computing device 3.

[0086] The information generated in this way can then be stored, for example also in the form of a file, in the further storage device 5, wherein in particular the third computing device 7 can access the information stored in this way at runtime.

[0087] Thus, from this stored, computing-device-specific access information, further access information for use by the third computing device 7 can be generated by executing a further translation algorithm, wherein this access information is described in various programming languages. In particular, this further access information can be C#-based / coded. This can also be done using a so-called search-and-replace algorithm. For example, it is possible for the third computing device 7 to access the stored, computing-device-specific access information at runtime and then, likewise at runtime, execute the further translation algorithm. The information generated by the translation can then be stored in a memory device (not shown) of the third computing device 7.

[0088] Furthermore, the computing device-specific access information serves to program the CPU-based computing device 3. For this purpose, this access information can be stored in the memory of an external development computing device, wherein this memory device can be accessed during compilation to generate code or code means that can be executed by the CPU computing device 2.

[0089] Fig. 2a shows a schematic flow diagram of a method according to the invention for accessing a memory 4 of an integrated circuit 2 by a CPU-based computing device 3 (see Fig. 1 ). In a first step S1, predetermined IC-specific memory information (which is stored, for example, in Fig. 4a are shown) generates computing device-specific information for access by the CPU-based computing device 3 to the memory 4. This has already been explained above. Step S1 can be performed by the CPU-based computing device 3 or by another, in particular external, computing device. This first step S1 can, in particular, be a step that is performed before the execution of the access method in the second step S2 and is therefore not necessarily part of the access method.

[0090] In a second step S2, which is carried out in particular during the runtime of a data transmission or communication between these computing devices 2, 3, the CPU-based computing device 3 accesses the memory 4 of the integrated circuit 2 depending on the computing device-specific access information generated in this way. In particular, the CPU-based computing device 3 can generate a command for the integrated circuit 2, the execution of which by the integrated circuit 2 requires memory access, wherein, for example, an address value of the corresponding memory location can be encoded directly in the command. The command can, as explained above, be, for example, a read command or a write command.

[0091] Fig. 2b shows a schematic flow diagram of a method according to the invention in a further embodiment. Here, the first two steps S1, S2 correspond to the Fig. 2b The method described corresponds to the first two steps S1, S2 of the Fig. 2a procedure described.

[0092] In a third step S3, a third computing device 7 (see Fig. 1 ) accesses the memory 4 of the integrated circuit 2 depending on further access information. This access can also be performed during the runtime of a data transmission or communication between these computing devices 2, 7. The further access information is generated for this purpose from the computing device-specific access information.

[0093] Fig. 3a shows a schematic flow diagram of a method according to the invention in a further embodiment. Here, the first step S1 is shown in more detail than in the Fig. 2a illustrated embodiment. In sub-step S1a of the first step S1, the IC-specific memory information is provided, for example, by specification by a user. In a second sub-step S1b of the first step S1, the access information is generated by executing a translation algorithm.

[0094] The second step S2 of the Fig. 3a The embodiment shown corresponds to the second step S2 of the Fig. 2a illustrated embodiment.

[0095] Fig. 3b shows a schematic flow diagram of a method according to the invention in a further embodiment. Here, the first step S1 is shown in more detail than in the Fig. 2b The first two sub-steps S1a, S1b of the embodiment shown in Fig. 3b The process described corresponds to the first two sub-steps S1a, S1b of the Fig. 3a In a third sub-step S3a, further access information for access by a third computing device 7 (see Fig. 1 ) is generated from the computing device-specific access information generated in the second sub-step S2a. This can be done by executing a further translation algorithm and can be executed at runtime of the method.

[0096] The translation algorithm can be implemented in such a way that the computing device-specific access information and the further access information are described in different programming languages.

[0097] The second step S2 of the Fig. 3b The embodiment shown corresponds to the second step S2 of the Fig. 2a The third step S3 of the embodiment shown in Fig. 3b The embodiment shown corresponds to the third step S3 of the Fig. 2b illustrated embodiment. Here, it is shown that the second step S2 and the third step do not necessarily have to be carried out sequentially.

[0098] Fig. 4a shows an example representation of IC-specific memory information defined in the form of a VHDL-based file.

[0099] Shown is a constant memory area const (see Fig. 4b ) of the memory 4 of the integrated circuit 2. In addition to this constant memory area const, the memory 4 includes a so-called buffer memory area buffer (see also Fig. 4b ).

[0100] A first line defines the number of memory blocks no_hwb, which in the present embodiment is 8 (2 exp(3)). A second line specifies the size of such a memory block, namely the number of memory locations, which in the present example is 4 (2 exp(2)). A third line specifies the number of memory locations of the buffer memory area buffer, which in the present embodiment is 2 exp(13).

[0101] In lines 4 to 6, the address value of the first memory location of three memory blocks is defined. This shows that only three of the eight defined memory blocks are defined in the memory information. This, in turn, means that five additional memory blocks are available, for example, for other applications that require reconfiguration of the memory information.

[0102] Lines 7 to 11 define the address values ​​of the four memory locations of the first memory block. Lines 12 to 15 define the address values ​​of the four memory locations of the second memory block, and lines 16 to 19 define the four memory locations of the third memory block.

[0103] In Fig. 4b Shown is a schematic division of the memory 4 of the integrated circuit 2 (see Fig. 1 ), which includes a buffer memory area (buffer) and a constant memory area (const). The memory locations of the constant memory area (const) adjoin the memory locations of the buffer memory area (buffer). List of reference symbols

[0104] 1Network 2Integrated circuit 3CPU-based computing device 4Memory 5Further storage device 6Coordinate measuring device 7Third computing device S1First step S1aFirst sub-step S1bSecond sub-step S2Second step bufferBuffer memory area constConstant memory area

Claims

1. Method for accessing a memory (4) of an integrated circuit (2) by way of a further computing device (3), wherein • computing-device-specific access information for the access is generated from predetermined IC-specific memory information, which is encoded in a file and provided with predetermined characters or strings and at least includes information about memory locations of a memory block of a first memory area, said information including address values or a value for the calculation of an address value, by way of a computer-implemented execution of a predetermined translation algorithm by virtue of the predetermined characters or strings of the IC-specific memory information being translated into characters or strings that are assigned to these predetermined characters or strings, wherein the computing-device-specific access information is encoded in a further file that is stored in a memory device, wherein • the memory device is accessed during a compiling process to generate code that can be executed by the further computing device, wherein the code is generated in such a way that • the further computing device (3) accesses the memory (4) of the integrated circuit (2) depending on the computing-device-specific access information when the code is executed, wherein the further computing device uses the computing-device-specific access information to generate an access command in which an address value of a memory location of the memory of the integrated circuit (2) is encoded.

2. Method according to Claim 1, characterized in that the integrated circuit (2) is in the form of an FPGA and / or the further computing device (3) is in the form of a CPU computing device.

3. Method according to either one of the preceding claims, characterized in that the IC-specific memory information is described based on VHDL and / or the computing device-specific information is described based on C or C++.

4. Method according to any one of the preceding claims, characterized in that the IC-specific memory information includes information about a memory size and / or information about a number and size of memory areas and / or about a number and size of memory blocks of the memory or memory area and / or about a size of a constant memory area (const) and / or about a size of a buffer memory area (buffer).

5. Method according to any one of the preceding claims, characterized in that a second further computing device (7) accesses the memory (4) of the integrated circuit (2) depending on the further access information, wherein the further access information is generated from the computing-device-specific access information by way of an execution of a predetermined translation algorithm.

6. Method according to any one of the preceding claims, characterized in that the information about memory locations of a memory block includes information about a first memory location of a first memory block, wherein the first memory location of a first memory block is determined depending on information about a first memory location of a first memory area.

7. Method according to Claim 6, characterized in that the information about memory locations of a further memory block includes information about a first memory location of the further memory block, wherein the first memory location of the further memory block is determined depending on the information about the first memory location of the first memory block and depending on the information about the size of the memory blocks and / or that information about a further memory location of a memory block is determined depending on the information about the first memory location of the memory block and a predetermined memory location count constant.

8. Method according to any one of the preceding claims, characterized in that the access information is stored in a memory device of the further computing device (3) or in a memory device that can be accessed thereby.

9. Method according to any one of the preceding claims, characterized in that the integrated circuit and the further computing device (3) are part of a coordinate measuring device.

10. Method according to any one of the preceding claims, characterized in that the method is a computer-implemented method.

11. Program that, when executed on or by a computer, causes the computer to perform all steps of a method for accessing a memory of an integrated circuit according to any one of Claims 1 to 10.

12. Apparatus for data processing, comprising means (2) for performing the steps of a method for accessing a memory of an integrated circuit according to any one of Claims 1 to 10.

13. Network having at least one integrated circuit (2) and at least one further computing device (3), wherein the further computing device (3) accesses the memory (4) of the integrated circuit (2) depending on computing-device-specific information, which is generated from predetermined IC-specific memory information with predetermined characters or strings and is encoded in a file and at least includes information about memory locations of a memory block of a first memory area, said information including address values or a value for the calculation of an address value, by way of a computer-implemented execution of a predetermined translation algorithm by virtue of the predetermined characters or strings of the IC-specific memory information being translated into characters or strings that are assigned to these predetermined characters or strings, wherein a further file that encodes the computing-device-specific access information is generated and stored in a memory device, wherein the memory device is accessed during a compiling process to generate code that can be executed by the further computing device (3), wherein the code is generated in such a way that the further computing device (3) accesses the memory (4) of the integrated circuit (2) when the code is executed depending on the computing-device-specific access information, wherein the further computing device (3) uses the computing-device-specific access information to generate an access command, wherein the further computing device (3) generates an access command in which an address value of a memory location of the memory of the integrated circuit (2) is encoded.