METHOD FOR OPERATING A DEVICE, DEVICE AND SYSTEM

Description

[0001] The present invention relates to a method for operating a device, a device and a system with at least two devices.

[0002] This patent application claims priority from German patent application DE 10 2019 131 848.3.

[0003] It is known from the prior art to equip devices with internal clocks that are incremented by an internal clock generator. However, the frequencies of such internal clock generators are known to be subject to manufacturing tolerances and can also depend on external conditions such as temperature. This means that the internal clocks of two devices can run at different speeds.

[0004] Various methods for synchronizing the internal clocks of multiple devices are known in the art. Such synchronization can be achieved, for example, using a time source connected to the devices via a data network or using time information contained in GPS signals.

[0005] Synchronous clocks that derive their time base from the mains frequency of a power supply network are also known from the state of the art.

[0006] The document FRANK H ET AL: "Clock synchronization of distributed computers in building automation networks using an AC power supply", INDUSTRIAL ELECTRONICS, 2008. IECON 2008. 34TH ANNUAL CONFERENCE OF IEEE, IEEE, PISCATAWAY, NJ, USA, November 10, 2008 (2008-11-10), pages 2730-2735, XP031825841, ISBN: 978-1-4244-1767-4, describes a method for time synchronization between a master and a slave. The master generates a timestamp at a zero crossing of the mains voltage and sends it to the slave. The slave synchronizes its time based on the received timestamp.

[0007] The article ANTHONY ROWE ET AL: "Low-power clock synchronization using electromagnetic energy radiating from AC power lines", PROCEEDINGS OF THE 7TH ACM CONFERENCE ON EMBEDDED NETWORKED SENSOR SYSTEMS, CA, USA, NOVEMBER 04 - 06, 2009, ACM, NEW YORK, NY, USA, November 4, 2009 (2009-11-04), pages 211-224, XP058271115, DOI: 10.1145 / 1644038.1644060: ISBN: 978-1-60558-519-2 describes a device for achieving clock synchronization that uses a magnetic field radiated from AC power lines as a synchronization signal.

[0008] The document "REAL TIME CLOCK TIMEBASE WITH AUTOMATIC 50 / 60 HERTZ SYNCHRONIZATION", MOTOROLA TECHNICAL DEVELOPMENTS, Vol. 4, No. 1, April 1, 1984 (1984-04-01), pages 20-21, XP0014393903, describes a real-time clock timebase with automatic line frequency synchronization.

[0009] US 4 583 865 A describes a method for synchronizing a clock with a mains frequency.

[0010] One object of the present invention is to provide a method for operating a device. Another object of the present invention is to provide a device. Another object of the present invention is to provide a system comprising a first such device and a second such device. These objects are achieved by a method for operating a device, by a device, and by a system having the features of the respective independent claims. Various developments are specified in the dependent claims.

[0011] In a method for operating a device that has an internal clock and an internal clock and is connected to a network, the internal clock is incremented by means of the internal clock. The internal clock is synchronized with a network frequency of the network. The network can be a power supply network, for example. This method advantageously ensures that the internal clock of the device runs synchronously with the network frequency of the network. This advantageously ensures that the internal clock of this device runs just as fast as the internal clocks of other devices that are also synchronized with the network frequency of the network. The internal clocks of such devices thus run synchronously.Since the internal clock of the device is incremented by means of the internal clock generator, the internal clock of the device can advantageously have a high temporal resolution, in particular a temporal resolution that is higher than the mains frequency of the network.

[0012] In one embodiment of the method, the internal clock is periodically synchronized with the grid frequency. This advantageously ensures that the time advance of the device's internal clock is regularly adjusted to the time base specified by the grid frequency.

[0013] In one embodiment of the method, the grid is a power supply network. Zero crossings of a voltage in the grid are detected. The internal clock is synchronized with the grid frequency at each zero crossing of the voltage.

[0014] Advantageously, zero crossings of the grid voltage can be detected with high accuracy. This advantageously enables particularly precise synchronization of the internal clock with the grid frequency.

[0015] In one embodiment of the method, the internal clock has a frequency that is higher than the grid frequency of the network. The frequency of the internal clock can, for example, be several orders of magnitude higher than the grid frequency of the network. Advantageously, the device's internal clock can thus have a temporal resolution that is finer than one period of the grid frequency of the network.

[0016] The method comprises steps for recording a measured value and assigning the measured value a time stamp from the internal clock. The time stamp of the internal clock can indicate the time at which the measured value was recorded. The synchronization of the internal clock with the grid frequency according to the method advantageously ensures that the time stamp refers to a time system synchronous with the grid frequency.

[0017] In one embodiment of the method, this comprises a further step of sending the time-stamped measured value via a data network. This advantageously allows the time-stamped measured value to be further processed at another location, for example, in another network participant of the data network.

[0018] In one embodiment of the method, this comprises a step of outputting a signal at a specified time value of the internal clock. It is advantageous for the internal clock to be synchronized with the network frequency to ensure synchronization of the time values ​​of different network participants in the data network.

[0019] A device comprises an internal clock that can be incremented by an internal clock generator, and a network connection for connection to a network. The device is designed to synchronize the internal clock with a network frequency of the network. Advantageously, the internal clock of this device thus runs synchronously with the network frequency of the network. This ensures that the internal clock of this device runs at the same speed as the internal clocks of other devices that also synchronize their internal clocks with the network frequency of the network. Since the internal clock of this device is incremented by means of the internal clock generator, the internal clock of the device can advantageously have a temporal resolution that is finer than one period of the network frequency of the network.

[0020] In one embodiment of the device, the mains connection can be connected to a power supply network. The device is designed to detect zero crossings of a mains voltage. Advantageously, zero crossings of the mains voltage can be detected with high accuracy, enabling particularly precise synchronization of the internal clock with the mains frequency.

[0021] In one embodiment of the device, the internal clock has a frequency that is higher than the mains frequency of the network. The frequency of the internal clock can, for example, be several orders of magnitude higher than the mains frequency of the network. Advantageously, the device's internal clock can thus have a temporal resolution that is finer than one period of the mains frequency of the network.

[0022] The device is designed to record a measured value and assign a timestamp from the internal clock to the recorded value. The timestamp can indicate the value of the internal clock at the time the measured value was recorded. Since the device's internal clock can be synchronized with the grid frequency, the timestamp is then available in a time system that is synchronous to the grid frequency.

[0023] In one embodiment of the device, it is configured to transmit the measured value with the time stamp over a data network. This advantageously allows the measured value with the time stamp to be further processed at another location, for example, in another network participant of the data network.

[0024] In one embodiment of the device, it is configured to output a signal at a specified time value of the internal clock. It is advantageous that the device's internal clock can be synchronized with the network frequency to ensure synchronization of the time values ​​of different network participants in the data network.

[0025] In one embodiment of the device, it is configured as an EtherCAT network node. Advantageously, the internal clock of this EtherCAT network node can be synchronized with the network frequency.

[0026] A system comprises a first device and a second device, each configured as described above. The first device and the second device are connected to a common network. This provides both devices with access to the network frequency of the common network to synchronize their respective internal clocks. If the first device synchronizes its internal clock with the network frequency of the network and the second device also synchronizes its internal clock with the same network frequency of the common network, then the internal clocks of both devices are advantageously synchronized with each other.

[0027] The invention is explained in more detail below with reference to the figures. These show: Fig. 1 a schematic representation of a system with two devices connected to a network; Fig. 2 a time course of a voltage in the network; Fig. 3 a first data packet; and Fig. 4 a second data packet.

[0028] Fig. 1 shows a schematic representation of a system 10. The system 10 comprises a plurality of devices 100. In Fig. 1 In the example shown, the system 10 comprises a first device 100, 101 and a second device 100, 102. However, the system 10 may also comprise more than two devices 100.

[0029] The devices 100 of the system 10 have similarities, which are described below. In addition, differences may also exist between the individual devices 100 of the system 10. In Fig. 1 In the example of the system 10 shown, there are similarities and differences between the first device 100, 101 and the second device 100, 102.

[0030] The devices 100 of the system 10 each have an internal clock generator 110. The internal clock generator 110 provides a clock signal with a frequency 111. The frequency 111 of the clock signal provided by the internal clock generator 110 of the first device 100, 101 can differ from the frequency 111 of the clock signal provided by the internal clock generator 110 of the second device 100, 102 such that the clock signal of the internal clock generator 110 of the first device 100, 101 has a first frequency 111, 113 and the clock signal of the internal clock generator 110 of the second device 100, 102 has a second frequency 111, 115. The frequencies 111 of the internal clock generators 110 of the devices 100 can be, for example, several MHz or several GHz.

[0031] Each device 100 of system 10 has an internal clock 120. The internal clock 120 can be implemented, for example, as a data register. A numerical value stored in this data register represents a time value of the internal clock 120 of the device 100. The time value of the internal clock 120 can be represented, for example, with a resolution of 1 µs or 1 ns.

[0032] Each device 100 is configured to increment its internal clock 120 using the internal clock generator 110. For this purpose, the respective device 100 can, for example, have an adjustable parameter 112 that specifies the ratio with which the internal clock 120 is incremented to the frequency 111 of the internal clock generator 110.

[0033] Each device 100 of system 10 has a network connection 130. The network connection 130 is provided for connecting the respective device 100 to a network 200. All devices 100 of system 10 are connected to the same network 200.

[0034] The network 200 provides a network frequency of 230.

[0035] The network 200 can, for example, be a power supply network. In this case, the network 200 provides a voltage 210 whose voltage value changes periodically with the network frequency 230. In the example described with reference to the figures, the network 200 is configured as a power supply network.

[0036] However, the network 200 can also be another network that provides the network frequency 230. For example, the network 200 can be formed by a simple line into which the network frequency 230 is coupled.

[0037] If the network 200 is a power supply network, the network 200 can serve as a power supply to the devices 100. However, this is not mandatory. The devices 100 can also cover their energy needs from other energy sources.

[0038] The frequencies 111 of the internal clock generators 110 of the individual devices 100 of the system 10 can each exhibit deviations from their target values ​​due to component tolerances. Furthermore, the frequencies 111 of the internal clock generators 110 of the devices 100 of the system 10 can be subject to temporal fluctuations, which can be caused, for example, by temperature changes. This results in the internal clocks 120 of the devices 100 of the system 10 running at different speeds if the internal clocks 120 are not synchronized. For example, if the internal clock 120 of the first device 100, 101 and the internal clock 120 of the second device 100, 102 run at different speeds, the time of the internal clock 120 of the first device 100, 101 and the time of the internal clock 120 of the second device 100, 102 increasingly drift apart over time.

[0039] To prevent this, each device 100 of the system 10 is designed to synchronize its internal clock 120 with the grid frequency 230 of the common grid 200. This also synchronizes the internal clocks 120 of the individual devices 100 with each other.

[0040] The mains frequency 230 is typically several orders of magnitude lower than the frequency 111 of the internal clock generator 110 of the devices 100. The mains frequency 230 can be, for example, 50 Hz or 60 Hz.

[0041] Fig. 2 shows a schematic representation of a time-dependent curve 400 of the voltage 210 of the network 200. The voltage 210 has periodically occurring zero crossings 220 over the time 400. At a first time 401, a first zero crossing 220, 221 of the voltage 210 occurs. At a second time 402, a second zero crossing 220, 222 of the voltage 210 occurs. Between the first zero crossing 220, 221 and the second zero crossing 220, 222 there is a half-cycle of the voltage 210, so that the time interval between the first time 401 and the second time 402 corresponds to a half-cycle duration 235, which is calculated as half the inverse of the network frequency 230 of the network 200. For example, if the mains frequency is 230 Hz or 50 Hz, the half-period duration is 235 10 ms.

[0042] In order to synchronize the respective internal clock 120 with the grid frequency 230 of the grid 200, each device 100 can be configured to detect the zero crossings 220 of the voltage 210 of the grid 200. At each zero crossing 220, a current value of the internal clock 120 of the respective device 100 is determined. This is shown in Fig. 2 shown schematically. At the first zero crossing 220, 221 of the voltage 210 at the first time 401, the internal clock 120 has a first clock value 121. At the second zero crossing 220, 222 at the second time 402, the internal clock 120 has a second clock value 122. Since the internal clock 120 has been incremented between the first time 401 and the second time 402, the second clock value 122 is greater than the first clock value 121. The difference between the first clock value 121 and the second clock value 122 can be referred to as the clock advance 123.

[0043] If the respective device 100 knows the mains frequency 230 of the mains 200, the internal clock 120 can be synchronized with the mains frequency 230 of the mains 200 as follows: The period of time elapsed between the first time 401 and the second time 402 corresponds to the half-period 235 of the mains frequency 230 of the mains 200, which is also known to the respective device 100. By comparing the clock advance 123 with the half-period 235, it can be determined whether the internal clock 120 of the respective device 100 is running too fast or too slow. If the clock advance 123 is greater than the half-period 235, the internal clock 120 is running too fast and must be slowed down. If the clock advance 123 is less than the half-period 235, the internal clock 120 is running too slowly and must be accelerated.The internal clock 120 can be slowed down or accelerated in each device 100 of the system 10, for example, by adjusting the adjustable parameter 112, which specifies the ratio with which the respective internal clock 120 is incremented to the frequency 111 of the internal clock generator 110.

[0044] An alternative way to synchronize the internal clock 120 with the grid frequency 230 of the grid 200 is to regulate the speed of the internal clock 120 so that the clock advance 123 between consecutive zero crossings 220 of the voltage 210 always remains approximately the same. If the clock advance 123 between consecutive zero crossings 220 of the voltage 210 increases over time, the internal clock 120 runs too fast and must be slowed down. If the clock advance 123 between consecutive zero crossings 220 of the voltage 210 decreases over time, the internal clock 120 runs too slowly and must be accelerated. The slowing down or speeding up of the internal clock 120 can in turn be carried out for each device 100 of the system 10, for example, by adjusting the adjustable parameter 112, which specifies the ratio with which the respective internal clock 120 is incremented to the frequency 111 of the internal clock generator 110.With this option for synchronizing the internal clock 120 with the mains frequency 230 of the network 200, the devices 100 do not need to know the mains frequency 230 of the network 200.

[0045] The described synchronization of the internal clock 120 with the grid frequency 230 of the grid 200 is expediently performed periodically. For example, the internal clock 120 can be synchronized with the grid frequency 230 of the grid 200 at every zero crossing 220 of the voltage 210 of the grid 200. However, it is also possible to synchronize the internal clock 120 less frequently than at every zero crossing 220 of the voltage 210 of the grid 200. For example, the internal clock could be synchronized only at every other zero crossing 220 of the voltage 210 of the grid 200.

[0046] In addition to the components described above, which are present in all devices 100, the devices 100 of the system 10 may have further components and features, which may alternatively be omitted. Some such features are described below by way of example. Each of the devices 100 of the system 10 may optionally have one or more of these or other features.

[0047] In Fig. 1 In the example shown, the first device 100, 101 has a sensor input 140. The first device 100, 101 is designed to detect a measured value 141 by means of the sensor input 140. The measured value 141 can be, for example, an electrical voltage value. The first device 100, 101 can be designed to provide the measured value 141 with a time stamp 124 by creating a Fig. 3 schematically illustrated first data packet 310 is formed. The time stamp 124 indicates the value of the internal clock 120 of the first device 100, 101 at the time at which the measured value 141 was recorded.

[0048] The first device 100, 101 has in the Fig. 1 In the example shown, the first device 100, 101 has a data connection 160, via which the first device 100, 101 is connected to a data network 300. The data network 300 can be, for example, an Ethernet-based data network. For example, the data network 300 can be an EtherCAT data network. In this case, the first device 100, 101 is configured as an EtherCAT network participant.

[0049] The first device 100, 101 can be designed to Fig. 3 The first data packet 310 shown with the measured value 141 and the time stamp 124 associated with the measured value 141 is to be sent via the data network 300. The first device 100, 101 can send the first data packet 310, for example, to another device 100 of the system 10. Since this additional device 100 also synchronizes its internal clock 120 with the network frequency 230 of the network 200, the time stamp 124 contained in the first data packet 310 then refers to a time system that is synchronous with the internal clock 120 of the additional device 100.

[0050] In Fig. 1 In the example shown, the first device 100, 101 has a signal output 150. The first device 100, 101 is designed to output a signal 151 via the signal output 150. The first device 100, 101 can, for example, be designed to output the signal 151 with a fixed signal value 152 at a fixed time value 125 of the internal clock 120 of the first device 100, 101. The time value 125 and the signal value 152 can, for example, be stored by the first device 100, 101 in a Fig. 4schematically illustrated second data packet 320 via the data network 300. The first device 100, 101 can receive the second data packet 320, for example, from another device 100 of the system 10. Since the internal clock 120 of this additional device 100 is also synchronized with the network frequency 230 of the network 200, the additional device 100 can set the time value 125 based on its internal clock 120, which is synchronous with the internal clock 120 of the first device 100, 101.

[0051] The devices 100 of the system 10 can, for example, be configured as Internet of Things (IoT) devices (IoT devices). The devices 100 of the system 10 can, for example, be distributed control and measurement devices of an industrial plant, a wind farm, a solar farm, or another plant. For example, the first device 100, 101 of the system 10 can be arranged on a blade of a wind turbine, while the second device 100, 102 is arranged on a hub of the wind turbine. List of reference symbols

[0052] 10System 100Device 101First device 102Second device 110internal clock 111frequency 112parameter 113first frequency 115second frequency 120internal clock 121first clock value 122second clock value 123clock progress 124timestamp 125time value 130Network connection 140Sensor input 141Measured value 150Signal output 151Signal 152Signal value 160Data connection 200Network 210Voltage 220Zero crossing 221First zero crossing 222Second zero crossing 230Network frequency 235Half-period duration 300Data network 310First data packet 320Second data packet 400time 401first time 402second time

Claims

1. A method for operating a device (100), which comprises an internal clock generator (110) and an internal clock (120) and is connected to a network (200), wherein the internal clock (120) is incremented by means of the internal clock generator (110), wherein the internal clock (120) is synchronized with a network frequency (230) of the network (200), wherein the method comprises the following steps: - detecting a measuring value (141); - providing the measuring value (141) with a time stamp (124) of the internal clock (120).

2. The method according to claim 1, wherein the internal clock (120) is periodically synchronized with the network frequency (230) of the network (200).

3. The method according to claim 2, wherein the network (200) is a power-supply network, wherein zero crossings (220) of a voltage (210) of the network (200) are detected, wherein the internal clock (120) is synchronized with the network frequency (230) of the network (200) for each occurring zero crossing (220) of the voltage (210).

4. The method according to any one of the preceding claims, wherein the internal clock generator (110) has a frequency (111) which is higher than the network frequency (230) of the network (200).

5. The method according to any one of the preceding claims, wherein the method comprises the following further step: - sending out the measuring value (141) provided with the time stamp (124) via a data network (300).

6. The method according to any one of the preceding claims, wherein the method comprises the following step: - outputting a signal (151) at a predefined time value (125) of the internal clock (120).

7. A device (100) comprising an internal clock (120) which may be incremented by means of an internal clock generator (110), and comprising a network connection (130) for connecting to a network (200) wherein the device (100) is embodied to synchronize the internal clock (120) with a network frequency (230) of the network (200), wherein the device (100) is configured to detect a measuring value (141) and to provide the detected measuring value (141) with a time stamp (124) of the intenal clock (120).

8. The device (100) according to claim 7, wherein the network connection (130) may be connected to a power-supply network, wherein the device (100) is embodied to detect zero crossings (220) of a voltage (210) of the network (200).

9. The device (100) according to any one of claims 7 and 8, wherein the internal clock generator (110) has a frequency (111) which is higher than the network frequency (230) of the network (200).

10. The device (100) according to any one of claims 7 to 9, wherein the device (100) is embodied to send out the measuring value (141) provided with the time stamp (124) via a data network (300).

11. The device according to any one of claims 7 to 10, wherein the device (100) is embodied to output a signal (151) at a predefined time value (125) of the internal clock.

12. The device (100) according to any one of claims 7 to 11, wherein the device (100) is embodied as an EtherCAT-network subscriber.

13. A system (10), comprising a first device (100, 101) and a second device (100, 102), each of which is embodied according to any one of claims 7 to 12, wherein the first device (100, 101) and the second device (100, 102) are connected to a shared network (200).