METHOD FOR OPERATING A DRIVE SYSTEM AND DRIVE SYSTEM FOR IMPLEMENTING THE METHOD

Description

[0001] The invention relates to a method for operating a drive system and a drive system for carrying out the method.

[0002] It is well known that a drive system enables electric motors to be operated with speed control or torque control.

[0003] From the DE 10 2018 210 244 A1 A method for operating an electric drive system is known.

[0004] From the DE 10 2016 008 951 A1 A method for controlling a voltage intermediate circuit is known.

[0005] From the DE 10 2006 039406 A1 The closest prior art is a method for controlling a large number of servo motor drives.

[0006] The invention is therefore based on the object of developing a drive system, whereby the service life is to be increased.

[0007] According to the invention, the object is achieved in the drive system according to the claims 1 and in the method according to the claims 14 specified characteristics.

[0008] Important features of the method for operating a drive system comprising several, in particular more than two, inverters are that a respective electric motor is fed from the AC voltage side connection of the respective inverter, wherein the DC voltage side terminals of the respective inverters are connected in parallel to one another and this parallel connection is connected to the DC voltage side terminal of a rectifier, in particular a rectifier capable of feedback, in particular by means of busbars, wherein each inverter has semiconductor switches controlled according to a respective pulse width modulation, wherein the inverters are designed as bus participants of a data bus (35), to which a module designed as a master is also connected, in particular wherein the module comprises the rectifier, wherein the master, in particular upon commissioning of the drive system, assigns the bus addresses to the inverters and then the polarity of its pulse width modulation, in particular its pulse width modulation method, is specified to each inverter,wherein the polarity of the pulse width modulation of a first of the inverters differs from the polarity of the pulse width modulation of a second of the inverters, in particular such that the pulse width modulation of the control signals for the controllable semiconductor switches of a first of the inverters is carried out in counter-synchronous fashion to the pulse width modulation of the control signals for the controllable semiconductor switches of a second of the inverters.

[0009] The advantage here is that compensating currents, especially leakage currents, are reduced and a mains filter on the rectifier's mains side therefore has a longer service life.

[0010] In an advantageous embodiment, each inverter has parallel-connected half-bridges fed by the DC voltage, each of which is designed as a series circuit of at least two controllable semiconductor switches. The semiconductor switches of the respective inverter are controlled with pulse-width-modulated control signals according to the pulse-width modulation of the inverter and their polarity. It is advantageous that the different inverters can have different polarities. This allows the compensating currents in or via the intermediate circuit to be reduced, and components can be subjected to a lower load, in particular a line filter arranged at the AC-side connection of the rectifier.

[0011] In an advantageous embodiment, at the beginning of each pulse width modulation period the upper switch of the first half-bridge of the first inverter is opened and the lower switch of this first half-bridge of the first inverter is closed, in particular wherein the upper switch is connected to the upper potential of the voltage applied to the DC voltage terminal of the inverter and wherein the lower switch is connected to the lower potential of the voltage applied to the DC voltage terminal of the inverter. It is advantageous in this case that the first inverter has a positive polarity and thus the next adjacent inverter can be assigned a reverse, i.e., negative, polarity.

[0012] In an advantageous embodiment, the inverters are arranged in a row along the data bus, starting from the master, wherein in the first process step, starting from the master, in particular successively, each inverter assigns a bus address to the inverter following it in the series, until an inverter recognises itself as the last in the series due to the failure of a further assignment of a bus address and then in the second process step, a default value is set as the polarity of its pulse width modulation, after which, starting from the last inverter, in particular successively, each inverter transmits to its upstream inverter in the series a polarity inverted to its own polarity, which the upstream inverter sets as the polarity of its pulse width modulation, especially if it is not designed as a double inverter, especially a double axis, and otherwise passes on to the inverter upstream of it, In particular, the inverter configured as a dual inverter has a single bus address, and two individual inverters arranged in a common housing have pulse width modulations with mutually inverted polarity. The advantage here is that a decentralized automatic assignment of addresses and polarity is not required.

[0013] In an advantageous embodiment, the data bus has a forward channel and a reverse channel such that each inverter has an input and an output of the forward channel and an input and an output of the reverse channel, wherein the master is connected to the input of the forward channel of the first inverter and to the output of the reverse channel of the first inverter, For address assignment, the master sends a first bus address to a first inverter via the forward channel, which the first inverter adopts as its own bus address, wherein the first inverter generates a second bus address from the first bus address, in particular by incrementing it, and sends it to the second inverter via the forward channel, wherein the second inverter takes over the second bus address and generates a third bus address from the second bus address, in particular by incrementing it, and forwards it via its forward channel, wherein each further inverter adopts the bus address received via its input of the forward channel as its own bus address and generates a further bus address from the received bus address, in particular by incrementation, and sends it to the subsequent inverter via the forward channel, A final inverter identifies itself as the last inverter if a subsequent transmission of the bus address it generated fails. The advantage of this method is that a high level of security can be achieved during the process, as the forward channel and reverse channel are separate, allowing each bus participant to first examine the received data to determine whether it is intended for them or whether they should forward it.

[0014] According to the invention,In particular during commissioning, the master sends a broadcast telegram over the data bus for address assignment, which assigns a respective piece of address information to a respective piece of information about a polarity, in particular so that the first inverter is assigned a first polarity and the second inverter a second polarity, in particular a polarity different from the first polarity. The advantage here is that the inverters receive an address one after the other, with only one of the inverters being ready to use the respective address transmitted with the broadcast telegram.

[0015] In an advantageous embodiment, a voltage signal can be transmitted from the master to a first inverter, and a voltage signal can be transmitted from each respective inverter to the next inverter. The respective inverter receiving the voltage signal then extracts the information regarding address and / or polarity contained in a subsequent broadcast telegram from the master. The advantage here is that only one of the inverters is always ready to extract the address contained in the broadcast telegram, and after extraction, the inverter then transmits a voltage signal to prepare the next inverter.

[0016] In an advantageous embodiment, the inverters are arranged in a series with respect to the transmission of the voltage signal and / or with respect to the data bus, in particular so that from the first inverter to the second-to-last inverter in the series, each inverter is followed by another inverter. It is advantageous in this case that the inverters can be connected to a serial data bus.

[0017] In an advantageous embodiment, a last inverter, in particular one from which no downstream inverter can supply a voltage signal, specifies to its upstream inverter the polarity inverted from its own polarity used in pulse width modulation, after which this upstream inverter specifies to its upstream inverter the polarity inverted from its own polarity used in pulse width modulation. Advantageously, the address assignment is forward in the inverter series and the polarity assignment is reversed in the series.

[0018] In an advantageous design, the master transmits the polarity to be used in the respective pulse width modulation to the inverters after the address has been assigned, wherein the polarities are each assigned in such a way that the sum of the rated power of the respective inverter multiplied by their respective polarity is minimal in magnitude, in particular wherein adjacently arranged inverters preferably have a different polarity from one another. It is advantageous that the different polarities are assigned in such a way that, depending on the respective rated power of the inverters, the load caused by compensating currents, in particular leakage currents, is as low as possible, particularly in the intermediate circuit. The sum of the products of the rated power and the polarity is preferably as small as possible.

[0019] In an advantageous embodiment, for address assignment, each inverter supplies a voltage signal to a downstream inverter. This signal signals the downstream inverter to accept the address contained in the next broadcast telegram from the master as its own bus address and to supply a further voltage signal to another inverter, if present, and otherwise to adapt the polarity of its pulse width modulation to the polarity information contained in the broadcast telegram. The advantage here is that decentralized assignment of polarities is feasible.

[0020] In an advantageous embodiment, the drive system comprises a first inverter and a second inverter, wherein a first electric motor is fed from the AC voltage side connection of the first inverter, wherein a second electric motor is fed from the AC voltage side connection of the second inverter, wherein the DC voltage side connection of the first inverter is connected in parallel to the DC voltage side connection of the second inverter and this parallel connection is supplied from a DC voltage, in particular intermediate circuit voltage, in particular by means of busbars, wherein the first inverter has half-bridges connected in parallel to one another and fed from the DC voltage, each of which is designed as a series connection of at least two controllable semiconductor switches, wherein the second inverter has half-bridges connected in parallel to one another and fed from the DC voltage, each of which is designed as a series connection of at least two controllable semiconductor switches, wherein the semiconductor switches of the first inverter are controlled with pulse-width-modulated control signals,wherein the semiconductor switches of the second inverter are controlled by pulse-width modulated control signals, wherein the pulse width modulation of the control signals for the controllable semiconductor switches of the first inverter is carried out in counter-synchronous fashion to the pulse width modulation of the control signals for the controllable semiconductor switches of the second inverter.

[0021] The advantage here is that DC-side leakage currents, especially compensating currents, can be reduced or prevented. This also reduces the load on a line filter and thus increases its service life, as well as the service life of the entire drive system.

[0022] In an advantageous embodiment, the drive system comprises a first inverter and a second inverter, wherein a first electric motor is fed from the AC voltage side connection of the first inverter, wherein a second electric motor is fed from the AC voltage side connection of the second inverter, wherein the DC voltage side connection of the first inverter is connected in parallel to the DC voltage side connection of the second inverter and this parallel connection is supplied from a DC voltage, in particular intermediate circuit voltage, in particular by means of busbars, wherein the first inverter has half-bridges connected in parallel to one another and fed from the DC voltage, each of which is designed as a series connection of at least two controllable semiconductor switches, wherein the second inverter has half-bridges connected in parallel to one another and fed from the DC voltage, each of which is designed as a series connection of at least two controllable semiconductor switches, wherein the semiconductor switches of the first inverter are controlled with pulse-width-modulated control signals,wherein the semiconductor switches of the second inverter are controlled with pulse-width modulated control signals, wherein, as long as the quotient of the pulse width modulation ratio of the control signal for a first semiconductor bridge of the first inverter and the pulse width modulation ratio of the control signal for a second semiconductor bridge of the second inverter is less than a threshold value, in particular 1, at the beginning of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter is open and the lower switch of this first half-bridge of the first inverter is closed and the upper switch of the second half-bridge of the second inverter is closed and the lower switch of this second half-bridge of the second inverter is open, and that,as long as the quotient of the pulse width modulation ratio of the control signal for a first semiconductor bridge of the first inverter and the pulse width modulation ratio of the control signal for a second semiconductor bridge of the second inverter is greater than the threshold value, in particular 1, at the beginning of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter is open and the lower switch of this first half-bridge of the first inverter is closed and the upper switch of the second half-bridge of the second inverter is open and the lower switch of this second half-bridge of the second inverter is closed.

[0023] The advantage here is that compensating currents are reduced, thus reducing the load on the mains filter and increasing its service life.

[0024] In an advantageous embodiment, the drive system comprises a first inverter and a second inverter, wherein a first electric motor is fed from the AC voltage side connection of the first inverter, wherein a second electric motor is fed from the AC voltage side connection of the second inverter, wherein the DC voltage side connection of the first inverter is connected in parallel to the DC voltage side connection of the second inverter and this parallel connection is supplied from a DC voltage, in particular intermediate circuit voltage, in particular by means of busbars, wherein the first inverter has half-bridges connected in parallel to one another and fed from the DC voltage, each of which is designed as a series connection of at least two controllable semiconductor switches, wherein the second inverter has half-bridges connected in parallel to one another and fed from the DC voltage, each of which is designed as a series connection of at least two controllable semiconductor switches, wherein the semiconductor switches of the first inverter are controlled with pulse-width-modulated control signals,wherein the semiconductor switches of the second inverter are controlled with pulse-width modulated control signals, wherein, as long as the difference between the pulse width modulation ratio of the control signal for a first semiconductor bridge of the first inverter and the pulse width modulation ratio of the control signal for a second semiconductor bridge of the second inverter is smaller than a threshold value, in particular 50%, at the beginning of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter is open and the lower switch of this first half-bridge of the first inverter is closed and the upper switch of the second half-bridge of the second inverter is closed and the lower switch of this second half-bridge of the second inverter is open, and that,as long as the difference between the pulse width modulation ratio of the control signal for a first semiconductor bridge of the first inverter and the pulse width modulation ratio of the control signal for a second semiconductor bridge of the second inverter is greater than the threshold value, in particular 50%, at the beginning of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter is open and the lower switch of this first half-bridge of the first inverter is closed and the upper switch of the second half-bridge of the second inverter is open and the lower switch of this second half-bridge of the second inverter is closed.

[0025] The advantage here is that compensating currents are reduced, thus reducing the load on the mains filter and increasing its service life.

[0026] In an advantageous embodiment, the DC voltage is made available at the DC voltage side connection of a mains-fed rectifier, in particular wherein the rectifier, in particular at its AC voltage side connection, is supplied from an AC voltage network, in particular with three-phase voltage,

[0027] In particular, the DC-side connection of the rectifier is connected in parallel with the DC-side connection of the first inverter and the DC-side connection of the second inverter. This has the advantage of reducing compensating currents, thus reducing the load on the line filter and increasing its service life.

[0028] In an advantageous embodiment, the pulse width modulation signals of the first inverter are synchronized, in particular synchronized, with the pulse width modulation signals of the second inverter. This has the advantage of reducing compensating currents, thus reducing the load on the line filter and increasing its service life.

[0029] In an advantageous embodiment, the pulse width modulation periods of the first and second inverters begin synchronously and / or simultaneously. This is advantageous because compensating currents are reduced, thus reducing the load on the line filter and increasing its service life.

[0030] In an advantageous embodiment, within each pulse width modulation period, the first switching edge of a control signal for an upper semiconductor switch of the first inverter is inverted and / or occurs inversely to the first switching edge of a control signal for an upper semiconductor switch of the second inverter. This has the advantage of reducing compensating currents, thus reducing the load on the line filter and increasing its service life.

[0031] In an advantageous embodiment, one of the controllable semiconductor switches, i.e. upper semiconductor switch, of a respective half-bridge is connected to the upper potential of the DC voltage.

[0032] In an advantageous embodiment, one of the controllable semiconductor switches, i.e. lower semiconductor switch, of a respective half-bridge is connected to the lower potential of the

[0033] The advantage here is that the half-bridge, i.e., one bridge branch, can be supplied with DC voltage and can be implemented as a series circuit of two semiconductor switches, particularly IGBTs or MODFETs.

[0034] In an advantageous embodiment, at the beginning of each pulse width modulation period

[0035] the upper switch of a first half-bridge of the first inverter is opened and the lower switch of this first half-bridge of the first inverter is closed and

[0036] The upper switch of a second half-bridge of the second inverter is closed, and the lower switch of this second half-bridge of the second inverter is open. The advantage of this is that the inverted timing of the two pulse-width modulations of the two inverters minimizes the compensating currents.

[0037] In an advantageous design, as long as the quotient of the pulse width modulation ratio of the control signal for a first semiconductor bridge of the first inverter and the pulse width modulation ratio of the control signal for a second semiconductor bridge of the second inverter is less than a threshold value, in particular 1, at the beginning of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter is open and the lower switch of this first half-bridge of the first inverter is closed and the upper switch of the second half-bridge of the second inverter is closed and the lower switch of this second half-bridge of the second inverter is open, - and,as long as the quotient of the pulse width modulation ratio of the control signal for a first semiconductor bridge of the first inverter and the pulse width modulation ratio of the control signal for a second semiconductor bridge of the second inverter is greater than the threshold value, in particular 1, at the beginning of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter is open and the lower switch of this first half-bridge of the first inverter is closed and the upper switch of the second half-bridge of the second inverter is open and the lower switch of this second half-bridge of the second inverter is closed.

[0038] The advantage here is that the inverted clocking is only executed when the threshold is exceeded. This minimizes compensating currents.

[0039] In an advantageous design, as long as the difference between the pulse width modulation ratio of the control signal for a first semiconductor bridge of the first inverter and the pulse width modulation ratio of the control signal for a second semiconductor bridge of the second inverter is smaller than a threshold value, in particular 50%, at the beginning of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter is open and the lower switch of this first half-bridge of the first inverter is closed and the upper switch of the second half-bridge of the second inverter is closed and the lower switch of this second half-bridge of the second inverter is open, and,as long as the difference between the pulse width modulation ratio of the control signal for a first semiconductor bridge of the first inverter and the pulse width modulation ratio of the control signal for a second semiconductor bridge of the second inverter is greater than the threshold value, in particular 50%, at the beginning of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter is open and the lower switch of this first half-bridge of the first inverter is closed and the upper switch of the second half-bridge of the second inverter is open and the lower switch of this second half-bridge of the second inverter is closed.

[0040] The advantage here is that the inverted clocking is only executed when the threshold is exceeded. This minimizes compensating currents.

[0041] In an advantageous embodiment, a synchronization signal, in particular a synchronization signal comprising synchronization pulses, is modulated onto busbars that connect the DC-side terminals of the inverters to one another and to the DC-side terminal of the rectifier. This advantageously involves synchronizing the pulse width modulation frequency of the first inverter with that of the second inverter, allowing the inverse clocking to be implemented in a synchronized manner. The synchronization signal is transmitted via a data bus connection that connects the signal electronics of the two inverters. Alternatively, modulation onto the busbars is also possible, eliminating the need for an additional communication connection between the inverters.

[0042] Important features of the drive system for carrying out one of the aforementioned processes are that the DC side connections of the inverters are connected to each other by means of busbars and to the DC side connection of the rectifier.

[0043] The advantage is that a simple, cost-effective connection is possible.

[0044] Further advantages emerge from the dependent claims. The invention is not limited to the combination of features in the claims. Further possible combinations of claims and / or individual claim features and / or features of the description and / or the figures will become apparent to those skilled in the art, particularly from the problem and / or the problem posed by comparison with the prior art.

[0045] The invention will now be explained in more detail with the aid of schematic illustrations: In the Figure 1the phase voltages at a first AC-side terminal of a first inverter 1 and at a first AC-side terminal of a first inverter 2 are shown.

[0046] In the Figure 2 the phase voltages against earth potential are shown.

[0047] In the Figure 3 a drive system according to the invention with more than two inverters is shown.

[0048] As in the Figures 1 and 2 As shown, a first drive system according to the invention has a first inverter 1 and a second inverter 2, which are supplied in parallel with a DC voltage via their DC voltage side connection.

[0049] This DC voltage is preferably provided by a mains-powered rectifier.

[0050] Preferably, each of the two inverters (1, 2) has a smoothing capacitor, in particular a multi-piece smoothing capacitor, at its DC voltage side connection.

[0051] Each of the two inverters (1, 2) has three parallel series circuits, each of which has two controllable semiconductor switches. A respective phase voltage is thus provided to the electric motor at the connection node of the two controllable semiconductor switches of a respective series circuit.

[0052] Preferably, the AC voltage connection of the inverter is three-phase, so that each inverter (1, 2) has three of these series circuits and thus three phase voltages are provided to the motor. Each inverter (1, 2) has an electronic circuit designed as signal electronics, which generates pulse-width-modulated control signals for the controllable semiconductor switches of the inverter (1, 2).

[0053] As in Figure 1 As shown, to generate a respective value of phase voltage, the pulse width modulation ratio is specified within a pulse width modulation period. Figure 1 A pulse width modulation ratio of 50% is shown. At the beginning of the pulse width modulation period, the lower semiconductor switch of the series circuit is closed and the upper semiconductor switch of the series circuit is opened.

[0054] In this case, the terminal for the phase voltage is connected to the lower potential of the DC voltage, i.e., the intermediate circuit voltage U_z. After a quarter of the pulse-width modulation period has elapsed, the lower semiconductor switch is opened and the upper one is closed, so that the terminal for the phase voltage is now connected to the upper potential of the DC voltage, and this lasts for half the period.

[0055] According to the invention, the second inverter 2 is operated with inverted switching edges relative to the first inverter. Figure 1For example, a pulse width modulation ratio of 50% is again selected. However, in the series connection of the second inverter 2, at the beginning of the pulse width modulation period, the upper semiconductor switch of the series connection is closed and the lower semiconductor switch of the series connection is opened. The connection for the phase voltage of the second inverter 2 belonging to this series connection is therefore connected to the upper potential of the DC voltage, i.e. the intermediate circuit voltage U_z. After a quarter of the period of the pulse width modulation period has elapsed, the upper semiconductor switch is opened and the lower one is closed, so that the connection for the phase voltage is now connected to the lower potential of the DC voltage, whereby this lasts for half the period.

[0056] If other pulse width modulation ratios are controlled in the series circuits instead of 50%, the respective switching edge is shifted to plus + or minus -, as can be seen from the Figure 1 visible. Thus, the semiconductor switches of the half-bridge of the first inverter 1 do not switch at exactly the same time as the half-bridge of the second inverter 2. In this way, compensating currents in the intermediate circuit, i.e. between the DC voltage side connections of the inverters (1, 2), are at least reduced or even completely avoided.

[0057] This advantage of the invention is particularly important when very long cables are used from the AC-side connection of the respective inverter (1, 2) to the respective electric motor. This is because the cables and motors have high earth capacitances, so that a common line filter arranged on the line-fed rectifier providing the DC voltage is exposed to high leakage currents.

[0058] If the first switching edge jumps to the upper potential within the pulse width modulation period, the pulse width modulation has a positive polarity. If the first switching edge jumps to the lower potential within the pulse width modulation period, the pulse width modulation has a negative polarity.

[0059] To synchronize the pulse width modulation of the two inverters (1, 2), a synchronization signal is transmitted periodically. For this purpose, the signal electronics of the first inverter 1 are preferably connected to the signal electronics of the second inverter 2 via a data bus connection. In the simplest case, this data bus connection is implemented as a wired connection, particularly a shielded cable.

[0060] Alternatively, the synchronization signal is modulated onto the DC-side connection of the inverters (1, 2). Since the upper potential of the DC-side connection of the first inverter 1 is preferably connected to the upper potential of the DC-side connection of the second inverter 1 via a busbar to enable the passage of a strong current, the synchronization signal is modulated onto the current present in the busbar. The medium-frequency or high-frequency synchronization signal is coupled to the busbar in the first inverter 1 via a capacitor; the signal is also coupled out in the second inverter 2 via a capacitor. Alternatively, an inductive and thus safe and potential-free coupling and decoupling would be possible, but this would result in greater complexity.

[0061] In further embodiments according to the invention, the described inversion of the pulse width modulation signal in the second inverter 2 is only operated as long as the difference between the two pulse width modulation ratios is less than 50%. If this 50% is exceeded, the inversion is canceled and a synchronous, equally timed pulse width modulation signal is used.

[0062] Alternatively, the quotient of the two pulse width modulation ratios can also be used as a criterion. If this quotient exceeds 1, the inversion described above is applied; otherwise, it is not applied.

[0063] In this way, a reduction in the compensating currents can be achieved even when the two inverters (1, 2) have very different operating points. This is the case, for example, when the first inverter 1 generates a high phase voltage, in particular a potential close to the upper potential of the DC voltage, and the second inverter 2 generates a low phase voltage, in particular a potential close to the lower potential of the DC voltage. An example of a high phase voltage is 0.9 U_z, and an example of a low phase voltage is 0.1 * U_z.

[0064] As in Figure 3 As shown, a second drive system has a data bus 35, via which a supply module designed as master 3 is connected to inverters (31, 32, 33, 34) for data exchange.

[0065] The supply module has a mains-powered rectifier, from whose DC voltage side connection the aforementioned inverters (31, 32, 33, 34) are powered. For this purpose, the DC voltage side connections of the inverters (31, 32, 33, 34) are connected in parallel to the DC voltage side connection of the rectifier.

[0066] The rectifier is preferably designed to be capable of regenerating energy, in particular as an AC / DC converter which, when the drive system's power is predominantly motor-driven, rectifies electrical power from the AC voltage supply network and makes it available to the inverters at the DC-side connection as an intermediate circuit voltage, and when the drive system's power is predominantly generator-driven, feeds electrical power from the DC-side connection of the rectifier back into the AC voltage network.

[0067] In addition, when the drive system is commissioned, the supply module designed as master 30 first assigns the bus addresses to the inverters (31, 32, 33, 34) designed as bus participants and arranged serially with respect to the data bus.

[0068] To this end, the master 30 assigns a first bus address to the first inverter 31 in the serial arrangement, as seen from the master. This is done by the master 30 generating a voltage signal that signals the first inverter 31, i.e., the one directly connected to an electrical line, to adopt the bus address contained in the next broadcast telegram sent by the master as its own bus address. The first inverter 31 then generates a similar voltage signal for the second inverter 32, so that the bus address contained in the next broadcast telegram is adopted by the second inverter 32. This address assignment process continues until the last inverter 34 implemented as a bus participant.

[0069] After or upon completion of address assignment, the master sends a predefined pulse width modulation polarity to the last bus node, or the last node uses a default value for its polarity. This defines the pulse width modulation for the last inverter, specifically the direction of the first switching edge within each pulse width modulation period. For example, the direction of this first switching edge is specified as a rising edge rather than a falling edge.

[0070] The last inverter 34 then generates a voltage signal on the or on another electrical line, which specifies an inverted edge direction for the first switching edge of its pulse width modulation to the preceding inverter 33. It is also easy to implement this for the last inverter 34 to transmit a polarity inverted to its own polarity to the preceding inverter 33. This process is continued up to the first inverter 31, so that each of the nearest adjacent bus devices has inverted edge directions for their respective first switching edges in the respective pulse width modulation period.

[0071] Advantageously, the master does not have to calculate in advance which inverter will have which polarity and therefore does not have to make a central specification, but the polarity is assigned decentrally.

[0072] In another embodiment of the invention, after the addresses have been assigned to the bus nodes, the rated power of the respective inverter is determined, and the polarity is then assigned based on this, so that approximately half of the rated power of the drive system has a first polarity and the remaining inverters have the inverted polarity. In addition, the polarity is preferably assigned such that the nearest adjacent inverters along the serial connection have as different polarities as possible.

[0073] The polarity assignment is therefore carried out according to these two optimization criteria.

[0074] The second inverter 32 has two AC-side connections, so that a second electric motor M2 and a third electric motor M3 can each be supplied with a pulse-width modulated voltage. The same polarity is used for both pulse-width modulations, since both pulse-width modulations are implemented in the same device, i.e., within the same housing.

[0075] It is also important for the drive system that a line filter is arranged between the AC voltage supply network, which is preferably designed as a three-phase voltage network, and the AC voltage side connection of the rectifier of the supply module.

[0076] This line filter has three capacitors that are electrically connected to each other at their first terminal and connected to a respective phase of the AC-side terminal of the supply module's rectifier at their other terminal. Thus, a star point is formed at each of the first terminals. This star point is galvanically connected to a protective conductor and / or to electrical ground.

[0077] At the DC voltage side connection of the rectifier, a voltage divider is formed from two series-connected capacitors, the connecting node of which, in particular the potential created by the division of the intermediate circuit voltage, is galvanically connected to the star point, in particular also to the protective conductor and / or to electrical earth.

[0078] Furthermore, three additional capacitors are provided, which are electrically connected to each other at their first terminal and connected to a respective motor phase at their other terminal. Thus, a star point is also formed at their first terminal, which is electrically connected to the aforementioned star point.

[0079] The inverter, in turn, has three half-bridges connected in parallel to each other, powered by the DC voltage present at the inverter's DC-side terminal. Their connecting nodes, in particular the bridge branches, are connected to the motor phases. Each of the half-bridges has a series circuit consisting of an upper and a lower controllable semiconductor switch.

[0080] In another embodiment of the invention, each inverter is as shown in Figure 3shown, connected to its neighboring inverter or master with a forward channel and a reverse channel.

[0081] At the beginning of commissioning or initialization, each inverter first reports by sending a telegram to the master 30 on the reverse channel, which is then forwarded by the upstream inverter via its reverse channel until it reaches the master 30.

[0082] To assign the address, the master 30 sends a bus address to the first inverter 31 on the forward channel, which the first inverter 31 adopts for itself. The first inverter 31 then adds or increments a value to the bus address and transmits this resulting bus address to the second inverter 32 on the forward channel. The second inverter 32 then proceeds in the same way, followed by the third inverter 33. If the fourth inverter 33 sends its incremented bus address on its forward channel and then receives no response on its input for the reverse channel within a certain time period, it determines that it is the last inverter in the drive system.It therefore reads the default value of the parameter describing the polarity of its pulse width modulation from its data memory and activates it in the signal electronics of its inverter that executes the pulse width modulation.

[0083] The last inverter 34 then sends information about the polarity of the last inverter 34 to the upstream inverter 33 via the reverse channel. The inverter 33 receives this information and activates the polarity inverted to the polarity of the last inverter 34 in its pulse width modulation. This process continues until the first inverter 31.

[0084] However, if an inverter, which is also implemented as a bus participant and thus has only a single bus address, is multi-component, i.e., composed of two individual inverters arranged in a common housing, the information received from the downstream inverter via the reverse channel is forwarded unchanged to the inverter upstream of this inverter composed of two individual inverters, since the two individual inverters already have inverted polarity. This inverted polarity is preferably permanently fixed by hardware.

[0085] Such an inverter composed of two individual inverters, i.e. single inverters, can also be referred to as a double inverter or double axis. List of reference symbols

[0086] 1first inverter 2second inverter 30Master 31First inverter as first slave 32Second inverter as third slave 33Third inverter as third slave 34Last inverter as last slave 35Data bus M1first electric motor M2second electric motor M3third electric motor M4fourth electric motor Mnlast electric motor

Claims

1. Method for operating a drive system comprising a plurality of, in particular more than two, inverters (31, 32, 33, 34) and a data bus (35), wherein a respective electric motor (M1, M2, M3, M4, Mn) is fed from the AC-side terminal of the respective inverter (31, 32, 33, 34), wherein the DC-side terminals of the respective inverters (31, 32, 33, 34) are connected in parallel with one another, and this parallel connection is connected to the DC-side terminal of a rectifier, in particular a controllable and / or regenerative rectifier, in particular by means of conductor rails, wherein the respective inverter (31, 32, 33, 34) comprises respective semiconductor switches which are actuated according to a respective pulse width modulation, wherein the inverters (31, 32, 33, 34) are configured as bus subscribers of a data bus (35), to which a module configured as master (30) is also connected, in particular wherein the module comprises the rectifier, wherein, in a first method step, in particular during initialization or start-up of the drive system, a respective bus address is assigned to each inverter (31, 32, 33, 34), and thereafter, in a second method step, there is specified to each inverter (31, 32, 33, 34) the polarity of its pulse width modulation, in particular its pulse width modulation method, wherein the polarity of the pulse width modulation of a first of the inverters (31, 32, 33, 34) differs from the polarity of the pulse width modulation of a second of the inverters (31, 32, 33, 34), in particular such that the pulse width modulation of the actuation signals for the controllable semiconductor switches of the first of the inverters (31, 32, 33, 34) is implemented in a manner clocked anti-synchronously to the pulse width modulation of the actuation signals for the controllable semiconductor switches of the second of the inverters (31, 32, 33, 34), characterized in that for address assignment, a respective inverter (31, 32, 33, 34) supplies to a downstream inverter (31, 32, 33, 34) a voltage signal by which the respective downstream inverter (31, 32, 33, 34) is signaled to adopt the address contained in the chronologically next broadcast telegram from the master (30) as its own bus address and to supply a further voltage signal to a further inverter (31, 32, 33, 34) if such an inverter is present, and, if not, to adjust the polarity of its pulse width modulation to the polarity information contained in the broadcast telegram.

2. Method according to claim 1, characterized in that each inverter (31, 32, 33, 34) comprises half-bridges which are connected in parallel with one another and which are fed from the DC voltage, each half-bridge being configured as a series connection of at least two controllable semiconductor switches, wherein the semiconductor switches of the respective inverter (31, 32, 33, 34) are actuated by pulse-width-modulated actuation signals according to the pulse width modulation of the inverter (31, 32, 33, 34) and the polarity of the latter.

3. Method according to claim 1 or 2, characterized in that, at the start of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter (31) is open and the lower switch of this first half-bridge of the first inverter (31) is closed, in particular wherein the upper switch is connected to the upper potential of the voltage applied to the DC-side terminal of the inverter (31, 32, 33, 34), and wherein the lower switch is connected to the lower potential of the voltage applied to the DC-side terminal of the inverter (31, 32, 33, 34).

4. Method according to any one of the preceding claims, characterized in that, starting from the master (30), the inverters (31, 32, 33, 34) are arranged in series along the data bus (35), wherein, in the first method step, starting from the master and in particular successively, each inverter (31, 32, 33, 34) assigns a bus address to the inverter (31, 32, 33, 34) arranged downstream of it in the series, until an inverter (31, 32, 33, 34) recognizes itself as the last in the series as a result of failing to further assign a bus address, and then, in the second method step, sets a default value as the polarity of its pulse width modulation, after which, starting from the last inverter (31, 32, 33, 34) and in particular successively, each inverter (31, 32, 33, 34) transmits to the inverter (31, 32, 33, 34) arranged upstream of it in the series a polarity that is the inverse of its own polarity, which the upstream inverter (31, 32, 33, 34) sets as the polarity of its pulse width modulation, in particular if said upstream inverter is not configured as a double inverter, in particular a double axis, and otherwise forwards it to the inverter (31, 32, 33, 34) arranged next upstream, in particular wherein the inverter (31, 32, 33, 34) configured as a double inverter has a single bus address and two single inverters arranged in a common housing, the pulse width modulations of which have a mutually inverse polarity.

5. Method according to any one of the preceding claims, characterized in that the data bus (35) comprises a forward channel and a reverse channel such that each inverter (31, 32, 33, 34) has an input and an output of the forward channel and an input and an output of the reverse channel, wherein the master (30) is connected to the input of the forward channel of the first inverter (31) and to the output of the reverse channel of the first inverter (31), wherein, for address assignment, the master (30) sends to a first inverter (31, 32, 33, 34), via the forward channel, a first bus address, which the first inverter (31) adopts as its own bus address, wherein the first inverter (31) generates from the first bus address a second bus address, in particular by incrementation, and sends this via the forward channel to the second inverter (32), wherein the second inverter (32) adopts the second bus address and generates from the second bus address a third bus address, in particular by incrementation, and forwards this via its forward channel, wherein each further inverter (31, 32, 33, 34) adopts the bus address received via the input of its forward channel as its own bus address, generates from the received bus address a further bus address, in particular by incrementation, and sends this via the forward channel to the downstream inverter (31, 32, 33, 34), wherein a last inverter (31, 32, 33, 34) recognizes itself as the last inverter (31, 32, 33, 34) as a result of failing to send onward the bus address that it has generated.

6. Method according to any one of claims 1 to 3, characterized in that, for address assignment, the master (30) sends a broadcast telegram via the data bus (35) recurrently over time, in particular at start-up and recurrently over time, which assigns respective information about a polarity to a respective piece of address information, in particular such that a first polarity is assigned to the first inverter (31) and a second polarity, which in particular is different from the first, is assigned to the second inverter (32).

7. Method according to claim 6, characterized in that a voltage signal can be fed from the master (30) to a first inverter (31), and a voltage signal can be fed from a respective inverter (31, 32, 33, 34) to a respective next inverter (31, 32, 33, 34), wherein the respective inverter (31, 32, 33, 34) receiving the voltage signal then takes the information regarding the address and / or polarity that is contained in the chronologically next broadcast telegram from the master (30) for itself and only thereafter sends a voltage signal to the respective next inverter (31, 32, 33, 34), in particular wherein the inverters (31, 32, 33, 34) are arranged in series with regard to the forwarding of the voltage signal and / or with regard to the data bus (35), in particular such that another inverter (31, 32, 33, 34) is arranged downstream of each of the inverters (31, 32, 33, 34) from the first inverter (31) to the penultimate inverter (32) in the series.

8. Method according to claim 6 or 7, characterized in that a last inverter (31, 32, 33, 34), in particular from which no voltage signal can be fed to any downstream inverter (31, 32, 33, 34), specifies to the inverter (31, 32, 33, 34) arranged upstream of it the polarity that is the inverse of its own polarity used in the pulse width modulation, after which said upstream inverter (31, 32, 33, 34) specifies to the inverter (31, 32, 33, 34) arranged upstream of it the polarity that is the inverse of its own polarity used in the pulse width modulation.

9. Method according to any one of claims 1 to 3, characterized in that, after the address assignment to the inverters (31, 32, 33, 34), the master (30) transmits to the inverters the polarity that is to be used in their respective pulse width modulation, wherein the polarities are in each case assigned in such a way that the sum of the nominal power of the respective inverter (31, 32, 33, 34) multiplied by the respective polarity thereof becomes minimal in terms of absolute value, in particular wherein adjacently arranged inverters (31, 32, 33, 34) preferably have a different polarity than each other.

10. Method according to any one of the preceding claims, characterized in that the first inverter (31) comprises half-bridges which are connected in parallel with one another and which are fed from the DC voltage, each half-bridge being configured as a series connection of at least two controllable semiconductor switches, wherein the second inverter (32) comprises half-bridges which are connected in parallel with one another and which are fed from the DC voltage, each half-bridge being configured as a series connection of at least two controllable semiconductor switches, wherein the semiconductor switches of the first inverter (31) are actuated by pulse-width-modulated actuation signals, wherein the semiconductor switches of the second inverter (32) are actuated by pulse-width-modulated actuation signals, wherein - as long as the quotient of the pulse width modulation ratio of the actuation signal for a first semiconductor bridge of the first inverter (31) and the pulse width modulation ratio of the actuation signal for a second semiconductor bridge of the second inverter (32) is below a threshold value, in particular 1, at the start of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter (31) is open and the lower switch of this first half-bridge of the first inverter (31) is closed, and the upper switch of the second half-bridge of the second inverter (32) is closed and the lower switch of this second half-bridge of the second inverter (32) is open; - and, as long as the quotient of the pulse width modulation ratio of the actuation signal for a first semiconductor bridge of the first inverter (31) and the pulse width modulation ratio of the actuation signal for a second semiconductor bridge of the second inverter (32) is above the threshold value, in particular 1, at the start of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter (31) is open and the lower switch of this first half-bridge of the first inverter (31) is closed, and the upper switch of the second half-bridge of the second inverter (32) is open and the lower switch of this second half-bridge of the second inverter (32) is closed.

11. Method according to any one of the preceding claims, characterized in that the drive system comprises a first inverter (31) and a second inverter (32), wherein a first electric motor (M1) is fed from the AC-side terminal of the first inverter (31), wherein a second electric motor (M2) is fed from the AC-side terminal of the second inverter (32), wherein the DC-side terminal of the first inverter (31) is connected in parallel with the DC-side terminal of the second inverter (32) and this parallel connection is supplied from a DC voltage, in particular a DC link voltage, in particular by means of conductor rails, wherein the first inverter comprises half-bridges which are connected in parallel with one another and which are fed from the DC voltage, each half-bridge being configured as a series connection of at least two controllable semiconductor switches, wherein the second inverter (32) comprises half-bridges which are connected in parallel with one another and which are fed from the DC voltage, each half-bridge being configured as a series connection of at least two controllable semiconductor switches, wherein the semiconductor switches of the first inverter (31) are actuated by pulse-width-modulated actuation signals, wherein the semiconductor switches of the second inverter (32) are actuated by pulse-width-modulated actuation signals, characterized in that - as long as the difference between the pulse width modulation ratio of the actuation signal for a first semiconductor bridge of the first inverter (31) and the pulse width modulation ratio of the actuation signal for a second semiconductor bridge of the second inverter (32) is below a threshold value, in particular 50%, at the start of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter (31) is open and the lower switch of this first half-bridge of the first inverter (31) is closed, and the upper switch of the second half-bridge of the second inverter (32) is closed and the lower switch of this second half-bridge of the second inverter (32) is open; - and, as long as the difference between the pulse width modulation ratio of the actuation signal for a first semiconductor bridge of the first inverter (31) and the pulse width modulation ratio of the actuation signal for a second semiconductor bridge of the second inverter (32) is above the threshold value, in particular 50%, at the start of a respective pulse width modulation period, the upper switch of the first half-bridge of the first inverter (31) is open and the lower switch of this first half-bridge of the first inverter (31) is closed, and the upper switch of the second half-bridge of the second inverter (32) is open and the lower switch of this second half-bridge of the second inverter (32) is closed.

12. Method according to any one of the preceding claims, characterized in that the DC voltage is made available at the DC-side terminal of a mains-powered rectifier, in particular an AC / DC converter, in particular wherein the rectifier, in particular at the AC-side terminal thereof, is supplied from an AC voltage network, in particular with a three-phase voltage, in particular wherein the DC-side terminal of the rectifier is connected in parallel with the DC-side terminal of the first inverter (31) and with the DC-side terminal of the second inverter (32).

13. Method according to any one of the preceding claims, characterized in that the pulse width modulation signals of the first inverter (31) run synchronously to the pulse width modulation signals of the second inverter (32), in particular are synchronized therewith, and / or in that the start of the pulse width modulation periods of the first and second inverter (32) occurs synchronously, and / or in that, within each pulse width modulation period, the first switching edge of an actuation signal for an upper semiconductor switch of the first inverter (31) is inverted and / or occurs inversely in relation to the first switching edge of an actuation signal for an upper semiconductor switch of the second inverter (32), and / or in that one of the controllable semiconductor switches, i.e. the upper semiconductor switch, of a respective half-bridge is connected to the upper potential of the DC voltage, and / or in that one of the controllable semiconductor switches, i.e. the lower semiconductor switch, of a respective half-bridge is connected to the lower potential of the DC voltage, and / or in that, at the start of a respective pulse width modulation period, the upper switch of a first half-bridge of the first inverter (31) is open and the lower switch of this first half-bridge of the first inverter (31) is closed, and the upper switch of a second half-bridge of the second inverter (32) is closed and the lower switch of this second half-bridge of the second inverter (32) is open.

14. Method according to any one of the preceding claims, characterized in that a synchronization signal, in particular a synchronization signal containing synchronization pulses, is modulated onto conductor rails which connect the DC-side terminals of the inverters (31, 32, 33, 34) to one another and to the DC-side terminal of the rectifier, or in that a synchronization signal, in particular a synchronization signal containing synchronization pulses, is sent recurrently over time by the master (30) as a broadcast telegram to all the inverters (31, 32, 33, 34) by means of the data bus (35), in particular wherein the pulse width modulation of all the inverters (31, 32, 33, 34) is synchronized as a function of the synchronization signal.

15. Drive system for carrying out the method according to any one of the preceding claims, characterized in that the DC-side terminals of the inverters (31, 32, 33, 34) are connected to one another and to the DC-side terminal of the rectifier by means of conductor rails, and in that a respective inverter (31, 32, 33, 34) is connected to at least one upstream or downstream inverter (31, 32, 33, 34) by means of at least one line so as to feed a voltage signal by means of at least one electrical line.