METHOD TO DISPLAY AN ANIMATION DURING THE START-UP OF A DEVICE

Description

TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of electronic devices intended to be connected to a display means. The present invention relates to a method for displaying an animation by an electronic device for a terminal and in particular a method for displaying an animation during the start-up phase of an electronic box. The invention also relates to a device implementing said method. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Starting an electronic device is done in several stages. First, the basic input / output system initializes the RAM. Once the initialization stage is complete, the basic input / output system loads a startup program or boot program into the RAM. This boot program is responsible for initializing peripherals such as a display chip and loading the operating system into RAM. However, the operating system implementing the device is not immediately operational. As a result, during the first moments after starting the device, the operating system does not yet have access to the display chip drivers and therefore cannot control the display chip to inform, for example, about the progress of the startup.However, during these early moments, the boot program can be programmed to statically configure the video output chip registers to display an image indicating that the device has been powered on.

[0003] To produce an image, a display chip typically has two registers: a video output register and a display register. The video output register can be configured to perform progressive display or interlaced display. When the video output register is configured for progressive display, an image is displayed line by line. When the video output register is configured for interlaced display, the image is divided into a first field, called an odd field, comprising the odd lines of the image, and a second field, called an even field, comprising the even lines of the image, and the image is displayed first by displaying the odd field and then by displaying the even field.The display register contains a chained configuration table, otherwise called a node, this node containing in particular the memory address of the image (in the case of a progressive mode display) or of the frame to be displayed (in the case of an interlaced mode display), the choice of the display mode through the video output register conditioning the configuration of the display register.

[0004] In progressive display, the node in the display register contains the memory address of the image to be displayed, but also its own address, or in other words, the node points to itself. Display is therefore done by continuously traversing the node.

[0005] In the context of an interlaced display, the display register contains a first node comprising the address of the odd frame of the image to be displayed and allows the display of the odd lines of this image. This first node also includes the memory address of the second node. The second node contains the address of the even frame of the image to be displayed and allows the display of the even lines of this image. The second node also includes the memory address of the first node. The display is therefore done by scanning the first node then scanning the second node leading to the display of the odd lines then the even lines of the image to be displayed. Thus, in contrast to progressive display, the display alternates between the display of the odd lines (or odd frame) and the display of the even lines (or even frame) of the same image.

[0006] However, since the registers are programmed statically, it is not possible to display an animation, as an animation requires at least two images. It is therefore known to display a static image during the boot phase, and this image can be displayed either via an interlaced display or via a progressive display. The animation can therefore only appear on the display device when the operating system has access to the display chip drivers. Depending on the operating system and the security measures in place, this animation only appears 5 to 15 seconds after the electronic device has actually started up. During this interval, it is common for the user to mistake the fixed image for a malfunction of the electronic box and unplug it during the boot sequence.The document "Buffer mechanism for pel positioning of multiple video images, including overlapping, on a raster-scan CRT", IBM TECHNICAL DISCLOSURE BULLETIN, INTERNATIONAL BUSINESS MACHINES CORP. (THORNWOOD), US, vol. 29, no. 11, April 1, 1987 (1987-04-01), pages 4714-4717, describes a buffer mechanism for positioning multiple video images, including overlapping ones, on a raster-scan CRT display. The system uses five main components (Loader, VDE Buffer, Transformer, Scan Buffer, and Displayer) to efficiently manage the storage, transformation, and display of video defined elements (VDEs), thereby enabling precise pixel positioning and controlled image overlay.

[0007] There is therefore a need to display an animation during the very first moments of the startup phase of an electronic device, that is to say before the operating system takes control of the display, demonstrating that said startup has been successful. SUMMARY OF THE INVENTION

[0008] The invention offers a solution to the problems mentioned above, by proposing a programming method allowing the display of an animation from the first moments of the start-up phase.

[0009] For this, the invention proposes a method for displaying an animation by a display chip of an electronic device, said electronic device comprising a non-volatile memory and a random access memory, said display chip comprising a video output register and a display register; the method comprising a first static programming phase comprising: a video output register configuration step; a writing step of n images in RAM, n being an integer greater than or equal to two; a step of writing into the RAM of a plurality of nodes such that each node comprises the RAM address of at least a portion of an image among the n images as well as the RAM address of the next node, the last node comprising the RAM address of the first node; a step of configuring the display register.

[0010] The method also comprises a second phase of reading the n images by said display chip, said reading being done using the display register so as to display said animation.

[0011] Thus, the n images are displayed successively, generating an animation from the first moments of starting the device. Indeed, given that each node also includes an address of at least a part of an image among the n images, the display of a succession of images giving rise to an animation is obtained. At least a part of an image means that a node can contain the memory address of an even or odd frame of an image or the memory address of an image. Furthermore, the animation is based on static programming of the display registers and ingeniously takes advantage of the progressive or interlaced reading mode in order to display an animation. It is therefore not necessary to adapt the display chip to the method of the invention.

[0012] The invention also provides an electronic device comprising a non-volatile memory, a random access memory and a display chip, said display chip comprising a video output register and a display register. The device further comprises means for implementing the method according to the invention.

[0013] An electronic device is understood to mean any electronic device intended to be connected to a display means. The electronic device according to the invention may, for example, consist of an electronic box intended to be connected to a television such as an STB (Set Top Box). Alternatively, the display device may be incorporated into the electronic device. For example, the electronic device according to the invention may consist of a smartphone. Furthermore, a display chip is understood to mean a chip which includes in particular one or more means of connection to a display device. For example, the display chip may include an HDMI or VGA port.

[0014] The invention also provides a computer program product comprising instructions which cause the device according to the invention to execute the steps of the display method according to the invention.

[0015] The invention also provides a computer-readable medium, on which the computer program according to the invention is recorded.

[0016] In addition to the characteristics which have just been mentioned in the preceding paragraph, the display method according to one aspect of the invention may have one or more additional characteristics among the following, considered individually or according to all technically possible combinations.

[0017] Advantageously, a boot program responsible for booting an operating system is stored in the non-volatile memory, the electronic device comprising an elementary input / output system configured to load said boot program into RAM, the n images being included in said boot program so that the step of writing the n images into RAM is carried out when said boot program is loaded by said elementary input / output system.

[0018] Thus, the storage of the startup program and the images composing the animation to be displayed is carried out in a single step.

[0019] Advantageously, the step of configuring the video output register and the display register is performed by the elementary input / output system. Thus, the animation display can take place as soon as the startup program is loaded.

[0020] Alternatively, a boot program responsible for booting an operating system is stored in the non-volatile memory, the electronic device comprising an elementary input / output system configured to load said boot program into RAM, the n images being stored in the non-volatile memory and the step of writing the n images into the RAM being done by copying the images stored in the non-volatile memory to the RAM by the boot program.

[0021] Thus, it is possible to obtain an animation comprising a large number of images without slowing down the loading of the startup program, the loading of the latter into memory being done independently of the loading of the images making up the animation.

[0022] Advantageously, the step of configuring the video output register and the display register is performed by the startup program. Thus, the animation display can take place as soon as the startup program is loaded.

[0023] Advantageously, the n images are stored as compressed images. This reduces the memory footprint of the compressed images.

[0024] Preferably, the writing of the n images in the RAM is done in a dedicated area of ​​the RAM. This prevents the memory space containing the images from being allocated to the operating system when it loads. The animation can therefore continue even after the operating system has loaded, which gives the operating system time to load the display chip drivers. This avoids an interruption of the animation during the startup phase.

[0025] Advantageously, the configuration of the video output register during the video output register configuration step is carried out so that the display is in progressive mode and that each node includes the address of an image.

[0026] This results in a higher quality animation than an animation of the same resolution in interlaced mode.

[0027] Advantageously, the animation is broken down into a first graphic plane and a second graphic plane, the first graphic plane constituting a fixed part of the animation and the second graphic plane constituting a changing part of the animation, the display chip comprising means for superimposing the first graphic plane on the second graphic plane; and in that the step of writing in the RAM of a plurality of nodes comprises two sub-steps: a first sub-step of writing a node comprising the address in RAM MV of an image intended to be displayed in the first graphics plane, the node further comprising its own address in RAM MV; a second sub-step of writing a plurality of nodes Ni, each node comprising the address in RAM MV of an image intended to be displayed in the second graphics plane as well as the address in RAM MV of the following node, the last node comprising the address in RAM MV of the first node.

[0028] Advantageously, the configuration of the video output register during the step of configuring the video output register is carried out so that the display is in interlaced mode, the plurality of nodes comprising even nodes and odd nodes, and each odd node comprising the address of an odd frame of an image and each even node comprising the address of an even frame of an image.

[0029] Using interlaced mode allows animation to be displayed in high resolution even if the bandwidth of the video connection connecting the display chip to a display medium is low.

[0030] Advantageously, the animation is broken down into a first graphic plane and a second graphic plane, the first graphic plane constituting the fixed part of the animation and the second graphic plane constituting the changing part of the animation, the display chip comprising means for superimposing the first graphic plane on the second graphic plane; and in that the step of writing in the RAM of a plurality of nodes comprises two sub-steps: a first sub-step of writing a first node and a second node, the first node comprising the RAM address of the odd frame of an image intended to be displayed in the first graphics plane as well as the RAM address of the second node, the second node comprising the RAM address of the even frame of the image intended to be displayed in the first graphics plane as well as the RAM address of the first node; a second sub-step of writing a plurality of nodes, each odd node comprising the RAM address of the odd frame of an image intended to be displayed in the second graphics plane and each even node comprising the RAM address of the even frame of an image intended to be displayed in the second graphics plane, the last node comprising the RAM address of the first node.

[0031] This avoids storing redundant elements in memory between two images, the redundant elements making up the fixed part of the animation.

[0032] Using an animation that takes into account the first graphic plane and the second graphic plane therefore saves memory. BRIEF DESCRIPTION OF THE FIGURES

[0033] The figures are presented for information purposes only and in no way limit the invention and illustrate: there figure 1 , an electronic device implementing a method according to the invention as well as an example of a node; the figure 2 , a flowchart of an embodiment of the method according to the invention; the figure 3 , a first example of embodiment of the method according to the invention; the figure 4 , a second example of embodiment of the method according to the invention. DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT OF THE INVENTION

[0034] Unless otherwise specified, the same element appearing in different figures has a single reference.

[0035] According to a first embodiment illustrated in the Figures 1A-B And 2 , the invention relates to an electronic device DE comprising a non-volatile memory MN, a random access memory MV and a display chip PA, said display chip PA comprising a video output register RV and a display register RA. The invention also relates to a display method using a display chip intended to be implemented in such an electronic device.

[0036] MV RAM can consist of dedicated memory on the PA chip or RAM (Random Access Memory) for an operating system. MN non-volatile memory can consist of a hard disk or flash memory.

[0037] The method according to the invention comprises a first static programming phase comprising a step E1 of configuring the RV video output register. This step may for example consist of configuring the RV video output register so as to obtain a progressive or interlaced display.

[0038] The first phase of the method further comprises a step E2 of writing n images into the RAM MV, n being an integer greater than or equal to two. Since an animation consists of at least two images, it is indeed necessary in this step that the writing concerns at least two images. Thus, during this step, the images making up the animation are copied from the non-volatile memory MN to the RAM MV.

[0039] The first phase of the method further comprises a step E3 of writing into the RAM of a plurality of nodes Ni. Here, the term "plurality of nodes Ni" means a chained configuration table such that each node Ni comprises the RAM address Nin of at least part of an image as well as the RAM address Nir of the following node, the last node then comprising the RAM address of the first node N1.

[0040] The first phase of the method also comprises a step E4 of configuring the display register RA. This step may consist of copying into the display register RA the first node of the plurality of nodes Ni loaded into RAM.

[0041] The method according to the invention also comprises a second phase of reading the n images by said display chip (PA), said reading being done using the display register (RA) so as to display said animation.

[0042] In the method according to the invention, the configuration of the registers is carried out statically. In other words, once configured, the registers are no longer reconfigured and the animation occurs by taking advantage of the operation of the display chip. In other words, the method according to the invention can be used without any particular adaptation of the display chip and allows the latter to display an animation through a static configuration of the display register and the video output register.

[0043] Indeed, as explained previously, the display chip PA displays the image or the part of the image whose address is included in a first node loaded into the display register RA. Once this image or this part of the image is displayed, a second node whose address in RAM MV is included in the first node is in turn loaded into the display register RA. In this way, the chip copies from the RAM into the display register successively the nodes of the plurality of nodes Ni.

[0044] It is therefore understood that step E3 of writing the plurality of nodes Ni is a function of the display mode chosen during step E1 of configuring the video output register RV.

[0045] In one embodiment, the display mode is a progressive display mode. The step E3 of writing the plurality of nodes Ni is then performed so that each node Ni comprises the address Nin of an image as well as the address Nir of the following node, the last node comprising the address of the first node N1. By configuring the nodes Ni in this way and the display being done in progressive mode, the reading of a node Ni by the display chip PA leads to the display of an image. Each node Ni being relative to an image, the animation will be done by the reading, by the display chip PA, of the plurality of nodes Ni. Taking the example of a refresh rate of 60Hz, the maximum animation speed is therefore 30 cycles per second. It is however possible to envisage configuring the nodes Ni so that a plurality of nodes point to the same image in order to be able to modulate the animation speed.

[0046] In an example of realization illustrated in the figure 3, the first node N1 comprises the RAM address N1n of the image I1 as well as the RAM address of the following node N2. The node N2 comprises the RAM address of the image 11 as well as the RAM address of the following node N3. The third node N3 comprises the RAM address of the image I2 as well as the RAM address of the node N4. The node N4 comprises the RAM address of the image I2 as well as the RAM address of the first node N1, the node N4 being the last node of the plurality of nodes. By traversing the four nodes N1, N2, N3, N4, the display chip PA successively and cyclically displays two images 11, I2 thus producing an animation. In the case where the refresh rate is 60Hz, an animation lasting 1 / 15 of a second is thus obtained, in other words 15 animation cycles per second.The nodes can also be configured so that the first 30 nodes contain the RAM address of a first image and the next 30 nodes contain the RAM address of a second image. In this case, the animation speed is only 2 images per second, in other words one animation cycle per second. Thus, the animation sequence can be modulated by changing the number of nodes containing the RAM address of the different images making up the animation.

[0047] In an alternative embodiment, the display mode is an interlaced display mode and each image is divided into a first frame called an odd frame comprising the odd lines of the image and a second frame called an even frame comprising the even lines of the image. The step E3 of writing the plurality of nodes Ni is then carried out so that each node Ni comprises the RAM address Nin of a frame of an image as well as the RAM address Nir of the following node, the last node comprising the RAM address Nir of the first node N1. By configuring the nodes Ni in this way, it is ensured that the frames of the images will be displayed one after the other. Since the display is in interlaced mode, reading a node Ni leads to the display of a frame. It is therefore necessary to browse two nodes to display an image. Each node Ni being relative to a frame of an image, the animation comprising nimages will be done by reading at least 2 n knots.

[0048] In an example illustrated in the figure 4, nodes N1 and N3 each correspond to an odd frame T1 and nodes N2 and N4 each correspond to an even frame TP. The first node N1 comprises the RAM address N1n of the odd frame I1TI of a first image I1 as well as the RAM address N1r of the second node N2. The second node N2 comprises the RAM address of the even frame I1TP of the image I1 as well as the RAM address of node N3. Node N3 comprises the RAM address of the odd frame I2TI of a second image I2 as well as the RAM address of the fourth node N4. Node N4 comprises the RAM address of the even frame I2TP of the image I2 as well as the RAM address of the first node N1, node N4 being the last node. Assuming a 60Hz display refresh rate, the two images alternate every 1 / 15 of a second. In other words, the maximum animation speed is 15 cycles per second.However, we can consider configuring the Ni nodes so that a plurality of Ni nodes point to the same image in order to be able to modulate the animation speed. In other words, a first node points to the odd frame of an image and the next node points to the even frame of the same image, and this is done repeatedly over several consecutive pairs of nodes. For example, we can configure the nodes so that the first 30 nodes point to a first image (15 of the nodes pointing to the odd frame of the first image and 15 nodes pointing to the even frame of the first image) and the next 30 nodes point to a second image (15 of the nodes pointing to the odd frame of the first image and 15 nodes pointing to the even frame of the first image). Then, the animation speed is only 2 images per second. In other words, the animation speed is only 1 cycle per second.

[0049] Regardless of the display mode chosen, step E2 of writing n images into the RAM RV can be done in two distinct ways.

[0050] In one embodiment, a boot program is responsible for loading an operating system into memory and the n images are stored in said boot program. These images are therefore written into RAM MV at the same time as the boot program. In other words, in this embodiment, the loading of the images into RAM MV is carried out by the elementary input / output system. Since the images are available as soon as the boot program is loaded into memory, the elementary input / output system can also be in charge of the register configuration step, which makes it possible to have a display of the animation from the first moments of booting immediately after loading the boot program, and therefore the images, into RAM MV. This embodiment makes it possible to load into memory all of the elements necessary for the display in a single step.The basic input / output system may be a BIOS (Basic Input Output System) or a security coprocessor. A security coprocessor is a logical unit responsible for initializing the MV RAM, verifying the boot program by verifying a fingerprint of the latter, and storing the boot program in MV RAM. However, if the number or resolution of images is high, the memory size of the boot program into which the images have been incorporated may become large, which may slow down the operation of verifying the integrity of the boot program by the basic input / output system.

[0051] Another embodiment can then be envisaged in which the n images are stored in the non-volatile memory MN of the electronic device DE independently of the startup program and are loaded into RAM MV after the startup program has been loaded by said startup program. Thus, the memory footprint of the startup program is reduced. In this embodiment, the startup program can be in charge of configuring the video output registers RV and display RA.

[0052] In one embodiment, the n images are stored as compressed images, which makes it possible to reduce the memory footprint of the images. For example, a compression algorithm of the run length encoding (LRE) type can be considered. More generally, any compression algorithm supported by the PA display chip can be used. It can therefore also be a proprietary compression algorithm.

[0053] In one embodiment, the writing of the n images in the RAM is done in a dedicated area of ​​the RAM MV. This makes it possible to keep the images in memory once the operating system is loaded by preventing any overwriting of the images by at least part of the operating system code. Indeed, there is a delay between the moment when the operating system is loaded into memory and the moment when the operating system actually takes control of the display chip PA. Ensuring that the images remain in memory after the operating system is loaded makes it possible to guarantee that the animation will remain displayed until the display chip is actually taken over by the operating system.

[0054] In one embodiment, the animation may be decomposed into a first graphics plane and a second graphics plane, the first graphics plane constituting the fixed portion of the animation and the second graphics plane constituting the changing portion of the animation, the display chip comprising means for superimposing the first graphics plane on the second graphics plane.

[0055] When the display is carried out in progressive mode, the step of writing to the RAM of a plurality of nodes then comprises two sub-steps: a first sub-step of writing a node comprising the address in RAM MV of an image intended to be displayed in the first graphic plane, the node further comprising its own address in RAM; a second sub-step of writing a plurality of nodes Ni, each node comprising the address in RAM MV of an image intended to be displayed in the second graphic plane as well as the address in RAM MV of the following node, the last node comprising the address in RAM MV of the first node.

[0056] Alternatively, when the display is performed in interlaced mode, the step of writing to the RAM of a plurality of nodes comprises two sub-steps: a first sub-step of writing a first node and a second node, the first node comprising the address in RAM MV of the odd frame of an image intended to be displayed in the first graphics plane as well as the address in RAM MV of the second node, the second node comprising the address in RAM MV of the even frame of the image intended to be displayed in the first graphics plane as well as the address in RAM MV of the first node; a second sub-step of writing a plurality of nodes Ni, each odd node comprising the address in RAM MV of the odd frame of an image intended to be displayed in the second graphics plane and each even node comprising the address in RAM MV of the even frame of an image intended to be displayed in the second graphics plane, the last node comprising the address in RAM MV of the first node.

[0057] Thus, in these two alternative embodiments, the animation is only possible if the number of images is greater than three. Indeed, the animation is broken down into two parts: a first part relating to the fixed elements of the animation which will constitute the first graphic plane, a second part relating to the mobile elements of the animation. For example, in the case of an animation comprising a background on which a point flashes, the first plane will consist of the background and the second graphic plane will consist of the flashing point. In this example, the display of the background, that is to say the first graphic plane, will be done using a single node or a pair of nodes comprising the RAM address of the background image while the display of the second graphic plane will be done using a plurality of nodes Ni as explained previously.This is of course an example and we could consider a second plan consisting of a more complex animation with a larger number of images possibly associated with a larger number of nodes.

[0058] In these two alternative embodiments, step E4 of configuring the display register RA may consist of assigning a memory location of the display register RA to each graphics plane, copying into a first location of the display register RA the node (in the case of a progressive display) or the first node of the pair of nodes (in the case of an interlaced display) corresponding to the first graphics plane and copying into a second memory location of the display register RA the first node of the plurality of nodes Ni loaded into RAM MV corresponding to the second graphics plane.Reading each of these memory locations is carried out in the same way as in the case of a single graphics plane described previously, that is to say by displaying the image or the frame of the image whose address in RAM MV is contained in a first node and then loading the next node whose address in RAM MV is contained in the first node. Since reading is carried out simultaneously on the two memory locations, two graphics planes are displayed, the second graphics plane being superimposed on the first graphics plane.

Claims

1. Method for display of an animation by a display chip (PA) of an electronic device (DE), said electronic device (DE) comprising a non-volatile memory (MN) and a random-access memory (MV), said display chip (PA) comprising a video output register (RV) and a display register (RA); the method being performed when the electronic device (DE) is started and being characterized in that it comprises a first static programming phase comprising: - a step (E1) for configuration of the video output register (RV), which is carried out so that the display is achieved either in progressive mode or interlaced mode; - a step (E2) for writing n images into the random-access memory (MV), where n is an integer equal to or greater than two, the n images forming, when they are displayed successively, the animation to be displayed; - a step (E3) for writing a plurality of nodes (Ni) into the random-access memory (MV) such that each node comprises the random-access memory (MV) address of at least a frame of an image from amongst the n images, as well as the random-access memory (MV) address of the following node, where the last node comprises the random access memory (MV) address of the first node, the step E3 being function of a display mode chosen during the step E1; - a step (E4) for configuration of the display register (RA), during which a node of the plurality of nodes (Ni) is loaded in the display register (RA) ; and in that it then comprises a second phase for reading of the n images by said display chip (PA), the reading phase comprising: - a display phase, by the display chip (PA), of the image or of the frame of the image whose address is contained in the node of the plurality of nodes (Ni) loaded in the display register (RA), said "loaded node"; - then, once this image or this frame of the image is displayed, a phase of loading into the display register (RA), by the display chip (PA), the node whose address in the random-access memory (MV) is included in the "loaded node"; these two phases being repeated so as to scan the plurality of nodes (Ni) and thus to display the animation obtained by the successive display of the n images.

2. Method according to the previous claim characterized in that a starting program which is in charge of starting an operating system is stored in the nonvolatile memory (MN), and in that the electronic device (DE) comprises an elementary input / output system configured to load said starting program into the random-access (MV) memory and in that the n images are included in said starting program such that the step (E3) for writing the n images into the random-access memory (MV) is carried out during loading of said starting program by said elementary input / output system.

3. Method according to claim 1 characterized in that a starting program which is in charge of starting an operating system is stored in the non-volatile memory (MN), in that the electronic device (DE) comprises an elementary input / output system configured to load said starting program into the random-access memory (MV), and in that the n images are stored in the non-volatile memory (MN) and in that the step for writing (E3) the n images into the random access memory is carried out by copying of the images stored in the non-volatile memory (MN) to the random-access memory (MV) by said starting program.

4. Method according to one of the previous claims characterized in that the n images are stored in compressed form.

5. Method according to one of the preceding claims characterized in that writing of the n images into the random access memory (MV) is carried out in a reserved zone of said random-access memory (MV).

6. Method according to one of the preceding claims characterized in that the configuration of the video output register (RV) during the video output register (RV) configuration step (E1) is performed in such a way that the display is carried out in progressive mode and in that each node comprises the random-access memory (MV) address of an image.

7. Method according to the preceding claim characterized in that the animation is broken down into a first graphics plane and into a second graphics plane, where the first graphics plane constitutes a fixed part of the animation and the second graphics plane constitutes a changing part of the animation, where the display chip (PA) comprises means for superimposing the first graphics plane onto the second graphics plane; and in that the step (E3) for writing a plurality of nodes (Ni) into the random-access memory (MV) comprises two sub-steps: - a first sub-step for writing a node comprising the random-access memory (MV) address of an image intended to be displayed in the first graphics plane, where the node moreover comprises its own address in random access memory (MV) address; - a second sub-step for writing a plurality of nodes (Ni), each node comprising the random access memory (MV) address of an image intended to be displayed in the second graphics plane as well as the random-access memory (MV) address of the following node, with the last node comprising the random-access memory (MV) address of the first node.

8. Method according to one of claims 1 to 5 characterized in that the configuration of the video output register (RV) during the video output register (RV) configuration step is carried out in such a way that the display is made in interlaced mode, in that the plurality of nodes (Ni) comprise even nodes and odd nodes, and in that each odd node comprises the random-access memory (MV) address of an odd frame of an image and each even node comprises the random access memory address (MV) of an even frame of an image.

9. Method according to the preceding claim characterized in that the animation is broken down into a first graphics plane and into a second graphics plane, where the first graphics plane constitutes the fixed part of the animation and the second graphics plane constitutes the changing part of the animation, where the display chip (PA) comprises means for superimposing the first graphics plane onto the second graphics plane; and in that the step (E3) for writing a plurality of nodes (Ni) into the random-access memory (MV) comprises two sub-steps: - a first sub-step for writing a first node and a second node, where the first node comprises the random-access (MV) memory address of the odd frame of an image intended to be displayed in the first graphics plane as well as the random-access memory (MV) address of the second node, where the second node comprises the random access memory (MV) address of the even frame of the image intended to be displayed in the first graphics plane as well as the random access memory (MV) address of the first node; - a second sub-step for writing a plurality of nodes (Ni), where each odd node comprises the random-access memory (MV) address of the odd frame of an image intended to be displayed in the second graphics plane and each even node comprises the random access memory (MV) address of the even frame of an image intended to be displayed in the second graphics plane, where the last node comprises the random access memory (MV) address of the first node.

10. Electronic device (DE) comprising a non-volatile memory (MN), a random access memory (MV) and a display chip (PA), said display chip (PA) comprising a video output register (RV) and a display register (RA); where the device is characterized in that it moreover comprises means for implementing the method according to any of claims 1 to 9.

11. Computer programme product comprising instructions which lead the device according to claim 10 to execute the steps in the method according to any of claims 1 to 9.

12. Support which can be read by a computer on which the computer programme according to claim 11 is recorded.