SYSTEM, METHOD AND MANUFACTURED ARTICLE FOR SYNCHRONIZATION-FREE TRANSMISSION OF NEURON VALUES IN ARTIFICIAL NEURAL NETWORKS OF A HARDWARE

Description

BACKGROUND OF THE INVENTION Field of Invention

[0001] The present invention relates generally to the field of artificial neural networks (ANNs). More specifically, the present invention is related to a system and method for synchronization-free transmittal of neuron values in a hardware artificial neural network.Discussion of Related Art

[0002] Artificial neural networks (ANNs) are distributed computing systems, which consist of several neurons interconnected through connection points called synapses. Each synapse encodes the strength of the connection between the output of one neuron and the input of another. The output of each neuron is determined by the aggregate input received from other neurons that are connected to it, and thus by the outputs of these "upstream" connected neurons and the strength of the connections as determined by the synaptic weights. The ANN is trained to solve a specific problem (e.g., pattern recognition) by adjusting the weights of the synapses such that a particular class of inputs produces a desired output. The weight adjustment procedure is known as "learning." There are many algorithms in the ANN literature for performing learning that are suitable for various tasks such as image recognition, speech recognition, language processing, etc. Ideally, these algorithms lead to a pattern of synaptic weights that, during the learning process, converges toward an optimal solution of the given problem.

[0003] An attractive implementation of ANNs uses some (e.g., CMOS) circuitry to represent the neuron, the function of which is to integrate or sum the aggregate input from upstream neurons to which a particular neuron is connected, and apply some nonlinear function of the input to derive the output of that neuron. Because in general, each neuron is connected to some large fraction of the other neurons, the number of synapses (connections) is much larger than the number of neurons; thus, it is advantageous to use some implementation of synapses that can achieve very high density on a neuromorphic computing chip. One attractive choice is a non-volatile memory (NVM) technology such as resistive random access memory (RRAM) or phase-change memory (PCM). Another attractive choice is a capacitor-transistor pair. It should be noted that while the following document will discuss NVM-based synapses, the techniques, methods, and embodiments are equally relevant to systems based on capacitance-based synaptic elements. Since both positive and negative (i.e., excitatory and inhibitory) weights are desired, one scheme uses a pair of NVM (or two capacitor-transistor pairs) to represent the weight as the difference in conductance between the two (see M. Suri et al., IEDM Tech. Digest, 4.4 (2011)). This scheme is shown in FIG. 1. FIG. 1 illustrates a layer of an ANN implemented on a crossbar array, with pairs of NVM conductances acting as synaptic weights. The outputs of the upstream N i neurons are summed in parallel through pairs of NVM conductances into the positive and negative inputs of the downstream M i neurons. This parallelism is highly advantageous for efficient computation. It should be noted that while a non-linear 2-terminal access device is shown in this scheme, 3-terminal transistor access devices are equally relevant to this discussion.

[0004] The accumulated currents can be mirrored and integrated onto an output capacitor, such that the final analog voltage is representative of the output value of one of the neurons. While this capacitor is 'local' to this particular array and is an analog representation of its output, this value of the output neuron activation must be made available, preferably in a digital format, at the input of another 'downstream' neural network layer implemented on a second crossbar array. This second array could be at an arbitrary distance away from the source / upstream first crossbar array, and preferably, the CMOS chip would be designed in such a way that the mapping between sets of array outputs and subsequent sets of next-array inputs may be chosen by the user at runtime rather than during fabrication.

[0005] FIG. 2 illustrates current mirrors that are used to replicate the instantaneous currents in the crossbar onto an output stage, such that these currents are integrated onto an output capacitance whose final voltage represents the analog activation of the neuron Mi.

[0006] A simplified approximate method to convert an analog voltage to a digital value involves discharging the stored charge at a constant current, and counting the number of clock pulses until the capacitor is fully discharged. While local digitization followed by transmittal to the downstream array would be possible and potentially accurate, this would require very careful synchronization of clock signals all across the system (with minimal clock skew), which could prove to be expensive and power-hungry, if not impossible. The process of passing N such digital values (where N may be 100-1000) would then require qN individual bus lines for parallel transmission, OR would require serialization for slower transmission across fewer bus lines. Such an approach would also require careful re-buffering of the digitized data signals to avoid issues related to interconnect-induced slew (i.e., the phenomenon by which rising and falling edges of input signals become less 'sharp' due to resistive and capacitive effects as they propagate along a metal wire) which carries an additional area penalty.

[0007] WO 2005 / 038645 A in the name of Canon KK discloses a product-sum operation circuit including a pulse width / digital conversion circuit which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width / digital conversion circuit, and an accumulated sum circuit which multiplies each operand value output from the sorting circuit by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width / digital conversion circuit includes a counter which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0 - 11-(n-1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

[0008] JP 2007 228770 a in the name of Optrex KK discloses a protective device that protects a device to which a voltage is supplied, and more particularly a protective device that protects a device to which a voltage is supplied when the voltage supply is suddenly cut off.

[0009] US 2016 / 267378 A in the name of International Business Machines Corporation discloses neuromorphic synapse apparatus comprising a memelement for storing a synaptic weight, and programming logic. The memelement is adapted to exhibit a desired programming characteristic. The programming logic is responsive to a stimulus prompting update of the synaptic weight for generating a programming signal for programming the memelement to update said weight. The programming logic may be responsive to an input signal indicating an input weight-change value ΔWi, and may be adapted to generate a programming signal dependent on the input weight-change value ΔWi. The programming logic is adapted such that the programming signals exploit the programming characteristic of the memelement to provide a desired weight-dependent synaptic update efficacy.

[0010] Thus, there is a need in the art for a technique, given one or more analog values encoded as voltages on a plurality of capacitances, to convey these values to a bank of digital buffers located across an arbitrary distance across the chip.

[0011] Embodiments of the present invention are an improvement over prior art systems and methods.SUMMARY OF THE INVENTION

[0012] According to the present invention there is provided a method implemented in an Artificial Neural Network (ANN), as described in the independent claims.

[0013] In another embodiment, the present invention provides a system implemented in an Artificial Neural Network (ANN), as described in the independent claims.

[0014] Preferred features of the present invention are set out in the appended dependent claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Embodiments of the present invention are described in detail regarding the following figures. The drawings are provided for purposes of illustration only and merely depict examples of the present invention. These drawings are provided to facilitate the reader's understanding of the disclosure and should not be considered limiting of the breadth, scope, or applicability of the disclosure. It should be noted that for clarity and ease of illustration these drawings are not necessarily made to scale. FIG. 1 illustrates a layer of an ANN implemented on a crossbar array, with pairs of NVM conductances acting as synaptic weights. FIG. 2 illustrates current mirrors that are used to replicate the instantaneous currents in the crossbar onto an output stage, such that these currents are integrated onto an output capacitance whose final voltage represents the analog activation of the neuron Mi. FIG. 3 illustrates how an enable signal which starts the analog discharge is shared with a counter associated with the downstream neuron layer. FIG. 4 illustrates a sample circuit where a single counter at the downstream crossbar array can be shared by multiple digitizing flip-flops. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] While this invention is illustrated and described in a preferred embodiment, the invention may be produced in many different configurations. There is depicted in the drawings, and will herein be described in detail, a preferred embodiment of the invention, with the understanding that this description is to be considered as an exemplification of the principles of the invention and the associated functional specifications for its construction and is not intended to limit the invention to the embodiment illustrated. Those skilled in the art will envision many other possible variations within the scope of the present invention.

[0017] Note that in this description, references to "one embodiment" or "an embodiment" mean that the feature being referred to is included in at least one embodiment of the invention. Further, separate references to "one embodiment" in this description do not necessarily refer to the same embodiment; however, neither are such embodiments mutually exclusive, unless so stated and except as will be readily apparent to those of ordinary skill in the art. Thus, the present invention can include any variety of combinations and / or integrations of the embodiments described herein. Furthermore, references to "one unclaimed embodiment" mean that the combination of features is not covered by the claims but is nevertheless useful to understand the invention and its preferred embodiment.

[0018] A preferred embodiment of the invention described here can eliminate challenges related to synchronization of clock signals and slew in data, by encoding data into analog delays and digitizing only at the destination / downstream crossbar array. A preferred embodiment of the invention introduces an initial trigger signal at the source / upstream crossbar array, which traverses the same distance as the subsequent data signals. Both trigger and data signals are thus subject to the same slew effects and the same delays, at least to first order. This approach is well-suited to contexts where the overall application is resilient to small, zero-mean errors in the transmitted data, such as an Artificial Neural Network.

[0019] In a preferred embodiment of the present invention, once the integration operations of charge onto the capacitors in the upstream neurons has fully completed, an enable signal is generated by the control logic of the upstream crossbar array. This enable signal is used to commence discharge of the analog voltage stored on the capacitor in each output neuron, or alternatively, to commence a ramped voltage for use in comparing to these analog voltages. The enable signal is also transmitted to the input of a digital counter that is located at the downstream array. When received, the counter will start an upward count from zero using a clock which need only be synchronous in the local region of the downstream, destination array.

[0020] FIG. 3 illustrates how the enable signal, which starts the analog discharge, is shared with the counter in the output stage. When the comparator rising edge arrives at the FFs, the instantaneous value of the counter is captured. This value is a digital representation of the analog voltage on the upstream output capacitor and is stored locally in the downstream array, since both the arriving signals are subject to the same delays.

[0021] At some point in time, the capacitor voltage will drop below a reference voltage close to zero, or the stationary undischarged capacitor voltage will be passed by the reference voltage ramp. This will cause the output of a comparator, attached to both the output capacitance node and the reference voltage to undergo a '0' to '1' transition. This rising edge will be transmitted to the downstream array, where a bank of flip-flops receiving inputs in parallel from the outputs of the local counter can latch in the current values of the counter bits when this rising edge is received. While there is a non-negligible propagation delay from the output of the comparator (which is local to the upstream array) and the receiving flip-flops (which are local to the downstream array), this delay is comparable to, and is thus effectively offset by, the delay in the enable signal that commenced the counter operation. Thus, without needing to globally synchronize clocks across the chip, it is possible to effectively transmit information.

[0022] The idea can be extended to a single shared counter at the downstream array, with multiple rising edges from different comparators latching in the instantaneous counter value to different flip-flops at various instances in time. As before, so long as the distances are comparable, the latched in value is expected to be a reasonable approximate estimation of the 'true' analog voltage.

[0023] Both the trigger / enable signal and the comparator signal are conveyed on a multi-wire bus, such that the data pattern on this bus encodes the address of the capacitor from which the signal originated, and thus the address of the particular flip-flop which should be latched at the instant of arrival of this data pattern. The delays associated with encoding this address at the source array, and of decoding this address at the destination, need only be identical for each and every capacitor / flip-flop pair, and can be added into the delay associated with the arrival of the trigger signal. If this is done correctly, the first delay at the source between triggering capacitive readout and the transition of the comparator, and the second delay at the destination between triggering of the counter and the latching of the associated flip-flop, will differ by a constant value, which can be engineered to be zero or non-zero as desired. However, this approach could potentially cause some data values to be conveyed incorrectly due to contention (too many comparators tripping within the same short time window). Some tolerance to contention could be designed in by transmitting both a physical address and an encoded delay (after physical address decoding) to be imposed before latching. Thus, several simultaneous comparator events would be transmitted using the appropriate physical addresses and several different encoded delays such that the latching events at the destination occurred nearly simultaneously and at the desired delay (e.g., counter value).

[0024] FIG. 4 illustrates a sample circuit where a single counter at the downstream crossbar array can be shared by multiple digitizing flip-flops. Each arriving rising edge will independently capture different instantaneous values of this counter, depending on the exact arrival time.

[0025] In another unclaimed embodiment, the present invention provides a method implemented in an Artificial Neural Network (ANN), the ANN comprising a plurality of neurons arranged in layers, the layers comprising at least one upstream neuron layer and at least one downstream neuron layer, the output of the at least one upstream neuron layer connected to the input of the at least one downstream neuron layer, the method comprising: (a) commencing discharging of a capacitor in the upstream neuron layer based on an enable signal generated in the upstream neuron layer, the capacitor having an initial value representative of an output of the upstream neuron layer; (b) sharing the enable signal in (a) to an input of a digital counter located at the downstream neuron layer, where the counter, upon reception of the enable signal, starting an upward count from zero using a clock that is local to the downstream neuron layer; (c) monitoring output analog voltage of the capacitor and, when a voltage transition is detected in the monitored output analog voltage, (d) transmitting a voltage transition signal to the downstream neuron layer, and wherein the downstream neuron layer latches current value of the counter upon reception of the voltage transition signal, the latched current value equal to the initial value representative of an output of the upstream neuron layer and where the output value is communicated between the upstream neuron layer and the downstream neuron layer without global synchronization of clocks between the upstream neuron layer and the downstream neuron layer.

[0026] In a family of alternative unclaimed embodiments of the present invention, the capacitor associated with the upstream neuron is not in fact ramped down by discharging it, but instead its voltage is compared to a steadily increasing ramp, and the duration between the initial trigger of this ramp and the time at which the ramp voltage passes the capacitor voltage encodes the analog voltage for transmittal to the remote locale.

[0027] In another family of alternative unclaimed embodiments of the present invention, the duration arriving at the downstream neuron is not digitized, but instead immediately applied to the crossbar array of synaptic devices at that neuron, leading to integration onto a series of capacitors at the next layer of neurons even further downstream from this downstream neuron. Embodiments in which the incoming duration information is both digitized and is applied directly to the downstream synaptic array are also possible.

[0028] In yet another unclaimed embodiment, the present invention provides a system implemented in an Artificial Neural Network (ANN), the ANN comprising a plurality of neurons arranged in layers, the system comprising: (a) a first circuit in a downstream neuron layer, the input of the downstream neuron layer connected to an output of the upstream neuron layer, the first circuit comprising a digital counter and a plurality of flip-flops; (b) a second circuit in an upstream neuron layer, the second circuit comprising: (i) a third circuit to generate an enable signal for discharging a capacitor, the capacitor having an initial value representative of an output of the upstream neuron layer; (ii) a fourth circuit to share the generated enable signal to an input of the digital counter, where the counter, upon reception of the enable signal, starts an upward count from zero using a clock that is local to the downstream neuron layer; (iii) a fifth circuit to monitor output analog voltage of the capacitor and, when a voltage transition is detected in the monitored output analog voltage, (iv) a sixth circuit to transmit a voltage transition signal to the plurality of flip-flops in the first circuit in the downstream neuron layer, wherein the downstream neuron layer latches current value of the counter upon reception of the voltage transition signal, the latched current value equal to the initial value representative of an output of the upstream neuron layer, and wherein the output value is communicated between the upstream neuron layer and the downstream neuron layer without global synchronization of clocks between the upstream neuron layer and the downstream neuron layer.

[0029] In another unclaimed embodiment, the present invention provides a method implemented in an Artificial Neural Network (ANN), the ANN comprising a plurality of neurons arranged in layers, the layers comprising at least one upstream neuron layer and at least one downstream neuron layer, the output of the at least one upstream neuron layer connected to the input of the at least one downstream neuron layer, the method comprising: (a) commencing ramping of a threshold voltage for comparison to an output analog voltage associated with a capacitor in the upstream neuron layer based on an enable signal generated in the upstream neuron layer, where an initial value of the voltage associated with the capacitor represents an output of the upstream neuron layer; (b) sharing the enable signal in (a) to an input of a digital counter located at the downstream neuron layer, where the counter, upon reception of the enable signal, starting counting using a clock that is local to the downstream neuron layer; (c) monitoring the ramped threshold voltage in (a) and detecting a transition at which the ramped threshold voltage passes the output analog voltage of the capacitor in the upstream neuron layer; (d) transmitting a voltage transition signal to the downstream neuron layer, and wherein the downstream neuron layer latches current value of the counter upon reception of the voltage transition signal, the latched current value equal to the initial value representative of an output of the upstream neuron layer and where the output value is communicated between the upstream neuron layer and the downstream neuron layer without global synchronization of clocks between the upstream neuron layer and the downstream neuron layer.

[0030] It is understood that any specific order or hierarchy of steps in the processes disclosed is an illustration of example approaches. For example, in certain circumstances, multitasking and parallel processing may be advantageous.

[0031] The various embodiments of the present invention described above are provided by way of illustration only and should not be construed to limit the scope of the invention, which is defined in the appended claims. Those skilled in the art will readily recognize various modifications and changes that may be made, without departing from the scope of the present invention, which is defined in the appended claims.

Claims

1. A method implemented in an Artificial Neural Network (ANN), the ANN comprising a plurality of neurons arranged in layers, the layers comprising at least one upstream neuron layer and at least one downstream neuron layer, the output of the at least one upstream neuron layer connected to the input of the at least one downstream neuron layer, wherein a plurality of analog signals are transmitted on a plurality of transmission channels, all of the transmission channels sharing a common initialization trigger signal, by encoding each of the signals in the delay between the common initialization trigger signal and a subsequent unique termination trigger, the method comprising: (a) receiving an enable signal generated in the upstream neuron layer, thereby commencing discharging of a capacitor in the upstream neuron layer, the capacitor having an initial value representative of an output of the upstream neuron layer, wherein the capacitor is coupled to a comparator in the upstream neuron layer; (b) sharing the enable signal to an input of a digital counter located at the downstream neuron layer, where the counter, upon reception of the enable signal, starts counting using a clock that is local to the downstream neuron layer; (c) monitoring output analog voltage of the capacitor; and (d) when a voltage transition is detected in the monitored output analog voltage, (e) transmitting a voltage transition signal to a plurality of flip-flops at the downstream neuron layer, wherein the plurality of flip-flops are arranged in parallel with one another and each flip-flop is coupled to the counter such that each flip-flop receives a same counter value from the counter, wherein the downstream neuron layer latches a current value of the counter upon reception of the voltage transition signal, the latched current value being equal to the initial value representative of an output of the upstream neuron layer, and wherein the output value is communicated between the upstream neuron layer and the downstream neuron layer without global synchronization of clocks between the upstream neuron layer and the downstream neuron layer, and wherein the trigger signal, the enable signal and the voltage transition signal are conveyed on a bus between the upstream neuron layer and the downstream neuron layer as an encoded signal that includes an address of the capacitor and a delay to be imposed before latching the current value of the counter, wherein the address of the capacitor corresponds to the address of the particular flip-flop which should be latched at the instant of arrival of the voltage transition signal, and wherein the delays associated with encoding the capacitor address, and of decoding the address at the downstream neuron layer, need only be identical for each and every capacitor / flip-flop pair, and are added into the delay associated with the arrival of the trigger signal.

2. The method of claim 1, wherein the step of monitoring the output analog voltage of the capacitor comprises receiving, at a comparator, inputs of the output analog voltage of the capacitor and a reference voltage, wherein the comparator outputs a signal representative of the monitored output analog voltage of the capacitor.

3. The method of claim 2, wherein the digital counter located at the downstream neuron layer is shared with at least one other comparator located in another upstream neuron layer, wherein rising edges from different comparators are latched at different times according to corresponding instantaneous counter values.

4. The method of claim 1, wherein the transition signal is any of the following: (1) a signal that transitions from low '0' to high '1', and the current value of the counter in (d) is latched upon receiving a rising edge of the transition signal, and (2) a signal that transitions from high '1' to low '0', and the current value of the counter in (d) is latched upon receiving a falling edge of the transition signal.

5. The method of claim 1, wherein neurons in each of the upstream and downstream neuron layers are connected to each other via a synapse, each synapse having a synaptic weight encoding a connection strength between two connected neurons, the synaptic weights in the ANN being implemented using a non-volatile memory (NVM).

6. The method of claim 5, wherein the NVM is selected from the group consisting of resistive random access memory (RRAM) and phase-change memory (PCM).

7. A system implemented in an Artificial Neural Network (ANN), the ANN comprising a plurality of neurons arranged in layers, the system comprising: (a) a first circuit in a downstream neuron layer, the input of the downstream neuron layer connected to an output of the upstream neuron layer, wherein a plurality of analog signals are transmitted on a plurality of transmission channels, all of the transmission channels sharing a common initialization trigger signal, by encoding each of the signals in the delay between the common initialization trigger signal and a subsequent unique termination trigger, the first circuit comprising a digital counter and a plurality of flip-flops, wherein the plurality of flip-flops are arranged in parallel with one another and each flip-flop is coupled to the counter such that each flip-flop receives a same counter value from the counter; (b) a second circuit in an upstream neuron layer, the second circuit comprising: (i) a third circuit to generate an enable signal for discharging a capacitor, the capacitor having an initial value representative of an output of the upstream neuron layer; (ii) a fourth circuit to share the generated enable signal to an input of the digital counter, where the counter, upon reception of the enable signal, starts counting using a clock that is local to the downstream neuron layer; (iii) a fifth circuit to monitor output analog voltage of the capacitor, the fifth circuit comprising a comparator coupled to the capacitor, and (iv) a sixth circuit to transmit a voltage transition signal to the plurality of flip-flops in the first circuit in the downstream neuron layer when a voltage transition is detected in the monitored output analog voltage, wherein the downstream neuron layer latches current value of the counter upon reception of the voltage transition signal, the latched current value being equal to the initial value representative of an output of the upstream neuron layer, wherein the output value is communicated between the upstream neuron layer and the downstream neuron layer without global synchronization of clocks between the upstream neuron layer and the downstream neuron layer, and wherein the trigger signal, the enable signal and the voltage transition signal are conveyed on a bus between the upstream neuron layer and the downstream neuron layer as an encoded signal that includes an address of the capacitor and a delay to be imposed before latching the current value of the counter, wherein the address of the capacitor corresponds to the address of the particular flip-flop which should be latched at the instant of arrival of the voltage transition signal, and wherein the delays associated with encoding the capacitor address, and of decoding the address at the downstream neuron layer, need only be identical for each and every capacitor / flip-flop pair, and are added into the delay associated with the arrival of the trigger signal.

8. The system of claim 7, wherein the comparator receives as inputs the output analog voltage of the capacitor and a reference voltage, wherein the comparator outputs a signal representative of the monitored output analog voltage of the capacitor.

9. The system of claim 7, wherein the digital counter located at the downstream neuron layer is shared with at least one other comparator located in another upstream neuron layer, wherein rising edges from different comparators are latched at different times according to corresponding instantaneous counter values.

10. The system of claim 7, wherein each of the rising edges from different comparators are received by different sets of flip-flops in the downstream neuron layer.

11. The system of claim 7, wherein where neurons in each of the upstream and downstream neuron layers are connected to each other via a synapse, each synapse having a synaptic weight encoding a connection strength between two connected neurons, the synaptic weights in ANN are implemented using a non-volatile memory (NVM).