OVERVOLTAGE PROTECTION CIRCUIT

Description

Field of the Invention

[0001] The present invention relates to an over-temperature protection circuit.Background

[0002] Power semiconductor devices, such as power metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs), can be used as switching elements (or "switches") for switching inductive and / or resistive loads, such as lamps and LEDs, motors, solenoids and heaters, which are used in automotive, industrial and other applications.

[0003] A switching element, such as a MOSFET, may be a discrete component, or it may be integrated into a load switch integrated circuit (IC) or a pre-driver IC.

[0004] Integrated switching elements are often provided with over-temperature (OT) protection to ensure that the switching element does exceed a maximum acceptable operating temperature. This can occur, for example, if the resistance of the load drops to a low value or if there is a short circuit. OT protection is usually achieved by providing an OT sensor close to the switching element coupled to a circuit which, in the event of determining that the operating temperature of the switch exceeds the maximum operating temperature, triggers thermal shutdown.

[0005] OT protection, however, faces a number of challenges. For example, if the OT sensor is located too close to the switching element, for example inside a guard ring around the switching element, then the sensor may detect localised regions of high temperature ("hot spots") and trigger thermal shutdown in a situation when the device is still operating within acceptable limits. Furthermore, locating the OT sensor inside the guard ring, reduces the active driver area resulting in a larger IC and higher ON-state resistance R ON . Although, placing the OT sensor further away from the switching element, outside the guard ring, can help avoid or overcome these drawbacks, it introduces a time delay. In particular, if over temperature occurs, the sensor may detect this condition too late, by which time, the switching element may have suffered irreversible damage.

[0006] One solution, described in US 8,299,767 B1, is to dynamically maintain device operation within a safe operating area (SOA) by sensing instantaneous voltage and current of the device, determining, based on the sensed instantaneous voltage and current, a value that represents a power dissipated in the device, using the determined dissipated power and a model of thermal behaviour of the device to model a junction temperature of the device, and controlling operation of the device based on the modelled junction temperature. This, however, is a complex solution.

[0007] FR 2 826 198 A1 describes a device which acts on a switching component which is a power transistor of type MOSFET with the gate controlled by a voltage translation circuit which produces a switching signal derived from a logic control signal belonging to the range of lower voltage amplitudes. The device comprises an overheat control circuit connected to a detector element which detects the condition of overheating of the switching component and generates a logic inhibition signal which sets the logic control signal into a state bringing about a cooling of the switching component. The switching component is controlled as a two-position switch, and the range of the switching signal values comprises only two values corresponding to the opening and the closing of the switch, which is determined by the respective logic states of the logic control signal. The device comprises a logic circuit which is an AND gate whose one input and the output transmits the logic control signal to the voltage translator circuit, and the other input receives the logic inhibition signal from the overheat control circuit. The overheat control circuit comprises components for producing a temperature signal obtained by detecting a parameter linked to the functioning of the switching component, a comparator receiving the temperature signal on one input and a reference signal on the other input, and an inverter. The comparator is of analogue type with hysteresis effect, that is of the Schmitt trigger type. In the first embodiment, the temperature signal is obtained from a voltage on a component such as a diode which is in thermal contact with the switching component, and the signal is transmitted via an amplifier to the comparator. In the second embodiment, the temperature signal is obtained from the drain-source voltage which is converted into a power value dissipated by the switching organ, and then to the temperature signal as a function of the power value. The conversion includes a mathematical model in the form of analogue or digital circuits. At least a part of the overheat control circuit is implemented as an application-specific integrated circuit.Summary

[0008] According to a first aspect of the present invention there is provided an over-temperature protection circuit as specified in claim 1.

[0009] According to a second aspect of the present invention there is provided an over-temperature protection circuit as specified in claim 9.

[0010] According to a third aspect of the present invention there is provided an integrated circuit comprising the circuit of the first or second aspect of the invention.

[0011] According to a fourth aspect of the present invention there is provided a motor vehicle comprising the circuit of the first or second aspects of the invention or the integrated circuit of the second aspect of the invention.

[0012] The motor vehicle may be a motorcycle, an automobile (sometimes referred to as a "car"), a minibus, a bus, a truck or lorry. The motor vehicle may be powered by an internal combustion engine and / or one or more electric motors.

[0013] Optional features are specified in the dependent claims.Brief Description of the Drawings

[0014] Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a system for controlling and driving a load; Figure 2 is a schematic diagram of a load and a load switch which includes an integrated switching element and safe-operating area (SOA) based protection circuit; Figure 3 illustrates another SOA based protection circuit; Figure 4 illustrates simulated results of SOA-based protection for different values of source-drain voltage at -40 °C; Figure 5 illustrates simulated results of SOA-based protection for different values of source-drain voltage a room temperature at 25 °C; Figure 6 illustrates simulated results of SOA-based protection for different values of source-drain voltage a room temperature at 150 °C; Figure 7 illustrates simulated results of peak-energy density against ON time for an active area of 1 mm 2< ; Figure 8 illustrates simulated results of peak-energy density against ON time for an active area of 0.67 mm 2< ; Figure 9 illustrates simulated results of peak-energy density against ON time for an active area of 0.25 mm 2< ; Figure 10 illustrates a digital safe-operating area (SOA) based protection circuit; and Figure 11 illustrates a motor vehicle which comprises a system for controlling and driving a load. Detailed Description of Certain Embodiments

[0015] Referring to Figure 1, a system 1 for controlling and driving a load 2 is shown.

[0016] The system 1 includes a controller 3, such as a microcontroller, and a load switch integrated circuit (IC) 4 which includes control logic 5, a pre-driver 6 (or "gate driver") and an integrated driver 7.

[0017] The integrated driver 7 includes a switching element 8 in the form of an n-channel, power metal-oxide-semiconductor field-effect transistor (MOSFET) (herein also referred to as an "nMOSFET" or simply "nMOS transistor") and at least one temperature sensor 9.

[0018] The MOSFET 8 is configured in a common-source topology. The drain D of the MOSFET 8 is connected to output terminal OUTx of the load switch IC 4. A load 2 is connected between a positive voltage supply, V BAT , from a battery, e.g. battery 102 (Figure 9) and the output terminal OUTx. The source S is connected to ground GND via the switching element 9. In this case, a low-side switching configuration is used. A worst-case drain current, I limit_x , is defined by current limitation.

[0019] Behaviour of the temperature sensor(s) 9 is monitored by an over-temperature (OT) detection circuit 10 which is used to determine the presence of an OT condition of the MOSFET 8, for example resulting from a short, which might result in destructive heating of the MOSFET 8.

[0020] The load switch IC 4 also includes a safe operating area (SOA)-based over-temperature protection circuit 11 which uses an SOA-based determination to supplement over-temperature detection, and to cause temporary switching-off of the MOSFET 8 using a shutdown enable signal nSD (which is set to LOW in the event of over temperature).

[0021] As will be explained later, temperature-based protection and SOA-based protection operate independently. Thus, the MOSFET 8 can be switched off as a result of a temperature sensor 9 directly measuring an over temperature and / or the SOA-based circuit 11 inferring an over-temperature condition.

[0022] As will be explained in more detail hereinafter, the SOA-based protection circuit 11 effectively calculates an amount of power dissipated by the MOSFET 8, determines whether the power exceeds a given a threshold and, if so, causes temporary shutdown of the MOSFET 8.

[0023] Power P is related to voltage V and current I according to P = IV.

[0024] Although it might be preferable to determine current I accurately, this can be hard to achieve in practice. For example, it can be difficult to distinguish between a soft overload (where the current I exceeds a threshold I OC ) and a short circuit current whose value may be virtually unlimited. Therefore, a defined fast current limitation I limit can be used as a value for the current I. This can be sufficient since current can settle quickly (e.g. within 2 µs). As will be explained, the SOA-based protection circuit 11 can shut off current quickly, for example, in a little as ten or a few tens of microseconds.

[0025] If the voltage V is measured and a value of current I is assumed or defined, then a power P or a parameter which depends on power can be calculated simply using voltage V.

[0026] Driver control is carried out through a driver control signal ONx. The driver control signal ONx and the shutdown enable signal nSD are inputs to an AND gate 12. The output of the AND gate 12 is supplied to the input of the pre-driver 6.

[0027] Referring to Figure 2, a first SOA-based protection circuit 11, 11 1 is shown.

[0028] The circuit 11 senses the source-drain voltage VDS via a tap 13 (or "node") between the output terminal OUTx and the drain D of the MOSFET 8. The source-drain voltage VDS is converted into a current I sense_in by a sense resistor R VDS . The sense resistor R VDS preferably has a negative temperature coefficient to increase shutdown sensitivity at a high temperature, i.e. a high temperature of a substrate on which driver is formed.

[0029] A multiple-stage current mirror 14, in this case a two-stage current mirror, is used to generate a scaled-down current scaled by a scaling factor k, where k is about 100. Each stage scales the current by a factor of ten.

[0030] A first path 15 runs between the tap 13 and ground GND which comprises the sense resistor R VDS , a voltage regulator 16 (which is preferably variable), a channel of a first transistor Q1, in the form of an n-type MOSFET, whose gate is controlled by an over current signal OC supplied by the pre-driver 6 and a channel of second transistor Q2, in the form of an n-type MOSFET. The drain of the second transistor Q2 is connected to its gate. The over current signal OC signals start of an overload event. Below a given threshold OC limit , there is no need for shut down. Above the threshold OC limit, the circuit 11 starts to operate.

[0031] There are two aspects to over current management. First, there is an OC detector 10 which signals an OC event (i.e., when the current I OC rises above a programmable threshold), but which still results in the load 2 being driven with low R ON . If the load current increases further, then the driver goes into a current limitation mode. In current limitation mode, the driver acts as a current source with the level I (== I limit_x ). While the current is limited, the dissipated power just depends on the voltage drop across the driver. Expressed differently, there is no relevant SOA power dissipation below the OC detection threshold. To help try and guarantee correct normal operation, the SOA shut down circuit will be enabled just in case I OC is exceeded. Thus, the OC detector output can be seen as an ENABLE signal for the entire SOA shut down mechanism.

[0032] The voltage regulator 16 takes the form of a Zener diode ZD and is used to set a source-drain voltage threshold VDS_o. The source-drain voltage threshold VDS_o defines the voltage at which the SOA-based circuit 11 1 starts to integrate a power (VDS_o × I limit_x ). Expressed differently, the source-drain voltage threshold VDS_o marks the transition from unrestricted permanent power dissipation regime (i.e., which is not SOA critical) to a regime where power dissipation is monitored.

[0033] The value of the source-drain voltage threshold VDS_o depends on driver size and application. The value can be fixed, for example, by e-fuse programming (or other form of one-time programming).

[0034] The current in the path 15 is the sensed current I sense_in .

[0035] A second path 19 runs between ground GND and supply voltage VDD and includes the channel of a third transistor Q3, in the form of an n-type MOSFET, whose gate is connected to the gate of the second transistor Q2, and the channel of fourth transistor Q4, in the form of an n-type MOSFET. The source of the fourth transistor Q4 is connected to its gate.

[0036] A third path 27 runs between supply voltage VDD and ground GND, and includes a fifth transistor Q5, in the form of an n-type MOSFET, first and second nodes 29, 30 and a programmable current source 31 which drives a current i SOAref . A capacitor C SOA is arranged in parallel with the current source 31, i.e. between second node 30 and ground GND. The current in the third path 27 is a scaled sense current I sense_in / k.

[0037] Level shifting is used to provide and consistent swing amplitude at node 30.

[0038] The capacitor C SOA is used to integrate the scaled sense current I sense_in / k and, thus, effectively determine the accumulated deposited power.

[0039] The values of i SOAref , C SOA and / or R VDS are individually set for each driver class.

[0040] A fourth path 35 runs between supply voltage VDD and ground GND and includes a sixth transistor Q6, in the form of an n-type MOSFET, a level-setting resistor R (for example having a value of the order of a MΩ, 10s of MΩ) for controlling RS flip-flop operation, and a seventh transistor Q7, in the form of an n-type MOSFET. The gates of the sixth and seventh transistors Q6, Q7 are connected to the first and second nodes 29, 30 respectively.

[0041] A fourth node 39 between the source of the sixth transistor Q6 and the level-setting resistor R is connected to the input of a first Schmidt trigger 40. A fifth node 41 between the drain of the sixth transistor Q6 and the level-setting resistor R is connected to the input of a second Schmidt trigger 42.

[0042] The outputs of the Schmidt triggers 40, 42 are supplied to first inputs of respective first and second NAND gates 43, 44 whose outputs are provided to the second inputs of the other NAND 43, 44 (i.e. cross-coupled) to provide an RS flip-flop 45.

[0043] The output of the first NAND gate 43 (i.e. the non-inverting flip-flop output Q) is the SOA-based shutdown signal SOA_SD supplied to a first input of a third NOR gate 46. The second input of the third NOR gate 46 is an OR combination of over-temperature signals. The output of the third NOR gate 46 is provided as the shutdown enable signal nSD to the driver controller AND gate 12.

[0044] A short with a low source-drain voltage VDS leads to longer shut off time. As will be explained in more detail later, there is no shut down below a static power threshold P tot . The over-temperature sensor detector takes over shut down and releases the ONx driver control at T < T OT , where T OT is the threshold temperature for shut down.

[0045] The current i SOAref defines the duration of recovery ("cool down time") which is constant, but can be set for a given driver and an application.

[0046] Referring to Figure 3, a second SOA-based protection circuit 11, 11 2 is shown.

[0047] The second circuit 11, 11 2 senses the source-drain voltage VDS via the tap 13 between the output terminal OUTx and the drain D of the MOSFET 8 and the source-drain voltage VDS is converted into a current I sense_in by the sense resistor R VDS .

[0048] A path 51 runs between the tap 13 and ground GND which comprises the sense resistor R VDS , a voltage regulator 16 in the form of a Zener diode ZD, a switch S1 which is controlled by an over current signal OC supplied by the pre-driver 6, a node 52, a second switch S2 which is controlled by the SOA-based shutdown signal SOA_SD and a programmable current source 53 which drives a current i SOAref .

[0049] The node 52 is connected to the inverting input of an operational amplifier 54 of an integrator 55 comprising the operational amplifier 54 and a feedback capacitor C SOA . A voltage reference Vref is connected to the non-inverting input of the operational amplifier 54.

[0050] The output of the operational amplifier 54 is connected to the input of a Schmidt trigger 56. The output of the Schmidt trigger 56 is supplied to the input of an inverter 57 whose output is the SOA-based shutdown signal SOA_SD.

[0051] The output of the inverter is supplied to a first input of a NOR gate 58. The second input of the NOR gate 58 is an OR combination of over-temperature signals OTx. The output of the NOR gate 58 is provided as the shutdown enable signal nSD to the driver controller AND gate 12.

[0052] The second SOA-based protection circuit 11, 112 operates in substantially the same way as the first SOA-based protection circuit 11, 11 1 .

[0053] Figure 4 shows simulated results of shutdown signal SOA_SD against time generated by the protection circuit 11 shown in Figure 2 for six different values of source-drain voltage V SD , namely 2.5 V, 3 V, 4 V, 7 V, 14 V and 32 V, at -40 °C.

[0054] For source-drain voltages of 2.5 and 3.5 V, there is no shutdown within 10 ms and the shutdown signal SOA_SD stays LOW. For a source-drain voltage of 4 V, the shutdown signal SOA_SD goes HIGH at 2.4 ms and stays HIGH for 0.9 ms. The shutdown signal SOA_SD goes HIGH again at 5.1 ms and stays HIGH for 0.9 ms. As the source-drain voltage increases the duty cycle of shutdown signal SOA_SD increases.

[0055] Figure 5 shows simulated results of shutdown signal SOA_SD against time generated by the protection circuit 11 shown in Figure 2 for the same values of source-drain voltage V SD at 25 °C.

[0056] The results at 25 °C are similar to those for -40 °C, although the duty cycles are slightly higher for corresponding source-drain voltages.

[0057] Figure 6 shows simulated results of shutdown signal SOA_SD against time generated by the protection circuit 11 shown in Figure 2 for the same values of source-drain voltage V SD at 150 °C. The results show that the shutdown signal SOA_SD starts to go HIGH at a lower source-drain voltage, namely 3 V.

[0058] Figure 7 show plots of calculated energy density per square millimetre (in mJmm -2< ) again ON time (in µs) for a driver area of 0.8 mm 2< for three different ambient temperatures, namely- 40 °C, 25 °C and 150 °C. Figure 6 also shows plots of the measured, maximum safe operating area energy density against ON time for a correspondingly sized device at -27 °C and 150 °C.

[0059] The ON resistance is 350 mΩ and a thermal resistance Rth is 5.5 KW -1< . For the calculation, I_limit_max (i.e., I limit_x ) is 6.9A. The peak dissipated power is calculated by multiplying I_limit_max by V DS . The average current is calculated by multiplying I_limit_max by D, where D is the duty cycle. The average dissipated power is calculated by multiplying peak dissipated power by D. Peak energy is calculated by multiplying peak power by ON time. Peak energy density is calculated by multiplying peak energy by driver area. Average junction temperature is calculated by adding the ambient temperature (i.e. -40 °C, 25 °C or 150 °C) to the average dissipated power multiplied by the thermal resistance.

[0060] As shown in Figure 7, the calculated energy density per square millimetre are approximately the same at -40 °C, 25 °C and 150 °C increasing exponentially with ON time, but staying well within the safe operating area.

[0061] Figure 8 show plots of calculated energy density per square millimetre again ON time for a driver area of 0.61 mm 2< for the same three ambient temperatures. In this case, the ON resistance is 720 mΩ and a thermal resistance Rth is 7.2 KW -1< . For the calculation, I_limit_max is 4.1 A.

[0062] Figure 9 show plots of calculated energy density per square millimetre again ON time for a driver area of 0.28 mm 2< for the same three ambient temperatures. In this case, the ON resistance is 2,400 mΩ and a thermal resistance Rth is 15.8 KW -1< . For the calculation, I_limit_max is 1.4 A.

[0063] The SOA-based protection circuits 11 hereinbefore described are implemented by an analogue circuit. SOA-based protection, however, can be implemented by a digital circuit as will now be described in more detail.

[0064] Referring to Figure 10, a digital SOA-based protection circuit 11 3 is shown.

[0065] The circuit 11e includes an analogue-to-digital converter 61 which decimates the source-drain voltage VSD and outputs an n-bit voltage signal.

[0066] A clock signal CLK from a clock 62 digital voltage signal is frequency-multiplied by voltage signal using a multiplier 63. The multiplied digital voltage signal and the clock signal are supplied, via respective first and second switches S1, S2, to count-up and count-down inputs of a bi-directional pulse counter 64. The a source-drain voltage threshold VDS_o is considered inside the ADC 61 as an appropriate offset similar to the offset provided by the Zener diode ZD (Figure 2) in the analogue system. The overflow interrupt flag OF controls the second switch S2, i.e., the CLK signal supplied to the count-down input and the underflow interrupt flag UF controls the first switch S1, i.e. the multiplied digital signal.

[0067] The overflow interrupt flag OF SOA-based shutdown signal SOA_SD and is supplied to a NOR gate 65 in the same way as the analogue-based circuits 11 1 , 11 2 ,

[0068] Referring to Figure 11, a motor vehicle 101 is shown.

[0069] The motor vehicle 101 includes a battery 102 and a plurality of different loads 2, for example motors, supplied with power from the battery 102 and each controlled by a respective load switch 4 which is controlled by a controller 2. An SOA-based protection and shut down circuit 11 can be provided in a load switch 4.Modifications

[0070] It will be appreciated that various modifications may be made to the embodiments hereinbefore described. Such modifications may involve equivalent and other features which are already known in the design, manufacture and use of load switch drivers and component parts thereof and which may be used instead of or in addition to features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.

[0071] The nMOS transistor 6 may be a discrete component or may be integrated into a load switch IC or into the pre-driver IC 4.

Claims

1. An over-temperature protection circuit (11) comprising: an input (13) for sensing a source-drain voltage (VDS) at a node (13) arranged between an output terminal (OUTx) and a drain (D) of a transistor (8); a voltage-to-current converter (RVDS) configured to generate a current (Isense_in) in dependence upon the voltage, the voltage-to-current converter comprising a path (15, 19, 27; 51) arranged between the input (13) and a reference level (GND), the path comprising a resistor (RVDS); an accumulator (CSOA; 54, CSOA) including a capacitor (CSOA) arranged to integrate the current or a scaled current obtained from the current and to provide an output; and a comparator (R, 45; 56, 57) configured to determine whether the output exceeds a threshold and, in dependence on the output exceeding the threshold, to generate a signal (SOA_SD) for signalling that the transistor is be switched off.

2. The circuit of claim 1, further comprising: a current mirror (14).

3. The circuit of claim 1 or 2, wherein the accumulator (CSOA; 54, CSOA; 64) further comprises: an operational amplifier (54).

4. The circuit of any one of claims 1 to 3, wherein the resistor (RVDS) has a negative temperature coefficient.

5. The circuit of any one of claims 1 to 4, wherein the path further comprises: a voltage regulator (ZD).

6. The circuit of claim 5, wherein the voltage regulator (ZD) comprises: a Zener diode.

7. The circuit of any one of claims 1 to 6, wherein the path (15, 19, 27; 51) further comprises: a current source (31; 53) for driving a control current iSOAref for delivering a current to decrease the output of the accumulator and so set a recovery time during which the transistor is switched off.

8. The circuit of any one of claims 1 to 7, wherein the comparator (R, 45; 56, 57) comprises at least one Schmitt trigger.

9. An over-temperature protection circuit (11) comprising: an input (13) for sensing a source-drain voltage (VDS) at a node (13) arranged between an output terminal (OUTx) and a drain (D) of a transistor (8); an analogue-to-digital converter (61) configured to decimate the voltage (VDS) and output a digitised voltage; and a counter (64) configured to receive a signal dependent on the digitised voltage for incrementing the counter; wherein the counter is configured to determine whether the value exceeds a threshold value and, in dependence on the value exceeding the threshold value, to generate a signal (SOA_SD) for signalling that the transistor is be switched off.

10. The circuit of claim 9, further comprising: a clock (62) arranged to provide a clock signal (CLK); and a multiplier (63), wherein the multiplier is configured to multiply the clock signal (CLK) by the digitised voltage to provide a voltage-controlled, frequency-multiplied clock signal to the counter.

11. The circuit of claim 9 or 10, further comprising: first and second switches (S1, S2) arranged to control accumulation and reduction of the counter (64).

12. The circuit of any one of claim 1 to 11, further comprising: a gate (46; 65) configured to receive a receive an output from the from the comparator or counter and an output from an over-temperature detection circuit and to output a control signal (nSD) to cause the transistor to be switched off.

13. An integrated circuit (4) comprising the circuit of any one of claims 1 to 12; control logic (5); and a pre-driver (6) for controlling a driver for controlling switching of the transistor.

14. The integrated circuit of claim 13, further comprising: a driver (comprising the transistor.

15. A motor vehicle comprising: the circuit of any one of claims 1 to 12 or the integrated circuit of claim 13 or 14.