ARCHITECTURE OF INDUCTIVE WIRING, INTEGRATED CIRCUIT AND COMMUNICATION DEVICE
Patent Information
- Application Number
- DE602019065274
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2019-03-29
- Publication Date
- 2025-01-22
- Estimated Expiration
- 2039-03-29
AI Technical Summary
In integrated circuits, particularly RFICs, the insufficient metal arrangement area in the bottom metal layer of metal wires leads to poor yield and a risk of short-circuiting, especially when dummy metals are used under inductor devices, which can impair the inductor's performance.
The inductor device wiring architecture includes a plurality of dummy metals arranged in multiple metal layers under the inductor device, with the arrangement areas of dummy metals progressively increasing in a direction away from the inductor device, minimizing their impact on the inductor's performance while ensuring sufficient metal arrangement for chemical mechanical polishing.
This architecture reduces adverse effects on the inductor device performance, increases product yield, and improves processing quality by maintaining a sufficient metal arrangement area under the inductor device.